CN117500263A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN117500263A CN117500263A CN202210857963.8A CN202210857963A CN117500263A CN 117500263 A CN117500263 A CN 117500263A CN 202210857963 A CN202210857963 A CN 202210857963A CN 117500263 A CN117500263 A CN 117500263A
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000002955 isolation Methods 0.000 claims abstract description 112
- 239000003990 capacitor Substances 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000003860 storage Methods 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000003068 static effect Effects 0.000 abstract description 13
- 230000015556 catabolic process Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- Semiconductor Memories (AREA)
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Abstract
A semiconductor structure and method of forming the same, wherein the structure comprises: a substrate including a storage region including a first region and a second region; a first isolation trench located within the first region; a first isolation layer located within the first isolation trench, the first isolation layer covering a bottom surface and a portion of a sidewall surface of the first isolation trench; a plurality of additional trenches located within the second region; an insulating layer located on sidewall surfaces of the first isolation trench, bottom surfaces and sidewall surfaces of the additional trench, and top surfaces of the second region where the first isolation layer is exposed; and the upper electrode layer is positioned on the insulating layer, fills the first isolation groove and the additional groove, and forms a capacitor structure by the substrate, the insulating layer and the upper electrode layer. And forming a plurality of additional grooves in the second region, and increasing the right facing area between electrode layers in the capacitor structure by utilizing the bottom surface and the side wall surface of the additional grooves, so as to increase the capacitance of the capacitor structure and improve the performance of the single transistor static random access memory.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continued development of digital integrated circuits, integrated memory on chip has become an important component in digital systems. Static random access memory (Static Random Access Memory, SRAM) is an integral part of on-chip memory because of its low power consumption and high speed. The static random access memory can store data only by supplying power to the static random access memory, and the static random access memory does not need to be refreshed continuously.
However, the performance of the sram formed by the prior art is still poor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the capacitance of a capacitor structure.
In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate comprising a storage region comprising a first region and a second region adjacent to each other; a first isolation trench located within the first region; a first isolation layer located within the first isolation trench, the first isolation layer covering a bottom surface and a portion of a sidewall surface of the first isolation trench; a plurality of additional trenches located within the second region; an insulating layer located on sidewall surfaces of the first isolation trench, bottom surfaces and sidewall surfaces of the additional trench, and top surfaces of the second region where the first isolation layer is exposed; and the upper electrode layer is positioned on the insulating layer, fills the first isolation groove and the additional groove, and forms a capacitor structure by the substrate, the insulating layer and the upper electrode layer.
Optionally, the substrate further comprises: a device region adjacent to the storage region; the semiconductor structure further includes: and a transistor structure in the device region, the transistor structure being electrically connected to the capacitor structure.
Optionally, the material of the insulating layer includes: and (3) silicon oxide.
Optionally, the thickness of the insulating layer is: 1 nm-100 nm.
Optionally, the depth of the additional trench is: 5 nm-500 nm.
Optionally, the material of the upper electrode layer includes: and (3) polycrystalline silicon.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a storage area, and the storage area comprises a first area and a second area which are adjacent; forming a first isolation trench in the first region; forming a first isolation layer in the first isolation trench, wherein the first isolation layer covers the bottom surface and part of the side wall surface of the first isolation trench; forming a plurality of additional trenches in the second region; forming an insulating layer on the sidewall surface of the first isolation trench, the bottom surface and sidewall surface of the additional trench, and the top surface of the second region, where the first isolation layer is exposed; and forming an upper electrode layer on the insulating layer, wherein the upper electrode layer is filled with the first isolation groove and the additional groove, and a capacitor structure is formed by the substrate, the insulating layer and the upper electrode layer.
Optionally, the substrate further comprises: a device region adjacent to the storage region; the method for forming the semiconductor structure further comprises the following steps: a transistor structure is formed in the device region, the transistor structure being electrically connected to the capacitor structure.
Optionally, the forming process of the insulating layer includes: atomic layer deposition process.
Optionally, the material of the insulating layer includes: and (3) silicon oxide.
Optionally, the thickness of the insulating layer is: 1 nm-100 nm.
Optionally, the depth of the additional trench is: 5 nm-500 nm.
Optionally, the material of the upper electrode layer includes: and (3) polycrystalline silicon.
Optionally, the forming method of the first isolation layer includes: forming an isolation material layer in the first isolation trench and on the substrate; flattening the isolation material layer until the top surface of the substrate is exposed, and forming a first isolation layer; and performing etching back treatment on the first isolation layer so that part of the side wall surface of the first isolation groove is exposed by the first isolation layer.
Optionally, the method of forming a plurality of additional trenches in the second region includes: forming a photoresist layer on the substrate, wherein the photoresist layer exposes a part of the top surface of the second region; and etching the second region exposed by the photoresist layer by taking the photoresist layer as a mask to form a plurality of additional grooves.
Optionally, the process of etching the second region exposed by the photoresist includes: a dry etching process or a wet etching process.
Optionally, the forming process of the upper electrode layer includes: and (5) an epitaxial growth process.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the semiconductor structure provided by the technical scheme of the invention comprises the following components: a plurality of additional trenches located within the second region; an insulating layer located on sidewall surfaces of the first isolation trench, bottom surfaces and sidewall surfaces of the additional trench, and top surfaces of the second region where the first isolation layer is exposed; and the upper electrode layer is positioned on the insulating layer, fills the first isolation groove and the additional groove, and forms a capacitor structure by the substrate, the insulating layer and the upper electrode layer. And forming a plurality of additional grooves in the second region, and further increasing the opposite area between the electrode layers in the capacitor structure by utilizing the bottom surface and the side wall surfaces of the additional grooves, so as to increase the capacitance of the capacitor structure and improve the performance of the single transistor static random access memory.
Further, the thickness of the insulating layer is: 1 nm-100 nm. When the thickness of the insulating layer is less than 1 nm, insufficient insulation of the insulating layer may cause leakage or breakdown of the device; when the thickness of the insulating layer is greater than 100 nm, the modulating ability of the gate electrode to the transistor structure is reduced, and the transistor structure may not be turned on or off.
Further, the depth of the additional trench is: 5 nm-500 nm. When the depth of the additional groove is smaller than 5 nanometers, the opposite area between the electrode layers in the capacitor structure is less increased, and the capacitance of the capacitor structure is less increased; when the depth of the additional trench is greater than 500 nm, uniformity of the insulating layer formed in the additional trench may be reduced, and the upper electrode layer may not fill the bottom of the additional trench, which may easily cause defects in the formed capacitor structure.
The method for forming the semiconductor structure provided by the technical scheme of the invention comprises the following steps: forming a plurality of additional trenches in the second region; forming an insulating layer on the sidewall surface of the first isolation trench, the bottom surface and sidewall surface of the additional trench, and the top surface of the second region, where the first isolation layer is exposed; and forming an upper electrode layer on the insulating layer, wherein the upper electrode layer is filled with the first isolation groove and the additional groove, and a capacitor structure is formed by the substrate, the insulating layer and the upper electrode layer. And forming a plurality of additional grooves in the second region, and further increasing the opposite area between the electrode layers in the capacitor structure by utilizing the bottom surface and the side wall surfaces of the additional grooves, so as to increase the capacitance of the capacitor structure and improve the performance of the single transistor static random access memory.
Further, the thickness of the insulating layer is: 1 nm-100 nm. When the thickness of the insulating layer is less than 1 nm, insufficient insulation of the insulating layer may cause leakage or breakdown of the device; when the thickness of the insulating layer is greater than 100 nm, the modulating ability of the gate electrode to the transistor structure is reduced, and the transistor structure may not be turned on or off.
Further, the depth of the additional trench is: 5 nm-500 nm. When the depth of the additional groove is smaller than 5 nanometers, the opposite area between the electrode layers in the capacitor structure is less increased, and the capacitance of the capacitor structure is less increased; when the depth of the additional trench is greater than 500 nm, uniformity of the insulating layer formed in the additional trench may be reduced, and the upper electrode layer may not fill the bottom of the additional trench, which may easily cause defects in the formed capacitor structure.
Further, the forming process of the upper electrode layer includes: and the epitaxial growth process has stronger filling capability, so that the additional groove and the first isolation groove can be tightly filled, and the occurrence of a void (void) is avoided, thereby affecting the performance of the capacitor structure.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 7 are schematic structural views illustrating steps in a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the sram formed by the prior art is still poor. The present invention will now be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a semiconductor structure.
Referring to fig. 1, a semiconductor structure includes: a substrate 100, the substrate 100 including a storage region; a first isolation trench (not shown) located within the storage region; a first isolation layer 101 located within the first isolation trench, the first isolation layer 101 covering a bottom surface and a portion of a sidewall surface of the first isolation trench; an insulating layer 102 located on a sidewall surface of the first isolation trench where the first isolation layer 101 is exposed, and a top surface of the storage region; and an upper electrode layer 103 on the insulating layer 102, wherein the upper electrode layer 103 fills the first isolation trench, and a capacitor structure is formed by the substrate 100, the insulating layer 102 and the upper electrode layer 103.
In this embodiment, the substrate 100 further includes: a device region (not shown) adjacent to the memory region; the semiconductor structure further includes: and a transistor structure in the device region, the transistor structure being electrically connected to the capacitor structure. A single transistor static random access memory (i.e., 1T-SRAM) is constructed due to the transistor structure and the capacitor structure.
However, the capacitance of the single transistor sram should be as large as possible based on the electrical performance and functional considerations of the single transistor sram. The capacitance of the capacitor structure is as follows: cox=epsilon.s/Tox, where S is the facing area between the electrode layers; tox is the thickness of the insulating layer; epsilon is the dielectric constant of the insulating layer. The current single transistor sram uses the sidewall surface of the first isolation trench exposed by the first isolation layer 101 and the top surface of the storage area to increase the facing area between the electrode layers, so as to increase the capacitance of the capacitor structure, but the increasing amplitude is still limited, so as to affect the performance of the single transistor sram.
In order to solve the above-mentioned problems, the present invention provides a semiconductor structure and a method for forming the same, in which a plurality of additional trenches are formed in a second region, and the bottom surface and the sidewall surface of the additional trenches are used to further increase the facing area between electrode layers in a capacitor structure, so as to increase the capacitance of the capacitor structure, thereby improving the performance of a single transistor static random access memory.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 7 are schematic views of a semiconductor structure and a method for forming the same according to an embodiment of the present invention.
Referring to fig. 2, a substrate 200 is provided, the substrate 200 includes a storage area A1, and the storage area A1 includes a first area I and a second area II adjacent to each other.
In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon-on-insulator, germanium-on-insulator, or silicon-germanium-on-insulator.
In this embodiment, the substrate 200 further includes: a device region A2 adjacent to the memory region A1. Subsequently, a capacitor structure is formed in the memory area A1, and a transistor structure is formed in the device area A2, wherein the transistor structure and the capacitor structure are electrically connected to form a single transistor static random access memory (namely, 1T-SRAM).
Referring to fig. 3, a first isolation trench 201 is formed in a first region I.
In this embodiment, in the process of forming the first isolation trench 201 in the first region I, further includes: a second isolation trench 202 is formed within the device region A2.
In this embodiment, the first isolation trench 201 defines the size and location for the subsequent formation of the first isolation layer, and the second isolation trench 202 defines the size and location for the subsequent formation of the second isolation layer.
Referring to fig. 4, a first isolation layer 203 is formed in the first isolation trench 201, and the first isolation layer 203 covers a bottom surface and a portion of a sidewall surface of the first isolation trench 201.
In this embodiment, the method for forming the first isolation layer 203 includes: forming an isolation material layer (not shown) within the first isolation trench 201 and on the substrate 200; planarizing the isolation material layer until the top surface of the substrate 100 is exposed, forming a first isolation layer 203; the first isolation layer 203 is subjected to an etching back process such that the first isolation layer 203 exposes a portion of the sidewall surface of the first isolation trench 201.
In this embodiment, in the process of forming the first isolation layer 203, further including: a second isolation layer 204 is formed within the second isolation trench 202, the top surface of the second isolation layer 204 being flush with the top surface of the device region A2.
When the first isolation layer 203 is etched back, the second isolation layer 204 is covered by a sacrificial layer (not shown), so that the second isolation layer 204 is prevented from being damaged by etching during the etching back of the first isolation layer 203, and the sacrificial layer is removed after the etching back.
Referring to fig. 5, a plurality of additional trenches 205 are formed in the second region II.
In this embodiment, the method of forming the plurality of additional trenches 205 in the second region II includes: forming a photoresist layer (not shown) on the substrate 200, the photoresist layer exposing a portion of a top surface of the second region II; the second region II exposed by the photoresist layer is etched using the photoresist layer as a mask, forming a plurality of additional trenches 205.
In this embodiment, a dry etching process is used for etching the second region II exposed by the photoresist; in other embodiments, the process of etching the exposed second region of photoresist may also employ a wet etching process.
In this embodiment, the number of additional grooves 205 may be adjusted as desired. When the number of the additional grooves 205 is too small, the increase of the facing area between the electrode layers in the capacitor structure is small, and the increase of the capacitance of the capacitor structure is small; when the number of the additional trenches 205 is excessive, the leakage probability of the whole capacitor structure is increased.
In the present embodiment, the depth of the additional trench 205 is: 5 nm-500 nm. When the depth of the additional groove 205 is less than 5 nanometers, the facing area between the electrode layers in the capacitor structure is less increased, and the capacitance of the capacitor structure is less increased; when the depth of the additional trench 205 is greater than 500 nm, uniformity of an insulating layer formed in the additional trench 205 may be reduced, and an upper electrode layer formed later may not fill the bottom of the additional trench 205, which may easily cause defects in the formed capacitor structure.
In this embodiment, the preset capacitance value of the capacitor structure can be obtained by adjusting the number and depth of the additional grooves 205.
Referring to fig. 6, an insulating layer 206 is formed on the sidewall surfaces of the first isolation trench 201, the bottom surfaces and sidewall surfaces of the additional trench, and the top surface of the second region II, which are exposed by the first isolation layer 203.
In this embodiment, the insulating layer 206 is further formed on the device region A2, and the insulating layer 206 located on the device region A2 serves as a gate dielectric layer of the transistor structure.
In this embodiment, silicon oxide is used as the material of the insulating layer 206.
In this embodiment, the thickness of the insulating layer 206 is: 1 nm-100 nm. When the thickness of the insulating layer 206 is less than 1 nm, insufficient insulation of the insulating layer 206 may cause leakage or breakdown of the device; when the thickness of the insulating layer 206 is greater than 100 nm, the thickness of the corresponding gate dielectric layer is also greater than 100 nm, so that the modulation capability of the subsequently formed gate to the transistor structure is reduced, and the transistor structure may not be turned on or off.
In this embodiment, the insulating layer 206 is formed by an atomic layer deposition process.
Referring to fig. 7, an upper electrode layer 207 is formed on the insulating layer 206, the upper electrode layer 207 fills the first isolation trench 201 and the additional trench 205, and a capacitor structure is formed by the substrate 200, the insulating layer 206 and the upper electrode layer 207.
In this embodiment, by forming a plurality of additional trenches 205 in the second region II, the bottom surface and the sidewall surface of the additional trenches 205 are used to further increase the facing area between the electrode layers in the capacitor structure, thereby increasing the capacitance of the capacitor structure and improving the performance of the single transistor sram.
In this embodiment, the upper electrode layer 207 is also formed on the device region A2, and the upper electrode layer 207 located on the device region A2 serves as a gate of the transistor structure.
In this embodiment, the material of the upper electrode layer 207 is polysilicon.
In this embodiment, the formation process of the upper electrode layer 207 adopts an epitaxial growth process, and since the epitaxial growth process has a relatively strong filling capability, the additional trench 205 and the first isolation trench 201 can be filled tightly, so that a void (void) is avoided, and the performance of the capacitor structure is further affected.
In this embodiment, after forming the capacitor structure, the method further includes: source-drain doped layers (not labeled) are formed in the device region A2, and the source-drain doped layers are located on two sides of the grid electrode, so that a transistor structure is formed.
In this embodiment, the substrate 200 (i.e., the bottom electrode layer) in the capacitor structure is electrically connected to the source/drain doped layer in the transistor structure, thereby forming a single transistor static random access memory (i.e., 1T-SRAM).
In this embodiment, the process of the capacitor structure and the process of the transistor structure are compatible, so that the difficulty of the process can be effectively reduced, and the cost of the process can be reduced.
In this embodiment, after the basic structure of the single transistor sram is formed through the above steps, the storage area A1 is then ion-implanted to reduce the contact resistance of the substrate 200 as the lower electrode layer.
Accordingly, in an embodiment of the present invention, a semiconductor structure is further provided, please continue to refer to fig. 7, which includes: a substrate 200, the substrate 200 comprising a storage area A1, the storage area A1 comprising a first area I and a second area II adjacent to each other; a first isolation trench 201 located within the first region I; a first isolation layer 203 located within the first isolation trench 201, the first isolation layer 203 covering a bottom surface and a portion of sidewall surfaces of the first isolation trench 201; a number of additional trenches 205 located within the second region II; an insulating layer 206 located on sidewall surfaces of the first isolation trench 201, bottom surfaces and sidewall surfaces of the additional trench 205, and top surfaces of the second region II, where the first isolation layer 203 is exposed; an upper electrode layer 207 on the insulating layer 206, the upper electrode layer 207 filling the first isolation trench 201 and the additional trench 205, and a capacitor structure is formed by the substrate 200, the insulating layer 206 and the upper electrode layer 207.
In this embodiment, by forming a plurality of additional trenches 205 in the second region II, the bottom surface and the sidewall surface of the additional trenches 205 are used to further increase the facing area between the electrode layers in the capacitor structure, thereby increasing the capacitance of the capacitor structure and improving the performance of the single transistor sram.
In this embodiment, the substrate 200 further includes: a device region A2 adjacent to the memory region A1; the semiconductor structure further includes: the transistor structure in the device region A2 is electrically connected with the capacitor structure to form a single transistor static random access memory (i.e., 1T-SRAM).
In this embodiment, silicon oxide is used as the material of the insulating layer 206.
In this embodiment, the thickness of the insulating layer 206 is: 1 nm-100 nm. When the thickness of the insulating layer 206 is less than 1 nm, insufficient insulation of the insulating layer 206 may cause leakage or breakdown of the device; when the thickness of the insulating layer 206 is greater than 100 nm, the thickness of the corresponding gate dielectric layer is also greater than 100 nm, so that the modulation capability of the gate to the transistor structure is reduced, and the transistor structure may not be turned on or off.
In this embodiment, the number of additional grooves 205 may be adjusted as desired. When the number of the additional grooves 205 is too small, the increase of the facing area between the electrode layers in the capacitor structure is small, and the increase of the capacitance of the capacitor structure is small; when the number of the additional trenches 205 is excessive, the leakage probability of the whole capacitor structure is increased.
In the present embodiment, the depth of the additional trench 205 is: 5 nm-500 nm. When the depth of the additional groove 205 is less than 5 nanometers, the facing area between the electrode layers in the capacitor structure is less increased, and the capacitance of the capacitor structure is less increased; when the depth of the additional trench 205 is greater than 500 nm, uniformity of an insulating layer formed in the additional trench 205 may be reduced, and an upper electrode layer formed later may not fill the bottom of the additional trench 205, which may easily cause defects in the formed capacitor structure.
In this embodiment, the material of the upper electrode layer 207 is polysilicon.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (17)
1. A semiconductor structure, comprising:
a substrate comprising a storage region comprising a first region and a second region adjacent to each other;
a first isolation trench located within the first region;
a first isolation layer located within the first isolation trench, the first isolation layer covering a bottom surface and a portion of a sidewall surface of the first isolation trench;
a plurality of additional trenches located within the second region;
an insulating layer located on sidewall surfaces of the first isolation trench, bottom surfaces and sidewall surfaces of the additional trench, and top surfaces of the second region where the first isolation layer is exposed;
and the upper electrode layer is positioned on the insulating layer, fills the first isolation groove and the additional groove, and the substrate, the insulating layer and the upper electrode layer form a capacitor structure.
2. The semiconductor structure of claim 1, wherein the substrate further comprises: a device region adjacent to the storage region; the semiconductor structure further includes: and the transistor structure is positioned in the device region and is electrically connected with the capacitor structure.
3. The semiconductor structure of claim 1, wherein the material of the insulating layer comprises: and (3) silicon oxide.
4. The semiconductor structure of claim 1, wherein the insulating layer has a thickness of: 1 nm-100 nm.
5. The semiconductor structure of claim 1, wherein a depth of the additional trench is: 5 nm-500 nm.
6. The semiconductor structure of claim 1, wherein the material of the upper electrode layer comprises: and (3) polycrystalline silicon.
7. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a storage area, and the storage area comprises a first area and a second area which are adjacent;
forming a first isolation trench within the first region;
forming a first isolation layer in the first isolation trench, wherein the first isolation layer covers the bottom surface and part of the side wall surface of the first isolation trench;
forming a plurality of additional trenches within the second region;
forming an insulating layer on the sidewall surfaces of the first isolation trench, the bottom surfaces and sidewall surfaces of the additional trench, and the top surface of the second region, which are exposed by the first isolation layer;
and forming an upper electrode layer on the insulating layer, wherein the upper electrode layer fills the first isolation groove and the additional groove, and the substrate, the insulating layer and the upper electrode layer form a capacitor structure.
8. The method of forming a semiconductor structure of claim 7, wherein the substrate further comprises: a device region adjacent to the storage region; the method for forming the semiconductor structure further comprises the following steps: and forming a transistor structure in the device region, wherein the transistor structure is electrically connected with the capacitor structure.
9. The method of forming a semiconductor structure of claim 7, wherein the process of forming the insulating layer comprises: atomic layer deposition process.
10. The method of forming a semiconductor structure of claim 7, wherein the material of the insulating layer comprises: and (3) silicon oxide.
11. The method of forming a semiconductor structure of claim 7, wherein the insulating layer has a thickness of: 1 nm-100 nm.
12. The method of forming a semiconductor structure of claim 7, wherein the additional trench has a depth of 5 nm to 500 nm.
13. The method of forming a semiconductor structure of claim 7, wherein the material of the upper electrode layer comprises: and (3) polycrystalline silicon.
14. The method of forming a semiconductor structure of claim 7, wherein the method of forming a first isolation layer comprises: forming an isolation material layer in the first isolation trench and on the substrate; flattening the isolation material layer until the top surface of the substrate is exposed, so as to form the first isolation layer; and performing back etching treatment on the first isolation layer so that part of the side wall surface of the first isolation groove is exposed by the first isolation layer.
15. The method of forming a semiconductor structure of claim 7, wherein forming additional trenches in the second region comprises: forming a photoresist layer on the substrate, wherein the photoresist layer exposes a part of the top surface of the second region; and etching the second area exposed by the photoresist layer by taking the photoresist layer as a mask to form a plurality of additional grooves.
16. The method of forming a semiconductor structure of claim 15, wherein etching the second region exposed by the photoresist comprises: a dry etching process or a wet etching process.
17. The method of forming a semiconductor structure of claim 7, wherein the process of forming the upper electrode layer comprises: and (5) an epitaxial growth process.
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