CN117499751A - Display processing subsystem, system-on-chip, electronic device and display processing method - Google Patents

Abstract

The application provides a display processing subsystem, a system-level chip, electronic equipment and a display processing method, wherein a storage module and a direct register access module are added in the display processing subsystem when display processing is performed, and image quality configuration parameters can be stored and processed in batches.

Description

Display processing subsystem, system-on-chip, electronic device and display processing method

Technical Field

The application relates to the technical field of display processing, in particular to a display processing subsystem, a system-level chip, electronic equipment and a display processing method.

Background

With the progress of television main chip technology and the development of audio and video technology standards, such as dolby visual field, RMVB, blue light and other video technologies, dolby panoramic sound, dolby sound effect, DTS and other audio technologies are gradually popularized to intelligent television terminals, and these technology standards gradually penetrate into content ends such as HDMI signal equipment, OTT, local multimedia files and the like, so that a new audio and video content industry chain is formed, and the technology becomes a core point for promoting television function propaganda and sales. And thus the demand for video image quality processing is increasing.

Disclosure of Invention

In order to solve the technical problems, the application provides a display processing subsystem, a system-in-chip, an electronic device and a display processing method, optimizes the architecture of the display processing subsystem and the display processing method, can ensure that image quality configuration parameters are completely written into a related register in a specific time (such as non-display time of a picture), improves the processing efficiency, stability and robustness of the system, and is beneficial to improving the picture display quality.

According to a first aspect of the present application, there is provided a display processing subsystem comprising:

the storage module is used for receiving and storing the image quality configuration parameters;

the direct register access module is in communication connection with the storage module, and is used for reading a plurality of image quality configuration parameters from the storage module according to preset reading configuration information and outputting the image quality configuration parameters to a plurality of registers in batches;

and the image quality processing module is in communication connection with the direct register access module and is used for responding to the batch configuration of the plurality of registers by the direct register access module and processing the image quality of the image to be displayed.

Optionally, the storage module includes a storage unit, and the storage unit receives and stores a plurality of the image quality configuration parameters frame by frame.

Optionally, the storage module includes a plurality of storage units, and the plurality of storage units store the image quality configuration parameters of a plurality of frames in an asynchronous manner.

Optionally, the plurality of storage units are configured to perform read-write management on the image quality configuration parameters of the stored multi-frames in a first-in-first-out manner.

Optionally, the reading the configuration information includes: a start read address, the number of the image quality configuration parameters to be read, or a stop read address.

Optionally, the direct register access module is further configured to perform format recognition on the read multiple image quality configuration parameters, and implement batch output by performing batch processing after combining the identified multiple image quality configuration parameters with a predetermined format.

Optionally, the direct register access module outputs the read plurality of image quality configuration parameters to a plurality of registers in batches in a non-display interval of each frame so as to complete batch configuration of the plurality of registers.

Optionally, the display processing subsystem further comprises:

and the control module is used for adjusting the number of the storage units participating in the work in the storage module according to the load size of the system.

According to a second aspect of the present application, there is provided a system-on-chip comprising: a display processing subsystem as described in any of the embodiments herein.

According to a third aspect of the present application, there is provided an electronic device comprising: a system-on-chip as described in any of the embodiments herein.

According to a fourth aspect of the present application, there is provided a display processing method, including:

writing the calculated image quality configuration parameters into a storage module frame by frame;

a direct register access module is utilized to read a plurality of image quality configuration parameters corresponding to each frame from the storage module according to preset reading configuration information, and the image quality configuration parameters are output to a plurality of registers in batches;

and responding to batch configuration of the plurality of registers by the direct register access module, and performing image quality processing on the image to be displayed.

The scheme of the embodiment optimizes the architecture of the display processing subsystem and the display processing method, can improve the processing efficiency, stability and robustness of the system, and is beneficial to improving the picture display quality.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

FIG. 1 shows a block diagram of a display processing subsystem provided in accordance with a first embodiment of the present invention;

FIG. 2 shows a block diagram of a display processing subsystem provided in accordance with a second embodiment of the present invention;

FIG. 3 shows a block diagram of a system on chip provided in accordance with an embodiment of the present invention;

fig. 4 shows a block diagram of an electronic device provided according to an embodiment of the invention;

fig. 5 shows a flowchart of a display processing method according to an embodiment of the present invention.

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the accompanying drawings. This application may, however, be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

In the description of the present application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments. "and/or" herein is a description of an association relationship of an associated object, meaning that there may be three relationships, e.g., a and/or B, which may represent: a exists alone, A and B exist together, and B exists alone. "plurality" means two or more than two. In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.

In addition, in the drawings, the same reference numerals denote the same or similar structures, and thus repeated descriptions thereof will be omitted, that is, each part in the present specification is described in a combined manner of juxtaposition and progressive, each part is mainly described as a difference from other parts, and the same or similar parts are referred to each other.

In SoC (System on Chip) of a display System such as a television, a display processing subsystem is a very important module, and is composed of a plurality of sub-IP cores, including IP cores such as input signal detection, signal clipping, image quality processing, and signal output display. Input signal detection detects DTV, HDMI, CVBS and locally played high definition video in real time, and simultaneously performs real-time image quality processing on each frame of the signal to be received, such as Dolby vision (improving image effect by improving brightness and extending dynamic range), MEMC, DNR, and 3 DNR. Finally, the video signal and OSD (on-screen display) of each layer are mixed and output, and the system is not only abnormally complex, but also has very high real-time requirement. Taking the image quality processing mode of dolby vision as an example, it requires that each frame needs to calculate a set of parameters according to related algorithm and set the parameters on the corresponding image quality processing IP core, because the main chip of the television needs that the display processing of each frame must be effective in the inactive (active) interval of the vsync signal, if the system load is not high enough, the dolby vision processing can be completed barely, if the system load is heavy, the calculated parameters are not set on the image quality processing IP core, and an abnormality occurs in a certain frame of video. This not only affects dolby's FOV authentication, but also affects the visual experience of the television user.

In view of the above, the embodiments of the present application provide a new display processing subsystem, when performing image quality processing of an image to be displayed, a new hardware structure is added between a CPU (central processing unit) and an image quality processing IP core to assist in transmitting image quality configuration parameters from the CPU to the image quality processing IP core, by using this hardware mode, the setting of the image quality configuration parameters in a large scale is actively performed in an inactive section of a vertical synchronization signal, so that the load of the CPU and the complexity of software are greatly reduced, the processing efficiency, stability and robustness of the system can be improved, and compared with the mode of performing parameter configuration one by one in the inactive section of the vertical synchronization signal in the related art, the disclosed batch configuration scheme has higher efficiency, shorter required configuration time, can accurately perform setting of the required image quality configuration parameters in the inactive section of the vertical synchronization signal, effectively avoid image tearing, and is helpful for improving the image display quality.

In this embodiment, as shown in fig. 1 and 2, the display processing subsystem 302 includes: a storage module 102, a direct register access module 103, and an image quality processing module 104. The memory module 102 is communicatively connected to the CPU 101, the direct register access module 103 is communicatively connected to the memory module 102, and the image quality processing module 104 is communicatively connected to the direct register access module 103.

The storage module 102 is configured to receive and store the image quality configuration parameters in real time. The direct register access module 103 is configured to read a plurality of image quality configuration parameters from the storage module according to preset read configuration information, and output the image quality configuration parameters to a plurality of registers in batch. The image quality processing module 104 is configured to perform image quality processing on an image to be displayed in response to the batch arrangement of the plurality of registers by the direct register access module 103.

The image quality configuration parameters are obtained by the CPU 101 by calculation from the received video data using a correlation algorithm, for example. In some examples, the CPU 101 receives decoded video data sent by the video decoder frame by frame, performs preprocessing calculation on each frame of received video data in real time by using a related image quality processing algorithm (for example, the dolby algorithm is adopted when dolby view processing is performed), so as to obtain image quality configuration parameters corresponding to each frame of video data, and after writing the image quality configuration parameters corresponding to each frame of video data into the storage module 102 frame by frame, the storage module 102 stores the image quality configuration parameters corresponding to each register according to a preset format. The image quality configuration parameters corresponding to each frame of video data comprise a plurality of parameter data for configuring a plurality of registers.

In some examples, the reading the configuration information includes: the start read address and the number of image quality configuration parameters to be read. When the direct register access module 103 reads the image quality configuration parameters from the storage module 102, the image quality configuration parameters are read from the storage module 102 based on the initial reading address in the reading configuration information, and the current reading is stopped after the preset number of image quality configuration parameters are read, so that a plurality of image quality configuration parameters corresponding to each frame of video data can be continuously obtained, the method is simple and convenient, the rapid reading of the image quality configuration parameters corresponding to one frame of video data can be realized, and the direct register access module 103 can repeatedly read the image quality configuration parameters corresponding to each frame of video data frame by frame.

In other examples, the reading the configuration information includes: a start read address and a stop read address. When the direct register access module 103 reads the image quality configuration parameters from the storage module 102, the image quality configuration parameters are read from the storage module 102 based on the start reading address in the reading configuration information, and the current reading is stopped based on the end reading address in the reading configuration information, so that a plurality of image quality configuration parameters corresponding to each frame of video data can also be continuously obtained, and the direct register access module 103 repeats the process to read a plurality of image quality configuration parameters corresponding to each frame of video data frame by frame.

Illustratively, the direct register access module 103 is, for example, a reg_dma IP core.

In this embodiment, the direct register access module 103 identifies the format of the plurality of image quality configuration parameters read each time, and performs batch processing on the identified read data with the predetermined format, thereby implementing batch output of the plurality of image quality configuration parameters. In specific implementation, the direct register access module 103 reads the information stored in the storage module 102 according to the rising edge of the current vsync signal in the non-display interval of each frame, performs format recognition on the read information, combines the plurality of image quality configuration parameters with the predetermined format, and performs batch processing, so as to batch output the plurality of image quality configuration parameters with the predetermined format to a plurality of registers corresponding to the image quality processing module 104, and batch update of data in the plurality of registers is implemented, thereby completing batch configuration of the plurality of registers.

When the plurality of registers are configured in batch, the image quality processing module 104 is configured, so that the image quality processing module 104 can convert the image data to be displayed of the current frame into a corresponding image quality format, such as dolby view format, according to the configuration parameters, thereby achieving the purpose of improving the image quality.

It can be understood that, compared with the manner that the CPU directly writes the plurality of image quality configuration parameters processed in advance into the plurality of registers corresponding to the image quality processing module 104, in the related scheme, the storage module 102 and the direct register access module 103 are provided in the display processing subsystem 302, so that in each frame, when the configuration of the plurality of registers needs to be updated, only one writing action is required, the configuration update of the plurality of registers can be completed at one time, and the efficiency of the system is greatly improved. Meanwhile, the direct register access module 103 is used for replacing a CPU to perform writing work on a relevant register of the image quality processing module, so that the load of the CPU can be greatly reduced, the advantage of a system bus can be fully utilized, the system can operate more efficiently, and the time delay of the system is improved.

In some application scenarios, the load of the system is smaller than a specific threshold, and at this time, referring to fig. 1, the storage module 102 can meet the transmission requirement of the normal image quality configuration parameters even if only one storage unit is provided, and the storage unit receives a plurality of image quality configuration parameters frame by frame to store the view configuration parameters.

In some application scenarios, when the load of the system is greater than or equal to a specific threshold, referring to fig. 2, the storage module 102 includes a plurality of storage units (for example, including storage unit 0, storage unit 1, storage units 2, …, and storage units N, N is greater than or equal to 2), where the plurality of storage units store the image quality configuration parameters of the multiframe in an asynchronous manner. Meanwhile, the plurality of memory cells are configured to perform read-write management on the stored image quality configuration parameters of the plurality of frames in a first-in-first-out (FIFO) manner.

It can be understood that when the load of the system is relatively high or very high (for example, greater than or equal to a specific threshold value), the vsync signal may not be able to be pulled up yet, and then the video decoder sends new video frame information, at this time, by adopting the scheme shown in fig. 2 of the present application, that is, by setting a plurality of storage units in the storage module and reading in an asynchronous manner, even when the video decoder sends multiple frames of video data in advance, the system firmware (firmware) can also write the multiple frames of video data into the multiple storage units through the CPU 101, and cooperate with the read-write management manner of the multiple storage units by adopting the first-in-first-out (FIFO) method, so that when the rising edge of the vsync signal arrives, the direct register access module 103 can also read multiple image quality configuration parameters corresponding to each frame of video data stored in each storage unit, thereby not only ensuring that each frame of information can be processed asynchronously, but also ensuring the sequence of each frame, and thus effectively improving the stability and robustness of the system, and avoiding the occurrence of frame loss.

In a further preferred example, as shown in fig. 2, the display processing subsystem 302 further includes: and a control module 105, wherein the control module 105 is used for adjusting the number of the storage units participating in the work in the storage module 105 according to the load size of the system. It can be understood that in these examples, the requirements of the storage unit in the application scenarios of low load and high load can be simultaneously considered, the system can be switched between the high load and the low load in order, the frame loss can not occur, and the application range is wider.

Optionally, in some examples, the storage module 102 is a memory provided separately in the display subsystem; in other examples, the memory module 102 is native memory in a shared system on chip.

In summary, embodiments of the present invention have the following advantages:

1. the direct register access module 103 is used in the display processing subsystem to write the image quality configuration parameters into a plurality of registers in batches by matching with the storage module 102, so that CPU (central processing unit) intervention is not needed, the load of the CPU is reduced, and the time delay of the system is improved;

2. the asynchronous storage processing mode is adopted, so that the problem that a video decoder is not synchronous with a display processing subsystem is solved, and the stability of the system is enhanced;

3. when a plurality of storage units exist in the storage module 102, the storage units adopt a first-in first-out management mode, so that not only is no frame dropping ensured, but also the reading sequence of a plurality of image quality configuration parameters corresponding to each frame of video data is ensured, and the robustness of the system is enhanced;

4. the scheme of the application can be used for a common television main chip system platform and has strong portability.

Further, the embodiment of the present application further provides a display processing method, which is applicable to the display processing subsystem 302 described in any embodiment of the present application, as shown in fig. 5, and the method includes:

step 501, writing the calculated image quality configuration parameters into a storage module frame by frame.

Step 502, a plurality of image quality configuration parameters corresponding to each frame are read from the storage module by using the direct register access module according to preset reading configuration information, and are output to a plurality of registers in batch.

In step 503, in response to the batch configuration of the plurality of registers by the direct register access module, image quality processing is performed on the image to be displayed.

It should be noted that, the specific implementation of each step in the above-described display processing method may refer to the foregoing embodiment of the display processing subsystem 302, which is not described herein again.

Further, the embodiment of the present application further provides a system-on-chip 300, as shown in fig. 3, where the system-on-chip 300 includes: a processor 301, a DSS (Display Sub-System) 302, a ROM (read only memory) 303, a RAM (random access memory) 304, a bus 305, and an I/O interface 306. The processor 301, DSS 302, ROM 303, RAM 304 and I/O interface 306 are connected to each other by a bus 305.

The processor 301 is, for example, the CPU 101 mentioned in any of the embodiments of the present application, and can perform various appropriate actions and processes according to a program stored in the ROM 303 or a program loaded from the storage section 402 into the RAM 304. Processor 301 may include, for example, a CPU 101, an instruction set processor and/or an associated chipset and/or special purpose microprocessor (e.g., an Application Specific Integrated Circuit (ASIC)), or the like, as referred to in any of the embodiments herein. Processor 301 may also include on-board memory for caching purposes. The processor 301 may comprise a single processing unit or a plurality of processing units for performing different actions in a software processing mechanism involved in the flow of the display processing method according to an embodiment of the present disclosure.

DSS 302 may refer to the aforementioned embodiments of display processing subsystem 302, and are not described in detail herein.

In the RAM 304, various programs and data required for the operation of the system level chip 300 are stored. The processor 301 performs corresponding various operations by executing programs in the ROM 303 and/or the RAM 304. Note that the above-described programs may also be stored in one or more memories other than the ROM 303 and the RAM 304. The processor 301 may also perform corresponding various operations by executing programs stored in one or more memories.

Further, the embodiment of the application further provides an electronic device 400, where the electronic device 400 is, for example, a television, a computer, a mobile phone, a tablet ammeter, a wearable device, and the like. As shown in fig. 4, the electronic device includes: the system-on-chip 300, the output portion 401, and one or more of the input portion 307, the storage portion 402, the communication portion 403, and the drive 404 as described in any of the embodiments of the present application. Wherein the output part 402, and one or more of the input part 401, the storage part 403, the communication part 404, and the driver 405 are connected to the system-on-chip 300 through an I/O interface of the system-on-chip 300.

The output section 402 includes components such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, and speakers, and the like. The input section 401 includes a keyboard, a mouse, a remote controller, and the like; the storage section 403 includes a hard disk or the like; the communication section 404 includes a network interface card such as a LAN card, a modem, or the like. The communication section 404 performs communication processing via a network such as the internet. The drive 405 can mount a removable medium such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like as needed so that a computer program read out therefrom is mounted into the storage section 403 as needed.

Finally, it should be noted that: it is apparent that the above examples are only examples for clearly illustrating the present application and are not limiting to the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are intended to be within the scope of the present application.

Claims (10)

1. A display processing subsystem, comprising:

the storage module is used for receiving and storing the image quality configuration parameters;

the direct register access module is in communication connection with the storage module, and is used for reading a plurality of image quality configuration parameters from the storage module according to preset reading configuration information and outputting the image quality configuration parameters to a plurality of registers in batches;

and the image quality processing module is in communication connection with the direct register access module and is used for responding to the batch configuration of the plurality of registers by the direct register access module and processing the image quality of the image to be displayed.

2. The display processing subsystem of claim 1, wherein the memory module comprises a memory unit that receives and stores a plurality of the image quality configuration parameters on a frame-by-frame basis.

3. The display processing subsystem of claim 1, wherein the storage module comprises a plurality of storage units that store the image quality configuration parameters for a plurality of frames in an asynchronous manner.

4. A display processing subsystem according to claim 3, wherein a plurality of said storage units are configured to read-write manage said image quality configuration parameters of stored multi-frames in a first-in-first-out manner.

5. The display processing subsystem of claim 1, wherein the direct register access module is further configured to format-identify the plurality of image quality configuration parameters read, and implement a batch output by batch processing of the plurality of image quality configuration parameters identified as having a predetermined format.

6. The display processing subsystem of claim 1, wherein the direct register access module outputs the read plurality of image quality configuration parameters to a plurality of registers in batches during a non-display interval of each frame to complete batch configuration of the plurality of registers.

7. The display processing subsystem of claim 3 or 4, wherein the display processing subsystem further comprises:

and the control module is used for adjusting the number of the storage units participating in the work in the storage module according to the load size of the system.

8. A system-on-chip, comprising: the display processing subsystem of any of claims 1-7.

9. An electronic device, comprising: the system-on-chip of claim 8.

10. A display processing method, comprising:

writing the calculated image quality configuration parameters into a storage module frame by frame;

a direct register access module is utilized to read a plurality of image quality configuration parameters corresponding to each frame from the storage module according to preset reading configuration information, and the image quality configuration parameters are output to a plurality of registers in batches;

and responding to batch configuration of the plurality of registers by the direct register access module, and performing image quality processing on the image to be displayed.