CN117498871B - Exponential DAC circuit for automatic optical power control - Google Patents
Exponential DAC circuit for automatic optical power control Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/50—Transmitters
- H04B10/564—Power control
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- H—ELECTRICITY
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- H03M1/66—Digital/analogue converters
Abstract
The invention discloses an exponential DAC circuit for automatic optical power control, which comprises a complementary current generating circuit, a first current proportion superposition circuit, a second current proportion superposition circuit, a current multiplication output circuit and a logic circuit, wherein the complementary current generating circuit is connected with the first current proportion superposition circuit; the complementary current generating circuit processes the input unit current to generate a current I A And current I B The method comprises the steps of carrying out a first treatment on the surface of the First current proportion superposition circuit pair current I A And current I B The current I is generated by correspondingly proportional conversion C And current I D The method comprises the steps of carrying out a first treatment on the surface of the Second current proportion superposition circuit pair current I C And current I D The conversion is correspondingly and proportionally carried out, and then the conversion result is summed to obtain the current I E The method comprises the steps of carrying out a first treatment on the surface of the Current multiplication output circuit pair current I E Amplifying to obtain an output current. The invention can reduce the chip area, ensure that the transmitting chain can still accurately set the driving output power when the light power is low, and obviously improve the working range of the chip and the stability of the signal light power.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to an exponential DAC circuit for automatic optical power control.
Background
In the optical module, the signal transmitting path Tx link and the signal receiving path Rx link are combined, so that the integration level of the module, the reliability of the system and the debugging performance are improved. In the Tx link, a monitor photodiode (Monitor Photodiode, MPD) monitors the backlight of the laser, generates photocurrent related to the average optical power of the signal, and controls the ibasi current of the Tx link through an automatic power control (Automatic Power Control, APC) loop to eliminate the effect of the average optical power variation of the laser due to temperature and aging.
The DAC circuit is used as a module for converting digital codes into currents, the performance of the DAC circuit plays a crucial role in the performance of automatic control of optical power, and in the system application of the optical module, the requirements of a transmission path Tx link on the DAC circuit include large current conversion range, high output current precision, small overall power consumption and the like, so that the architecture design of the DAC circuit based on the core indexes becomes particularly difficult.
Disclosure of Invention
The technical problems to be solved are as follows: the invention provides an exponential DAC circuit for automatic optical power control, which is characterized in that digital control current is used for complementation and corresponding coefficient superposition is carried out, so that exponential current can be generated in an automatic optical power control loop, the chip area is reduced, meanwhile, the driving output power of a transmitting link can still be accurately set at low optical power, and the working range of the chip and the stability of signal optical power are obviously improved.
The technical scheme is as follows:
an exponential DAC circuit for automatic optical power control, the exponential DAC circuit comprising a complementary current generating circuit, a first current proportion superimposing circuit, a second current proportion superimposing circuit, a current multiplying output circuit, and a logic circuit;
the logic circuit is respectively connected with the complementary current generating circuit, the first current proportion superposition circuit, the second current proportion superposition circuit and the current multiplication output circuit and is used for obtaining control signals of the complementary current generating circuit, the first current proportion superposition circuit, the second current proportion superposition circuit and the current multiplication output circuit after performing logic conversion treatment on the control digital code APCDAC [7:0] of the exponential DAC;
the complementary current generating circuit generates a unit current I UNIT Processing to generate a pair of complementary currents: current I A And current I B ；
The first current proportion superposition circuit comprises a first current mirror unit and a second current mirror unit which are mutually independent, and the first current mirror unit and the second current mirror unit respectively aim at current I A And current I B The current I is generated by correspondingly proportional conversion C And current I D ；
The second current proportion superposition circuit comprises a third current mirror unit and a fourth current mirror unit which are mutually connected, and the second current proportion superposition circuit adopts the third current mirror unit and the fourth current mirror unit to respectively pair the current I C And current I D After corresponding proportional conversion, the conversion results of the two are summed to obtain a current I E ；
The current multiplication output circuit multiplies the current I E Amplified by a corresponding multiple to obtain an output current I OUT 。
Further, the complementary current generating circuit includes a transistor (PM 1), a transistor (PM 2), a transistor (PM 3), a transistor (PM 4), a transistor (PM 5), a transistor (PM 6), a transistor (PM 7), a transistor (PM 8), a transistor (PM 9), a transistor (PM 10), and a transistor (PM 11), a transistor (PM 12) constituting a current mirror structure, and a demultiplexer (DEMUX 1), a demultiplexer (DEMUX 2), a demultiplexer (DEMUX 3), a demultiplexer (DEMUX 4), and a demultiplexer (DEMUX 5) constituting a selection path;
the collector of the transistor (PM 1) is connected with the emitter of the transistor (PM 2), the emitter of the transistor (PM 1) is respectively connected with the emitters of the transistor (PM 3), the transistor (PM 5), the transistor (PM 7), the transistor (PM 9) and the transistor (PM 11), and the base of the transistor (PM 1) is respectively connected with the bases of the transistor (PM 3), the transistor (PM 5), the transistor (PM 7), the transistor (PM 9) and the transistor (PM 11) and the collector of the transistor; the base of the transistor (PM 2) is respectively connected with the bases and the collectors of the transistor (PM 4), the transistor (PM 6), the transistor (PM 8), the transistor (PM 10) and the transistor (PM 12); the emitters of the transistors (PM 4, PM6, PM8, PM10 and PM 12) are respectively connected with the collectors of the transistors (PM 3, PM5, PM7, PM9 and PM 11); the collectors of the transistor (PM 4), the transistor (PM 6), the transistor (PM 8), the transistor (PM 10) and the transistor (PM 12) are respectively connected with the input ends of the demultiplexer (DEMUX 1), the demultiplexer (DEMUX 2), the demultiplexer (DEMUX 3), the demultiplexer (DEMUX 4) and the demultiplexer (DEMUX 5);
The aspect ratio of the transistor (PM 3) and the transistor (PM 4) is 8 times that of the transistor (PM 1) and the transistor (PM 2), respectively; the aspect ratio of the transistor (PM 5) and the transistor (PM 6) is 4 times the aspect ratio of the transistor (PM 1) and the transistor (PM 2), respectively; the aspect ratio of the transistor (PM 7) and the transistor (PM 8) is 2 times the aspect ratio of the transistor (PM 1) and the transistor (PM 2), respectively; the aspect ratio of the transistor (PM 9) and the transistor (PM 10) is equal to the aspect ratio of the transistor (PM 1) and the transistor (PM 2), respectively; the aspect ratio of the transistor (PM 11) and the transistor (PM 12) is equal to the aspect ratio of the transistor (PM 1) and the transistor (PM 2), respectively; the ratio of the width to length ratio of the transistors is equal to the ratio of the current replications of each branch in the current mirror;
the demultiplexer (DEMUX 1), the demultiplexer (DEMUX 2), the demultiplexer (DEMUX 3), the demultiplexer (DEMUX 4) and the demultiplexer (DEMUX 5) are respectively controlled by control signals (SE 1[3 ]]) Control signal (SE 1[2 ]]) Control signal (SE 1[1 ]]) Control signal (SE 1[0 ]]) Control signal (SE 1[4 ]]) Controlling; when the control signals of the 5 demultiplexers are all at low level, the current copied by the current mirror flows out of the branch marked with 0 to generate a current I A The method comprises the steps of carrying out a first treatment on the surface of the When the control signals of the 5 demultiplexers are all high level, the current copied by the current mirror flows out of the branch marked with 1 to generate a current I B The method comprises the steps of carrying out a first treatment on the surface of the Output current I A And output current I B Is a complementary current, the sum of the currents of which is fixed as a unit current I UNIT Is 16 times as large as that of (a);
the control signals (SE 1[3 ]), the control signals (SE 1[2 ]), the control signals (SE 1[1 ]), the control signals (SE 1[0 ]), and the control signals (SE 1[4 ]) are obtained by logic conversion of DAC register control signals APCDAC [4] -APCDAC [0 ].
Further, the first current proportion superimposing circuit includes a transistor (NM 1), a transistor (NM 2), a transistor (NM 3), a transistor (NM 4), a transistor (NM 5), a transistor (NM 6), a transistor (NM 7), a transistor (NM 8) constituting the first current mirror unit, and a transistor (NM 9), a transistor (NM 10), a transistor (NM 11), a transistor (NM 12), a transistor (NM 13), a transistor (NM 14), a transistor (NM 15) constituting the second current mirror unit;
the base of the transistor (NM 1) is respectively connected with the bases and the collectors of the transistor (NM 3) and the transistor (NM 5), and the collectors of the transistor (NM 1), the body transistor (NM 3) and the transistor (NM 5) are respectively connected with the emitters of the transistor (NM 2), the transistor (NM 4) and the transistor (NM 6);
The emitters of the transistor (NM 1), the transistor (NM 3) and the transistor (NM 5) are all grounded; the base of the transistor (NM 2) is respectively connected with the bases and the collectors of the transistor (NM 4) and the transistor (NM 5), the emitter of the transistor (NM 2) is connected with the collector of the transistor (NM 7), the collector of the transistor (NM 4) is connected with the emitters of the transistor (NM 7) and the transistor (NM 8), and the collector of the transistor (NM 6) is connected with the collector of the transistor (NM 8);
the transistors (NM 1, NM2, NM3, NM4, NM5 and NM 6) form a first current mirror structure, and the transistors (NM 7, NM 8) are used as switches of the first current mirror structure and are controlled by a control signal (SE 2[0 ]) and a control signal (SE 2[1 ]) which are respectively input to the bases of the transistors (NM 7, NM 8);
the bases of the transistors (NM 9) are respectively connected with the bases of the transistors (NM 11) and (NM 13), the collectors of the transistors (NM 9), the transistors (NM 11) and the transistors (NM 13) are respectively connected with the emitters of the transistors (NM 10), the transistors (NM 12) and the transistors (NM 14), and the emitters of the transistors (NM 11) and the transistors (NM 13) are grounded; the collectors of the transistors (NM 14, NM 15) are connected with each other;
The base of the transistor (NM 10) is respectively connected with the bases and the collectors of the transistor (NM 12) and the transistor (NM 14), and the collector of the transistor (NM 12) is connected with the emitter of the transistor (NM 15); the transistor (NM 9), the transistor (NM 10), the transistor (NM 11), the transistor (NM 12), the transistor (NM 13) and the transistor (NM 14) form a second current mirror structure, and the transistor (NM 15) is used as a switch of the second current mirror structure and is controlled by a control signal (SE 2[2 ]);
the aspect ratio of the transistor (NM 3) and the transistor (NM 4) is equal to the aspect ratio of the transistor (NM 1) and the transistor (NM 2), respectively; the aspect ratio of the transistor (NM 5) and the transistor (NM 6) is equal to the aspect ratio of the transistor (NM 1) and the transistor (NM 2), respectively; the aspect ratio of the transistor (NM 11) and the transistor (NM 12) is five seventh of the aspect ratio of the transistor (NM 9) and the transistor (NM 10), respectively; the aspect ratio of the transistor (NM 13) and the transistor (NM 14) is five seventh of the aspect ratio of the transistor (NM 9) and the transistor (NM 10), respectively;
the current I A Through the collector input of the transistor (NM 2), the current I is output through the collector of the transistor (NM 6) after corresponding proportional conversion C The method comprises the steps of carrying out a first treatment on the surface of the The current I B Through the collector input of the transistor (NM 10), the current I is output through the collector of the transistor (NM 14) after corresponding proportional conversion D ；
The control signals (SE 2[0 ]), the control signals (SE 2[1 ]), and the control signals (SE 2[2 ]) are obtained by logic conversion of DAC register control signals APCDAC [7] -APCDAC [4 ].
Further, the second current proportion superimposing circuit includes a transistor (PM 13), a transistor (PM 14), a transistor (PM 15), a transistor (PM 16), a transistor (PM 17), a transistor (PM 18), a transistor (PM 19), a transistor (PM 20), a transistor (PM 21), a transistor (PM 22), a transistor (PM 23), a transistor (PM 24), a transistor (PM 25), a transistor (PM 26), a transistor (PM 27), a transistor (PM 28), a transistor (PM 29), a transistor (PM 30), a transistor (PM 31), a transistor (PM 32), a transistor (PM 33), and a transistor (PM 34);
the base of the transistor (PM 13) is respectively connected with the bases of the transistor (PM 15), the transistor (PM 17) and the transistor (PM 19) and the collector of the transistor; the emitters of the transistors (PM 13, PM15, PM17 and PM 19) are connected with each other; the collectors of the transistors (PM 13, PM15, PM17 and PM 19) are respectively connected with the emitters of the transistors (PM 14, PM16, PM18 and PM 20);
The base of the transistor (PM 14) is respectively connected with the bases of the transistor (PM 16), the transistor (PM 18) and the transistor (PM 20) and the collector of the transistor; the collector of the transistor (PM 14) is connected with the collectors of the transistors (PM 29) and (PM 30), respectively; the collector of the transistor (PM 16) is connected to the emitter of the transistor (PM 29); the collector of the transistor (PM 18) is connected to the emitter of the transistor (PM 30) and the collector of the transistor (PM 31), respectively; the collector of the transistor (PM 20) is connected to the emitters of the transistor (PM 31) and the transistor (PM 32);
the base of the transistor (PM 27) is respectively connected with the bases of the transistor (PM 25), the transistor (PM 23) and the transistor (PM 21) and the collector of the transistor; the emitters of the transistors (PM 27, PM25, PM23 and PM 21) are connected with each other; the collectors of the transistors (PM 27, PM25, PM23 and PM 21) are respectively connected with the emitters of the transistors (PM 28, PM26, PM24 and PM 22);
The base of the transistor (PM 28) is respectively connected with the bases of the transistor (PM 26), the transistor (PM 24) and the transistor (PM 22) and the collector of the transistor; the collector of the transistor (PM 28) is connected with the collectors of the transistor (PM 33) and the transistor (PM 34), respectively; the collector of the transistor (PM 26) is connected to the emitter of the transistor (PM 34); the collector of the transistor (PM 24) is respectively connected with the collector of the transistor (PM 32) and the emitter of the transistor (PM 33); the collector of the transistor (PM 22) is connected to the emitter of the transistor (PM 32);
the aspect ratio of the transistor (PM 15) and the transistor (PM 16) is half the aspect ratio of the transistor (PM 13) and the transistor (PM 14), respectively; the aspect ratio of the transistor (PM 17) and the transistor (PM 18) is half the aspect ratio of the transistor (PM 13) and the transistor (PM 14), respectively; the aspect ratio of the transistor (PM 19) and the transistor (PM 20) is half the aspect ratio of the transistor (PM 13) and the transistor (PM 14), respectively; the aspect ratio of the transistor (PM 21) and the transistor (PM 22) is half the aspect ratio of the transistor (PM 27) and the transistor (PM 28), respectively; the aspect ratio of the transistor (PM 23) and the transistor (PM 24) is half the aspect ratio of the transistor (PM 27) and the transistor (PM 28), respectively; the aspect ratio of the transistor (PM 25) and the transistor (PM 26) is half the aspect ratio of the transistor (PM 27) and the transistor (PM 28), respectively;
The bases of the transistors (PM 29, PM30, PM31, PM32, PM33 and PM 34) are respectively input with a control signal (SE 3[0]]) Control signal (SE 3[0]]) Control signal (SE 3[1]]) Control signal (SE 3[3]]) Control signal (SE 3[2]]) Control signal (SE 3[2]]) The switch is used as a switch; current I C And current I D The current I is obtained by summing the corresponding proportion change through the collector of the transistor (PM 14) and the collector input of the transistor (PM 28) E Via the collector output of the transistor (PM 20);
the control signals (SE 3[0 ]), the control signals (SE 3[1 ]), the control signals (SE 3[3 ]), the control signals (SE 3[2 ]), and the control signals (SE 3[2 ]) are obtained by logic conversion of DAC register control signals APCDAC [7] -APCDAC [4 ].
Further, the current multiplication output circuit includes a transistor (NM 16), a transistor (NM 17), a transistor (NM 18), a transistor (NM 19), a transistor (NM 20), a transistor (NM 21), a transistor (NM 22), a transistor (NM 23), a transistor (NM 24), a transistor (NM 25), a transistor (NM 26), a transistor (NM 27), a transistor (NM 28), a transistor (NM 29), a transistor (NM 30), a transistor (NM 31), a transistor (NM 32);
The base of the transistor (NM 16) is respectively connected with the bases of the transistor (NM 18), the transistor (NM 20), the transistor (NM 22), the transistor (NM 24), the transistor (NM 26) and the collector of the transistor; the emitters of the transistor (NM 16), the transistor (NM 18), the transistor (NM 20), the transistor (NM 22), the transistor (NM 24) and the transistor (NM 26) are grounded; the collectors of the transistors (NM 16), (NM 18), (NM 20), (NM 22), (NM 24) and (NM 26) are respectively connected with the emitters of the transistors (NM 17), (NM 19), (NM 21), (NM 23), (NM 25) and (NM 27);
the base of the transistor (NM 17) is respectively connected with the bases of the transistor (NM 19), the transistor (NM 21), the transistor (NM 23), the transistor (NM 25) and the transistor (NM 27) and the collector of the transistor; the collectors of the transistors (NM 19), (NM 21), (NM 23), (NM 25) and (NM 27) are respectively connected with the emitters of the transistors (NM 28), (NM 29), (NM 30), (NM 31) and (NM 32); the collectors of the transistor (NM 28), the transistor (NM 29), the transistor (NM 30), the transistor (NM 31) and the transistor (NM 32) are connected with each other; the bases of the transistor (NM 28), the transistor (NM 29), the transistor (NM 30), the transistor (NM 31) and the transistor (NM 32) are respectively input with a control signal (SE 4[0 ]), a control signal (SE 4[1 ]), a control signal (SE 4[2 ]), a control signal (SE 4[3 ]), and a control signal (SE 4[4 ]);
The aspect ratio of the transistor (NM 18) and the transistor (NM 19) is half the aspect ratio of the transistor (NM 16) and the transistor (NM 17), respectively; the aspect ratio of the transistor (NM 20) and the transistor (NM 21) is equal to the aspect ratio of the transistor (NM 16) and the transistor (NM 17), respectively; the aspect ratio of the transistor (NM 22) and the transistor (NM 23) is twice the aspect ratio of the transistor (NM 16) and the transistor (NM 17), respectively; the aspect ratio of the transistor (NM 24) and the transistor (NM 25) is four times the aspect ratio of the transistor (NM 16) and the transistor (NM 17), respectively; the aspect ratio of the transistor (NM 26) and the transistor (NM 27) is eight times the aspect ratio of the transistor (NM 16) and the transistor (NM 17), respectively;
the current I E Output current I via collector input of transistor (NM 17) and via collector of transistor (NM 28) OUT ；
The control signals (SE 4[0 ]), the control signal (SE 4[1 ]), the control signal (SE 4[2 ]), the control signal (SE 4[3 ]), and the control signal (SE 4[4 ]) are obtained by logic conversion of DAC register control signals APCDAC [7] to APCDAC [5 ].
The beneficial effects are that:
the exponential DAC circuit for automatic optical power control of the invention can generate exponential current in the automatic optical power control loop by complementation of digital control current and corresponding coefficient superposition, and can ensure that the transmitting link can still accurately set driving output power when the optical power is low while reducing the chip area, thereby remarkably improving the working range of the chip and the stability of signal optical power.
Drawings
FIG. 1 is a schematic diagram of an exponential DAC circuit for automatic optical power control according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a logic control circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a complementary current generating circuit according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of a first current proportional-plus circuit according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a second current proportional-plus-add circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a current multiplying output circuit according to an embodiment of the present invention;
FIG. 7 shows the complementary current I according to an embodiment of the present invention A And complementary current I B A simulation result schematic diagram;
FIG. 8 is a graph showing the current complementary and proportional superposition current I according to an embodiment of the present invention E A simulation result schematic diagram;
FIG. 9 shows the present inventionOutput current I of the embodiment OUT A waveform schematic;
FIG. 10 is a schematic diagram showing the logic transformation relationship of control signals SE1[4] to SE1[0] according to the embodiment of the present invention;
FIG. 11 is a schematic diagram showing the logic transformation relationship of control signals SE2[2] to SE2[0] according to the embodiment of the present invention;
FIG. 12 is a diagram showing the logic transformation relationship of control signals SE3[3] to SE3[0] according to the embodiment of the present invention;
FIG. 13 is a schematic diagram showing the logic transformation relationship of the control signals SE4[4] to SE4[0] according to the embodiment of the invention.
Detailed Description
The following examples will provide those skilled in the art with a more complete understanding of the invention, but are not intended to limit the invention in any way.
The embodiment of the invention discloses an exponential DAC circuit for automatic optical power control, an implementation block diagram is shown in figure 1, and a DAC main module consists of a complementary current generating circuit, a first current proportion superposition circuit, a second current proportion superposition circuit, a current multiplication output circuit and a logic circuit. Unit current I UNIT Generating a pair of complementary currents through the complementary current generating circuit: current I A And current I B . The two currents are respectively sent to two submodules in the first current proportion superposition circuit, and the current I is obtained after corresponding proportion conversion C And current I D . The two currents are respectively sent to two sub-modules in the second current proportion superposition circuit, and are subjected to corresponding proportion conversion and summation to obtain a current I E . Current I E Sending the output current into a current multiplication output circuit, and obtaining output current I after corresponding multiplication amplification OUT . Digital code APCDAC [7:0 ] of control of exponential DAC]And after corresponding processing by the logic circuit, the control signal of each sub-module is obtained. Wherein the control signal SE1[4 ] ]~SE1[0]By DAC register control signal APCDAC [4 ]]~APCDAC[0]The corresponding relation is obtained through logic transformation and is shown in figure 10; control signal SE2[2 ]]~SE2[0]By DAC register control signal APCDAC [7 ]]~APCDAC[4]The corresponding relation is obtained through logic transformation and is shown in figure 11; control signal SE3[3 ]]~SE3[0]By DAC register control signal APCDAC [7 ]]~APCDAC[4]The corresponding relation is obtained through logic transformation and is shown in figure 12; control signal SE4[4 ]]~SE4[0]By DAC register control signal APCDAC [7 ]]~APCDAC[5]The corresponding relationship is shown in fig. 13 after logic transformation. Four sets of control signals SE1[4 ]]~SE1[0]、SE2[2]~SE2[0]、SE3[3]~SE3[0]And SE4[4 ]]~SE4[0]All output simultaneously without any sequence relationship, wherein the logic circuits are shown in figure 2. The logic circuit composed of the NOT gates INV1 to INV2 and the XOR gates XOR1 to XOR gate XOR4 together controls the DAC register control signal APCDAC [4 ]]~APCDAC[0]Logic transformation results in control signal SE1[4 ]]~SE1[0]The method comprises the steps of carrying out a first treatment on the surface of the The DAC register control signal APCDAC [7 ] is provided by a logic circuit consisting of the NOT gates INV3 to INV12, OR gates OR1 to OR gate OR2, NOR gate NOR1 and NAND gates NAND1 to NAND5]~APCDAC[4]Logic transformation results in control signal SE2[2 ]]~SE2[0]And control signal SE3[3 ]]~SE2[0]The method comprises the steps of carrying out a first treatment on the surface of the The DAC register control signal APCDAC [7 ] is supplied by a logic circuit consisting of the NOT gates INV13 to INV20, NOR gates NOR2 to NOR gate NOR5 and NAND gates NAND6 to NAND9 ]~APCDAC[5]Logic transformation results in control signal SE4[4 ]]~SE4[0]。
The complementary current generating circuit is shown in fig. 3. Twelve transistors from the transistors PM1 to PM12 constitute a current mirror structure, and a unit current I UNIT And copying the branch current with corresponding proportion through a current mirror structure. Wherein the aspect ratio of the transistor PM3 and the transistor PM4 is 8 times the aspect ratio of the transistor PM1 and the transistor PM2, respectively; the aspect ratio of the transistor PM5 and the transistor PM6 is 4 times the aspect ratio of the transistor PM1 and the transistor PM2, respectively; the aspect ratio of the transistor PM7 and the transistor PM8 is 2 times the aspect ratio of the transistor PM1 and the transistor PM2, respectively; the aspect ratio of the transistor PM9 and the transistor PM10 is equal to the aspect ratio of the transistor PM1 and the transistor PM2, respectively; the aspect ratio of the transistor PM11 and the transistor PM12 is equal to the aspect ratio of the transistor PM1 and the transistor PM2, respectively. The ratio of the aspect ratios of the transistors is equal to the ratio of the current replicas of each branch in the current mirror. The five demultiplexers DEMUX1 to DEMUX5 constitute a selection path, respectively defined by control signals SE1[4 ]]~SE1[0]And (5) controlling. When the control signal SE1[4 ]]~SE1[0]At low level, the current copied by the current mirror flows out of the branch marked with 0;when the control signal SE1[4 ] ]~SE1[0]At a high level, the current copied by the current mirror flows from the branch marked 1. Control signal SE1[4 ]]~SE1[0]By DAC register control signal APCDAC [4 ]]~APCDAC[0]Obtained by logic transformation. The sum of the currents flowing from the branches marked 0 is the output current I A The sum of the currents flowing from the branch marked 1 is the output current I B . Output current I A And output current I B Is a complementary current, the sum of the currents of which is fixed as a unit current I UNIT Is 16 times as large as the above.
The first current ratio superimposing circuit is shown in fig. 4. Six transistors from the transistors NM1 to NM6 and six transistors from the transistors NM9 to NM14 respectively form two sets of current mirror structures. The output current I of the current mirror structure in FIG. 3 A And output current I B The branch current with corresponding proportion is copied through the two groups of current mirror structures respectively. Wherein the aspect ratio of the transistor NM3 and the transistor NM4 is equal to the aspect ratio of the transistor NM1 and the transistor NM2, respectively; the aspect ratio of the transistor NM5 and the transistor NM6 is equal to the aspect ratio of the transistor NM1 and the transistor NM2, respectively. The aspect ratio of the transistor NM11 and the transistor NM12 is five sevenths of the aspect ratio of the transistor NM9 and the transistor NM10, respectively; the aspect ratio of the transistor NM13 and the transistor NM14 is five sevenths of the aspect ratio of the transistor NM9 and the transistor NM10, respectively. Transistor NM7, transistor NM8 and transistor NM15 are used as switches, respectively controlled by control signals SE2[2 ] ]~SE2[0]And (5) controlling. Control signal SE2[2 ]]~SE2[0]By DAC register control signal APCDAC [7 ]]~APCDAC[4]Obtained by logic transformation.
The second current ratio superimposing circuit is shown in fig. 5. Eight transistors from the transistors PM13 to PM20 and eight transistors from the transistors PM21 to PM28 respectively constitute two sets of current mirror structures. The output current I of the current mirror structure in FIG. 4 C And output current I D The branch current with corresponding proportion is copied through the two groups of current mirror structures respectively. Wherein the aspect ratio of the transistor PM15 and the transistor PM16 is half the aspect ratio of the transistor PM13 and the transistor PM14, respectively; the aspect ratio of the transistor PM17 and the transistor PM18 is the transistor PM13 and the transistor P, respectivelyHalf of the aspect ratio of M14; the aspect ratio of the transistor PM19 and the transistor PM20 is half the aspect ratio of the transistor PM13 and the transistor PM14, respectively; the aspect ratio of the transistor PM21 and the transistor PM22 is half the aspect ratio of the transistor PM27 and the transistor PM28, respectively; the aspect ratio of the transistor PM23 and the transistor PM24 is half the aspect ratio of the transistor PM27 and the transistor PM28, respectively; the aspect ratio of the transistor PM25 and the transistor PM26 is half the aspect ratio of the transistor PM27 and the transistor PM28, respectively. Six transistors PM29 to PM34 are used as switches, respectively controlled by control signals SE3[3 ] ]~SE3[0]And (5) controlling. Control signal SE3[3 ]]~SE3[0]By DAC register control signal APCDAC [7 ]]~APCDAC[4]Obtained by logic transformation.
The current multiplication output circuit is shown in fig. 6. The transistors NM16 to NM27 constitute a current mirror structure in total of twelve transistors. The output current I of the current mirror structure in FIG. 5 E The corresponding proportion of the branch current is replicated through the current mirror structure in fig. 6. Wherein the aspect ratio of the transistor NM18 and the transistor NM19 is half of the aspect ratio of the transistor NM16 and the transistor NM17, respectively; the aspect ratio of the transistor NM20 and the transistor NM21 is equal to the aspect ratio of the transistor NM16 and the transistor NM17, respectively; the aspect ratio of the transistor NM22 and the transistor NM23 is twice that of the transistor NM16 and the transistor NM17, respectively; the width-to-length ratio of the transistor NM24 and the transistor NM25 is four times that of the transistor NM16 and the transistor NM17, respectively; the aspect ratio of the transistor NM26 and the transistor NM27 is eight times the aspect ratio of the transistor NM16 and the transistor NM17, respectively. Five transistors from the transistors NM28 to NM32 are used as switches, and are respectively controlled by a control signal SE4[0 ]]~SE4[4]And (5) controlling. Control signal SE4[4 ]]~SE4[0]By DAC register control signal APCDAC [7 ]]~APCDAC[5]Obtained by logic transformation.
Complementary current I A And I B The simulation results of (2) are shown in fig. 7. Current I of unit current IUNIT after complementary amplification and proportional superposition E The simulation results of (2) are shown in fig. 8. The output current I of the exponential DAC applied to automatic optical power control OUT The simulation results are shown in FIG. 9, where DAC register control signals APCDAC [7:0 ]]Changing from 00h to FFh, corresponding output currentI OUT Exhibiting an exponential increase. Current magnitude and DAC register control signals APCDAC [7:0 ]]The relational formula of (2) is: i OUT =I UNIT * 2 APCDAC/32 . The abscissa axis apcset_dac in fig. 7, 8 and 9 is a constant without unit obtained by converting the DAC register control signal.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the invention without departing from the principles thereof are intended to be within the scope of the invention as set forth in the following claims.
Claims (5)
1. An exponential DAC circuit for automatic optical power control, wherein the exponential DAC circuit comprises a complementary current generating circuit, a first current proportion superposition circuit, a second current proportion superposition circuit, a current multiplication output circuit and a logic circuit;
The logic circuit is respectively connected with the complementary current generating circuit, the first current proportion superposition circuit, the second current proportion superposition circuit and the current multiplication output circuit and is used for obtaining control signals of the complementary current generating circuit, the first current proportion superposition circuit, the second current proportion superposition circuit and the current multiplication output circuit after performing logic conversion treatment on the control digital code APCDAC [7:0] of the exponential DAC;
the complementary current generating circuit generates a unit current I UNIT Processing to generate a pair of complementary currents: current I A And current I B ；
The first current proportion superposition circuit comprises a first current mirror unit and a second current mirror unit which are mutually independent, and the first current mirror unit and the second current mirror unit respectively aim at current I A And current I B The current I is generated by correspondingly proportional conversion C And current I D ；
The second current proportion superposition circuit comprises a third current mirror unit and a fourth current mirror unit which are connected with each other, a second current proportion superposition circuitThe current proportion superposition circuit adopts a third current mirror unit and a fourth current mirror unit to respectively pair the current I C And current I D After corresponding proportional conversion, the conversion results of the two are summed to obtain a current I E ；
The current multiplication output circuit multiplies the current I E Amplified by a corresponding multiple to obtain an output current I OUT 。
2. The exponential DAC circuit for automatic optical power control according to claim 1, wherein the complementary current generating circuit comprises a transistor (PM 1), a transistor (PM 2), a transistor (PM 3), a transistor (PM 4), a transistor (PM 5), a transistor (PM 6), a transistor (PM 7), a transistor (PM 8), a transistor (PM 9), a transistor (PM 10) and a transistor (PM 11), a transistor (PM 12) constituting a current mirror structure, and a demultiplexer (DEMUX 1), a demultiplexer (DEMUX 2), a demultiplexer (DEMUX 3), a demultiplexer (DEMUX 4), and a demultiplexer (DEMUX 5) constituting a selection path;
the collector of the transistor (PM 1) is connected with the emitter of the transistor (PM 2), the emitter of the transistor (PM 1) is respectively connected with the emitters of the transistor (PM 3), the transistor (PM 5), the transistor (PM 7), the transistor (PM 9) and the transistor (PM 11), and the base of the transistor (PM 1) is respectively connected with the bases of the transistor (PM 3), the transistor (PM 5), the transistor (PM 7), the transistor (PM 9) and the transistor (PM 11) and the collector of the transistor; the base of the transistor (PM 2) is respectively connected with the bases and the collectors of the transistor (PM 4), the transistor (PM 6), the transistor (PM 8), the transistor (PM 10) and the transistor (PM 12); the emitters of the transistors (PM 4, PM6, PM8, PM10 and PM 12) are respectively connected with the collectors of the transistors (PM 3, PM5, PM7, PM9 and PM 11); the collectors of the transistor (PM 4), the transistor (PM 6), the transistor (PM 8), the transistor (PM 10) and the transistor (PM 12) are respectively connected with the input ends of the demultiplexer (DEMUX 1), the demultiplexer (DEMUX 2), the demultiplexer (DEMUX 3), the demultiplexer (DEMUX 4) and the demultiplexer (DEMUX 5);
The aspect ratio of the transistor (PM 3) and the transistor (PM 4) is 8 times that of the transistor (PM 1) and the transistor (PM 2), respectively; the aspect ratio of the transistor (PM 5) and the transistor (PM 6) is 4 times the aspect ratio of the transistor (PM 1) and the transistor (PM 2), respectively; the aspect ratio of the transistor (PM 7) and the transistor (PM 8) is 2 times the aspect ratio of the transistor (PM 1) and the transistor (PM 2), respectively; the aspect ratio of the transistor (PM 9) and the transistor (PM 10) is equal to the aspect ratio of the transistor (PM 1) and the transistor (PM 2), respectively; the aspect ratio of the transistor (PM 11) and the transistor (PM 12) is equal to the aspect ratio of the transistor (PM 1) and the transistor (PM 2), respectively; the ratio of the width to length ratio of the transistors is equal to the ratio of the current replications of each branch in the current mirror;
the demultiplexer (DEMUX 1), the demultiplexer (DEMUX 2), the demultiplexer (DEMUX 3), the demultiplexer (DEMUX 4) and the demultiplexer (DEMUX 5) are respectively controlled by control signals (SE 1[3 ]]) Control signal (SE 1[2 ]]) Control signal (SE 1[1 ]]) Control signal (SE 1[0 ]]) Control signal (SE 1[4 ]]) Controlling; when the control signals of the 5 demultiplexers are all at low level, the current copied by the current mirror flows out of the branch marked with 0 to generate a current I A The method comprises the steps of carrying out a first treatment on the surface of the When the control signals of the 5 demultiplexers are all high level, the current copied by the current mirror flows out of the branch marked with 1 to generate a current I B The method comprises the steps of carrying out a first treatment on the surface of the Output current I A And output current I B Is a complementary current, the sum of the currents of which is fixed as a unit current I UNIT Is 16 times as large as that of (a);
the control signals (SE 1[3 ]), the control signals (SE 1[2 ]), the control signals (SE 1[1 ]), the control signals (SE 1[0 ]), and the control signals (SE 1[4 ]) are obtained by logic conversion of DAC register control signals APCDAC [4] -APCDAC [0 ].
3. The exponential DAC circuit for automatic optical power control according to claim 1, wherein the first current proportional superposition circuit comprises a transistor (NM 1), a transistor (NM 2), a transistor (NM 3), a transistor (NM 4), a transistor (NM 5), a transistor (NM 6), a transistor (NM 7), a transistor (NM 8) constituting a first current mirror unit, and a transistor (NM 9), a transistor (NM 10), a transistor (NM 11), a transistor (NM 12), a transistor (NM 13), a transistor (NM 14), a transistor (NM 15) constituting a second current mirror unit;
the base of the transistor (NM 1) is respectively connected with the bases and the collectors of the transistor (NM 3) and the transistor (NM 5), and the collectors of the transistor (NM 1), the body transistor (NM 3) and the transistor (NM 5) are respectively connected with the emitters of the transistor (NM 2), the transistor (NM 4) and the transistor (NM 6);
The emitters of the transistor (NM 1), the transistor (NM 3) and the transistor (NM 5) are all grounded; the base of the transistor (NM 2) is respectively connected with the bases and the collectors of the transistor (NM 4) and the transistor (NM 6), the emitter of the transistor (NM 2) is connected with the collector of the transistor (NM 7), the collector of the transistor (NM 4) is connected with the emitters of the transistor (NM 7) and the transistor (NM 8), and the collector of the transistor (NM 6) is connected with the collector of the transistor (NM 8);
the transistors (NM 1, NM2, NM3, NM4, NM5 and NM 6) form a first current mirror structure, and the transistors (NM 7, NM 8) are used as switches of the first current mirror structure and are controlled by a control signal (SE 2[0 ]) and a control signal (SE 2[1 ]) which are respectively input to the bases of the transistors (NM 7, NM 8);
the bases of the transistors (NM 9) are respectively connected with the bases of the transistors (NM 11) and (NM 13), the collectors of the transistors (NM 9), the transistors (NM 11) and the transistors (NM 13) are respectively connected with the emitters of the transistors (NM 10), the transistors (NM 12) and the transistors (NM 14), and the emitters of the transistors (NM 11) and the transistors (NM 13) are grounded; the collectors of the transistors (NM 14, NM 15) are connected with each other;
The base of the transistor (NM 10) is respectively connected with the bases and the collectors of the transistor (NM 12) and the transistor (NM 14), and the collector of the transistor (NM 12) is connected with the emitter of the transistor (NM 15); the transistor (NM 9), the transistor (NM 10), the transistor (NM 11), the transistor (NM 12), the transistor (NM 13) and the transistor (NM 14) form a second current mirror structure, and the transistor (NM 15) is used as a switch of the second current mirror structure and is controlled by a control signal (SE 2[2 ]);
the aspect ratio of the transistor (NM 3) and the transistor (NM 4) is equal to the aspect ratio of the transistor (NM 1) and the transistor (NM 2), respectively; the aspect ratio of the transistor (NM 5) and the transistor (NM 6) is equal to the aspect ratio of the transistor (NM 1) and the transistor (NM 2), respectively; the aspect ratio of the transistor (NM 11) and the transistor (NM 12) is five seventh of the aspect ratio of the transistor (NM 9) and the transistor (NM 10), respectively; the aspect ratio of the transistor (NM 13) and the transistor (NM 14) is five seventh of the aspect ratio of the transistor (NM 9) and the transistor (NM 10), respectively;
the current I A Through the collector input of the transistor (NM 2), the current I is output through the collector of the transistor (NM 6) after corresponding proportional conversion C The method comprises the steps of carrying out a first treatment on the surface of the The current I B Through the collector input of the transistor (NM 10), the current I is output through the collector of the transistor (NM 14) after corresponding proportional conversion D ；
The control signals (SE 2[0 ]), the control signals (SE 2[1 ]), and the control signals (SE 2[2 ]) are obtained by logic conversion of DAC register control signals APCDAC [7] -APCDAC [4 ].
4. The exponential DAC circuit for automatic optical power control according to claim 1, wherein the second current ratio superimposing circuit comprises a transistor (PM 13), a transistor (PM 14), a transistor (PM 15), a transistor (PM 16), a transistor (PM 17), a transistor (PM 18), a transistor (PM 19), a transistor (PM 20), a transistor (PM 21), a transistor (PM 22), a transistor (PM 23), a transistor (PM 24), a transistor (PM 25), a transistor (PM 26), a transistor (PM 27), a transistor (PM 28), a transistor (PM 29), a transistor (PM 30), a transistor (PM 31), a transistor (PM 32), a transistor (PM 33), and a transistor (PM 34);
the base of the transistor (PM 13) is respectively connected with the bases of the transistor (PM 15), the transistor (PM 17) and the transistor (PM 19) and the collector of the transistor; the emitters of the transistors (PM 13, PM15, PM17 and PM 19) are connected with each other; the collectors of the transistors (PM 13, PM15, PM17 and PM 19) are respectively connected with the emitters of the transistors (PM 14, PM16, PM18 and PM 20);
The base of the transistor (PM 14) is respectively connected with the bases of the transistor (PM 16), the transistor (PM 18) and the transistor (PM 20) and the collector of the transistor; the collector of the transistor (PM 14) is connected with the collectors of the transistors (PM 29) and (PM 30), respectively; the collector of the transistor (PM 16) is connected to the emitter of the transistor (PM 29); the collector of the transistor (PM 18) is connected to the emitter of the transistor (PM 30) and the collector of the transistor (PM 31), respectively; the collector of the transistor (PM 20) is connected to the emitters of the transistor (PM 31) and the transistor (PM 32);
the base of the transistor (PM 27) is respectively connected with the bases of the transistor (PM 25), the transistor (PM 23) and the transistor (PM 21) and the collector of the transistor; the emitters of the transistors (PM 27, PM25, PM23 and PM 21) are connected with each other; the collectors of the transistors (PM 27, PM25, PM23 and PM 21) are respectively connected with the emitters of the transistors (PM 28, PM26, PM24 and PM 22);
The base of the transistor (PM 28) is respectively connected with the bases of the transistor (PM 26), the transistor (PM 24) and the transistor (PM 22) and the collector of the transistor; the collector of the transistor (PM 28) is connected with the collectors of the transistor (PM 33) and the transistor (PM 34), respectively; the collector of the transistor (PM 26) is connected to the emitter of the transistor (PM 34); the collector of the transistor (PM 24) is respectively connected with the collector of the transistor (PM 32) and the emitter of the transistor (PM 33); the collector of the transistor (PM 22) is connected to the emitter of the transistor (PM 32);
the aspect ratio of the transistor (PM 15) and the transistor (PM 16) is half the aspect ratio of the transistor (PM 13) and the transistor (PM 14), respectively; the aspect ratio of the transistor (PM 17) and the transistor (PM 18) is half the aspect ratio of the transistor (PM 13) and the transistor (PM 14), respectively; the aspect ratio of the transistor (PM 19) and the transistor (PM 20) is half the aspect ratio of the transistor (PM 13) and the transistor (PM 14), respectively; the aspect ratio of the transistor (PM 21) and the transistor (PM 22) is half the aspect ratio of the transistor (PM 27) and the transistor (PM 28), respectively; the aspect ratio of the transistor (PM 23) and the transistor (PM 24) is half the aspect ratio of the transistor (PM 27) and the transistor (PM 28), respectively; the aspect ratio of the transistor (PM 25) and the transistor (PM 26) is half the aspect ratio of the transistor (PM 27) and the transistor (PM 28), respectively;
The bases of the transistors (PM 29, PM30, PM31, PM32, PM33 and PM 34) are respectively input with a control signal (SE 3[0]]) Control signal (SE 3[0]]) Control signal (SE 3[1]]) Control signal (SE 3[3]]) Control signal (SE 3[2]]) Control signal (SE 3[2]]) The switch is used as a switch; current I C And current I D The current I is obtained by summing the corresponding proportion change through the collector of the transistor (PM 14) and the collector input of the transistor (PM 28) E Via the collector output of the transistor (PM 20);
the control signals (SE 3[0 ]), the control signals (SE 3[1 ]), the control signals (SE 3[3 ]), and the control signals (SE 3[2 ])areobtained by logic conversion of DAC register control signals APCDAC [7] -APCDAC [4 ].
5. The exponential DAC circuit for automatic optical power control according to claim 1, wherein the current multiplication output circuit comprises a transistor (NM 16), a transistor (NM 17), a transistor (NM 18), a transistor (NM 19), a transistor (NM 20), a transistor (NM 21), a transistor (NM 22), a transistor (NM 23), a transistor (NM 24), a transistor (NM 25), a transistor (NM 26), a transistor (NM 27), a transistor (NM 28), a transistor (NM 29), a transistor (NM 30), a transistor (NM 31), a transistor (NM 32);
The base of the transistor (NM 16) is respectively connected with the bases of the transistor (NM 18), the transistor (NM 20), the transistor (NM 22), the transistor (NM 24), the transistor (NM 26) and the collector of the transistor; the emitters of the transistor (NM 16), the transistor (NM 18), the transistor (NM 20), the transistor (NM 22), the transistor (NM 24) and the transistor (NM 26) are grounded; the collectors of the transistors (NM 16), (NM 18), (NM 20), (NM 22), (NM 24) and (NM 26) are respectively connected with the emitters of the transistors (NM 17), (NM 19), (NM 21), (NM 23), (NM 25) and (NM 27);
the base of the transistor (NM 17) is respectively connected with the bases of the transistor (NM 19), the transistor (NM 21), the transistor (NM 23), the transistor (NM 25) and the transistor (NM 27) and the collector of the transistor; the collectors of the transistors (NM 19), (NM 21), (NM 23), (NM 25) and (NM 27) are respectively connected with the emitters of the transistors (NM 28), (NM 29), (NM 30), (NM 31) and (NM 32); the collectors of the transistor (NM 28), the transistor (NM 29), the transistor (NM 30), the transistor (NM 31) and the transistor (NM 32) are connected with each other; the bases of the transistor (NM 28), the transistor (NM 29), the transistor (NM 30), the transistor (NM 31) and the transistor (NM 32) are respectively input with a control signal (SE 4[0 ]), a control signal (SE 4[1 ]), a control signal (SE 4[2 ]), a control signal (SE 4[3 ]), and a control signal (SE 4[4 ]);
The aspect ratio of the transistor (NM 18) and the transistor (NM 19) is half the aspect ratio of the transistor (NM 16) and the transistor (NM 17), respectively; the aspect ratio of the transistor (NM 20) and the transistor (NM 21) is equal to the aspect ratio of the transistor (NM 16) and the transistor (NM 17), respectively; the aspect ratio of the transistor (NM 22) and the transistor (NM 23) is twice the aspect ratio of the transistor (NM 16) and the transistor (NM 17), respectively; the aspect ratio of the transistor (NM 24) and the transistor (NM 25) is four times the aspect ratio of the transistor (NM 16) and the transistor (NM 17), respectively; the aspect ratio of the transistor (NM 26) and the transistor (NM 27) is eight times the aspect ratio of the transistor (NM 16) and the transistor (NM 17), respectively;
the current I E Output current I via collector input of transistor (NM 17) and via collector of transistor (NM 28) OUT ；
The control signals (SE 4[0 ]), the control signal (SE 4[1 ]), the control signal (SE 4[2 ]), the control signal (SE 4[3 ]), and the control signal (SE 4[4 ]) are obtained by logic conversion of DAC register control signals APCDAC [7] to APCDAC [5 ].
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| CN112636761A (en) * | 2020-12-09 | 2021-04-09 | 二十一世纪（北京）微电子技术有限公司 | Exponential reference current type digital-to-analog conversion circuit and electronic equipment |
| CN115993721A (en) * | 2023-03-23 | 2023-04-21 | 杭州爱鸥光学科技有限公司 | Control method for realizing polarization tracking and stabilization |
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| CN101416396A (en) * | 2006-02-21 | 2009-04-22 | Nxp股份有限公司 | Exponential digital to analog converter |
| CN103368576A (en) * | 2013-07-15 | 2013-10-23 | 北京时代民芯科技有限公司 | Method for digitally controlling full deflection output current of digital analog converter |
| CN112640286A (en) * | 2018-09-07 | 2021-04-09 | 微芯片技术股份有限公司 | Adaptive slope compensation for current mode control |
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