CN117479681A - Display panel and display terminal - Google Patents

Display panel and display terminal Download PDF

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Publication number
CN117479681A
CN117479681A CN202310404413.5A CN202310404413A CN117479681A CN 117479681 A CN117479681 A CN 117479681A CN 202310404413 A CN202310404413 A CN 202310404413A CN 117479681 A CN117479681 A CN 117479681A
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CN
China
Prior art keywords
layer
shielding
display panel
metal
shielding layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310404413.5A
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Chinese (zh)
Inventor
尹翔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to CN202310404413.5A priority Critical patent/CN117479681A/en
Publication of CN117479681A publication Critical patent/CN117479681A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The application discloses a display panel and a display terminal; the display panel comprises a substrate, a shielding layer arranged on the substrate, and an array layer arranged on one side of the shielding layer far away from the substrate, wherein the array layer comprises a plurality of metal layers, the orthographic projection of the shielding layer on the substrate is positioned in the substrate, the orthographic projection of the metal layer on the shielding layer is positioned in the shielding layer, and the shielding layer is made of conductive materials; this application is through setting up the shielding layer between display panel's base plate and array layer, and the shielding layer is conductive material, and the shielding layer can shield static, prevents that display panel from being wounded by static, simultaneously, with the shielding layer integration inside display panel, can make display panel's product satisfy miniaturized, low cost's requirement.

Description

Display panel and display terminal
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display terminal.
Background
Display panels, integrated circuits, and other electronic functional components can be damaged by electrostatic discharge (ESD) devices, affecting product functionality.
In order to cope with the adverse effect caused by the electrostatic discharge, it is necessary to provide electrostatic protection. The application provides a display panel with electrostatic protection function, integrates electrostatic protection in the display panel, and makes the product of display panel satisfy miniaturized, low cost's requirement.
Disclosure of Invention
The application provides a display panel and display terminal, display panel with static protection integrated in display panel, makes display panel's product satisfy miniaturized, low cost's requirement.
In order to solve the above problems, the technical scheme provided by the application is as follows:
the application provides a display panel, the display panel includes:
a substrate;
a shielding layer disposed on the substrate;
the array layer is arranged on one side, far away from the substrate, of the shielding layer, and comprises a plurality of metal layers;
the orthographic projection of the shielding layer on the substrate is positioned in the substrate, the orthographic projection of the metal layer on the shielding layer is positioned in the shielding layer, and the shielding layer is made of conductive materials.
In the display panel, the orthographic projection of the shielding layer on the substrate coincides with the substrate, and the display panel further comprises a voltage input end, and the shielding layer is connected to the voltage input end.
In the display panel, the area of orthographic projection of the shielding layer on the substrate is smaller than that of the substrate, the shielding layer comprises a first shielding part and a second shielding part, the first shielding part is positioned in a display area of the display panel, the second shielding part is positioned in a non-display area of the display panel, and the display panel further comprises a voltage input end;
the non-display area is arranged on the periphery of the display area, the voltage input end is located in the non-display area, the first shielding part and the second shielding part are arranged in an insulating mode, and the first shielding part and the second shielding part are connected to the voltage input end or any one of the metal layers.
In the display panel of the present application, the metal layer includes at least one of a source drain layer, a gate layer, and a light shielding layer, the source drain layer, the gate layer, and the light shielding layer are located in the display area, the first shielding portion is connected to any one of the source drain layer, the gate layer, and the light shielding layer, and the second shielding portion is connected to the voltage input terminal.
In the display panel of the application, the metal layer at least comprises a first metal part and a second metal part, the first metal part is located in the display area, the second metal part is located in the non-display area, the first metal part at least comprises one of a source drain electrode layer, a grid electrode layer and a shading layer, the second metal part at least comprises a functional module, the first shielding part is connected to any one of the source drain electrode layer, the grid electrode layer and the shading layer, and the second shielding layer is connected to the functional module.
In the display panel of the present application, the voltage input terminal includes a first input terminal and a second input terminal, the first shielding part is connected to the first input terminal, and the second shielding part is connected to the second input terminal.
In the display panel of the application, the first shielding part is connected to the voltage input end, the metal layer at least comprises a functional module, the functional module is located in the non-display area, and the second shielding part is connected to the functional module.
In the display panel of the present application, the functional module includes any one of a power module, a voltage transformation module, a capacitor, and a metal wire.
In the display panel of the present application, the array layer includes a thin film transistor including:
the source electrode and the drain electrode are arranged on the source electrode layer and the drain electrode layer in the metal layer in the same layer;
the grid electrode is arranged on the grid electrode layer in the metal layer;
the active layer is arranged on one side of the grid electrode, which is away from the source electrode;
the display panel further includes an anode, wherein the source electrode is electrically connected with the light shielding layer in the metal layer, and the anode is electrically connected with the source electrode.
The application also provides a display terminal, wherein the display panel comprises the display panel.
The beneficial effects are that: the application discloses a display panel and a display terminal; the display panel comprises a substrate, a shielding layer arranged on the substrate, and an array layer arranged on one side, far away from the substrate, of the shielding layer, wherein the array layer comprises a plurality of layers of metal layers, the orthographic projection of the shielding layer on the substrate is positioned in the substrate, the orthographic projection of the metal layer on the shielding layer is positioned in the shielding layer, and the shielding layer is made of a conductive material; this application is through setting up the shielding layer between display panel's base plate and array layer, and the shielding layer is conductive material, and the shielding layer can shield static, prevents that display panel from being wounded by static, simultaneously, with the shielding layer integration inside display panel, can make display panel's product satisfy miniaturized, low cost's requirement.
Drawings
Technical solutions and other advantageous effects of the present application will be made apparent from the following detailed description of specific embodiments of the present application with reference to the accompanying drawings.
FIG. 1 is a schematic top view of a display panel of the present application;
FIG. 2 is a schematic cross-sectional view of a first display panel according to the present application;
FIG. 3 is a schematic cross-sectional view of a second display panel according to the present application;
FIG. 4 is a schematic cross-sectional view of a third display panel according to the present application;
fig. 5 is a schematic top-view enlarged structure at D in fig. 3.
Reference numerals illustrate:
the display device includes a substrate 10, a shielding layer 20, a shielding block 210, an array layer 30, a thin film transistor 70, a metal layer 31, a voltage input terminal 40, a display area AA, a non-display area NA, a first shielding part 21, a second shielding part 22, a source drain layer 310, a gate layer 320, a light shielding layer 330, a light shielding part 331, a first metal part 311, a second metal part 312, a functional module 50, a first input terminal 41, a second input terminal 42, a source electrode 310S, a drain electrode 310D, a gate electrode 321, an active layer 340, and an anode 60.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and explanation only and is not intended to limit the present application. In this application, unless otherwise indicated, terms of orientation such as "upper" and "lower" are used to generally refer to the upper and lower positions of the device in actual use or operation, and specifically the orientation of the drawing figures; while "inner" and "outer" are for the outline of the device.
Display panels, integrated circuits, and other electronic functional components can be damaged by electrostatic discharge (ESD) devices, affecting product functionality. In order to cope with the adverse effect caused by the electrostatic discharge, it is necessary to provide electrostatic protection. The present application proposes the following scheme based on the above technical problems.
The application provides a display panel, the display panel include base plate 10, set up in shielding layer 20 on the base plate 10, set up in shielding layer 20 is kept away from array layer 30 of one side of base plate 10, array layer 30 includes multilayer metal layer 31, shielding layer 20 orthographic projection on the base plate 10 is located in the base plate 10, metal layer 31 orthographic projection on the shielding layer 20 is located in the shielding layer 20, shielding layer 20 is the electrically conductive material.
This application is through setting up shielding layer 20 between display panel's base plate 10 and array layer 30, and shielding layer 20 is conductive material, and shielding layer 20 can shield static, prevents that display panel from being wounded by static, simultaneously, with shielding layer 20 integration inside display panel, can make display panel's product satisfy miniaturized, low cost's requirement.
In the present embodiment, the substrate 10 may be a flexible substrate or a rigid substrate. The flexible substrate may be polyimide, a polyethylene terephthalate, or the like. The rigid substrate may be glass or the like. The material of the substrate 10 is not limited in this application.
In this embodiment, the display panel may be, for example, an OLED panel, mini-LED panel, micro-LED panel, LCD panel, or the like.
It should be noted that, when the display panel is a self-luminous display panel such as an OLED panel, a Mini-LED panel, a Micro-LED panel, or an LCD panel, the shielding layer 20 may be a conductive material such as metal, metal oxide, graphite, or the like. The metal may be any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), etc., or an alloy thereof. The metal oxide may be any of ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), IGZTO (indium gallium zinc tin oxide), and the like.
When the display panel is an LCD panel, the shielding layer 20 is a conductive material, and in order to prevent the shielding layer 20 from blocking light of a backlight located under the LCD panel, the shielding layer 20 needs to be provided to be transparent. At this time, the shielding layer 20 may be a transparent metal or a transparent metal oxide, such as ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), or the like.
In this embodiment, as shown in fig. 1, the display panel includes a display area AA and a non-display area NA located at the periphery of the display area AA. A plurality of functional modules 50 are disposed in the non-display area NA, and the functional modules 50 include any one of a power module, a voltage transformation module, a capacitor, and a metal wire. The functional module 50 may also comprise other circuits or the like for providing corresponding functions to the display area AA.
A voltage input terminal 40 is disposed at one side of the display area AA of the display panel, and the voltage input terminal 40 is used for inputting a voltage or a signal. The voltage input terminal 40 may be a bonding terminal that is bonded to a chip, a flexible circuit board, a flip chip film, or the like, thereby implementing input of an external signal to the display panel. The voltage input terminal 40 may be other input modes in the field, which are not limited in this application.
In this embodiment, as shown in fig. 2, the array layer 30 includes a plurality of thin film transistors 70, capacitors, metal traces, etc. distributed in an array. The array layer 30 is used for providing driving signals for pixels of the display panel to control the display mode of each pixel.
It should be noted that, the array layer 30 is defined as a film layer including the display area AA and the non-display area NA in this application. In particular, in the display area AA of the display panel, the array layer 30 may include a plurality of thin film transistors 70, capacitors, metal traces, etc. distributed in an array. In the non-display area NA of the display panel, the array layer 30 may include a plurality of functional modules 50, etc.
The array layer 30 may include metal layers 31 and insulating layers between the metal layers 31. The metal layer 31 includes a source/drain layer 310, a gate layer 320, a light shielding layer 330, and the like of the thin film transistor 70. The insulating layer includes a buffer layer between the shielding layer 20 and the light shielding layer 330, a gate insulating layer between the gate layer 320 and the active layer 340, an interlayer insulating layer between the source and drain layers 310 and the active layer 340, and the like.
The metal layer 31 may be a single layer or a multilayer film formed of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), and the like. The insulating layer may be a single layer or a multi-layer film formed of one or more of silicon oxide, silicon nitride, silicon oxynitride, and the like. The materials of the metal layer 31 and the insulating layer may be set as needed, which is not limited in this application.
In the present embodiment, the orthographic projection of the shielding layer 20 on the substrate 10 is located in the substrate 10, and the orthographic projection of the metal layer 31 on the shielding layer 20 is located in the shielding layer 20. The area of the orthographic projection of the shielding layer 20 on the substrate 10 is smaller than or equal to the area of the substrate 10, and the area of the orthographic projection of the metal layer 31 on the shielding layer 20 is smaller than or equal to the area of the shielding layer 20. Through the arrangement, the shielding layer 20 can completely shield the metal layer 31, the shielding layer 20 can generate electrostatic shielding field, the electrostatic shielding effect can be achieved, and the interference of electronic devices below on signals of the display panel can be avoided.
The technical scheme of the present application is described below in connection with specific embodiments.
As shown in fig. 1 and 2, in the display panel of the present application, the front projection of the shielding layer 20 on the substrate 10 coincides with the substrate 10, and the display panel further includes a voltage input terminal 40, and the shielding layer 20 is connected to the voltage input terminal 40.
In this embodiment, as shown in fig. 2, fig. 2 is a schematic cross-sectional structure of a first display panel of the present application. The shielding layer 20 may be a film layer that is continuously disposed, that is, the orthographic projection of the shielding layer 20 completely covers the substrate 10, so as to enhance the electrostatic shielding area and enhance the electrostatic shielding effect.
The display panel further includes a voltage input terminal 40, and the voltage input terminal 40 may input a voltage or a signal. The shield layer 20 may be connected to the voltage input 40 by vias. As shown in fig. 2, the shielding layer 20 is connected to the voltage input terminal 40 through a via hole located right under the voltage input terminal 40, thereby achieving electrical connection of the shielding layer 20 and the voltage input terminal 40. The shield 20 may also be electrically connected to the voltage input 40 using other electrical connections known in the art. The connection via of the shielding layer 20 and the voltage input terminal 40 may be located in the display area AA or other positions than the display area NA. When the connection via of the shielding layer 20 and the voltage input terminal 40 is located at another position, the voltage input terminal 40 may extend to the connection via through a metal trace, so as to electrically connect the shielding layer 20 and the voltage input terminal 40 at another position. The connection manner and connection position of the shielding layer 20 and the voltage input terminal 40 are not limited in this application.
The voltage input 40 may be located in any of the metal layers 31. For example, the voltage input terminal 40 and the source/drain layer 310 may be disposed on the same layer, so that the voltage input terminal 40 and the source/drain layer 310 may be formed by the same patterning process and/or the same material, which simplifies the manufacturing process of the display panel and reduces the production cost.
The input voltage of the voltage input terminal 40 may be set as desired. For example, the voltage input terminal 40 may provide a voltage of-10V to 10V. In one embodiment, the voltage of the voltage input terminal 40 may be 0V or grounded, so as to conduct the static electricity on the shielding layer 20 for electrostatic protection.
As shown in fig. 3 and fig. 4, in the display panel of the present application, the area of the orthographic projection of the shielding layer 20 on the substrate 10 is smaller than the area of the substrate 10, the shielding layer 20 includes a first shielding part 21 and a second shielding part 22, the first shielding part 21 is located in a display area AA of the display panel, the second shielding part 22 is located in a non-display area NA of the display panel, and the display panel further includes a voltage input terminal 40; the non-display area NA is disposed on the periphery of the display area AA, the voltage input terminal 40 is disposed in the non-display area NA, the first shielding portion 21 and the second shielding portion 22 are disposed in an insulating manner, and the first shielding portion 21 and the second shielding portion 22 are connected to either the voltage input terminal 40 or the metal layer 31.
In the present embodiment, the area of the orthographic projection of the shielding layer 20 on the substrate 10 is smaller than that of the substrate 10, that is, the shielding layer 20 may include a plurality of patterned shielding blocks 210. For example, the shielding block 210 may be in a long bar shape, a square block shape, or the like, and the shielding block 210 may be provided according to the shape of a device to be shielded. The shape of the shielding block 210 is not limited in this application. The shielding blocks 210 may not be connected to each other, i.e., the shielding blocks 210 are isolated from each other, so that each shielding block 210 may be disposed to be connected to a different one of the metal layers 31. For example, the shielding block 210 may be connected to any one of the source and drain layers 310, the gate layer 320, and the light shielding layer 330. When it is necessary to connect the plurality of shielding blocks 210 to the same voltage, the plurality of shielding blocks 210 may also be connected. Whether or not a plurality of shielding blocks 210 are connected depends on whether or not the shielding blocks 210 accept the same voltage or signal.
The light shielding layer 330 includes a plurality of light shielding portions 331, where one light shielding portion 331 corresponds to the active layer 340 of a thin film transistor 70, and the light shielding portion 331 is located directly under the active layer 340, so as to prevent light incident from under the active layer 340 from irradiating the active layer 340 to cause electrical degradation of the active layer 340.
In some embodiments, the front projection of the thin film transistor 70 onto the shielding layer 20 may completely coincide with the shielding block 210, or the front projection of the thin film transistor 70 onto the shielding block 210 is located within the shielding block 210. At this time, the shape of the shielding block 210 may be the same as the shape of the orthographic projection of the thin film transistor 70 on the shielding block 210. With the above arrangement, the shielding block 210 can function to shield static electricity, preventing the thin film transistor 70 from being damaged by static electricity.
In some embodiments, the front projection of the light shielding layer 330 onto the shielding layer 20 may completely coincide with the shielding layer 20, or the front projection of the light shielding layer 330 onto the shielding layer 20 is located within the shielding layer 20. At this time, the shape of the shielding block 210 may be the same as the shape of the light shielding portion 331.
The shielding layer 20 includes a first shielding part 21 located in the display area AA and a second shielding part 22 located in the non-display area NA, and the first shielding part 21 and the second shielding part 22 are disposed to be insulated. The first shielding portion 21 and the second shielding portion 22 may be provided in an insulating manner in such a manner that the first shielding portion 21 and the second shielding portion 22 are disconnected, that is, the first shielding portion 21 and the second shielding portion 22 are not connected.
The first shielding part 21 may include a plurality of shielding blocks 210 separately provided, and the shielding blocks 210 may not be connected to each other, i.e., the shielding blocks 210 are isolated from each other. When it is necessary to connect the plurality of shielding blocks 210 to the same voltage, the plurality of shielding blocks 210 may also be connected. Whether or not a plurality of shielding blocks 210 are connected depends on whether or not the shielding blocks 210 accept the same voltage or signal.
The second shielding part 22 may include a plurality of shielding blocks 210 separately provided, and the shielding blocks 210 may not be connected to each other, i.e., the shielding blocks 210 are isolated from each other. When it is necessary to connect the plurality of shielding blocks 210 to the same voltage, the plurality of shielding blocks 210 may also be connected. Whether or not a plurality of shielding blocks 210 are connected depends on whether or not the shielding blocks 210 accept the same voltage or signal.
In some embodiments, the first shield 21 may be connected to the voltage input 40, and the voltage input 40 may provide a voltage of-10V to 10V. In one embodiment, the voltage at the voltage input 40 may be 0V or ground to conduct static electricity away from the shield 20.
In some embodiments, the first shield 21 may be connected to any of the metal layers 31. For example, the first shielding portion 21 may be connected to any one of the source and drain layer 310, the gate layer 320, and the light shielding layer 330. It should be noted that, when one shielding block 210 in the first shielding portion 21 is connected to any one of the source/drain layer 310, the gate layer 320 and the light shielding layer 330, the same shielding block 210 is no longer connected to the input voltage terminal, so as to avoid signal crosstalk.
In some embodiments, the second shield 22 may be connected to any of the metal layers 31. For example, the second shield 22 may be connected to the functional module 50. It should be noted that, when one shielding block 210 in the second shielding portion 22 is connected to the functional module 50, the same shielding block 210 is no longer connected to the input voltage terminal, so as not to cause signal crosstalk.
In the above-described embodiment, when the shielding block 210 overlaps with the orthographic projection of the light shielding portion 331, the shielding block 210 may form an auxiliary capacitance with the light shielding portion 331. At this time, the auxiliary capacitor can be connected in parallel with the storage capacitor of the display panel, so that the capacity value of the storage capacitor of the pixel can be increased, and the display effect of the display panel and the uniformity of the display picture are improved.
As shown in fig. 3, fig. 3 is a schematic cross-sectional structure of a second display panel of the present application. In the display panel of the present application, the metal layer 31 includes at least one of a source drain layer 310, a gate layer 320, and a light shielding layer 330, the source drain layer 310, the gate layer 320, and the light shielding layer 330 are located in the display area AA, the first shielding portion 21 is connected to any one of the source drain layer 310, the gate layer 320, and the light shielding layer 330, and the second shielding portion 22 is connected to the voltage input terminal 40.
As shown in fig. 3, in the present embodiment, the first shielding portion 21 may be connected to the gate layer 320. The first shielding portion 21 is disposed corresponding to the light shielding portion 331, that is, the first shielding portion 21 includes a plurality of shielding blocks 210, and one shielding block 210 is located directly below one light shielding portion 331. The auxiliary capacitance can be formed by overlapping the shielding block 210 with the light shielding portion 331. Fig. D shows a cross-sectional structure of the shield block 210 as an auxiliary capacitor plate. The shielding block 210 is electrically connected to the gate layer 320 through the first electrical connection post HL1, and the light shielding portion 331 is electrically connected to the source drain layer 310 through the second electrical connection post HL 2.
In the display panel, the gate electrode 321 of the thin film transistor 70 overlaps the source electrode 310S of the thin film transistor 70 to form a storage capacitor. The auxiliary capacitor and the storage capacitor can be connected in parallel through the arrangement. Thereby increasing the capacitance value of the storage capacitor of the pixel and improving the display effect of the display panel and the uniformity of the display picture.
Specifically, as shown in fig. 5, fig. 5 shows a case where the shielding block 210 overlaps the light shielding portion 331 to form an auxiliary capacitance. Fig. 5 is a schematic top-view enlarged structure at D in fig. 3. The shielding block 210, the gate layer 320, the light shielding portion 331, and the orthographic projection of the source/drain layer 310 overlap at least partially, and form a plate of the auxiliary capacitor. Wherein, the shielding block 210 is electrically connected with the gate layer 320 through the first electrical connection post HL1, and the light shielding portion 331 is electrically connected with the source drain layer 310 through the second electrical connection post HL2, thereby forming an auxiliary capacitor. The storage capacitor can be connected in parallel with the storage capacitor by connecting the gate electrode layer 320 in the storage capacitor to the gate electrode 321 of the thin film transistor 70 and connecting the source/drain electrode layer 310 in the storage capacitor to the source electrode 310S of the thin film transistor. Thereby increasing the capacitance value of the storage capacitor of the pixel and improving the display effect of the display panel and the uniformity of the display picture.
The plates of the auxiliary capacitor may be connected to the storage capacitor in parallel by the same-layer wiring or bridged to the storage capacitor by an electrical connection post, which is not limited in this application.
In this embodiment, the second shielding part 22 may be connected to the voltage input terminal 40, and the voltage input terminal 40 may provide a voltage of-10V to 10V. In one embodiment, the voltage at the voltage input 40 may be 0V or ground to conduct static electricity away from the shield 20.
In one embodiment, the source drain layer 310 further includes a plurality of data traces, and the first shielding portion 21 may be connected to the data traces through vias. When the first shielding part 21 is connected with the data wire, the pattern of the first shielding part 21 may be the same as the pattern of the data wire, i.e., the first shielding part 21 may be linear. By connecting the first shielding part 21 and the data wire in parallel through the via hole, the resistance of the data wire can be reduced, the delay of signals on the data wire can be reduced, and the display effect of the display panel can be improved.
In one embodiment, the gate layer 320 further includes a plurality of gate 321 traces. The first shielding part 21 may be wired with the gate electrode 321 through a via hole. When the first shielding part 21 is wired to the gate electrode 321, the pattern of the first shielding part 21 may be the same as the pattern of the gate electrode 321, i.e., the first shielding part 21 may be linear. By connecting the first shielding portion 21 and the wiring of the gate 321 in parallel through the via hole, the resistance of the wiring of the gate 321 can be reduced, the delay of the signal on the wiring of the gate 321 can be reduced, and the display effect of the display panel can be improved.
In this embodiment, the first shielding portion 21 may be connected in parallel with other wires of the metal layer 31, such as VDD wires, VSS wires, etc., so as to reduce the resistance of the corresponding metal wires. The scope of the metal wiring to which the first shielding portion 21 can be connected is not limited in this application.
In one embodiment, voltage input 40 is connected to a chip-binding. The second shield 22 is connected to the voltage input 40. The orthographic projection of the chip on the second shielding portion 22 is located in the second shielding portion 22, that is, the second shielding portion 22 completely shields the chip from being damaged by static electricity.
As shown in fig. 4, fig. 4 is a schematic cross-sectional structure of a third display panel of the present application. Fig. 4 differs from fig. 3 in that the second shielding portion 22 is different. In the display panel of the present application, the metal layer 31 includes at least a first metal portion 311 and a second metal portion 312, the first metal portion 311 is located in the display area AA, the second metal portion 312 is located in the non-display area NA, the first metal portion 311 includes at least one of a source drain layer 310, a gate layer 320 and a light shielding layer 330, the second metal portion 312 includes at least a functional module 50, the first shielding portion 21 is connected to any one of the source drain layer 310, the gate layer 320 and the light shielding layer 330, and the second shielding layer 20 is connected to the functional module 50.
In the present embodiment, the metal layer 31 includes a first metal portion 311 located in the display area AA and a second metal portion 312 located in the non-display area NA. The first metal portion 311 includes a source/drain layer 310, a gate layer 320, a light shielding layer 330, and the like. The second metal part 312 includes at least the functional module 50. The functional module 50 includes any one of a power module, a voltage transformation module, a capacitor, and a metal trace. The functional module 50 may also comprise other circuits or the like for providing corresponding functions to the display area AA. The functional module 50 may be disposed on the array layer 30. The second metal portion 312 may include metal traces, capacitors, etc. of the functional module 50. The first metal portion 311 and the second metal portion 312 may be formed in the same layer, so that the same patterning process and/or the same material is used, the manufacturing process of the display panel is simplified, and the production cost is reduced.
In the present embodiment, the second shielding layer 20 is connected to the functional module 50. In particular, the second shielding layer 20 may be connected to metal traces, capacitors, etc. in the second metal portion 312.
By electrically connecting the first shielding layer 20 with the metal wire, the resistance of the metal wire can be reduced, the delay of signals on the metal wire can be reduced, and the display effect of the display panel can be improved.
By connecting the second shielding layer 20 in parallel with the capacitor, the capacitance of the capacitor can be increased, and the display effect and the uniformity of the display picture of the display panel can be improved.
In the display panel of the present application, the voltage input terminal 40 includes a first input terminal 41 and a second input terminal 42, the first shielding part 21 is connected to the first input terminal 41, and the second shielding part 22 is connected to the second input terminal 42.
In the present embodiment, the voltage input terminal 40 includes a first input terminal 41 and a second input terminal 42, and the voltages of the first input terminal 41 and the second input terminal 42 may be set to be the same or different as needed. By setting the voltages of the first input terminal 41 and the second input terminal 42 to be different, the respective voltages can be set according to the respective needs of the first shielding portion 21 and the second shielding portion 22.
In some embodiments, the voltage at the first input 41 may be set as desired, or the voltage at the second input 42 may be set as desired. For example, adjusting the voltage at the set voltage input terminal 40 to a negative voltage may make the off-state performance of the thin film transistor 70 more reliable.
In the display panel of the present application, the first shielding part 21 is connected to the voltage input terminal 40, the metal layer 31 includes at least a functional module 50, the functional module 50 is located in the non-display area NA, and the second shielding part 22 is connected to the functional module 50.
In the present embodiment, the first shielding portion 21 is connected to the voltage input terminal 40. The voltage input terminal 40 may provide a voltage of-10V to 10V. In one embodiment, the voltage at the voltage input 40 may be 0V or ground to conduct static electricity away from the shield 20.
The second shield 22 is connected to the functional module 50. In particular, the second shielding layer 20 may be connected to metal traces, capacitors, etc. in the second metal portion 312.
By electrically connecting the second shielding layer 20 with the metal wire, the resistance of the metal wire can be reduced, the delay of signals on the metal wire can be reduced, and the display effect of the display panel can be improved.
By electrically connecting the second shielding layer 20 with the capacitor, the capacitance of the capacitor can be increased, and the display effect and the uniformity of the display screen of the display panel can be improved.
In the display panel of the present application, the functional module 50 includes any one of a power module, a voltage transformation module, a capacitor, and a metal wire.
In this embodiment, the functional module 50 may further include other modules, for example, a part of the modules disposed on the chip may be integrated into the display panel, thereby reducing the manufacturing cost of the chip. The present application is not limited to functional module 50.
As shown in fig. 2, in the display panel of the present application, the array layer 30 includes a thin film transistor 70, the thin film transistor 70 includes a source electrode 310S, a drain electrode 310D, a gate electrode 321, and an active layer 340, where the source electrode 310S and the drain electrode 310D are disposed on the source-drain electrode layer 310 in the metal layer 31 in the same layer, the gate electrode 321 is disposed on the gate electrode layer 320 in the metal layer 31, and the active layer 340 is disposed on a side of the gate electrode 321 facing away from the source electrode 310S; the display panel further includes an anode electrode 60, the source electrode 310S is electrically connected to the light shielding layer 330 in the metal layer 31, and the anode electrode 60 is electrically connected to the source electrode 310S.
As shown in fig. 2, in the present embodiment, the display panel is an OLED display panel. The source 310S of the thin film transistor 70 is electrically connected to the anode 60. In some embodiments, the drain 310D of the thin film transistor 70 may be electrically connected to the anode 60. That is, one of the source 310S or the drain 310D of the thin film transistor 70 is connected to the anode 60, which is not limited in this application.
The display panel further includes a layer of luminescent material, a cathode, etc. on the anode 60. The anode 60 serves to provide holes, and the cathode serves to provide electrons, which recombine in the light emitting material layer to emit light. The display panel includes a plurality of pixels, one pixel corresponding to each anode 60. By providing the light emitting color of the light emitting material layer, a red pixel emitting red light, a green pixel emitting green light, and a blue pixel emitting blue light can be formed. The thin film transistor 70, the capacitor, the data trace, the gate electrode 321 trace, etc. in the array layer 30 may form a driving circuit for controlling light emission of the pixel.
The functional module 50 of the non-display area NA of the display panel may be used to control the driving circuit to implement the display function.
The application also provides a display terminal, wherein the display panel comprises the display panel.
In this embodiment, the display terminal may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The display panel and the display terminal provided by the embodiments of the present application are described in detail, and specific examples are applied to illustrate the principles and the implementation of the present application, and the description of the above embodiments is only used to help understand the technical solution and the core idea of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. A display panel, comprising:
a substrate;
a shielding layer disposed on the substrate;
the array layer is arranged on one side, far away from the substrate, of the shielding layer, and comprises a plurality of metal layers;
the orthographic projection of the shielding layer on the substrate is positioned in the substrate, the orthographic projection of the metal layer on the shielding layer is positioned in the shielding layer, and the shielding layer is made of conductive materials.
2. The display panel of claim 1, wherein an orthographic projection of the shielding layer on the substrate coincides with the substrate, the display panel further comprising a voltage input, the shielding layer being connected to the voltage input.
3. The display panel of claim 1, wherein an area of the orthographic projection of the shielding layer on the substrate is smaller than an area of the substrate, the shielding layer including a first shielding portion and a second shielding portion, the first shielding portion being located in a display area of the display panel, the second shielding portion being located in a non-display area of the display panel, the display panel further including a voltage input terminal;
the non-display area is arranged on the periphery of the display area, the voltage input end is located in the non-display area, the first shielding part and the second shielding part are arranged in an insulating mode, and the first shielding part and the second shielding part are connected to the voltage input end or any one of the metal layers.
4. The display panel according to claim 3, wherein the metal layer includes at least one of a source/drain layer, a gate layer, and a light shielding layer, the source/drain layer, the gate layer, and the light shielding layer are located in the display region, the first shielding portion is connected to any one of the source/drain layer, the gate layer, and the light shielding layer, and the second shielding portion is connected to the voltage input terminal.
5. The display panel according to claim 3, wherein the metal layer includes at least a first metal portion and a second metal portion, the first metal portion is located in the display region, the second metal portion is located in the non-display region, the first metal portion includes at least one of a source drain layer, a gate layer, and a light shielding layer, the second metal portion includes at least a functional module, the first shielding portion is connected to any one of the source drain layer, the gate layer, and the light shielding layer, and the second shielding layer is connected to the functional module.
6. A display panel according to claim 3, wherein the voltage input comprises a first input and a second input, the first shield being connected to the first input, the second shield being connected to the second input.
7. A display panel according to claim 3, wherein the first shielding part is connected to the voltage input terminal, the metal layer comprises at least a functional module, the functional module is located in the non-display area, and the second shielding part is connected to the functional module.
8. The display panel of claim 5 or 7, wherein the functional module comprises any one of a power module, a voltage transformation module, a capacitor, and a metal trace.
9. The display panel of claim 1, wherein the array layer comprises a thin film transistor comprising:
the source electrode and the drain electrode are arranged on the source electrode layer and the drain electrode layer in the metal layer in the same layer;
the grid electrode is arranged on the grid electrode layer in the metal layer;
the active layer is arranged on one side of the grid electrode, which is away from the source electrode;
the display panel further includes an anode, wherein the source electrode is electrically connected with the light shielding layer in the metal layer, and the anode is electrically connected with the source electrode.
10. A display terminal comprising the display panel according to any one of claims 1 to 9.
CN202310404413.5A 2023-04-12 2023-04-12 Display panel and display terminal Pending CN117479681A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310404413.5A CN117479681A (en) 2023-04-12 2023-04-12 Display panel and display terminal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310404413.5A CN117479681A (en) 2023-04-12 2023-04-12 Display panel and display terminal

Publications (1)

Publication Number Publication Date
CN117479681A true CN117479681A (en) 2024-01-30

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310404413.5A Pending CN117479681A (en) 2023-04-12 2023-04-12 Display panel and display terminal

Country Status (1)

Country Link
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