CN117479548A - Magnetic memory array, preparation method thereof, data access method and electronic equipment - Google Patents

Magnetic memory array, preparation method thereof, data access method and electronic equipment Download PDF

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Publication number
CN117479548A
CN117479548A CN202311449059.4A CN202311449059A CN117479548A CN 117479548 A CN117479548 A CN 117479548A CN 202311449059 A CN202311449059 A CN 202311449059A CN 117479548 A CN117479548 A CN 117479548A
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control line
magnetic memory
write
current control
magnetic
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Inventor
张和
欧乾雷
王昭昊
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Zhizhen Storage Beijing Technology Co ltd
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Zhizhen Storage Beijing Technology Co ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1655—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1657—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods

Abstract

The invention provides a magnetic memory array, a preparation method thereof, a data access method and electronic equipment, and belongs to the technical field of semiconductors. The magnetic memory array comprises a plurality of magnetic memory cells arranged in an array, each magnetic memory cell comprises a magnetic memory device and a write access transistor, the magnetic memory device comprises an SOT bottom electrode layer and a Magnetic Tunnel Junction (MTJ), and a first end of the write access transistor is connected with a first end of the SOT bottom electrode layer. The gates of the write memory transistors of each row are connected to form a write control line, the second ends of the write memory transistors of each column are connected to form a first write current control line, the second ends of the SOT bottom electrode layers of each column are connected to form a second write current control line, and for each row of magnetic memory cells, the Magnetic Tunnel Junctions (MTJs) of the row are connected to form a read bit line. Each magnetic memory cell has only a write access transistor, and a read access transistor is removed, so that the formed magnetic memory array has a simpler circuit structure, smaller layout occupation and larger memory density.

Description

Magnetic memory array, preparation method thereof, data access method and electronic equipment
Technical Field
The invention relates to the technical field of semiconductors, in particular to a magnetic memory array, a preparation method thereof, a data access method and electronic equipment.
Background
The spin-orbit torque magnetic memory (Spin Orbit Torque-Magnetic Random Access Memory, SOT-MRAM) has the advantages of non-volatility, high-speed low-power consumption data writing, high device durability and the like, and is a novel spin memory device (also called SOT device). The core structure of SOT-MRAM mainly includes: the SOT bottom electrode layer (or heavy metal layer) and the sandwich structure magnetic tunnel junction (Magnetic Tunnel Junction, MTJ), the top layer of the sandwich structure is a pinning layer, the magnetization direction of the pinning layer cannot change, the middle layer is a barrier layer, the bottom layer is a free layer, and the magnetization direction of the pinning layer can change. When currents in different directions are introduced into the heavy metal layer, the magnetization direction of the free layer can be changed.
The magnetic memory array is composed of magnetic memory units, and the magnetic memory units comprise magnetic memory devices and control MOS tubes. For the case of a SOT-MRAM device, the magnetic memory cell includes a memory cell that typically includes two MOS transistors, one referred to as a write access transistor (e.g., a write gate MOS transistor) and one referred to as a read access transistor (e.g., a read gate MOS transistor), as shown in FIG. 1. The magnetic memory array structure occupies a large layout area, has a complex layout structure and low memory density, and is not beneficial to the integration of memory devices.
Disclosure of Invention
It is an object of embodiments of the present invention to provide a magnetic memory array that facilitates the integration of memory devices.
To achieve the above object, an embodiment of the present invention provides a magnetic memory array including a plurality of magnetic memory cells arranged in an array, each magnetic memory cell including a magnetic memory device including a SOT bottom electrode layer and a magnetic tunnel junction MTJ, and a write access transistor having a first end connected to a first end of the SOT bottom electrode layer. For each row of magnetic memory cells, the gates of the write access transistors of the row are connected to form a write control line, and for each column of magnetic memory cells, the second ends of the write access transistors of the column are connected to form a first write current control line, and the second ends of the SOT bottom electrode layers of the column are connected to form a second write current control line. For each row of magnetic memory cells, the magnetic tunnel junctions MTJ of the row are connected to form a read bit line, and data reading of the magnetic tunnel junctions MTJ of the selected magnetic memory cell is accomplished by controlling the read bit line and the second write current control line.
Optionally, the memory array implementing a multiply-accumulate operation process includes: for each row of magnetic memory cells, determining a first set of operational data for each magnetic tunnel junction MTJ by controlling the write control line, the first write current control line, and the second write current control line for each row to flip the magnetic tunnel junction MTJ for each row into a high resistance state or a low resistance state; for any column of magnetic memory cells, determining a second set of operation data for each magnetic tunnel junction MTJ of the column by controlling the read bit line of each magnetic memory cell of the column, connecting the second write current control line of the column to a fixed level, reading the current on the second write current control line, and obtaining multiply-accumulate data for the first set of operation data and the second set of operation data for each magnetic tunnel junction MTJ of the column.
Optionally, selecting the magnetic tunnel junction MTJ by controlling the write control line, the first write current control line, and the second write current control line; and generating write currents in different directions by controlling the first write current control line and the second write current control line so as to flip the selected Magnetic Tunnel Junction (MTJ) into a high-resistance state or a low-resistance state, thereby realizing data writing of the Magnetic Tunnel Junction (MTJ).
Optionally, the SOT bottom electrode layer is a heavy metal layer, and the magnetic tunnel junction MTJ comprises a free layer, a barrier layer and a pinning layer sequentially grown on the SOT bottom electrode layer.
The embodiment of the invention also provides a preparation method of the magnetic storage array, which comprises the following steps: preparing a magnetic memory cell by preparing a finished magnetic memory device and a write access transistor, wherein the magnetic memory device comprises an SOT bottom electrode layer and a Magnetic Tunnel Junction (MTJ); connecting a first end of the write access transistor with a first end of the SOT bottom electrode layer; and arranging a plurality of prepared magnetic memory cells in an array, wherein for each row of magnetic memory cells, the gates of the write access transistors of the row are connected to form a write control line, the Magnetic Tunnel Junctions (MTJs) of the row are connected to form a read bit line, and for each column of magnetic memory cells, the second ends of the write access transistors of the column are connected to form a first write current control line, and the second ends of the SOT bottom electrode layers of the column are connected to form a second write current control line.
Optionally, preparing the magnetic memory device includes: preparing a heavy metal layer serving as the SOT bottom electrode layer; and forming the Magnetic Tunnel Junction (MTJ) by sequentially growing a free layer, a barrier layer and a pinning layer on the SOT bottom electrode layer.
The embodiment of the invention also provides a data access method for the magnetic storage array, which comprises the following steps: completing data writing to the magnetic tunnel junction MTJ of the selected magnetic memory cell by controlling a write control line, a first write current control line, and the second write current control line; and completing data reading of the magnetic tunnel junction MTJ of the selected magnetic memory cell by controlling a read bit line and the second write current control line.
Optionally, the data access method further includes implementing a multiply-accumulate operation procedure: for each row of magnetic memory cells, determining a first set of operational data for each magnetic tunnel junction MTJ by controlling the write control line, the first write current control line, and the second write current control line for each row to flip the magnetic tunnel junction MTJ for each row into a high resistance state or a low resistance state; and for any column of magnetic memory cells, determining a second set of operation data for each magnetic tunnel junction MTJ of the column by controlling the read bit line of each magnetic memory cell of the column, connecting the second write current control line of the column to a fixed level, reading the current on the second write current control line, and obtaining multiply-accumulate data for the first set of operation data and the second set of operation data for each magnetic tunnel junction MTJ of the column.
Optionally, the writing of data to the magnetic tunnel junction MTJ of the selected magnetic memory cell is accomplished by controlling the write control line, the first write current control line, and the second write current control line, including: selecting the magnetic tunnel junction MTJ by controlling the write control line, the first write current control line, and the second write current control line; and generating write currents of different directions by controlling the first write current control line and the second write current control line to flip the selected magnetic tunnel junction MTJ to a high resistance state or a low resistance state.
The embodiment of the invention also provides electronic equipment, which comprises a processor and the magnetic storage array coupled with the processor.
Through the technical scheme, the magnetic memory array provided by the embodiment of the invention comprises a plurality of magnetic memory units which are arranged in an array, wherein each magnetic memory unit is only provided with a write access transistor, and a read access transistor is removed. Compared with the magnetic memory array formed by the existing magnetic memory units, the embodiment of the invention has simpler circuit structure, smaller layout occupation and larger memory density.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain, without limitation, the embodiments of the invention. In the drawings:
FIG. 1 is a schematic diagram of a prior art magnetic memory cell;
FIG. 2 is a schematic diagram of a magnetic memory array according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of data reading according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of data storage according to an embodiment of the present invention;
FIG. 5 is a schematic flow chart of a method for fabricating a magnetic memory array according to an embodiment of the present invention;
FIG. 6 is a flow chart of a method for accessing data in a magnetic memory array according to an embodiment of the present invention.
Detailed Description
The following describes the detailed implementation of the embodiments of the present invention with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
It should be noted that, in the embodiment of the present application, directional indications (such as up, down, left, right, front, and rear … …) are referred to, and the directional indications are merely used to explain the relative positional relationship, movement conditions, and the like between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present application, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be regarded as not exist and not within the protection scope of the present application.
FIG. 2 is a schematic diagram of a magnetic memory array according to an embodiment of the present invention, and referring to FIG. 2, the magnetic memory array includes a plurality of magnetic memory cells arranged in an array, each of the magnetic memory cells includes a magnetic memory device including a SOT bottom electrode layer and a magnetic tunnel junction MTJ, and a write memory transistor having a first end connected to a first end of the SOT bottom electrode layer.
For each row of magnetic memory cells, the gates of the write access transistors of the row are connected to form a write control line, for each column of magnetic memory cells, the second ends of the write access transistors of the column are connected to form a first write current control line, the second ends of the SOT bottom electrode layers of the column are connected to form a second write current control line, and for each row of magnetic memory cells, the Magnetic Tunnel Junctions (MTJs) of the row are connected to form a read bit line.
The SOT bottom electrode layer which is preferable in the embodiment of the invention can be a heavy metal layer, and the Magnetic Tunnel Junction (MTJ) comprises a free layer, a barrier layer and a pinning layer which are sequentially grown on the SOT bottom electrode layer.
Referring to the magnetic memory array shown in fig. 2, the gates of the write access transistors of each row of magnetic memory cells are connected together to form a write control line (e.g., WWL1, WWL2, etc.), the second ends (source or drain) of the write access transistors of each column of magnetic memory cells are connected together to form a first write current control line (e.g., BL1, BL2, etc.), and the second ends of the SOT bottom electrode layers of the column are connected together to form a second write current control line (e.g., SL1, SL2, etc.).
Preferably, the magnetic tunnel junction MTJ is selected by controlling the write control line, the first write current control line, and the second write current control line; and generating write currents in different directions by controlling the first write current control line and the second write current control line so as to flip the selected Magnetic Tunnel Junction (MTJ) into a high-resistance state or a low-resistance state, thereby realizing data writing of the Magnetic Tunnel Junction (MTJ).
Fig. 2 also shows an implementation of data writing, please refer to fig. 2, taking writing to the magnetic memory device of the upper left magnetic memory cell as an example, the write control line WWL1 is controlled to be opened (at this time, the write control lines of other rows may be controlled to be closed, for example, the write control line WWL2 is controlled to be closed), and a current path is formed through the write control line WWL1, the first write current control line BL1 and the second write current control line BL2 to select the magnetic memory cell (for example, the upper left memory cell). The first write current control line and the second write current control line can independently control the direction of write current and whether the write current is suspended, for example, the current control line is used for conducting write current from the first current control line BL1 to the second current control line SL1 to the SOT bottom electrode layer of the selected magnetic storage device, and the free layer direction of the corresponding magnetic tunnel junction MTJ is controlled to be reversed, for example, the selected magnetic tunnel junction MTJ is reversed to be in a high resistance state; when the passing direction of the write current is the second current control line SL1 to the first current control line BL1, the free layer direction of the corresponding magnetic tunnel junction MTJ is controlled to be inverted, for example, the selected magnetic tunnel junction MTJ is inverted to a low resistance state in which the low resistance state and the high resistance state are opposite states, and the above example is not particularly limited.
Preferably, the reading of data to the magnetic tunnel junction MTJ of the selected magnetic memory cell is accomplished by controlling the read bit line and the second write current control line.
Referring to FIG. 3, the magnetic tunnel junction MTJ tips of each row of magnetic memory cells are connected together to form a read bit line (e.g., RBL1, RBL2, etc.), and data reading of the magnetic tunnel junction MTJ of a selected magnetic memory cell is accomplished by controlling the read bit line and the second write current control line. For example, taking the case of reading the data of the upper left cell, the write control line (e.g., WWL1, WWL2, etc.) may be turned off, the other read bit line (e.g., RBL2, etc.), the first write current control line (e.g., BL1, BL2, etc.), the second write current control line (e.g., SL2, etc.), and the read current in the direction of the read bit line (RBL 1) to the second current control line (SL 1) may be applied to complete the data reading.
Accordingly, the magnetic memory array provided by the embodiment of the invention comprises a plurality of magnetic memory cells arranged in an array, wherein each magnetic memory cell has only a write access transistor, and a read access transistor is removed. Compared with the magnetic memory array formed by the existing magnetic memory units, the embodiment of the invention has simpler circuit structure, smaller layout occupation and larger memory density.
The magnetic memory unit in the magnetic memory array of the embodiment of the invention is a spin-orbit torque magnetic memory, and can be used in neural networks such as BNN and the like due to the binary property of the spin-orbit torque magnetic memory. Important operations in neural networks include multiply-accumulate operations, e.g., operations in which two sets of data are correspondingly multiplied and then accumulated.
The embodiment of the invention also provides an example for realizing multiply-accumulate operation based on the magnetic storage array. Preferably, the memory array implements a multiply-accumulate operation process comprising: for each row of magnetic memory cells, determining a first set of operational data for each magnetic tunnel junction MTJ by controlling the write control line, the first write current control line, and the second write current control line for each row to flip the magnetic tunnel junction MTJ for each row into a high resistance state or a low resistance state; for any column of magnetic memory cells, determining a second set of operation data for each magnetic tunnel junction MTJ of the column by controlling the read bit line of each magnetic memory cell of the column, connecting the second write current control line of the column to a fixed level, reading the current on the second write current control line, and obtaining multiply-accumulate data for the first set of operation data and the second set of operation data for each magnetic tunnel junction MTJ of the column.
Referring to fig. 2 and 4, taking two rows and two columns of magnetic memory arrays as an example, a multiply-accumulate operation of two sets of data is implemented: 1) A first set of operational data for each magnetic tunnel junction MTJ is determined. Referring to fig. 2, in the first example, the write control line WWL1 is turned on, the control signals associated with the other rows are turned off, the first write current control lines (BL 1, BL2, etc.) and the second write current control lines (SL 1, SL2, etc.) are controlled, respectively, and the two magnetic memory cells in the first row are written to opposite states by generating write currents in different directions. For example, the magnetic tunnel junctions MTJ (a and B) are in a "low resistance, high resistance" state, or a "high resistance, low resistance" state; the "low resistance, high resistance" states of the magnetic tunnel junctions MTJ (a and B), for example, correspond to a first set of operation data of "1 and 0". Through the above steps, a first set of operation data for each magnetic tunnel junction MTJ is determined for each row of magnetic memory cells with the magnetic tunnel junction MTJ flipped to a high resistance state or a low resistance state.
2) And (3) an operation stage. Referring to fig. 4, in the operation phase, the control signals written to the control lines (e.g., WWL1, WWL2, etc.) are turned off. For any column of magnetic memory cells (e.g., a first column), a second set of operational data for each magnetic tunnel junction MTJ of the column is determined by controlling the read bit line of each magnetic memory cell of the column, e.g., applying corresponding voltages V on read bit lines RBL1 and RBL2 1 And V 2 That is, the second set of operation data corresponding to the magnetic tunnel junctions MTJ (a and C) is "V 1 And V 2 ", wherein V 1 、V 2 May be "0" or "1". Connecting the second current control line SL1 to a fixed level (e.g. GND)Current i=v on the second current control line SL1 1 /R A +V 2 /R C . Wherein R is A 、R C First set of operating data, V, characterizing magnetic tunnel junctions, MTJs (A and C) 1 And V 2 A second set of operation data characterizing the magnetic tunnel junctions MTJ (a and C) and thus the current on the second current control line SL1 is read through the second current control line, i.e. a multiply-accumulate result of both sets of operands is obtained.
Fig. 5 is a flow chart of a method for preparing a magnetic memory array according to an embodiment of the invention, please refer to fig. 5, the method for preparing a magnetic memory array may include the following steps:
step S110: a magnetic memory cell is fabricated by fabricating a completed magnetic memory device and a write access transistor, the magnetic memory device including a SOT bottom electrode layer and a magnetic tunnel junction MTJ.
Preferably, preparing the magnetic memory device includes: preparing a heavy metal layer serving as the SOT bottom electrode layer; and forming the Magnetic Tunnel Junction (MTJ) by sequentially growing a free layer, a barrier layer and a pinning layer on the SOT bottom electrode layer.
Step S120: and connecting the first end of the write access transistor with the first end of the SOT bottom electrode layer.
Step S130: and arranging a plurality of prepared magnetic memory cells in an array, wherein for each row of magnetic memory cells, the grid electrodes of the writing memory transistors of the row are connected to form a writing control line, the Magnetic Tunnel Junctions (MTJs) of the row are connected to form a reading bit line, for each column of magnetic memory cells, the second ends of the writing memory transistors of the column are connected to form a first writing current control line, and the second ends of the SOT bottom electrode layers of the column are connected to form a second writing current control line.
As shown in FIG. 2, the prepared magnetic memory array has the gates of the write access transistors of each row of magnetic memory cells connected together to form a write control line (e.g., WWL1, WWL2, etc.), the second ends (source or drain) of the write access transistors of each column of magnetic memory cells connected together to form a first write current control line (e.g., BL1, BL2, etc.), and the second ends of the SOT bottom electrode layers of the column connected together to form a second write current control line (e.g., SL1, SL2, etc.). The magnetic tunnel junction MTJ tips of each row of magnetic memory cells are connected together to form a read bit line (e.g., RBL1, RBL2, etc.). By controlling the write control line, the first write current control line, and the second write current control line, data writing to the magnetic tunnel junction MTJ of the selected magnetic memory cell is completed, as shown in fig. 2 and the above examples. By controlling the read bit line and the second write current control line, data reading of the magnetic tunnel junction MTJ of the selected magnetic memory cell is completed, as shown in fig. 3 and the above examples, and will not be repeated here.
Accordingly, a magnetic memory array prepared in accordance with an embodiment of the present invention includes a plurality of magnetic memory cells arranged in an array, each magnetic memory cell having only a write access transistor, the read access transistor being removed. Compared with the magnetic memory array prepared by the existing magnetic memory unit, the embodiment of the invention has simpler circuit structure, smaller layout occupation and larger memory density.
FIG. 6 is a flowchart of a data access method for a magnetic memory array according to an embodiment of the present invention, please refer to FIG. 6, wherein the data access method is used for accessing data of the magnetic memory array shown in FIG. 3, and the data access method may include the following steps:
step S210: data writing to the magnetic tunnel junction MTJ of the selected magnetic memory cell is accomplished by controlling a write control line, a first write current control line, and the second write current control line.
Step S220: data reading of the magnetic tunnel junction MTJ of the selected magnetic memory cell is accomplished by controlling a read bit line and the second write current control line.
Preferably, step S110 may include: selecting the magnetic tunnel junction MTJ by controlling the write control line, the first write current control line, and the second write current control line; and generating write currents of different directions by controlling the first write current control line and the second write current control line to flip the selected magnetic tunnel junction MTJ to a high resistance state or a low resistance state.
Referring to fig. 2, taking the write to the magnetic memory device of the upper left magnetic memory cell as an example, the write control line WWL1 is controlled to be turned on, and at this time, the write control lines of other rows may be controlled to be turned off, for example, the write control line WWL2 is controlled to be turned off, and the read bit lines (for example, RBL1, RBL2, etc.) may be controlled to be suspended; a current path is formed through the write control line WWL1, the first write current control line BL1, and the second write current control line BL2 to select a magnetic memory cell (e.g., an upper left memory cell). The first write current control line and the second write current control line can independently control the direction of write current and whether the write current is suspended, for example, the current control line is used for conducting write current from the first current control line BL1 to the second current control line SL1 to the SOT bottom electrode layer of the selected magnetic storage device, and the free layer direction of the corresponding magnetic tunnel junction MTJ is controlled to be reversed, for example, the selected magnetic tunnel junction MTJ is reversed to be in a high resistance state; when the direction of the write current is the second current control line SL1 to the first current control line BL1, the free layer direction of the corresponding magnetic tunnel junction MTJ is controlled to flip, e.g., flip the selected magnetic tunnel junction MTJ to a low resistance state.
Referring to FIG. 3, the magnetic tunnel junction MTJ tips of each row of magnetic memory cells are connected together to form a read bit line (e.g., RBL1, RBL2, etc.), and data reading of the magnetic tunnel junction MTJ of a selected magnetic memory cell is accomplished by controlling the read bit line. For example, taking the case of reading the data of the upper left cell, the write control line (e.g., WWL1, WWL2, etc.) may be turned off, the other read bit line (e.g., RBL2, etc.), the first write current control line (e.g., BL1, BL2, etc.), the second write current control line (e.g., SL2, etc.), and the read current in the direction of the read bit line (RBL 1) to the second current control line (SL 1) may be applied to complete the data reading.
Preferably, the data access method further includes implementing a multiply-accumulate operation procedure: for each row of magnetic memory cells, determining a first set of operational data for each magnetic tunnel junction MTJ by controlling the write control line, the first write current control line, and the second write current control line for each row to flip the magnetic tunnel junction MTJ for each row into a high resistance state or a low resistance state; for any column of magnetic memory cells, determining a second set of operation data for each magnetic tunnel junction MTJ of the column by controlling the read bit line of each magnetic memory cell of the column, connecting the second write current control line of the column to a fixed level, reading the current on the second write current control line, and obtaining multiply-accumulate data for the first set of operation data and the second set of operation data for each magnetic tunnel junction MTJ of the column.
Taking two rows and two columns of magnetic storage arrays as an example, the multiply-accumulate operation of two groups of data is realized:
1) A first set of operational data for each magnetic tunnel junction MTJ is determined. Referring to fig. 2, in the first example, the write control line WWL1 is turned on, the control signals associated with the other rows are turned off, the first write current control lines (BL 1, BL2, etc.) and the second write current control lines (SL 1, SL2, etc.) are controlled, respectively, and the two magnetic memory cells in the first row are written to opposite states by generating write currents in different directions. For example, the magnetic tunnel junctions MTJ (a and B) are in a "low resistance, high resistance" state, or a "high resistance, low resistance" state; the "low resistance, high resistance" states of the magnetic tunnel junctions MTJ (a and B), for example, correspond to a first set of operation data of "1 and 0". Through the above steps, a first set of operation data for each magnetic tunnel junction MTJ is determined for each row of magnetic memory cells with the magnetic tunnel junction MTJ flipped to a high resistance state or a low resistance state.
2) And (3) an operation stage. Referring to fig. 4, in the operation phase, the control signals written to the control lines (e.g., WWL1, WWL2, etc.) are turned off. For any column of magnetic memory cells (e.g., a first column), a second set of operational data for each magnetic tunnel junction MTJ of the column is determined by controlling the read bit line of each magnetic memory cell of the column, e.g., applying corresponding voltages V on read bit lines RBL1 and RBL2 1 And V 2 That is, the second set of operation data corresponding to the magnetic tunnel junctions MTJ (a and C) is "V 1 And V 2 ", wherein V 1 、V 2 May be "0" or "1". Connecting the second current control line SL1 to a fixed level (e.g., GND), the current i=v on the second current control line SL1 1 /R A +V 2 /R C . Wherein R is A 、R C First set of operating data, V, characterizing magnetic tunnel junctions, MTJs (A and C) 1 And V 2 A second set of operation data characterizing the magnetic tunnel junctions MTJ (a and C) and thus the current on the second current control line SL1 is read through the second current control line, i.e. a multiply-accumulate result of both sets of operands is obtained.
The embodiment of the invention also provides electronic equipment, which comprises a processor and the magnetic storage array coupled with the processor.
Technical details and effects of the data access method and the electronic device provided by the embodiments of the present invention are similar to those of the magnetic storage array provided by the embodiments of the present invention, and reference may be made to the above, and details are not repeated here.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises an element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and changes may be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. which are within the spirit and principles of the present application are intended to be included within the scope of the claims of the present application.

Claims (10)

1. A magnetic memory array comprising a plurality of magnetic memory cells arranged in an array, each magnetic memory cell comprising a magnetic memory device comprising a SOT bottom electrode layer and a magnetic tunnel junction MTJ, and a write memory transistor having a first end connected to a first end of the SOT bottom electrode layer,
for each row of magnetic memory cells, the gates of the write access transistors of the row are connected to form a write control line, for each column of magnetic memory cells, the second ends of the write access transistors of the column are connected to form a first write current control line, the second ends of the SOT bottom electrode layers of the column are connected to form a second write current control line,
for each row of magnetic memory cells, the magnetic tunnel junctions MTJ of the row are connected to form a read bit line, and data reading of the magnetic tunnel junctions MTJ of the selected magnetic memory cell is accomplished by controlling the read bit line and the second write current control line.
2. The magnetic memory array of claim 1, wherein the memory array implements a multiply-accumulate operation process comprising:
for each row of magnetic memory cells, determining a first set of operational data for each magnetic tunnel junction MTJ by controlling the write control line, the first write current control line, and the second write current control line for each row to flip the magnetic tunnel junction MTJ for each row into a high resistance state or a low resistance state;
for any column of magnetic memory cells, determining a second set of operating data for each magnetic tunnel junction MTJ of the column by controlling the read bit line of each magnetic memory cell of the column,
and connecting the second write current control line of the column to a fixed level, and reading the current on the second write current control line to obtain multiply-accumulate data of the first group of operation data and the second group of operation data of each Magnetic Tunnel Junction (MTJ) of the column.
3. The magnetic memory array of claim 1, wherein the magnetic tunnel junction MTJ is selected by controlling the write control line, the first write current control line, and the second write current control line;
and generating write currents in different directions by controlling the first write current control line and the second write current control line so as to flip the selected Magnetic Tunnel Junction (MTJ) into a high-resistance state or a low-resistance state, thereby realizing data writing of the Magnetic Tunnel Junction (MTJ).
4. The magnetic memory array of claim 1, wherein the SOT bottom electrode layer is a heavy metal layer and the magnetic tunnel junction MTJ comprises a free layer, a barrier layer, and a pinned layer grown sequentially on the SOT bottom electrode layer.
5. A method of fabricating a magnetic memory array, the method comprising:
preparing a magnetic memory cell by preparing a finished magnetic memory device and a write access transistor, wherein the magnetic memory device comprises an SOT bottom electrode layer and a Magnetic Tunnel Junction (MTJ);
connecting a first end of the write access transistor with a first end of the SOT bottom electrode layer; and
a plurality of prepared magnetic memory cells are arranged in an array,
for each row of magnetic memory cells, the gates of the write memory transistors of the row are connected to form a write control line, the magnetic tunnel junctions of the row are connected to form a read bit line,
for each column of magnetic memory cells, the second ends of the write access transistors of the column are connected to form a first write current control line, and the second ends of the SOT bottom electrode layers of the column are connected to form a second write current control line.
6. The method of manufacturing a magnetic memory array of claim 5, wherein manufacturing the magnetic memory device comprises:
preparing a heavy metal layer serving as the SOT bottom electrode layer; and
and forming the Magnetic Tunnel Junction (MTJ) by sequentially growing a free layer, a barrier layer and a pinning layer on the SOT bottom electrode layer.
7. A method of data access to the magnetic storage array of claim 5 or 6, the method comprising:
completing data writing to the magnetic tunnel junction MTJ of the selected magnetic memory cell by controlling a write control line, a first write current control line, and the second write current control line; and
data reading of the magnetic tunnel junction MTJ of the selected magnetic memory cell is accomplished by controlling a read bit line and the second write current control line.
8. The data access method of claim 7, further comprising implementing a multiply-accumulate operation:
for each row of magnetic memory cells, determining a first set of operational data for each magnetic tunnel junction MTJ by controlling the write control line, the first write current control line, and the second write current control line for each row to flip the magnetic tunnel junction MTJ for each row into a high resistance state or a low resistance state; and
for any column of magnetic memory cells, determining a second set of operating data for each magnetic tunnel junction MTJ of the column by controlling the read bit line of each magnetic memory cell of the column,
and connecting the second write current control line of the column to a fixed level, and reading the current on the second write current control line to obtain multiply-accumulate data of the first group of operation data and the second group of operation data of each Magnetic Tunnel Junction (MTJ) of the column.
9. The method of claim 7, wherein the writing of data to the magnetic tunnel junction MTJ of the selected magnetic memory cell is accomplished by controlling the write control line, the first write current control line, and the second write current control line, comprising:
selecting the magnetic tunnel junction MTJ by controlling the write control line, the first write current control line, and the second write current control line; and
by controlling the first write current control line and the second write current control line, write currents in different directions are generated to flip the selected magnetic tunnel junction MTJ into a high resistance state or a low resistance state.
10. An electronic device comprising a processor and the magnetic storage array of any of claims 1-4 coupled to the processor.
CN202311449059.4A 2023-11-02 2023-11-02 Magnetic memory array, preparation method thereof, data access method and electronic equipment Pending CN117479548A (en)

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