CN117479037A - Pixel circuit, control method and image sensor - Google Patents

Abstract

The invention describes a pixel circuit comprising: a pixel array including a plurality of pixel units arranged in a bayer array, each pixel unit being composed of n ² A pixel composition having the same color filter; the transmission control line respectively triggers and turns on the transmission transistor of each pixel in the first pixel unit and the second pixel unit so as to output a first output value corresponding to each pixel in the first pixel unit and a second output value corresponding to each pixel in the second pixel unit, and focus control is performed based on the first output value and the second output value; or the transmission control line respectively triggers and turns on the transmission transistor of each pixel in the first pixel unit and the second pixel unit to output a first output value and a second output value corresponding to each pixel in the first pixel unitAnd a third output value corresponding to each pixel in the pixel unit and the second pixel unit, and performing focusing control based on the first output value and the third output value. The invention also describes a control method of the pixel circuit and an image sensor comprising the pixel circuit.

Description

Pixel circuit, control method and image sensor

Technical Field

The present invention relates to the field of image sensors, and more particularly, to a pixel circuit, a control method thereof, and an image sensor including the pixel circuit.

Background

The automatic focusing technology plays an important role in the image sensor, and especially when consumer electronic products such as mobile phones are used for shooting, the automatic focusing technology can further improve user experience. Currently, phase detection autofocus (Phase Detection Auto Focus, PDAF) technology is common in high-end CMOS image sensor chips. The PDAF is realized by selecting some pixel points in a pixel array as phase detection pixels, shielding the left half and the right half (or the upper half and the lower half) of the phase detection pixels respectively by special materials, respectively obtaining left phase information and right phase information of incident light during reading, and calculating the amount of lens movement required by an algorithm. The disadvantage of this method is that: the pixels used for phase detection cannot be imaged normally, and algorithm compensation is performed on the actual image according to imaging information of surrounding pixels, so that the number of pixels used for phase detection cannot be too large (for example, 3% or 6% PDAF); at the same time, the light quantity is small under the condition of dark light, which leads to insufficient accuracy of phase detection and compensation.

With the increasing of the image sensor array, in 1 hundred million or even more than 2 hundred million pixels, the data size, the frame rate and the power consumption are continuously increased along with the increasing of the array, and in the existing photographing technology, various optimization schemes are required to promote the phase focusing technology so as to meet the performance requirements in terms of the data size, the power consumption and the frame rate.

Disclosure of Invention

In view of the above, the present invention provides a pixel circuit, a control method of the pixel circuit, and an image sensor including the pixel circuit.

The present invention provides a pixel circuit, comprising:

a pixel array including a plurality of pixel units arranged in a bayer array, each ofThe pixel unit is composed of n ² Each pixel comprises a photoelectric conversion element and a transmission transistor, and n is an even number greater than or equal to 4;

a transfer control line configured to control a transfer transistor that selects a pixel to be read to be turned on to transfer accumulated charges of the photoelectric conversion element in the pixel to a floating diffusion point;

a bit line configured to read out a pixel signal of a pixel to be read;

wherein, at least a plurality of pixel units comprise a first pixel unit and a second pixel unit; the transmission control line triggers and turns on the transmission transistor of each pixel in the first pixel unit so as to output a first output value corresponding to each pixel in the first pixel unit through the bit line, and the transmission control line triggers and turns on the transmission transistor of each pixel in the second pixel unit so as to output a second output value corresponding to each pixel in the second pixel unit through the bit line, and focus control is performed based on the first output value and the second output value; or,

the transmission control line triggers and turns on the transmission transistor of each pixel in the first pixel unit so as to output a first output value corresponding to each pixel in the first pixel unit through the bit line, and the transmission control line triggers and turns on the transmission transistor of each pixel in the second pixel unit so as to output a third output value corresponding to each pixel in the first pixel unit and the second pixel unit through the bit line, and focus control is performed based on the first output value and the third output value.

Optionally, the first pixel unit is composed of pixels located in odd columns in the pixel unit, and the second pixel unit is composed of pixels located in even columns in the pixel unit; alternatively, the first pixel unit is composed of pixels located in even columns in the pixel unit, and the second pixel unit is composed of pixels located in odd columns in the pixel unit.

Optionally, the first pixel unit is composed of pixels located in odd lines in the pixel unit, and the second pixel unit is composed of pixels located in even lines in the pixel unit; alternatively, the first pixel unit is composed of pixels located in even rows in the pixel unit, and the second pixel unit is composed of pixels located in odd rows in the pixel unit.

Optionally, n=4, each pixel unit includes 4 four-shared pixel units, each four-shared pixel unit is composed of 2×2 pixels sharing one microlens, and the transfer transistors of the 2×2 pixels are coupled to the same floating diffusion point.

Optionally, in a single pixel unit: the bit lines correspondingly arranged comprise a first bit line and a second bit line, wherein the first bit line is arranged corresponding to two four shared pixel units positioned in the same column, and the second bit line is arranged corresponding to the other two four shared pixel units positioned in the same column.

Optionally, the first bit line and the second bit line are shorted to combine and read out pixel signals of four shared pixel cells located in the same row in the pixel cells.

Optionally, four shared pixel units located in the same column in the pixel units simultaneously receive the row selection control signal, so as to read out the pixel signals through the first bit line or the second bit line in a merging way.

Optionally, four sharing pixel units located in the same column in the pixel units receive the row selection control signal at the same time, and the first bit line and the second bit line are in short circuit, so that the pixel signals of the four sharing pixel units in the pixel units are combined and read out.

Optionally, a combination control switch triggered to be conducted by a combination control signal is arranged between the first bit line and the second bit line so as to control whether the first bit line is short-circuited with the second bit line or not.

Optionally, the pixel circuit further includes: a reset transistor coupled between the first voltage source and the floating diffusion point and configured to reset the pixel circuit; and/or an amplifying transistor coupled to the floating diffusion point and configured to amplify the voltage signal of the floating diffusion point; and/or a dual conversion gain control unit coupled between the reset transistor and the floating diffusion point, configured to implement gain control; and/or a row selection transistor, wherein the row selection transistor is coupled between the output end of the amplifying transistor and the bit line, and the grid electrode of the row selection transistor receives a row selection control signal and is used for outputting a voltage signal of the floating diffusion point.

Optionally, two bit lines are correspondingly disposed in the four shared pixel units of each column, odd columns in the bit lines of adjacent columns are shorted with each other to form a first bit line group, even columns in the bit lines of adjacent columns are shorted with each other to form a second bit line group, so that the four shared pixel units located in the same row in the pixel units are combined and read through the first bit line group or the second bit line group.

Alternatively, four shared pixel units located in the same column in the pixel units simultaneously receive the row selection control signal to be combined and read out through the first bit line group or the second bit line.

Alternatively, two adjacent pixel cells having different color filters in the column direction receive the row selection control signal simultaneously, and one is read out through the first bit line group and the other is read out through the second bit line group.

The invention also provides an image sensor comprising the pixel circuit.

The invention also provides a control method of the pixel circuit, which comprises the following steps:

triggering and turning on the transmission transistor of each pixel in the first pixel unit to obtain left focusing phase information, resetting a floating diffusion point in a pixel circuit, triggering and turning on the transmission transistor of each pixel in the second pixel unit to obtain right focusing phase information, performing phase difference based on the left focusing phase information and the right focusing phase information, and performing focusing control; or,

triggering and turning on the transmission transistor of each pixel in the first pixel unit to obtain upper focusing phase information, resetting a floating diffusion point in a pixel circuit, triggering and turning on the transmission transistor of each pixel in the second pixel unit to obtain lower focusing phase information, performing phase difference based on the upper focusing phase information and the lower focusing phase information, and performing focusing control; or,

triggering and conducting the transmission transistor of each pixel in the first pixel unit to obtain left focusing phase information or right focusing phase information, triggering and conducting the transmission transistor of each pixel in the second pixel unit to obtain image information, performing phase difference based on the left focusing phase information or right focusing phase information and the image information, and performing focusing control; or,

and triggering and conducting the transmission transistor of each pixel in the first pixel unit to obtain upper focusing phase information or lower focusing phase information, triggering and conducting the transmission transistor of each pixel in the second pixel unit to obtain image information, and performing focusing control based on the upper focusing phase information or lower focusing phase information and the image information phase difference.

Compared with the prior art, the invention has at least one of the following outstanding advantages:

the invention designs a pixel structure which can be used for 1 hundred million pixels and 2 hundred million pixels so as to improve the resolution of an image sensor. The first focusing phase information and the second focusing phase information or the first focusing phase information and the image information are utilized to perform phase calculation, so that the density of the phase point is 100%, and the technical problem that the pixel point of phase detection cannot be imaged normally is solved; meanwhile, the combined readout in the pixel circuit brings a pixel photosensitive area with sensitivity equivalent up to a plurality of times, so that the signal to noise ratio is greatly improved, and the phase focusing capability under weak light can be further optimized.

Drawings

Fig. 1 is a schematic diagram of a partial structure of a pixel array provided in the present application;

FIG. 2 is a schematic diagram of a pixel circuit corresponding to the pixel array shown in FIG. 1;

fig. 3 is a schematic diagram of an implementation of phase focusing provided in the present application;

fig. 4 is a schematic structural diagram of a pixel array provided in the present application;

FIG. 5 is a timing control diagram of the pixel circuit shown in FIG. 4;

FIG. 6 is another timing control diagram of the pixel circuit shown in FIG. 4;

FIG. 7 is a timing control diagram of the pixel circuit shown in FIG. 4;

FIG. 8 is a timing control diagram of the pixel circuit shown in FIG. 4;

FIG. 9 is a schematic diagram of another pixel array according to the present disclosure;

fig. 10 is a schematic structural diagram of an image sensor provided in the present application.

Detailed Description

In order that the above objects, features and advantages of the invention will be readily understood, a further description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

It is noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be embodied in many other forms than those herein described, and those skilled in the art may readily devise numerous other arrangements that do not depart from the spirit of the invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

Referring to fig. 1, a pixel array 10 includes a plurality of pixel units 100 arranged in a bayer array RGGB, each pixel unit 100 is formed by n ² The pixels 101 having the same color filters are composed, and n is an even number of 4 or more.

It will be appreciated that in fig. 1, n=4, i.e. one pixel unit is composed of 16 pixels with the same color filter, in other embodiments of the present application, n may be equal to 6, i.e. one pixel unit is composed of 36 pixels with the same color filter, or n may be equal to 8, i.e. one pixel unit is composed of 64 pixels with the same color filter, and the pixel units in the pixel array are all arranged in the form of a bayer array RGGB, and the layout of such a pixel array may be applied in 1 hundred million or even more than 2 hundred million pixels, thereby improving the resolution of the image sensor.

Fig. 2 is a schematic structural diagram of a pixel circuit corresponding to the pixel array shown in fig. 1. Wherein each pixel comprises a photoelectric conversion element PD and a transfer transistor TX. The pixel circuit further includes: a transfer control line TX configured to control a transfer transistor TX that selects and turns on a pixel to be read to transfer accumulated charges of the photoelectric conversion element PD in the pixel to the floating diffusion FD. As shown in fig. 2, the pixel circuit includes four transmission control lines TXA, TXB, TXC and TXD, wherein the transmission control line TXA corresponds to the transmission transistor TXA of the PD1, the transmission control line TXB corresponds to the transmission transistor TXB of the PD2, the transmission control line TXC corresponds to the transmission transistor TXC of the PD3, and the transmission control line TXD corresponds to the transmission transistor TXD of the PD4 to turn on the transmission transistors of the pixels, respectively. The pixel circuit further includes: and a bit line configured to read out a pixel signal of a pixel to be read.

It should be noted that, in the following description, n=4 is taken as an example, that is, one pixel unit is formed by 16 pixels with the same color filter, which is not described in detail later. Referring to fig. 1 and 2 in combination, each pixel unit 100 includes 4 four-shared pixel units 200, each four-shared pixel unit 200 is composed of 2×2 pixels 101 sharing one microlens, and the transfer transistors TX of the 2×2 pixels are coupled to the same floating diffusion FD.

Optionally, with continued reference to fig. 2, the pixel circuit further includes: a reset transistor RST coupled between the first voltage source and the floating diffusion FD and configured to reset the pixel circuit; and/or an amplifying transistor SF coupled to the floating diffusion FD and configured to amplify the voltage signal of the floating diffusion FD; and/or a dual conversion gain control unit DCG coupled between the reset transistor RST and the floating diffusion FD, configured to implement gain control; and/or, a row selection transistor RS, the row selection transistor RS is coupled between the output end of the amplifying transistor SF and the bit line bit, and a gate of the row selection transistor RS receives a row selection control signal RS for outputting a voltage signal of the floating diffusion FD.

The at least several pixel units include a first pixel unit and a second pixel unit. It will be understood that at least a number of pixel units means that some of the pixel units in the pixel array may be selected for phase focusing, or all of the pixel units in the pixel array may be selected for phase focusing. Optionally, the first pixel unit is composed of pixels in odd columns in the pixel unit, and the second pixel unit is composed of pixels in even columns in the pixel unit, so that focusing control can be realized by respectively obtaining left and right focusing phase information, and focusing control can also be realized by obtaining left focusing phase information and total image information of the pixel unit; or the first pixel unit consists of pixels in even columns in the pixel unit, the second pixel unit consists of pixels in odd columns in the pixel unit, so that focusing control can be realized by respectively obtaining left and right focusing phase information, and focusing control can also be realized by obtaining right focusing phase information and total image information of the pixel unit. Optionally, the first pixel unit is composed of pixels located in odd lines in the pixel unit, and the second pixel unit is composed of pixels located in even lines in the pixel unit, so that focusing control can be realized by respectively obtaining upper and lower focusing phase information, and focusing control can be realized by obtaining upper focusing phase information and total image information of the pixel unit; or the first pixel unit consists of pixels in even lines in the pixel unit, and the second pixel unit consists of pixels in odd lines in the pixel unit, so that focusing control can be realized by respectively obtaining upper and lower focusing phase information, and focusing control can also be realized by obtaining lower focusing phase information and total image information of the pixel unit.

Fig. 3 is a schematic diagram of an implementation of phase focusing provided in the present application, as shown in fig. 3. Taking left-right focusing control as an example, a first pixel unit L comprises pixels L0-L7, a second pixel unit R comprises pixels R0-R7, a transmission control line triggers and turns on transmission transistors of the pixels L0-L7 in the first pixel unit L so as to output first output values corresponding to the pixels L0-L7 in the first pixel unit L through a bit line bit, then a floating diffusion point of the pixel unit is reset so as to clear phase information corresponding to the first output values, and then the transmission control line triggers and turns on transmission transistors of the pixels R0-R7 in the second pixel unit R so as to output second output values corresponding to the pixels R0-R7 in the second pixel unit R through the bit line, and focusing control is performed based on the first output values and the second output values; or the transmission control line triggers and turns on the transmission transistor of each pixel L0-L7 in the first pixel unit L so as to output a first output value corresponding to each pixel L0-L7 in the first pixel unit L through a bit line, and the transmission control line further triggers and turns on the transmission transistor of R0-R7 in the second pixel unit R so as to output a third output value through the bit line, and the voltage value corresponding to the phase information of each pixel L0-L7 in the first pixel unit L still remains at a floating diffusion point, so that the output third output value is a value corresponding to the total image information of each pixel L0-L7 in the first pixel unit L and each pixel R0-R7 in the second pixel unit R, and focus control is performed based on the first output value and the third output value.

Therefore, in this application, the phase difference can be calculated by combining (l0+l1)/(l2+l3)/(l4+l5)/(l6+l7) to read out the first focus phase information and combining (r0+r1)/(r2+r3)/(r4+r5)/(r6+r7) in a similar manner to read out the second focus phase information, which is called the RSRS pattern, and performing the subsequent digital processing on the first focus phase information and the second focus phase information, thereby performing the auto focus. The first focusing phase information may be read out by combining (l0+l1)/(l2+l3)/(l4+l5)/(l6+l7), and the floating diffusion FD in the pixel circuit may also hold the voltage corresponding to the first focusing phase information, and the phase difference may be calculated by turning on the transfer transistor corresponding to each pixel of (r0+r1)/(r2+r3)/(r4+r5)/(r6+r7), and superimposing the two pixel signals of (l0+l1)/(l2+l3)/(l4+l7) and (r0+r1)/(r2+r3)/(r4+r5)/(r6+r7) to obtain the total image information after addition. This mode, known as RSS mode, can optimize power consumption and dark optical signal to noise ratio, and may be a mainstream application in 1 hundred million or even more than 2 hundred million pixels.

It should be noted that both of the above-mentioned phase focusing modes can be applied to all pixels in the pixel array to implement the omnidirectional auto-focusing (ALL Direction Auto Focus, ADAF) technique in the pixel array.

With continued reference to fig. 4, fig. 4 is a schematic structural diagram of a pixel array provided in the present application. In a single pixel cell: the bit line correspondingly arranged comprises a first bit line and a second bit line, wherein the first bit line is arranged corresponding to two four shared pixel units positioned in the same column, and the second bit line is arranged corresponding to the other two four shared pixel units positioned in the same column. As shown in fig. 4, among the 4 four sharing pixel units of Column0 and Column1 in Row0 and Row1, two four sharing pixel units located in Column0 correspond to the first bit line bit 0, and two four sharing pixel units located in Column1 correspond to the second bit line bit 1, so as to read out the image signals respectively.

Optionally, with continued reference to fig. 4, a combination control switch triggered to be turned on by the combination control signal hbin_ctrl may be disposed between the first bit line and the second bit line to control whether the first bit line is shorted with the second bit line.

In some embodiments of the present application, as shown in fig. 5, when Row0 and Row1 are read, first, the transmission control lines TXB and TXD control the transmission transistors TXB and TXD of the PD2 and PD4 to be turned on, and the pixel signals of the pixels located in the odd columns in the pixel units are read out to obtain the left focus phase information; then, the reset transistor RST resets the floating diffusion FD of the pixel circuit to clear the left focus phase information in the floating diffusion FD; then, the transfer control lines TXA and TXC control the transfer transistors TXA and TXC of the PD1 and PD3 to be turned on, and read out the pixel signals of the pixels located in even columns in the pixel unit to obtain right focus phase information.

In some embodiments of the present application, as shown in fig. 6-8, when Row0 and/or Row1 is read, first, the transmission control lines TXB and TXD control the transmission transistors TXB and TXD of the PD2 and PD4 to be turned on, and the pixel signals of the pixels located in the odd columns in the pixel units are read out to obtain the left focus phase information; then, the transmission control lines TXA and TXC control the transmission transistors TXA and TXC of the PD1 and PD3 to be turned on, and since the corresponding voltage of the left focus phase information is still remained in the floating diffusion FD, the corresponding voltage is overlapped with the right focus phase information of the pixels located in the even columns in the pixel unit, so as to obtain the image information of the pixel unit.

As shown in fig. 6, the first bit line and the second bit line are shorted by controlling the combined control signal hbin_ctrl to be at a high level, so that the pixel signals of four shared pixel cells located in the same row in the pixel cells are combined and read out, thereby realizing lateral combining (H2 binning). Because the color filters of the two four-shared pixel units located in the same Row in the pixel units are the same, and the four-shared pixel units located in the same Row receive the same Row selection control signal, the total image signals can be read out through the short circuit of the two bit lines and then sent to an analog-to-digital converter AD for subsequent data processing, for example, when Row0 Row is read, the pixels of Column0/Column1 are binned, and the binned data can be gated and output from Column0 or Column1 in the Column direction, so that the pixels in the Column direction are sparse, the data is halved, and the frame rate is improved. And when reading data of a certain row in the transverse binding process, only one AD of the two AD is needed to be selected as two bit lines are short-circuited, and the rest AD can be idle.

As shown in fig. 7, four shared pixel units located in the same column in the pixel units simultaneously receive a row selection control signal to merge and read out the pixel signals through the first bit line or the second bit line, so as to realize vertical merging (V2 binning). Because the color filters of two four-shared pixel units located in the same column in the pixel units are the same, the two four-shared pixel units receive the same Row selection control signal, for example, row0 and Row1 are the same color filters, the same Row selection control signal can be adopted by rs <0> and rs <1>, and the rs signal of one Row can be selected in the longitudinal binding process. The total line number is half less, the frame rate of pixel processing is further improved, and the image capturing aiming at slow motion can be further improved.

As shown in fig. 8, four shared pixel units located in the same column in the pixel units simultaneously receive a row selection control signal, and control the combined control signal hbin_ctrl to be at a high level so as to short the first bit line and the second bit line, so that the pixel signals of the four shared pixel units in the pixel units are combined and read out, thereby realizing horizontal and vertical combination (V2H 2 binding). Because the color filters of four sharing pixel units in the pixel unit are the same, the four sharing pixel units in different columns in the pixel unit can simultaneously receive the row selection control signals, the two bit lines are short-circuited, and the total image signals are read out to an AD for subsequent data processing. Because the Column direction of the pixel array is sparse when the horizontal binning is performed, an AD is in an idle state in the Column direction, and the row direction of the pixel array is sparse when the vertical binning is performed, when the scheme of the horizontal-vertical binning is adopted, the simultaneous horizontal and vertical binning can be realized, for example, when Column0/Column1 horizontal binning is performed, the bit line0 and the bit line1 are short-circuited, and the data is output through the AD0 together after the binning is assumed, and the AD1 is idle; and simultaneously makes Row0/1 longitudinal binding, then at this time, the image information of four-shared pixel units of Row0/1 and Column0/Column1 is simultaneously output data through AD 0. Thus, not only the data of 2 times of the transverse data is halved, but also the data of 2 times of the longitudinal data is halved. The whole realization effect is that the data output quantity at the same moment is 1/2 before unbinding, and the whole data quantity is changed into 1/4 of the original data quantity, so that the frame rate of image processing is greatly improved, and more slow actions can be captured. In addition, the first focusing phase information and the second focusing phase information or the first focusing phase information and the image information can be utilized to perform phase calculation, so that the density of the phase point is 100%, and simultaneously, the binning brings about a pixel photosensitive area with sensitivity equivalent to 16 times, so that the signal to noise ratio is greatly improved, and the phase focusing capability under weak light can be further optimized.

In some embodiments of the present application, two bit lines are correspondingly disposed in four shared pixel units of each column, odd columns in the bit lines of adjacent columns are shorted to each other to form a first bit line group, even columns in the bit lines of adjacent columns are shorted to each other to form a second bit line group, so that four shared pixel units located in the same row in the pixel units are combined and read out through the first bit line group or the second bit line group. As shown in fig. 9, fig. 9 is a schematic structural diagram of another pixel array provided in the present application; in this embodiment of the present application, a 2x bit line method is used to implement a binding mode, two bit lines are correspondingly provided for each Column of four shared pixel units, and four bit lines, namely, bl0_0, bl1_0, bl0_1 and bl1_1, are provided in fig. 9, wherein bl0_0, bl0_1 and four shared pixel units located on Column0 are correspondingly provided, and bl1_0, bl1_1 and four shared pixel units located on Column1 are correspondingly provided. It will be appreciated that the corresponding arrangement is not specifically referred to herein as a connection relationship. The specific implementation mode of implementing the binding by 2x bit line is as follows: when Column0/Column1 is laterally pinned, a first bit line group formed by shorting bl0_0 and bl1_0 in odd columns in the bit lines is quantized by AD0, and a second bit line group formed by shorting bl0_1 and bl1_1 in even columns in the bit lines is quantized by AD 1. According to the embodiment of the application, all the AD are in the working state in the transverse binding process by adopting the mode of 2x bit line and two-by-two short circuit, and idle AD does not exist, so that the efficiency of subsequent data processing is improved.

Optionally, four shared pixel units located in the same column in the pixel unit simultaneously receive the row selection control signals, so that the longitudinal combined readout in the pixel unit can be realized through the combination and readout of the first bit line group or the second bit line. And the bit lines are in double short circuit to enable four sharing pixel units positioned in the same row in the pixel units to be read out in a merging way, and when the four sharing pixel units positioned in the same column in the pixel units simultaneously receive row selection control signals, the horizontal and vertical merging read out can be realized, namely, the merging read out of all four sharing pixel units in the pixel units can be realized.

In some embodiments of the present application, two adjacent pixel cells having different color filters in the column direction receive row selection control signals simultaneously, and one is read out through a first bit line group and the other is read out through a second bit line group. With continued reference to fig. 9, when Row0/Row1 and Row2/Row 3 respectively perform vertical alignment, the four rows receive Row selection control signals simultaneously, then at this time, four shared pixel units corresponding to Row0/Row1 and Column0/Column1 are output through a first bit line group formed by shorting BL0_0 and BL1_0 simultaneously, data is output through AD0 quantization, and four shared pixel units corresponding to Row2/Row 3 and Column0/Column1 are output through a second bit line group formed by shorting BL0_1 and BL1 simultaneously, and data is output through AD1 quantization, thereby realizing horizontal vertical alignment in the pixel unit. According to the embodiment of the application, through selecting 4 rows on the corresponding columns at the same time, all the AD is in the working state, and idle AD does not exist, so that the efficiency of subsequent data processing is improved.

Referring to fig. 10, as shown in fig. 10, the present application further provides an image sensor 1000, which includes a pixel array 1100, the pixel array 1100 is arranged in rows and columns, the pixel array in the pixel array 1100 may be the pixel structure shown in fig. 4 or fig. 9, the pixel circuit structure may be the pixel structure shown in fig. 2, and the detailed description is omitted herein.

In addition, as an exemplary embodiment, the image sensor 1000 further includes a logic control module 1200, a row driving module 1300, a column driving module 1400, a column a/D converting module 1500, and an image processing module 1600; wherein:

the logic control module 1200 is used for controlling the working sequential logic of the whole system;

one end of the row driving module 1300 and one end of the column driving module 1400 are connected with the logic control module 1200, and the other end of the row driving module is coupled with the pixel array 1100, and is used for driving and controlling each control signal line in the pixel array 1100; specifically, the row driving module 1300 is configured to provide corresponding row control signals to the pixel array 1100; the column driving module 1400 is used for providing corresponding column control signals to the pixel array 1100;

the column a/D conversion module 1500 corresponds to each column of pixels in the pixel array 1100, and is configured to implement analog/digital conversion of a column signal under the control of the logic control module 120;

the image processing module 1600 is used for performing image processing on the image digital signal output by the column a/D conversion module 150 under the control of the logic control module 1200.

The application also provides a control method of the pixel circuit, which at least comprises the following steps:

s10: triggering and conducting a transmission transistor of each pixel in the first pixel unit to obtain left focusing phase information;

s11: resetting a floating diffusion point in a pixel circuit;

s12: triggering and conducting a transmission transistor of each pixel in the second pixel unit to obtain right focusing phase information;

s13: and performing phase difference based on the left focusing phase information and the right focusing phase information, and performing focusing control.

Resetting the floating diffusion point in the pixel circuit before triggering and conducting the transmission transistor of each pixel in the second pixel unit to obtain right focusing phase information so as to empty the corresponding voltage value of the left focusing phase information in the floating diffusion point, and then triggering and conducting the transmission transistor of each pixel in the second pixel unit to obtain right focusing phase information.

In some embodiments of the present application, at least the following steps are included:

s20: the upper focusing phase information is obtained by triggering and conducting the transmission transistor of each pixel in the first pixel unit;

s21: resetting a floating diffusion point in a pixel circuit;

s22: triggering and conducting a transmission transistor of each pixel in the second pixel unit to obtain lower focusing phase information;

s23: and performing phase difference based on the upper focusing phase information and the lower focusing phase information, and performing focusing control.

And resetting the floating diffusion point in the pixel circuit before triggering and conducting the transmission transistor of each pixel in the second pixel unit to obtain right focusing phase information so as to empty the corresponding voltage value of the upper focusing phase information in the floating diffusion point, and then triggering and conducting the transmission transistor of each pixel in the second pixel unit to obtain lower focusing phase information.

In some embodiments of the present application, at least the following steps are included:

s30: triggering and conducting a transmission transistor of each pixel in the first pixel unit to obtain left focusing phase information or right focusing phase information;

s31: triggering and conducting a transmission transistor of each pixel in the second pixel unit to obtain image information;

s32: and performing focusing control by performing phase difference based on the left focusing phase information or the right focusing phase information and the image information.

Because the left focusing phase information or the right focusing phase information is obtained by transferring the charge of the first pixel unit to the floating diffusion point, the floating diffusion point further generates a voltage value corresponding to one of the left focusing phase information or the right focusing phase information, at the moment, the transmission transistor of each pixel in the second pixel unit is directly triggered and turned on, and the charge of the photoelectric conversion element of the second pixel unit is transferred to the floating diffusion point, so that the image information after the left focusing phase information and the right focusing phase information are overlapped can be obtained.

In some embodiments of the present application, at least the following steps are included:

s40: triggering and conducting a transmission transistor of each pixel in the first pixel unit to obtain upper focusing phase information or lower focusing phase information;

s41: triggering and conducting a transmission transistor of each pixel in the second pixel unit to obtain image information;

s42: and performing focus control based on the upper focus phase information or the lower focus phase information and the image information phase difference.

Because the upper focusing phase information or the lower focusing phase information is obtained by transferring the charge of the first pixel unit to a floating diffusion point, the floating diffusion point further generates a voltage value corresponding to one of the upper focusing phase information or the lower focusing phase information, at the moment, the transmission transistor of each pixel in the second pixel unit is directly triggered and turned on, and the charge of the photoelectric conversion element of the second pixel unit is transferred to the floating diffusion point, so that the image information after the upper focusing phase information and the lower focusing phase information are overlapped can be obtained.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (15)

1. A pixel circuit, comprising:

a pixel array including a plurality of pixel units arranged in a bayer array, each of the pixel units being composed of n ² A pixel composition having the same color filter, each of the pixels including a photoelectric conversion element and a transfer transistor, and n being an even number of 4 or more;

a transfer control line configured to control a transfer transistor that selects and turns on the pixel to be read to transfer accumulated charges of photoelectric conversion elements in the pixel to a floating diffusion point;

a bit line configured to read out a pixel signal of the pixel to be read;

wherein at least a plurality of the pixel units comprise a first pixel unit and a second pixel unit; the transmission control line is configured to trigger and turn on a transmission transistor of each pixel in the first pixel unit so as to output a first output value corresponding to each pixel in the first pixel unit through the bit line, and is further configured to trigger and turn on a transmission transistor of each pixel in the second pixel unit so as to output a second output value corresponding to each pixel in the second pixel unit through the bit line, and perform focus control based on the first output value and the second output value; or,

the transmission control line is configured to trigger and turn on a transmission transistor of each pixel in the first pixel unit so as to output a first output value corresponding to each pixel in the first pixel unit through the bit line, and is further configured to trigger and turn on a transmission transistor of each pixel in the second pixel unit so as to output a third output value corresponding to each pixel in the first pixel unit and the second pixel unit through the bit line, and perform focus control based on the first output value and the third output value.

2. The pixel circuit of claim 1, wherein the first pixel cell is comprised of pixels in odd columns in the pixel cell and the second pixel cell is comprised of pixels in even columns in the pixel cell; or,

the first pixel unit is composed of pixels in even columns in the pixel unit, and the second pixel unit is composed of pixels in odd columns in the pixel unit.

3. The pixel circuit of claim 1 wherein said first pixel cell is comprised of pixels in odd rows of said pixel cells and said second pixel cell is comprised of pixels in even rows of said pixel cells; or,

the first pixel unit is composed of pixels located in even lines in the pixel unit, and the second pixel unit is composed of pixels located in odd lines in the pixel unit.

4. The pixel circuit of claim 1 wherein n = 4, each of the pixel cells comprises 4 four shared pixel cells, each of the four shared pixel cells consisting of 2x 2 pixels sharing a microlens, and the transfer transistors of the 2x 2 pixels are coupled to the same floating diffusion point.

5. The pixel circuit of claim 4, wherein in a single one of said pixel cells:

the bit lines correspondingly arranged comprise a first bit line and a second bit line, wherein the first bit line is arranged corresponding to two four shared pixel units positioned in the same column, and the second bit line is arranged corresponding to the other two four shared pixel units positioned in the same column.

6. The pixel circuit of claim 5, wherein the first bit line and the second bit line are shorted to merge pixel signals of the four shared pixel cells located in the same row of the pixel cells.

7. The pixel circuit of claim 5, wherein the four shared pixel cells in the same column of the pixel cells simultaneously receive a row select control signal to read out pixel signals through the first bit line or the second bit line in a merged manner.

8. The pixel circuit of claim 5 wherein the four shared pixel cells in the same column of pixel cells receive a row select control signal simultaneously, the first bit line and the second bit line being shorted to combine and read pixel signals of each of the four shared pixel cells.

9. A pixel circuit according to any one of claims 5 to 8, wherein a combination control switch is provided between the first bit line and the second bit line, which is triggered to turn on by a combination control signal, to control whether the first bit line is shorted with the second bit line.

10. The pixel circuit of claim 4, wherein the pixel circuit further comprises:

a reset transistor coupled between a first voltage source and the floating diffusion point, configured to reset the pixel circuit; and/or the number of the groups of groups,

an amplifying transistor coupled to the floating diffusion point and configured to amplify and output a voltage signal of the floating diffusion point; and/or the number of the groups of groups,

a dual conversion gain control unit coupled between the reset transistor and the floating diffusion point and configured to implement gain control; and/or the number of the groups of groups,

and the grid electrode of the row selection transistor is used for receiving a row selection control signal and outputting a voltage signal of the floating diffusion point.

11. The pixel circuit of claim 4 wherein said four shared pixel cells of each column are each provided with two bit lines, odd ones of said bit lines of adjacent columns being shorted to each other to form a first bit line group, and even ones of said bit lines of adjacent columns being shorted to each other to form a second bit line group, such that said four shared pixel cells of the same row within said pixel cells are combined and read out by said first bit line group or said second bit line.

12. The pixel circuit of claim 11, wherein the four shared pixel cells located in the same column within the pixel cell simultaneously receive a row select control signal to be combined and read out through the first bit line group or the second bit line.

13. The pixel circuit of claim 12, wherein two adjacent pixel cells having different color filters in the column direction receive row select control signals simultaneously, and one is read out through the first bit line group and the other is read out through the second bit line group.

14. An image sensor comprising a pixel circuit as claimed in any one of claims 1 to 13.

15. A control method of a pixel circuit according to any one of claims 1 to 13, characterized in that the control method comprises:

triggering and conducting the transmission transistor of each pixel in the first pixel unit to obtain left focusing phase information, resetting a floating diffusion point in the pixel circuit, triggering and conducting the transmission transistor of each pixel in the second pixel unit to obtain right focusing phase information, performing phase difference based on the left focusing phase information and the right focusing phase information, and performing focusing control; or,

triggering and conducting the transmission transistor of each pixel in the first pixel unit to obtain upper focusing phase information, resetting a floating diffusion point in the pixel circuit, triggering and conducting the transmission transistor of each pixel in the second pixel unit to obtain lower focusing phase information, performing phase difference based on the upper focusing phase information and the lower focusing phase information, and performing focusing control; or,

triggering and conducting the transmission transistor of each pixel in the first pixel unit to obtain left focusing phase information or right focusing phase information, triggering and conducting the transmission transistor of each pixel in the second pixel unit to obtain image information, performing phase difference based on the left focusing phase information or right focusing phase information and the image information, and performing focusing control; or,

and triggering and conducting the transmission transistor of each pixel in the first pixel unit to obtain upper focusing phase information or lower focusing phase information, triggering and conducting the transmission transistor of each pixel in the second pixel unit to obtain image information, and performing focusing control based on the upper focusing phase information or lower focusing phase information and the image information phase difference.