CN117478493A - Initialization method and system for local area network switch - Google Patents

Abstract

The method is applied to a system comprising h local area network switches, the system comprises m processors for initializing the h local area network switches, h is more than or equal to 2, m is more than or equal to 1, m and h are integers, and the system can be applied to intelligent vehicles or new energy vehicles, and the method comprises the following steps: after a first processor of the m processors is powered on, the first processor initializes n local area network switches belonging to the h local area network switches, n is greater than or equal to 1 and less than or equal to h, n is an integer, and the first processor is also used for other tasks except initializing the n local area network switches. The method can realize the rapid initialization of a plurality of local area network switches without adding an external processor, thereby not only reducing the starting time consumption of the whole system, but also reducing the cost.

Description

An initialization method and system for a local area network switch

Technical field

The present application relates to the field of vehicle technology, and in particular, to an initialization method and system for a local area network switch.

Background technique

With the development of science and technology, local area network switch (LSW) has also been used in vehicle communications in the field of automotive technology. After each power-on, the LAN switch needs to be initialized before it can work normally. Initialization mainly includes loading of firmware and configuration files. In some business scenarios, multiple LAN switches need to be initialized quickly.

However, initializing multiple LAN switches can require significant processing resources. Therefore, how to rationally use processing resources to achieve rapid initialization of multiple LAN switches has become an urgent technical issue that needs to be solved.

Therefore, how to quickly initialize multiple LAN switches at low cost is an urgent technical problem to be solved.

Contents of the invention

This application provides an initialization method and system for a local area network switch, in order to reduce the cost of quickly initializing multiple local area network switches.

In the first aspect, this application provides a method for initializing a LAN switch, which method is applied to a system including h LAN switches, and the system includes m processors for initializing the h LAN switches, h≥ 2. m≥1, m and h are integers. The method may be executed by a first processor in the system, which is any one of the m processors.

Exemplarily, the method includes: after the first processor is powered on, the first processor initializes n LAN switches, which belong to the above-mentioned h LAN switches, 1≤n≤h, n is an integer , the first processor is also used for other tasks besides initializing the n LAN switches.

Among them, the first processor can be used to initialize n local area network switches and can also be used for other tasks, that is, the effect of multiplexing the first processor is achieved. The first processor is any one of the m processors. Therefore, the m processors can be used to initialize the LAN switch and other tasks. In other words, this solution reuses m processors in the system. processor to initialize h LAN switches in the system.

Therefore, through the method provided by this application, the processing resources in the system can be reasonably utilized to achieve rapid initialization of multiple LAN switches without the need to add an external processor. In this way, the processing resources can be efficiently utilized and the cost can be reduced. reduce.

In addition, if the m processors are controlled so that the m processors are powered on at the same time, the m processors can be used to initialize h LAN switches in parallel. Therefore, the initialization of the h LAN switches can be completed quickly, and the startup time of the entire system can be reduced. In other words, using the solution provided by this application is also beneficial to reducing the startup time of the system.

In conjunction with the first aspect, in some possible implementations, after the first processor is powered on, the method may further include: the first processor determining that the n corresponding LAN switches are powered normally and have not been initialized.

In conjunction with the first aspect, in some possible implementations, the first processor includes at least one core.

That is to say, the first processor may be a single-core processor or a multi-core processor.

Optionally, the first processor includes k cores, n cores among the k cores correspond to n processes, and one process among the n processes is used to initialize one of the above-mentioned n LAN switches. , 1≤n≤k, k≥2, k is an integer.

The first processor may be a multi-core processor, and the n cores in the first processor may initialize the n LAN switches based on the corresponding n processes. When n ≥ 2, the first processor can quickly initialize multiple LAN switches based on n parallel processes, which can reduce the startup time of the entire system without adding external hardware.

Optionally, the first processor includes one core, and this core corresponds to n processes, and one process among the n processes is used to initialize one of the above-mentioned n LAN switches.

The first processor may be a single-core processor, and this core in the first processor may initialize n local area network switches based on n processes. When n ≥ 2, the first processor can quickly initialize multiple LAN switches based on n parallel processes, which can reduce the startup time of the entire system without adding external hardware.

Combined with the first aspect, in some possible implementations, the first processor is a microcontroller unit (microcontroller unit, MCU) or a system on chip (system on chip, SOC).

Combined with the first aspect, in some possible implementations, m=1, the first processor is used to initialize the h local area network switches, n=h.

Using one processor and based on multiple parallel processes, multiple LAN switches can be initialized in parallel, which can quickly complete the initialization of multiple LAN switches without adding external hardware and reduce the startup consumption of the entire system. hour.

Combined with the first aspect, in some possible implementations, m≥2.

Utilize at least two processors to jointly initialize multiple LAN switches. When multiple processors are powered on at the same time, multiple LAN switches can be quickly initialized in parallel, reducing the startup time of the entire system.

Optionally, when m≥2, the m processors include at least one MCU and at least one SOC.

When using at least two processors to jointly initialize multiple LAN switches, the types of processors may be different. For example, the m processors include at least one MCU and at least one SOC. In the case where the MCU is powered on earlier than the SOC Under this condition, the MCU can first initialize part of the multiple LAN switches, and the subsequently powered-on SOC can initialize the remaining unpowered parts of the multiple LAN switches. When the power-on time interval between the MCU and the SOC is small, it can also It can quickly initialize multiple LAN switches without adding external hardware, reducing the startup time of the entire system.

With reference to the first aspect, in some possible implementations, the corresponding relationship between each of the m processors and each of the h LAN switches is preset.

It should be understood that the preset corresponding relationship may be fixed, that is, a fixed setting or a default setting, or it may be flexibly adjusted according to the actual situation, that is, a dynamic setting or a flexible setting. In this application, Without any qualification.

Combined with the first aspect, in some possible implementations, the first processor initializes the n LAN switches, including: the first processor configures the firmware content and configuration files of the n LAN switches to the corresponding LAN respectively. switch to achieve complete initialization of the above n LAN switches.

Complete initialization can be understood as completing firmware loading and configuration file loading in one go.

The first processor loads the firmware and then the configuration file for the n LAN switches at once, instead of loading the configuration file for the first time and then loading the firmware for the second time. Therefore, it is possible to load the n LAN switches at once. Complete initialization of a LAN switch.

Combined with the first aspect, in some possible implementations, the first processor configures the firmware content and configuration files of the n LAN switches to the corresponding LAN switches respectively, including: the first processor calls the preset n The driver of the interface configures the firmware content and configuration files of the above n LAN switches to the corresponding LAN switches respectively; wherein, one of the above n interfaces corresponds to one of the above n LAN switches.

Optionally, the above-mentioned preset n interface types include one or more of the following: serial peripheral interface (SPI), management data input/output (MDIO) interface, internal integration Inter-integrated circuit (I2C) interface, universal asynchronous receiver/transmitter (UART) interface, general-purpose input/output (GPIO) interface, universal serial bus (universal serial bus , USB) interface, Ethernet (ethernet, ETH) interface, high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIE) interface.

Optionally, when n≥2, the above-mentioned preset n interfaces include at least two interfaces of the same type.

In the second aspect, this application provides a LAN switch system, which includes m processors and h LAN switches. The m processors are used to initialize the h LAN switches, m≥1, h≥2, m and h are integers; among them, the first processor among the m processors is used to initialize n LAN switches after power-on. These n LAN switches belong to the above-mentioned h LAN switches, 1≤n≤h , n is an integer, and the first processor is also used for other tasks besides initializing the n LAN switches.

Among them, the first processor can be used to initialize n local area network switches and can also be used for other tasks, that is, the effect of multiplexing the first processor is achieved. The first processor is any one of the m processors. Therefore, the m processors can be used to initialize the LAN switch and other tasks. In other words, this solution reuses m processors in the system. processor to initialize h LAN switches in the system.

Therefore, through the method provided by this application, the processing resources in the system can be reasonably utilized to achieve rapid initialization of multiple LAN switches without the need to add an external processor. In this way, the processing resources can be efficiently utilized and the cost can be reduced. reduce.

In addition, if the m processors are controlled so that the m processors are powered on at the same time, the m processors can be used to initialize h LAN switches in parallel. Therefore, the initialization of the h LAN switches can be completed quickly, and the startup time of the entire system can be reduced. In other words, using the solution provided by this application is also beneficial to reducing the startup time of the system.

Combined with the second aspect, in some possible designs, the first processor is also used to determine that the n corresponding LAN switches are powered normally and have not been initialized.

In conjunction with the second aspect, in some possible designs, the first processor includes at least one core.

That is to say, the first processor may be a single-core processor or a multi-core processor.

Optionally, the first processor includes k cores, n cores among the k cores correspond to n processes, and one process among the n processes is used to initialize one of the above-mentioned n LAN switches. , 1≤n≤k, k≥2, k is an integer.

The first processor may be a multi-core processor, and the n cores in the first processor may initialize the n LAN switches based on the corresponding n processes. When n ≥ 2, the first processor can quickly initialize multiple LAN switches based on n parallel processes, which can reduce the startup time of the entire system without adding external hardware.

Optionally, the first processor includes one core, and this core corresponds to n processes, and one process among the n processes is used to initialize one of the above-mentioned n LAN switches.

The first processor may be a single-core processor, and this core in the first processor may initialize n local area network switches based on n processes. When n ≥ 2, the first processor can quickly initialize multiple LAN switches based on n parallel processes, which can reduce the startup time of the entire system without adding external hardware.

Combined with the second aspect, in some possible designs, the first processor is an MCU or SOC.

Combined with the second aspect, in some possible designs, m=1, the first processor is used to initialize the above-mentioned h LAN switches, n=h.

Using one processor and based on multiple parallel processes, multiple LAN switches can be initialized in parallel, which can quickly complete the initialization of multiple LAN switches without adding external hardware and reduce the startup consumption of the entire system. hour.

Combined with the second aspect, in some possible designs, m≥2.

Utilize at least two processors to jointly initialize multiple LAN switches. When multiple processors are powered on at the same time, multiple LAN switches can be quickly initialized in parallel, reducing the startup time of the entire system.

Optionally, when m≥2, the m processors include at least one MCU and at least one SOC.

When using at least two processors to jointly initialize multiple LAN switches, the types of processors may be different. For example, the m processors include at least one MCU and at least one SOC. In the case where the MCU is powered on earlier than the SOC Under this condition, the MCU can first initialize part of the multiple LAN switches, and the subsequently powered-on SOC can initialize the remaining unpowered parts of the multiple LAN switches. When the power-on time interval between the MCU and the SOC is small, it can also It can quickly initialize multiple LAN switches without adding external hardware, reducing the startup time of the entire system.

Combined with the second aspect, in some possible designs, the corresponding relationship between each of the m processors and each of the h LAN switches is preset.

It should be understood that the preset corresponding relationship may be fixed, that is, a fixed setting or a default setting, or it may be flexibly adjusted according to the actual situation, that is, a dynamic setting or a flexible setting. In this application, Without any qualification.

Combined with the second aspect, in some possible designs, the first processor is specifically used to: configure the firmware content and configuration files of the above n LAN switches to the corresponding LAN switches respectively, so as to realize the complete integration of the above n LAN switches. initialization.

Complete initialization can be understood as completing firmware loading and configuration file loading in one go.

The first processor loads the firmware and then the configuration file for the n LAN switches at once, instead of loading the configuration file for the first time and then loading the firmware for the second time. Therefore, it is possible to load the n LAN switches at once. Complete initialization of a LAN switch.

Combined with the second aspect, in some possible designs, the first processor is specifically used to: call the drivers of the preset n interfaces, and configure the firmware content and configuration files of the above n LAN switches to the corresponding LAN switches respectively. ; Wherein, one interface among the above n interfaces corresponds to one LAN switch among the above n LAN switches.

Optionally, the above-mentioned preset n interface types include one or more of the following: SPI, MDIO interface, I2C interface, UART interface, GPIO interface, USB interface, ETH interface, and PCIE interface.

Optionally, when n≥2, the above-mentioned preset n interfaces include at least two interfaces of the same type.

Optionally, the above system is applied to a vehicle.

In a third aspect, this application provides a chip system, which includes at least one processor and is configured to support the implementation of the functions involved in the above-mentioned first aspect and any possible implementation of the first aspect.

In a possible design, the chip system also includes a memory, which is used to store program instructions and data. The memory is located within the processor or outside the processor.

The chip system can be composed of chips or include chips and other discrete devices.

In a fourth aspect, a computer-readable storage medium is provided. A computer program (which may also be called a code, or an instruction) is stored on the computer storage medium. When the computer program is run by a computer, the above-mentioned first The method in any possible implementation manner of the first aspect and the first aspect is executed.

In a fifth aspect, a computer program product is provided. The computer program product includes: a computer program (which can also be called a code, or an instruction). When the computer program is run, any of the above-mentioned aspects and the first aspect are enabled. The method in one possible implementation is executed.

It should be understood that the third to fifth aspects of the present application correspond to the technical solutions of the first and second aspects of the present application, and the beneficial effects achieved by each aspect and corresponding feasible implementations are similar, and will not be described again. .

Description of the drawings

Figure 1 is a schematic system architecture diagram of a local area network switch system provided by an embodiment of the present application;

Figure 2 is a schematic flow chart of the initialization method of the LAN switch provided by the embodiment of the present application;

Figure 3 is a schematic diagram of the initialization method of the LAN switch provided by the embodiment of the present application;

Figure 4 is a schematic system architecture diagram of another LAN switch system provided by an embodiment of the present application.

Detailed ways

The technical solutions in this application will be described below with reference to the accompanying drawings.

In order to clearly describe the technical solutions of the embodiments of the present application, the following description is first made.

First, in the embodiments of this application, “at least one type” refers to one type or multiple types. "And/or" describes the association of associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural. The character "/" generally indicates that the related objects are in an "or" relationship, but it does not exclude the situation that the related objects are in an "and" relationship. The specific meaning can be understood based on the context.

Second, in the embodiments of this application, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, devices, systems, and products that include a series of modules, modules or units. or devices are not necessarily limited to those modules, modules or units expressly listed, but may include other modules, modules or units not expressly listed or inherent to such devices, systems, products or devices.

In addition, the parameters involved in the embodiments of this application are briefly described below.

h: The number of all LAN switches included in the LAN switch system, h≥2, h is an integer.

m: The number of processors included in the LAN switch system for initializing h LAN switches, m≥1, m is an integer.

n: The number of local area switches that the first processor among m processors needs to be initialized, 1≤n≤h, n is an integer.

k: the number of all cores included in the first processor, 1≤n≤k, k≥2, and k is an integer.

With the development of science and technology, LAN switches have also been used in vehicle communications in the field of vehicle technology. There is a type of LAN switch that needs to be initialized before it can work properly every time it is powered on. Initialization mainly includes loading firmware and loading configuration files. In some application scenarios, multiple LAN switches need to be initialized quickly. Currently, a known solution for initializing multiple LAN switches requires an additional processor to specifically initialize multiple LAN switches. The implementation of this solution is complex and relies on additional processors, which is costly. Higher; another known solution for initializing multiple LAN switches is to load the firmware and the configuration file in two steps. The first time is to load the configuration file, and the second time to load the firmware. This solution cannot be done at once. Complete initialization of multiple LAN switches simultaneously.

To sum up, initializing multiple LAN switches may require a lot of processing resources. How to rationally use processing resources to achieve rapid initialization of multiple LAN switches has become an urgent technical issue that needs to be solved. Therefore, embodiments of the present application provide a method and system for initializing a LAN switch, which can reasonably utilize the processing resources in the system to achieve rapid initialization of multiple LAN switches without adding an external processor. In this way, the processing Resources are used efficiently and costs are reduced.

Figure 1 is a schematic system architecture diagram of a local area network switch system provided by an embodiment of the present application.

As shown in Figure 1, the LAN switch system may include h LAN switches, for example, LAN switch 1, LAN switch 2, LAN switch 3, LAN switch 4, LAN switch 5, LAN switch 6, LAN switch 7, ..., LAN Switch h, and m processors used to initialize these h LAN switches, for example, processor 1, processor 2,..., processor m.

Figure 2 is a schematic flow chart of the initialization method of a LAN switch provided by an embodiment of the present application.

The method shown in Figure 2 can be applied to the system of the LAN switch shown in Figure 1. The method can be executed by the first processor in the system. The first processor is any one of the above m processors. device.

As shown in FIG. 2 , the method 200 may include step 210 and step 220 . Each step in Figure 2 is described in detail below.

In step 210, after the first processor is powered on, it is determined that the n corresponding LAN switches are powered normally and have not been initialized.

It should be noted that the corresponding relationship between each of the above-mentioned m processors and each of the above-mentioned h LAN switches is preset. It should also be noted that the preset corresponding relationship can be fixed, that is, fixed settings or default settings, or can be flexibly adjusted according to actual conditions, that is, dynamic settings or flexible settings. This application does not make any limitation on this.

For example, after the first processor is powered on, that is, after the first processor is started, the first processor can determine whether the power supply of the n corresponding LAN switches is normal, and can determine whether the power supply of each of the n LAN switches is normal. Whether the LAN switch has not been initialized.

In step 220, the first processor initializes n LAN switches.

The first processor determines that the power supply of the corresponding n LAN switches is normal. For example, the voltage value of the power supply to each of the LAN switches is less than or equal to the first preset voltage value, and is greater than or equal to the second preset voltage value. voltage value (the second preset voltage value < the first preset voltage value), and each of the n LAN switches has not been initialized, the n LAN switches can be initialized.

It should be understood that in the case where one or more of the n LAN switches have abnormal power supply but the one or more LAN switches have not been initialized, the first processor may not supply power to the one or more LAN switches if the power supply is abnormal. The LAN switch is initialized. For example, the first processor determines that the power supply to the LAN switch 1 is abnormal (for example, the voltage of the power supply to the LAN switch 1 is greater than the first preset voltage value or less than the second preset voltage value), and the LAN switch 1 has not been initialized. , then the first processor may not initialize the LAN switch 1.

It should also be understood that when the power supply to one or more of the n LAN switches has been initialized, regardless of whether the power supply to the one or more LAN switches is normal, the first processor may not provide the power to the one or more LAN switches. The LAN switch that has been initialized is initialized. For example, if the first processor determines that the LAN switch 2 has been initialized but the power supply to the LAN switch 2 is abnormal, the first processor may not initialize the LAN switch 2 .

It should be noted that in the above method 200, after the first processor is powered on, the first processor may not perform the step of determining that the n corresponding LAN switches are powered normally and have not been initialized. That is, the first processor The processing may not determine whether the power supply of each of the corresponding n LAN switches is normal, nor whether each of the n LAN switches has not been initialized. That is to say, step 210 is an optional step. After being powered on, the first processor can directly initialize the n LAN switches. The embodiments of the present application do not limit this.

For example, as shown in Figure 3, after the first processor is powered on, it can start initializing n corresponding LAN switches at the same time.

In a possible implementation, the first processor initializes n LAN switches, including: the first processor configures the firmware content and configuration files of the n LAN switches to the corresponding LAN switches respectively, so as to realize the above n Complete initialization of a LAN switch.

Wherein, the firmware contents and configuration files of the n local area network switches may be pre-burned and stored in the storage unit (for example, flash memory) of the first processor. The firmware content may include a chip driver software table, which may include, for example, content related to port information initialization, chip internal random access memory (RAM) initialization, etc. The configuration file may include content related to port packet sending and receiving control, protocol content support, virtual local area network (VLAN) configuration, routing control, etc.

In addition, complete initialization can be understood as completing firmware loading and configuration file loading in one go.

After the first processor is powered on, the first processor can read the firmware contents of the n LAN switches and write the firmware contents of each LAN switch into the corresponding LAN switches respectively, that is, for the n LAN switches Firmware is loaded for each LAN switch in Configuration files are loaded for each of the LAN switches.

The first processor loads the firmware and then the configuration file for the n LAN switches at once, instead of loading the configuration file for the first time and then loading the firmware for the second time. Therefore, it is possible to load the n LAN switches at once. Complete initialization of a LAN switch.

Optionally, the first processor configures the firmware contents and configuration files of the n LAN switches to the corresponding LAN switches respectively, including: the first processor calls the preset drivers of the n interfaces, and converts the n LAN switches to The firmware content and configuration file are respectively configured to the corresponding LAN switches; wherein, one of the above-mentioned n interfaces corresponds to one of the above-mentioned n LAN switches.

For example, the first processor can be connected to its corresponding n LAN switches through preset n interfaces. Therefore, the first processor can call the preset drivers of the n interfaces to connect the corresponding n LAN switches to the preset n interfaces. The firmware content and configuration files of the n LAN switches are configured to the corresponding LAN switches respectively. That is, by calling the preset drivers of the n interfaces, the firmware loading and configuration file loading of the n LAN switches are implemented. Thus achieving complete initialization of these n LAN switches.

Optionally, the preset n interface types may include one or more of the following: SPI, MDIO interface, I2C interface, UART interface, GPIO interface, USB interface, ETH interface, PCIE interface, etc.

Optionally, the first processor is an MCU or SOC.

It should be noted that in current technology, MCU does not support the simultaneous use of the ETH interface and the MDIO interface. That is to say, when the first processor is an MCU, if the above-mentioned preset n interfaces include at least one ETH interface, Then these n interfaces do not include the MDIO interface; if the above-mentioned preset n interfaces include at least one MDIO interface, then these n interfaces do not include the ETH interface. However, this is not limited to future technologies. The MCU can support the implementation of this solution when the ETH interface and the MDIO interface are used simultaneously. The embodiments of this application do not impose any limitation on this.

In a possible implementation manner, when n≥2, the above-mentioned preset n interfaces include at least two interfaces of the same type.

That is to say, the same type of interface can exist among the preset multiple interfaces. For example, n=4, the preset 4 interfaces may include 2 MDIO interfaces, 1 I2C interface and 1 UART interface.

Of course, in some other implementations, when n≥2, the above-mentioned preset n interfaces may include n interfaces of different types. For example, n=6, the preset 6 interfaces can include 1 SPI, 1 MDIO interface, 1 I2C interface, 1 UART interface, 1 GPIO interface and 1 USB interface.

In a possible implementation, the first processor includes at least one core.

That is to say, the first processor may be a single-core processor (a processor including 1 core) or a multi-core processor. For example, the first processor may include k cores, k≥2, and the k The n cores in the core may be used to initialize n LAN switches. When k>n, the other k-n cores may not be used to initialize the LAN switches. This embodiment of the present application does not impose any limitation on this. Currently, commonly used processors include single-core processors, quad-core processors, six-core processors, and eight-core processors. These types of processors are all suitable for the initialization method of a LAN switch provided by the embodiment of the present application. The embodiments of the present application do not limit this.

Optionally, the first processor includes k cores, n cores among the k cores correspond to n processes one-to-one, and one process among the n processes is used to process one of the above-mentioned n LAN switches. Perform initialization.

In this implementation, the first processor may be a multi-core processor, and n cores in the first processor may initialize n LAN switches based on corresponding n processes. It can be understood that when n ≥ 2, these n processes can be n processes in parallel, so as to initialize the initialization time corresponding to the LAN switch that takes the longest time to initialize among the n LAN switches. , which is the total time consumed to initialize these n LAN switches.

It should be noted that when n ≥ 2, the "parallel n processes" mentioned in the embodiment of this application can be understood as multiple program segments running at the same time, and the execution of these program segments overlaps in time. , is not limited to complete overlap in a strict sense. That is to say, the "parallel" mentioned in the embodiments of this application allows for time errors, and is not "simultaneous" in the strict sense, as can be understood by those skilled in the art.

That is to say, when n ≥ 2, the first processor can quickly initialize multiple LAN switches based on n parallel processes, which can reduce the startup time of the entire system without adding external hardware. Thereby reducing costs.

As an example, k≥2, n=1, that is to say, the first processor is a multi-core processor, and the first processor can initialize a local area network switch based on one of the multiple cores.

In another example, k=6, n=6, that is to say, the first processor is a six-core processor, and the first processor can initialize six LAN switches in parallel based on these six cores.

In another example, k=8, n=6, that is to say, the first processor is an eight-core processor, and the first processor can perform processing on six LAN switches in parallel based on six of the eight cores. initialization.

Optionally, in some possible implementations, the first processor includes a core, which core corresponds to n processes, and one of the n processes is used to control one of the n LAN switches. Perform initialization.

In this implementation, the first processor can be a single-core processor. This core in the first processor can initialize n LAN switches in parallel based on n processes, which can be done without adding external hardware. In this case, multiple LAN switches can be initialized quickly, thereby reducing the startup time of the entire system. It can be understood that when n ≥ 2, these n processes can be n processes in parallel, so as to initialize the initialization time corresponding to the LAN switch that takes the longest time to initialize among the n LAN switches. , which is the total time consumed to initialize these n LAN switches.

That is to say, when n ≥ 2, the first processor can quickly initialize multiple LAN switches based on n parallel processes, which can reduce the startup time of the entire system without adding external hardware.

In a possible implementation, m=1, the first processor is used to initialize the h local area network switches, n=h.

In this implementation, the above-mentioned LAN switch system may include a processor for initializing h LAN switches. Using this processor, multiple LAN switches can be initialized in parallel based on multiple parallel processes. It can quickly initialize multiple LAN switches without adding external hardware, reducing the startup time of the entire system.

Figure 4 is a schematic system architecture diagram of another LAN switch system provided by an embodiment of the present application.

As an example and not a limitation, as shown in Figure 4, the LAN switch system includes a processor for initializing h LAN switches. The processor is a first processor. The first processor may be a SOC. The first processor may be a SOC. A processor can use its h cores to start h parallel processes at the same time to initialize all LAN switches (that is, h LAN switches) included in the LAN switch system in parallel.

In more detail, the first processor can use core 1 to realize the complete initialization of the LAN switch 1 by calling the driver of the MDIO interface 1; it can use the core 2 to realize the complete initialization of the LAN switch 2 by calling the driver of the MDIO interface 2. Complete initialization; you can use core 3 to achieve complete initialization of LAN switch 3 by calling the driver of the I2C interface; you can use core 4 to achieve complete initialization of LAN switch 4 by calling the driver of the ETH interface; you can use core 5 to achieve complete initialization of LAN switch 3. The complete initialization of the LAN switch 5 can be realized by calling the driver of the UART interface; the complete initialization of the LAN switch 6 can be realized by calling the driver of the GPIO interface using the core 6; the complete initialization of the LAN switch 6 can be realized by calling the driver of the USB interface using the core 7 Complete initialization of LAN switch 7; you can use core h to achieve complete initialization of LAN switch h by calling the driver of the PCIE interface. In the entire above process, multiple LAN switches can be quickly initialized without adding an external processor, which can reduce the startup time of the entire system.

In one possible implementation, m≥2.

In this implementation manner, the above-mentioned LAN switch system may include multiple processors for initializing h LAN switches, and these multiple processors are used to jointly initialize multiple LAN switches. When the power-on time of these multiple processors is the same, multiple LAN switches can be quickly initialized in parallel, reducing the startup time of the entire system.

It should be noted that the times at which these multiple processors are powered on may be the same or different. For example, when the multiple processors are all MCUs or all are SOCs, the times at which the multiple processors are powered on may be the same or different. When the multiple processors include both MCUs and SOCs, the times at which the multiple processors are powered on may be different. The embodiments of the present application do not limit this.

Optionally, when m≥2, the m processors include at least one MCU and at least one SOC.

When using these at least two processors to jointly initialize multiple LAN switches, the types of processors may be different. For example, the m processors include at least one MCU and at least one SOC, and the MCU is powered on earlier than the SOC. In this case, the MCU can first initialize part of the multiple LAN switches, and the subsequently powered-on SOC can initialize the remaining unpowered parts of the multiple LAN switches. When the power-on time interval between the MCU and the SOC is small, It can also quickly initialize multiple LAN switches without adding external hardware, reducing the startup time of the entire system.

For example, h=10, m=2, that is to say, the LAN switch system includes ten LAN switches and two processors. Of the two processors, one can be a single-core SOC and the other can be A multi-core MCU may be an eight-core MCU. After the eight-core MCU is powered on, it can use its six cores to start six parallel processes and call six preset interface drivers to initialize the six LAN switches corresponding to the eight-core MCU. ; After the single-core SOC is powered on, it can use its core to start four parallel processes and call the drivers of the four preset interfaces to initialize the four LANs corresponding to the single-core SOC. switch. During the entire above process, the ten LAN switches can be quickly initialized without adding an external processor, which can reduce the startup time of the entire system.

It should be noted that in the initialization method of a LAN switch provided by the embodiment of the present application, the direct memory access (DMA) technology and task time sharing are simultaneously used to load the firmware and configuration files of multiple LAN switches. Calling technology, using DMA technology is equivalent to transferring data from the internal memory of the processor to the running memory of the processor. Compared with the input/output (IO) reading and writing method, it can improve the loading speed, thus improving the initialization time. The speed of a LAN switch, that is, the startup speed of a system including multiple LAN switches is improved. Moreover, while the core in the processor is reading and writing the firmware content and configuration files of the LAN switch, the core of the processor can also be cut off to perform other tasks, making full use of the processor's resources.

Based on the above solution, by reusing m processors in the system to initialize h LAN switches in the system, the processing resources in the system can be reasonably utilized to achieve rapid initialization of multiple LAN switches without By adding an external processor, processing resources can be efficiently utilized and costs can be reduced. In addition, if the m processors are controlled so that the m processors are powered on at the same time, the m processors can be used to initialize h LAN switches in parallel. Therefore, the initialization of the h LAN switches can be completed quickly, and the startup time of the entire system can be reduced. In other words, using the solution provided by this application is also beneficial to reducing the startup time of the system.

The embodiment of the present application also provides a LAN switch system, which includes m processors and h LAN switches. The m processors are used to initialize the h LAN switches, m≥1, h≥2, m , h is an integer; wherein, each of the m processors can be used to implement the above method 200. That is, any one of the m processors may be the first processor in the above method 200. For relevant descriptions, please refer to the relevant content in the previous article. For the sake of brevity, I will not repeat them here.

The LAN switch systems shown in FIG. 1 and FIG. 4 provide two examples of the LAN switch system according to the embodiments of the present application. For relevant descriptions, please refer to the relevant content in the previous article. For the sake of brevity, I will not repeat them here.

By way of example and not limitation, the above-mentioned LAN switch system may be applied to vehicles.

That is to say, the LAN switch system provided by the embodiment of the present application can be deployed on a vehicle. The embodiments of this application do not limit this in any way.

The present application also provides a chip system, which includes at least one processor for implementing the functions involved in the method executed by the first processor in the embodiment shown in FIG. 2 .

In a possible design, the chip system further includes a memory, the memory is used to store program instructions and data, and the memory is located within the processor or outside the processor.

The chip system can be composed of chips or include chips and other discrete devices.

This application also provides a computer program product. The computer program product includes: a computer program (which may also be called a code or an instruction). When the computer program is run, it causes the computer to execute the method of the embodiment shown in Figure 2 .

The present application also provides a computer-readable storage medium that stores a computer program (which may also be referred to as code or instructions). When the computer program is run, the computer is caused to execute the method of the embodiment shown in FIG. 2 .

It should be understood that the processor in the embodiment of the present application may be an integrated circuit chip with signal processing capabilities. During the implementation process, each step of the above method embodiment can be completed through an integrated logic circuit of hardware in the processor or instructions in the form of software. The above-mentioned processor may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable processors. Logic devices, discrete gate or transistor logic devices, discrete hardware components. Each method, step and logical block diagram disclosed in the embodiment of this application can be implemented or executed. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly implemented by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other mature storage media in this field. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

It should also be understood that the memory in the embodiments of the present application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory can be read-only memory (ROM), programmable ROM (PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically removable memory. Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory. Volatile memory can be RAM, which acts as an external cache. By way of illustration, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (synchlink DRAM, SLDRAM) ) and direct memory bus random access memory (direct rambus RAM, DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

The terms "unit", "module", etc. used in this specification may be used to refer to computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution.

Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or a combination of computer software and electronic hardware. accomplish. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each specific application, but such implementations should not be considered beyond the scope of this application. In the several embodiments provided in this application, it should be understood that the disclosed devices, equipment and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, indirect coupling or communication connection of devices or modules, and may be in electrical, mechanical or other forms.

The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional module in each embodiment of the present application can be integrated into one processing module, or each module can exist physically alone, or two or more units can be integrated into one module.

In the above embodiments, the functions of each functional module can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (program) are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, e.g., the computer instructions may be transferred from a website, computer, server, or data center Transmission to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more available media integrated therein. The available media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, digital video discs, DVDs), or semiconductor media (eg, solid state disks, SSDs) )wait.

If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage media include: U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk and other media that can store program codes.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application. should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (27)

1. The initialization method of the local area network switch is characterized in that the method is applied to a system comprising h local area network switches, the system comprises m processors for initializing the h local area network switches, the powering-on moments of the m processors are the same, h is more than or equal to 2, m is more than or equal to 1, m and h are integers, and the method comprises the following steps:

after a first processor of the m processors is powered on, the first processor initializes n local area network switches, the n local area network switches belong to the h local area network switches, n is greater than or equal to 1 and less than or equal to h, n is an integer, and the first processor is also used for other tasks except initializing the n local area network switches.

2. The method of claim 1, wherein the first processor comprises at least one core.

3. The method of claim 2, wherein the first processor comprises k cores, n cores of the k cores correspond to n processes, one of the n processes to initialize one of the n local area network switches, 1 n k, k 2 k being an integer.

4. The method of claim 2, wherein the first processor comprises a core, the core corresponding to n processes, one of the n processes to initialize one of the n lan switches.

5. The method of any one of claims 1 to 4, wherein the first processor is a micro control unit, MCU, or a system on chip, SOC.

6. The method of any of claims 1 to 5, wherein m = 1, the first processor is configured to initialize the h local area network switches, n = h.

7. The method of any one of claims 1 to 5, wherein m.gtoreq.2.

8. The method of any one of claims 1 to 7, wherein a correspondence between each of the m processors and each of the h lan switches is preset.

9. The method of any of claims 1-8, wherein the first processor initializing n local area network switches comprises:

the first processor configures the firmware content and the configuration file of the n local area network switches to the corresponding local area network switches respectively so as to realize complete initialization of the n local area network switches.

10. The method of claim 9, wherein the first processor respectively configures firmware content and configuration files of the n local area network switches to corresponding local area network switches, comprising:

The first processor calls preset n interfaces to drive, and the firmware content and the configuration files of the n local area network switches are respectively configured to the corresponding local area network switches;

wherein one of the n interfaces corresponds to one of the n lan switches.

11. The method of claim 10, wherein the type of the predetermined n interfaces includes one or more of: serial peripheral interface SPI, management data input and output MDIO interface, internal integrated circuit I2C interface, universal asynchronous receiving and transmitting transmitter UART interface, universal input and output GPIO interface, universal serial bus USB interface, ethernet ETH interface, high-speed serial computer expansion bus standard PCIE interface.

12. The method according to claim 10 or 11, wherein the preset n interfaces comprise at least two interfaces of the same type when n is ≡2.

13. The local area network switch system is characterized by comprising m processors and h local area network switches, wherein the m processors are used for initializing the h local area network switches, m is more than or equal to 1, h is more than or equal to 2, and m and h are integers;

the first processor of the m processors is used for initializing n local area network switches after power-on, the n local area network switches belong to the h local area network switches, n is more than or equal to 1 and less than or equal to h, and n is an integer, and the first processor is also used for other tasks except initializing the n local area network switches.

14. The system of claim 13, wherein the first processor comprises at least one core.

15. The system of claim 14, wherein the first processor comprises k cores, n cores of the k cores correspond to n processes, one of the n processes to initialize one of the n local area network switches, 1 n k, k 2, k being an integer.

16. The system of claim 14, wherein the first processor comprises a core, the core corresponding to n processes, one of the n processes to initialize one of the n local area network switches.

17. The system of any one of claims 13 to 16, wherein the first processor is a micro control unit, MCU, or a system on chip, SOC.

18. The system of any of claims 13 to 17, wherein m = 1, the first processor is configured to initialize the h local area network switches, n = h.

19. The system of any one of claims 13 to 18, wherein m is ≡2.

20. The system according to any one of claims 13 to 19, wherein a correspondence between each of the m processors and each of the h lan switches is preset.

21. The system of any one of claims 13 to 20, wherein the first processor is specifically configured to:

and respectively configuring the firmware content and the configuration files of the n local area network switches to the corresponding local area network switches to realize the complete initialization of the n local area network switches.

22. The system of claim 21, wherein the first processor is specifically configured to:

invoking preset drives of n interfaces, and respectively configuring firmware content and configuration files of the n local area network switches to corresponding local area network switches;

wherein one of the n interfaces corresponds to one of the n lan switches.

23. The system of claim 22, wherein the type of the predetermined n interfaces includes one or more of: serial peripheral interface SPI, management data input and output MDIO interface, internal integrated circuit I2C interface, universal asynchronous receiving and transmitting transmitter UART interface, universal input and output GPIO interface, universal serial bus USB interface, ethernet ETH interface, high-speed serial computer expansion bus standard PCIE interface.

24. The system of claim 22 or 23, wherein the predetermined n interfaces comprise at least two interfaces of the same type when n is ≡2.

25. The system of any one of claims 13 to 24, wherein the system is applied to a vehicle.

26. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when executed, causes a computer to perform the method of any of claims 1 to 12.

27. A computer program product comprising a computer program which, when run, causes a computer to perform the method of any one of claims 1 to 12.