CN117478493A - Initialization method and system for local area network switch - Google Patents

Abstract

The method is applied to a system comprising h local area network switches, the system comprises m processors for initializing the h local area network switches, h is more than or equal to 2, m is more than or equal to 1, m and h are integers, and the system can be applied to intelligent vehicles or new energy vehicles, and the method comprises the following steps: after a first processor of the m processors is powered on, the first processor initializes n local area network switches belonging to the h local area network switches, n is greater than or equal to 1 and less than or equal to h, n is an integer, and the first processor is also used for other tasks except initializing the n local area network switches. The method can realize the rapid initialization of a plurality of local area network switches without adding an external processor, thereby not only reducing the starting time consumption of the whole system, but also reducing the cost.

Description

Initialization method and system for local area network switch

Technical Field

The present disclosure relates to the field of vehicle technologies, and in particular, to a method and system for initializing a lan switch.

Background

With the development of technology, local area network switches (local area network switch, LSW) have also been used in vehicle-mounted communications in the automotive field. After each power-on, the local area network switch needs to be initialized to work normally, and the initialization mainly comprises firmware loading and configuration file loading. In some traffic scenarios, initialization needs to be done quickly for multiple lan switches.

However, initializing multiple lan switches may require more processing resources. Therefore, how to reasonably use processing resources to implement rapid initialization of the plurality of lan switches becomes a technical problem to be solved.

Therefore, how to quickly initialize a plurality of lan switches with low cost is a technical problem to be solved.

Disclosure of Invention

The application provides an initialization method and system of a local area network switch, which aim to reduce the cost of rapidly completing initialization of a plurality of local area network switches.

In a first aspect, the present application provides a method for initializing a lan switch, where the method is applied to a system including h lan switches, and the system includes m processors for initializing the h lan switches, where h is greater than or equal to 2, m is greater than or equal to 1, and m and h are integers. The method may be performed by a first processor in the system, the first processor being any one of the m processors.

Illustratively, the method includes: after the first processor is powered on, the first processor initializes n local area network switches belonging to the h local area network switches, n is greater than or equal to 1 and less than or equal to h, n is an integer, and the first processor is also used for other tasks except initializing the n local area network switches.

The first processor may be used to initialize n lan switches, and may be used for other tasks, that is, to achieve the effect of multiplexing the first processor. The first processor is any one of m processors, so that the m processors can be all processors used for initializing the local area network switch and other tasks, in other words, the scheme realizes the initialization of h local area network switches in the system by multiplexing the m processors in the system.

Therefore, by the method provided by the application, the processing resources in the system can be reasonably utilized to realize the rapid initialization of a plurality of local area network switches without adding an external processor, so that the processing resources are efficiently utilized, and the cost is reduced.

In addition, if the m processors are controlled so that the power-on moments of the m processors are the same, the m processors may be used to initialize the h lan switches in parallel. Therefore, the initialization of the h local area network switches can be completed quickly, and the starting time consumption of the whole system is reduced. In other words, the scheme provided by the application is also beneficial to reducing the time consumption of starting the system.

With reference to the first aspect, in some possible implementations, after the first processor is powered up, the method may further include: the first processor determines that the n lan switches corresponding thereto are powered normally and are not initialized.

With reference to the first aspect, in some possible implementations, the first processor includes at least one core.

That is, the first processor may be a single-core processor or a multi-core processor.

Optionally, the first processor includes k cores, n cores of the k cores correspond to n processes, one process of the n processes is used for initializing one local area network switch of the n local area network switches, n is equal to or less than 1 and is equal to or less than k, k is equal to or greater than 2, and k is an integer.

The first processor may be a multi-core processor, and the n cores in the first processor may initialize the n lan switches based on the corresponding n processes. When n is more than or equal to 2, the first processor can realize the quick completion initialization of a plurality of local area network switches based on n parallel processes, and the time consumption for starting the whole system can be reduced under the condition of not adding external hardware.

Optionally, the first processor includes a core, where the core corresponds to n processes, and one of the n processes is used to initialize one of the n lan switches.

The first processor may be a single-core processor and the one core in the first processor may initialize n lan switches based on n processes. When n is more than or equal to 2, the first processor can realize the quick completion initialization of a plurality of local area network switches based on n parallel processes, and the time consumption for starting the whole system can be reduced under the condition of not adding external hardware.

With reference to the first aspect, in some possible implementations, the first processor is a micro control unit (micro controller unit, MCU) or a System On Chip (SOC).

With reference to the first aspect, in some possible implementations, m=1, and the first processor is configured to initialize the above-mentioned h lan switches, where n=h.

By using one processor, based on a plurality of parallel processes, a plurality of local area network switches can be initialized in parallel, so that the initialization of the plurality of local area network switches can be quickly completed without adding external hardware, and the starting time consumption of the whole system is reduced.

With reference to the first aspect, in some possible implementations, m is greater than or equal to 2.

At least two processors are utilized to initialize a plurality of local area network switches in common. Under the condition that the power-on time of the plurality of processors is the same, the initialization of the plurality of local area network switches is quickly completed in parallel, and the starting time consumption of the whole system is reduced.

Optionally, when m is equal to or greater than 2, at least one MCU and at least one SOC are included in the m processors.

When at least two processors are utilized to initialize a plurality of local area network switches together, the types of the processors can be different, for example, m processors comprise at least one MCU and at least one SOC, the MCU can initialize a part of the plurality of local area network switches first under the condition that the MCU is electrified earlier than the SOC, the subsequent electrified SOC can initialize the rest part which is not electrified in the plurality of local area network switches, and the initialization of the plurality of local area network switches can be quickly completed under the condition that external hardware is not added even when the time interval of electrifying the MCU and the SOC is smaller, so that the starting time consumption of the whole system is reduced.

With reference to the first aspect, in some possible implementations, a correspondence between each of the m processors and each of the h lan switches is preset.

It should be understood that the preset correspondence may be fixed, i.e. fixed or default, or may be flexibly adjusted according to the actual situation, i.e. dynamic or flexible, which is not limited in this application.

With reference to the first aspect, in some possible implementations, the initializing, by the first processor, n lan switches includes: the first processor configures the firmware content and the configuration file of the n lan switches to the corresponding lan switches respectively, so as to implement complete initialization of the n lan switches.

Complete initialization is understood to be the completion of firmware loading and profile loading at once.

The first processor loads the firmware for the n lan switches once, and then loads the configuration file, instead of loading the configuration file for the first time and then loading the firmware for the second time, so that the n lan switches can be completely initialized.

With reference to the first aspect, in some possible implementations, the first processor configures firmware content and configuration files of the n lan switches to corresponding lan switches respectively, including: the first processor calls the preset n interfaces to drive, and the firmware content and the configuration files of the n local area network switches are respectively configured to the corresponding local area network switches; wherein one of the n interfaces corresponds to one of the n lan switches.

Optionally, the types of the n preset interfaces include one or more of the following: serial peripheral interface (serial peripheral interface, SPI), management data input output (management data input/output, MDIO) interface, inter-integrated circuit, I2C interface, universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface, general-purpose input/output (GPIO) interface, universal serial bus (universal serial bus, USB) interface, ethernet (ETH) interface, high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIE) interface.

Optionally, when n is greater than or equal to 2, the preset n interfaces include at least two interfaces with the same type.

In a second aspect, the present application provides a lan switch system, the system including m processors and h lan switches, the m processors being configured to initialize the h lan switches, m being greater than or equal to 1, h being greater than or equal to 2, m, h being an integer; the first processor of the m processors is used for initializing n local area network switches after power-on, the n local area network switches belong to the h local area network switches, n is more than or equal to 1 and less than or equal to h, and n is an integer, and the first processor is also used for other tasks except initializing the n local area network switches.

The first processor may be used to initialize n lan switches, and may be used for other tasks, that is, to achieve the effect of multiplexing the first processor. The first processor is any one of m processors, so that the m processors can be all processors used for initializing the local area network switch and other tasks, in other words, the scheme realizes the initialization of h local area network switches in the system by multiplexing the m processors in the system.

Therefore, by the method provided by the application, the processing resources in the system can be reasonably utilized to realize the rapid initialization of a plurality of local area network switches without adding an external processor, so that the processing resources are efficiently utilized, and the cost is reduced.

In addition, if the m processors are controlled so that the power-on moments of the m processors are the same, the m processors may be used to initialize the h lan switches in parallel. Therefore, the initialization of the h local area network switches can be completed quickly, and the starting time consumption of the whole system is reduced. In other words, the scheme provided by the application is also beneficial to reducing the time consumption of starting the system.

With reference to the second aspect, in some possible designs, the first processor is further configured to determine that n lan switches corresponding thereto are powered normally and are not initialized.

With reference to the second aspect, in some possible designs, the first processor includes at least one core.

That is, the first processor may be a single-core processor or a multi-core processor.

Optionally, the first processor includes k cores, n cores of the k cores correspond to n processes, one process of the n processes is used for initializing one local area network switch of the n local area network switches, n is equal to or less than 1 and is equal to or less than k, k is equal to or greater than 2, and k is an integer.

The first processor may be a multi-core processor, and the n cores in the first processor may initialize the n lan switches based on the corresponding n processes. When n is more than or equal to 2, the first processor can realize the quick completion initialization of a plurality of local area network switches based on n parallel processes, and the time consumption for starting the whole system can be reduced under the condition of not adding external hardware.

Optionally, the first processor includes a core, where the core corresponds to n processes, and one of the n processes is used to initialize one of the n lan switches.

The first processor may be a single-core processor and the one core in the first processor may initialize n lan switches based on n processes. When n is more than or equal to 2, the first processor can realize the quick completion initialization of a plurality of local area network switches based on n parallel processes, and the time consumption for starting the whole system can be reduced under the condition of not adding external hardware.

With reference to the second aspect, in some possible designs, the first processor is an MCU or an SOC.

With reference to the second aspect, in some possible designs, m=1, and the first processor is configured to initialize the above-mentioned h lan switches, where n=h.

By using one processor, based on a plurality of parallel processes, a plurality of local area network switches can be initialized in parallel, so that the initialization of the plurality of local area network switches can be quickly completed without adding external hardware, and the starting time consumption of the whole system is reduced.

With reference to the second aspect, in some possible designs, m.gtoreq.2.

At least two processors are utilized to initialize a plurality of local area network switches in common. Under the condition that the power-on time of the plurality of processors is the same, the initialization of the plurality of local area network switches is quickly completed in parallel, and the starting time consumption of the whole system is reduced.

Optionally, when m is equal to or greater than 2, at least one MCU and at least one SOC are included in the m processors.

When at least two processors are utilized to initialize a plurality of local area network switches together, the types of the processors can be different, for example, m processors comprise at least one MCU and at least one SOC, the MCU can initialize a part of the plurality of local area network switches first under the condition that the MCU is electrified earlier than the SOC, the subsequent electrified SOC can initialize the rest part which is not electrified in the plurality of local area network switches, and the initialization of the plurality of local area network switches can be quickly completed under the condition that external hardware is not added even when the time interval of electrifying the MCU and the SOC is smaller, so that the starting time consumption of the whole system is reduced.

With reference to the second aspect, in some possible designs, a correspondence between each of the m processors and each of the h lan switches is preset.

It should be understood that the preset correspondence may be fixed, i.e. fixed or default, or may be flexibly adjusted according to the actual situation, i.e. dynamic or flexible, which is not limited in this application.

With reference to the second aspect, in some possible designs, the first processor is specifically configured to: and respectively configuring the firmware content and the configuration files of the n local area network switches to the corresponding local area network switches to realize the complete initialization of the n local area network switches.

Complete initialization is understood to be the completion of firmware loading and profile loading at once.

The first processor loads the firmware for the n lan switches once, and then loads the configuration file, instead of loading the configuration file for the first time and then loading the firmware for the second time, so that the n lan switches can be completely initialized.

With reference to the second aspect, in some possible designs, the first processor is specifically configured to: calling preset n interfaces to drive, and respectively configuring the firmware content and configuration files of the n local area network switches to the corresponding local area network switches; wherein one of the n interfaces corresponds to one of the n lan switches.

Optionally, the types of the n preset interfaces include one or more of the following: SPI, MDIO interface, I2C interface, UART interface, GPIO interface, USB interface, ETH interface, PCIE interface.

Optionally, when n is greater than or equal to 2, the preset n interfaces include at least two interfaces with the same type.

Alternatively, the above system is applied to a vehicle.

In a third aspect, the present application provides a chip system comprising at least one processor for supporting the implementation of the functions of the first aspect and any of the possible implementations of the first aspect.

In one possible design, the system on a chip also includes memory to hold program instructions and data, the memory being located either within the processor or external to the processor.

The chip system may be formed of a chip or may include a chip and other discrete devices.

In a fourth aspect, a computer-readable storage medium is provided, on which a computer program (which may also be referred to as code, or instructions) is stored which, when executed by a computer, causes the method of any one of the possible implementations of the first aspect and the above to be performed.

In a fifth aspect, there is provided a computer program product comprising: a computer program (which may also be referred to as code, or instructions) which, when executed, causes the method of the first aspect and any one of the possible implementations of the first aspect to be performed.

It should be understood that the third to fifth aspects of the present application correspond to the technical solutions of the first and second aspects of the present application, and the advantages obtained by each aspect and the corresponding possible embodiments are similar, and are not repeated.

Drawings

Fig. 1 is a schematic diagram of a system architecture of a lan switch system according to an embodiment of the present application;

FIG. 2 is a schematic flow chart of a method for initializing a LAN switch provided in an embodiment of the present application;

fig. 3 is a schematic diagram of an initialization method of a lan switch according to an embodiment of the present application;

fig. 4 is a schematic diagram of a system architecture of another lan switch system according to an embodiment of the present application.

Detailed Description

The technical solutions in the present application will be described below with reference to the accompanying drawings.

For the sake of clarity in describing the technical solutions of the embodiments of the present application, the following description is first made.

First, in the present embodiment, "at least one" means one kind or plural kinds. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the front-to-rear associated object is an "or" relationship, but does not exclude the case where the front-to-rear associated object is an "and" relationship, and the meaning of the specific representation may be understood in conjunction with the context.

Second, in the embodiments of the present application, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a device, system, article, or apparatus that comprises a list of modules, or units is not necessarily limited to those modules, or units that are expressly listed or inherent to such device, system, article, or unit.

In addition, the parameters involved in the embodiments of the present application are briefly described below.

h: the number of all local area switches included in the local area network switch system is equal to or greater than 2,h and is an integer.

m: the number of processors included in the local area network switch system for initializing h local area network switches is more than or equal to 1, and m is an integer.

n: the number of the local area switches which need to be initialized by a first processor in the m processors is more than or equal to 1 and less than or equal to h, and n is an integer.

k: the number of all cores included in the first processor is 1-n-k, k is more than or equal to 2, and k is an integer.

With the development of technology, lan switches have also been used in vehicle-mounted communications in the field of vehicle technology. After each power-on, a local area network switch needs to be initialized to work normally, and the initialization mainly comprises firmware loading and configuration file loading. In some application scenarios, initialization needs to be done quickly for multiple lan switches. Currently, a known scheme for initializing a plurality of lan switches requires an additional processor to initialize the plurality of lan switches, and the implementation of the scheme is complex and depends on the additional processor, so that the cost is high; another known scheme for initializing a plurality of lan switches is that firmware loading and profile loading are performed twice, the first time of profile loading and the second time of firmware loading are performed, and this scheme cannot complete initialization of a plurality of lan switches at one time.

In summary, the initialization of the lan switches may consume more processing resources, and how to reasonably use the processing resources to implement the fast initialization of the lan switches becomes a technical problem to be solved. Therefore, the embodiment of the application provides an initialization method and system for the local area network switch, which can reasonably utilize processing resources in the system to realize quick initialization of a plurality of local area network switches without adding an external processor, so that the processing resources are efficiently utilized, and the cost is reduced.

Fig. 1 is a schematic diagram of a system architecture of a lan switch system according to an embodiment of the present application.

As shown in fig. 1, the lan switch system may include h lan switches, for example, lan switch 1, lan switch 2, lan switch 3, lan switch 4, lan switch 5, lan switch 6, lan switches 7, … …, lan switch h, and m processors for initializing the h lan switches, for example, processor 1, processor 2, … …, processor m.

Fig. 2 is a schematic flowchart of an initialization method of a lan switch according to an embodiment of the present application.

The method shown in fig. 2 may be applied to the system of the lan switch shown in fig. 1, and the method may be performed by a first processor in the system, where the first processor is any one of the m processors.

As shown in fig. 2, the method 200 may include steps 210 and 220. The steps in fig. 2 are described in detail below.

In step 210, after the first processor is powered on, it is determined that n lan switches corresponding thereto are powered normally and are not initialized.

It should be noted that, the corresponding relationship between each of the m processors and each of the h lan switches is preset. It should be further noted that the preset correspondence may be fixed, i.e. fixed or default, or may be flexibly adjusted according to the actual situation, i.e. dynamically set or flexibly set. The present application is not limited in any way.

For example, after the first processor is powered on, that is, after the first processor is started, the first processor may determine whether power is normally supplied to n lan switches corresponding to the first processor, and may determine whether each of the n lan switches is uninitialized.

In step 220, the first processor initializes n lan switches.

The first processor may initialize the n lan switches after determining that the n lan switches corresponding thereto are powered normally, for example, the voltage value of the power supplied to each of the n lan switches is less than or equal to a first preset voltage value, and greater than or equal to a second preset voltage value (the second preset voltage value < the first preset voltage value), and each of the n lan switches is not initialized.

It should be appreciated that in the event that one or more of the n lan switches are not powered properly, but the one or more lan switches are not initialized, the first processor may not initialize the one or more powered improperly lan switches. For example, the first processor determines that the power supply to the lan switch 1 is abnormal (e.g., the voltage of the power supply to the lan switch 1 is greater than the first preset voltage value or less than the second preset voltage value), and the lan switch 1 is not initialized, the first processor may not initialize the lan switch 1.

It should also be appreciated that in the event that one or more of the n lan switches are powered up, the first processor may not initialize the one or more initialized lan switches, whether or not the power to the one or more lan switches is normal. For example, the first processor determines that the lan switch 2 has been initialized, but the power supply to the lan switch 2 is abnormal, the first processor may not initialize the lan switch 2.

It should be noted that, in the above method 200, after the first processor is powered on, the first processor may not perform the step of determining that the power of the n lan switches corresponding thereto is normal and not initialized, that is, the first process may not determine whether the power of each of the n lan switches corresponding thereto is normal or not, and may not determine whether each of the n lan switches is not initialized. That is, step 210 is an optional step, and the first processor may directly initialize the n lan switches after power-up. The embodiments of the present application are not limited in this regard.

Illustratively, as shown in fig. 3, after the first processor is powered on, initializing n lan switches corresponding thereto may be started simultaneously.

In one possible implementation, the initializing n lan switches by the first processor includes: the first processor configures the firmware content and the configuration file of the n local area network switches to the corresponding local area network switches respectively so as to realize the complete initialization of the n local area network switches.

The firmware content and the configuration files of the n lan switches may be pre-burned and stored in a storage unit (e.g. flash memory) of the first processor. The firmware content may include a chip driver table that may include, for example, content related to port information initialization, chip internal random access memory (random access memory, RAM) initialization, and the like. The configuration file may include content related to port messaging control, protocol content support, virtual local area network (virtual local area network, VLAN) configuration, routing control, and the like.

In addition, complete initialization may be understood as completing firmware loading and profile loading at once.

After the first processor is electrified, the first processor can read the firmware content of n local area network switches and write the firmware content of each local area network switch into the corresponding local area network switch respectively, namely, carry out firmware loading on each local area network switch in the n local area network switches; then, the first processor may read the configuration files of the n lan switches, and write the configuration files of each lan switch into the corresponding lan switch, that is, load the configuration files of each lan switch of the n lan switches.

The first processor loads the firmware for the n lan switches once, and then loads the configuration file, instead of loading the configuration file for the first time and then loading the firmware for the second time, so that the n lan switches can be completely initialized.

Optionally, the first processor configures firmware content and configuration files of the n lan switches to the corresponding lan switches respectively, including: the first processor calls the preset n interfaces to drive, and the firmware content and the configuration files of the n local area network switches are respectively configured to the corresponding local area network switches; wherein one of the n interfaces corresponds to one of the n lan switches.

The first processor may be connected to the corresponding n lan switches through preset n interfaces, so that the first processor may configure the firmware content and the configuration file of the corresponding n lan switches to the corresponding lan switches by calling the preset n interfaces, that is, by calling the preset n interfaces, to implement firmware loading and configuration file loading of the n lan switches, thereby implementing complete initialization of the n lan switches.

Optionally, the types of the n interfaces may include one or more of the following: SPI, MDIO interface, I2C interface, UART interface, GPIO interface, USB interface, ETH interface, PCIE interface, etc.

Optionally, the first processor is an MCU or an SOC.

It should be noted that, in the current technology, the MCU does not support simultaneous use of the ETH interface and the MDIO interface, that is, when the first processor is the MCU, if at least one ETH interface is included in the n preset interfaces, the MDIO interface is not included in the n interfaces; if at least one MDIO interface is included in the n preset interfaces, the ETH interface is not included in the n interfaces. However, this is not limited to implementation of the present solution when the MCU may support simultaneous use of the ETH interface and the MDIO interface in future technologies, and the embodiments of the present application are not limited in this regard.

In one possible implementation, when n is greater than or equal to 2, the preset n interfaces include at least two interfaces of the same type.

That is, among the preset plurality of interfaces, the same type of interface may exist. For example, n=4, and the preset 4 interfaces may include 2 MDIO interfaces, 1I 2C interface, and 1 UART interface.

Of course, in other implementations, when n+.2, the n interfaces preset above may include n interfaces of different types. For example, n=6, and the preset 6 interfaces may include 1 SPI, 1 MDIO interface, 1I 2C interface, 1 UART interface, 1 GPIO interface, and 1 USB interface.

In one possible implementation, the first processor includes at least one core.

That is, the first processor may be a single-core processor (including a processor with 1 core) or may be a multi-core processor, for example, the first processor may include k cores with k being ≡2, n cores of the k cores may be used to initialize n lan switches, and when k > n, the other k-n cores may not be used to initialize lan switches, which is not limited in any way in the embodiments of the present application. Currently, processors commonly used include a single-core processor, a four-core processor, a six-core processor, and an eight-core processor, and these types of processors are all suitable for the initialization method of the lan switch provided in the embodiments of the present application. The embodiments of the present application are not limited in this regard.

Optionally, the first processor includes k cores, n cores in the k cores are in one-to-one correspondence with n processes, and one process in the n processes is used for initializing one lan switch in the n lan switches.

In such an implementation, the first processor may be a multi-core processor, and the n cores in the first processor may initialize the n lan switches based on the corresponding n processes. It can be understood that when n is greater than or equal to 2, the n processes may be n processes in parallel, so that the initializing duration corresponding to the local area network switch with the longest time consumption during the initializing of the n local area network switches is the total duration consumed for initializing the n local area network switches.

It should be noted that, when n is equal to or greater than 2, the "parallel n processes" in the embodiments of the present application may be understood as a plurality of program segments running simultaneously, and the execution of the program segments is overlapped in time, and is not limited to being completely overlapped in a strict sense. That is, "parallel" as referred to in the embodiments of the present application is "simultaneous" in the sense that errors in time are allowed, and not strictly speaking, as will be understood by those skilled in the art.

That is, when n is greater than or equal to 2, the first processor can implement the initialization of multiple local area network switches based on n parallel processes, so that the starting time consumption of the whole system can be reduced without adding external hardware, and the cost is reduced.

In one example, k+_2, n=1, i.e., the first processor is a multi-core processor, the first processor may initialize a lan switch based on one of the cores.

As yet another example, k=6 and n=6, that is, the first processor is a six-core processor, and the first processor may initialize six lan switches in parallel based on the six cores.

As yet another example, k=8, n=6, that is, the first processor is an eight-core processor, which may initialize six lan switches in parallel based on six of the eight cores.

Optionally, in some possible implementations, the first processor includes a core, where the core corresponds to n processes, and one of the n processes is used to initialize one of the n lan switches.

In this implementation manner, the first processor may be a single-core processor, and the one core in the first processor may initialize n lan switches in parallel based on n processes, so that initialization of multiple lan switches can be quickly completed without adding external hardware, thereby reducing starting time consumption of the whole system. It can be understood that when n is greater than or equal to 2, the n processes may be n processes in parallel, so that the initializing duration corresponding to the local area network switch with the longest time consumption during the initializing of the n local area network switches is the total duration consumed for initializing the n local area network switches.

That is, when n is greater than or equal to 2, the first processor can implement the initialization of multiple lan switches based on n parallel processes, so that the starting time of the whole system can be reduced without adding external hardware.

In one possible implementation, m=1, and the first processor is configured to initialize the above-mentioned h lan switches, where n=h.

In this implementation manner, the lan switch system may include a processor for initializing h lan switches, and with this processor, based on a plurality of parallel processes, the plurality of lan switches may be initialized in parallel, so that the initialization of the plurality of lan switches may be quickly completed without adding external hardware, and the starting time of the whole system may be reduced.

Fig. 4 is a schematic diagram of a system architecture of another lan switch system according to an embodiment of the present application.

By way of example and not limitation, as shown in fig. 4, the lan switch system includes a processor for initializing h lan switches, where the processor is a first processor, and the first processor may be an SOC, and the first processor may use h cores included in the processor and simultaneously start h parallel processes to initialize all lan switches (i.e., h lan switches) included in the lan switch system in parallel.

In more detail, the first processor may utilize the core 1 to implement a complete initialization of the lan switch 1 by invoking the driving of the MDIO interface 1; the core 2 can be utilized to realize the complete initialization of the local area network switch 2 by calling the drive of the MDIO interface 2; the core 3 can be utilized to realize the complete initialization of the local area network switch 3 by calling the drive of the I2C interface; the core 4 can be utilized to realize the complete initialization of the local area network switch 4 by calling the drive of the ETH interface; the core 5 can be utilized to realize the complete initialization of the local area network switch 5 by calling the drive of the UART interface; the core 6 can be utilized to realize the complete initialization of the local area network switch 6 by calling the drive of the GPIO interface; the core 7 can be utilized to realize the complete initialization of the local area network switch 7 by calling the drive of the USB interface; the core h can be utilized to realize the complete initialization of the local area network switch h by calling the drive of the PCIE interface. In the whole process, the initialization of a plurality of local area network switches can be rapidly completed without adding an external processor, and the starting time consumption of the whole system can be reduced.

In one possible implementation, m.gtoreq.2.

In such an implementation, the lan switch system may include a plurality of processors for initializing the h lan switches, with the plurality of processors being utilized to collectively initialize the plurality of lan switches. Under the condition that the power-on moments of the processors are the same, the initialization of the local area network switches is quickly completed in parallel, and the starting time consumption of the whole system is reduced.

The power-up timings of the plurality of processors may be the same or different. For example, when the plurality of processors are all MCUs or are all SOCs, the power-up timings of the plurality of processors may be the same or different. When the plurality of processors includes both the MCU and the SOC, the times at which the plurality of processors are powered up may be different. The embodiments of the present application are not limited in this regard.

Optionally, when m is equal to or greater than 2, at least one MCU and at least one SOC are included in the m processors.

When the at least two processors are utilized to initialize the plurality of local area network switches together, the types of the processors can be different, for example, the m processors comprise at least one MCU and at least one SOC, the MCU can initialize a part of the plurality of local area network switches first under the condition that the MCU is electrified earlier than the SOC, the subsequent electrified SOC can initialize the rest part which is not electrified in the plurality of local area network switches, and the initialization of the plurality of local area network switches can be quickly completed under the condition that external hardware is not added even when the time interval of electrifying the MCU and the SOC is smaller, so that the starting time consumption of the whole system is reduced.

Illustratively, h=10, m=2, that is, the lan switch system includes ten lan switches and two processors, one of which may be a single core SOC and the other may be a multi-core MCU, which may be an eight-core MCU. After the eight-core MCU is electrified, six parallel processes can be started by utilizing six cores of the eight-core MCU, and the driving of six preset interfaces is called to initialize six local area network switches corresponding to the eight-core MCU; after the single-core SOC is powered on, the single-core SOC can be utilized to start four parallel processes, and four preset interface drives are called to initialize four local area network switches corresponding to the single-core SOC. In the whole process, the ten local area network switches can be initialized quickly without adding an external processor, and the starting time consumption of the whole system can be reduced.

It should be noted that, in the method for initializing the lan switch provided in the embodiment of the present application, the firmware loading and the configuration file loading of the lan switches use a direct memory access (direct memory access, DMA) technology and a task time-sharing calling technology, and the DMA technology is equivalent to the process of transferring data from the internal memory of the processor to the running memory of the processor, so that the loading speed can be increased compared with the input/output (IO) read-write mode, thereby increasing the speed of initializing the lan switches, that is, increasing the starting speed of the system including the lan switches. And the processor cores can be cut out to execute other tasks while the firmware content and the configuration file of the local area network switch are checked in the processor for reading and writing, so that the processor resources can be fully utilized.

Based on the scheme, the initialization of the h local area network switches in the system is realized by multiplexing the m processors in the system, so that the processing resources in the system can be reasonably utilized to realize the rapid initialization of a plurality of local area network switches without adding an external processor, and therefore, the processing resources are efficiently utilized, and the cost is reduced. In addition, if the m processors are controlled so that the power-on moments of the m processors are the same, the m processors may be used to initialize the h lan switches in parallel. Therefore, the initialization of the h local area network switches can be completed quickly, and the starting time consumption of the whole system is reduced. In other words, the scheme provided by the application is also beneficial to reducing the time consumption of starting the system.

The embodiment of the application also provides a local area network switch system, which comprises m processors and h local area network switches, wherein the m processors are used for initializing the h local area network switches, m is more than or equal to 1, h is more than or equal to 2, and m and h are integers; wherein each of the m processors is operable to implement the method 200 described above. That is, any one of the m processors may be the first processor in the method 200 described above. The relevant descriptions may be referred to in the foregoing, and for brevity, they are not repeated here.

The lan switch systems shown in fig. 1 and 4 provide two examples of lan switch systems for the embodiments of the present application. The relevant descriptions may be referred to in the foregoing, and for brevity, they are not repeated here.

By way of example and not limitation, the local area network switch system described above may be applied to a vehicle.

That is, the lan switch system provided in the embodiments of the present application may be deployed on a vehicle. The embodiments of the present application are not limited in any way.

The present application also provides a chip system, where the chip system includes at least one processor, for implementing the functions involved in the method performed by the first processor in the embodiment shown in fig. 2.

In one possible design, the system on a chip further includes a memory to hold program instructions and data, the memory being located either within the processor or external to the processor.

The chip system may be formed of a chip or may include a chip and other discrete devices.

The present application also provides a computer program product comprising: a computer program (which may also be referred to as code or instructions) which, when executed, causes a computer to perform the method of the embodiment shown in fig. 2.

The present application also provides a computer-readable storage medium storing a computer program (which may also be referred to as code or instructions). The computer program, when executed, causes a computer to perform the method of the embodiment shown in fig. 2.

It should be appreciated that the processor in the embodiments of the present application may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method embodiments may be implemented by integrated logic circuits of hardware in a processor or instructions in software form. The processor may be a general purpose processor, a digital signal processor (digital signal processor, DSP), an application specific integrated circuit (application specific integrated circuit, ASIC), a field programmable gate array (field programmable gate array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software modules in a decoded processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method.

It should also be appreciated that the memory in embodiments of the present application may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. The volatile memory may be RAM, which acts as external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

The terms "unit," "module," and the like as used in this specification may be used to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution.

Those of ordinary skill in the art will appreciate that the various illustrative logical blocks (illustrative logical block) and steps (steps) described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application. In the several embodiments provided in this application, it should be understood that the disclosed apparatus, device, and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.

The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist alone physically, or two or more units may be integrated into one module.

In the above embodiments, the functions of the respective functional modules may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (program) are loaded and executed on a computer, the processes or functions described in accordance with the embodiments of the present application are fully or partially produced. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital versatile disk (digital video disc, DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk, etc.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (27)

1. The initialization method of the local area network switch is characterized in that the method is applied to a system comprising h local area network switches, the system comprises m processors for initializing the h local area network switches, the powering-on moments of the m processors are the same, h is more than or equal to 2, m is more than or equal to 1, m and h are integers, and the method comprises the following steps:

after a first processor of the m processors is powered on, the first processor initializes n local area network switches, the n local area network switches belong to the h local area network switches, n is greater than or equal to 1 and less than or equal to h, n is an integer, and the first processor is also used for other tasks except initializing the n local area network switches.

2. The method of claim 1, wherein the first processor comprises at least one core.

3. The method of claim 2, wherein the first processor comprises k cores, n cores of the k cores correspond to n processes, one of the n processes to initialize one of the n local area network switches, 1 n k, k 2 k being an integer.

4. The method of claim 2, wherein the first processor comprises a core, the core corresponding to n processes, one of the n processes to initialize one of the n lan switches.

5. The method of any one of claims 1 to 4, wherein the first processor is a micro control unit, MCU, or a system on chip, SOC.

6. The method of any of claims 1 to 5, wherein m = 1, the first processor is configured to initialize the h local area network switches, n = h.

7. The method of any one of claims 1 to 5, wherein m.gtoreq.2.

8. The method of any one of claims 1 to 7, wherein a correspondence between each of the m processors and each of the h lan switches is preset.

9. The method of any of claims 1-8, wherein the first processor initializing n local area network switches comprises:

the first processor configures the firmware content and the configuration file of the n local area network switches to the corresponding local area network switches respectively so as to realize complete initialization of the n local area network switches.

10. The method of claim 9, wherein the first processor respectively configures firmware content and configuration files of the n local area network switches to corresponding local area network switches, comprising:

The first processor calls preset n interfaces to drive, and the firmware content and the configuration files of the n local area network switches are respectively configured to the corresponding local area network switches;

wherein one of the n interfaces corresponds to one of the n lan switches.

11. The method of claim 10, wherein the type of the predetermined n interfaces includes one or more of: serial peripheral interface SPI, management data input and output MDIO interface, internal integrated circuit I2C interface, universal asynchronous receiving and transmitting transmitter UART interface, universal input and output GPIO interface, universal serial bus USB interface, ethernet ETH interface, high-speed serial computer expansion bus standard PCIE interface.

12. The method according to claim 10 or 11, wherein the preset n interfaces comprise at least two interfaces of the same type when n is ≡2.

13. The local area network switch system is characterized by comprising m processors and h local area network switches, wherein the m processors are used for initializing the h local area network switches, m is more than or equal to 1, h is more than or equal to 2, and m and h are integers;

the first processor of the m processors is used for initializing n local area network switches after power-on, the n local area network switches belong to the h local area network switches, n is more than or equal to 1 and less than or equal to h, and n is an integer, and the first processor is also used for other tasks except initializing the n local area network switches.

14. The system of claim 13, wherein the first processor comprises at least one core.

15. The system of claim 14, wherein the first processor comprises k cores, n cores of the k cores correspond to n processes, one of the n processes to initialize one of the n local area network switches, 1 n k, k 2, k being an integer.

16. The system of claim 14, wherein the first processor comprises a core, the core corresponding to n processes, one of the n processes to initialize one of the n local area network switches.

17. The system of any one of claims 13 to 16, wherein the first processor is a micro control unit, MCU, or a system on chip, SOC.

18. The system of any of claims 13 to 17, wherein m = 1, the first processor is configured to initialize the h local area network switches, n = h.

19. The system of any one of claims 13 to 18, wherein m is ≡2.

20. The system according to any one of claims 13 to 19, wherein a correspondence between each of the m processors and each of the h lan switches is preset.

21. The system of any one of claims 13 to 20, wherein the first processor is specifically configured to:

and respectively configuring the firmware content and the configuration files of the n local area network switches to the corresponding local area network switches to realize the complete initialization of the n local area network switches.

22. The system of claim 21, wherein the first processor is specifically configured to:

invoking preset drives of n interfaces, and respectively configuring firmware content and configuration files of the n local area network switches to corresponding local area network switches;

wherein one of the n interfaces corresponds to one of the n lan switches.

23. The system of claim 22, wherein the type of the predetermined n interfaces includes one or more of: serial peripheral interface SPI, management data input and output MDIO interface, internal integrated circuit I2C interface, universal asynchronous receiving and transmitting transmitter UART interface, universal input and output GPIO interface, universal serial bus USB interface, ethernet ETH interface, high-speed serial computer expansion bus standard PCIE interface.

24. The system of claim 22 or 23, wherein the predetermined n interfaces comprise at least two interfaces of the same type when n is ≡2.

25. The system of any one of claims 13 to 24, wherein the system is applied to a vehicle.

26. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when executed, causes a computer to perform the method of any of claims 1 to 12.

27. A computer program product comprising a computer program which, when run, causes a computer to perform the method of any one of claims 1 to 12.