CN117476556A - Chip and forming method thereof, semiconductor structure and forming method thereof - Google Patents

Chip and forming method thereof, semiconductor structure and forming method thereof Download PDF

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Publication number
CN117476556A
CN117476556A CN202210871123.7A CN202210871123A CN117476556A CN 117476556 A CN117476556 A CN 117476556A CN 202210871123 A CN202210871123 A CN 202210871123A CN 117476556 A CN117476556 A CN 117476556A
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China
Prior art keywords
cutting
area
buffer
passivation layer
region
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CN202210871123.7A
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Chinese (zh)
Inventor
黄婷婷
费春潮
王亚平
毛乾君
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210871123.7A priority Critical patent/CN117476556A/en
Publication of CN117476556A publication Critical patent/CN117476556A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

A chip and a forming method thereof, a semiconductor structure and a forming method thereof, wherein the forming method of the chip comprises the following steps: providing a wafer, wherein the wafer comprises a plurality of main chip areas, a protection ring area surrounding each main chip area and a cutting channel area positioned between adjacent main chip areas, the protection ring area is positioned between the cutting channel area and the main chip area, and the cutting channel area comprises a cutting area and buffer areas positioned at two sides of the cutting area; forming passivation layers on the main chip region, the guard ring region and the dicing street region; forming a buffer opening in the passivation layer on the buffer region; cutting in the cutting area after forming the buffer opening; by forming the buffer opening in the passivation layer on the buffer area, even if a crack appears in the passivation layer in the process of cutting the wafer, when the crack is conducted to the buffer opening, the crack cannot continue to extend into the main chip area due to the fact that no conducting medium exists in the buffer opening, so that the reliability and performance of chips formed after the cutting are improved.

Description

Chip and forming method thereof, semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a chip and a forming method thereof, a semiconductor structure and a forming method thereof.
Background
In the semiconductor manufacturing process, after forming an integrated circuit on a wafer (wafer), the wafer needs to be cut into a plurality of discrete chips (chips) or dies (die), and then the discrete chips (chips) or dies (die) are packaged to form a chip package structure.
Blade dicing is a conventional wafer dicing process, and dicing is performed along dicing lanes on a wafer by using dicing tools when dicing the wafer, so that individual chips on the wafer are separated to form individual chips.
Along with the continuous improvement of the integration level of devices, the number of chips formed on a single wafer is increased, the area of a cutting channel between adjacent chips is also narrower, and particularly, when the wafer is cut by blade cutting along with the reduction of the width of the cutting channel to below 80 micrometers, the vicinity of the cutting channel can bear larger stress, and the problems of edge breakage, wafer breakage or breakage and the like are easily caused.
In view of this problem, a new dicing process, laser etching, is proposed, in which laser with high power is focused on the wafer surface to raise the local temperature of the wafer and decompose the wafer. The laser cutting has the advantages of high cutting speed and difficulty in mechanically damaging the wafer with brittle texture.
However, there are still a number of problems with laser cutting in the prior art.
Disclosure of Invention
The invention solves the technical problem of providing a chip and a forming method thereof, a semiconductor structure and a forming method thereof, so as to improve the reliability and performance of the chip.
In order to solve the above problems, the present invention provides a method for forming a chip, including: providing a wafer, wherein the wafer comprises a plurality of mutually separated main chip areas, a protection ring area surrounding each main chip area and a cutting channel area positioned between the adjacent main chip areas, the protection ring area is positioned between the cutting channel area and the main chip area, the cutting channel area comprises a cutting area and buffer areas positioned at two sides of the cutting area, and the buffer areas are positioned between the cutting area and the protection ring area; forming passivation layers on the main chip region, the guard ring region and the dicing street region; forming a buffer opening in the passivation layer on the buffer region; after the buffer opening is formed, cutting is performed in the cutting region, and the buffer opening blocks crack extension of the cutting region.
Optionally, the width dimension of the buffer opening is: 1.8-2.2 microns.
Optionally, the depth dimension of the buffer opening is: 0.99 to 1.01 microns.
Optionally, the passivation layer includes: a first passivation layer, and a second passivation layer on the first passivation layer.
Optionally, the material of the first passivation layer includes: silicon oxide; the material of the second passivation layer includes: silicon nitride and silicon oxide.
Optionally, the guard ring area is provided with a first blocking structure; the buffer area is internally provided with a second blocking structure.
Optionally, the first barrier structure and the second barrier structure each include: a plurality of conductive layers stacked repeatedly, and a plurality of conductive plugs positioned between adjacent conductive layers and respectively connected with the adjacent conductive layers.
Optionally, the method for cutting in the cutting area includes: performing first cutting treatment on the cutting area by adopting a first cutting process to form a cutting opening; and after the first cutting process, performing a second cutting process in the cutting opening by adopting a second cutting process until the wafer is penetrated.
Optionally, the first cutting process includes: and (5) a laser cutting process.
Optionally, the second cutting process includes: blade cutting process.
Correspondingly, the technical scheme of the invention also provides a chip, which comprises: a main chip region, a guard ring region surrounding each of the main chip regions, and a buffer region surrounding the guard ring region; and the passivation layer is positioned on the main chip region, the guard ring region and the buffer region, and a buffer opening is formed in the passivation layer positioned on the buffer region.
Optionally, the width dimension of the buffer opening is: 1.8-2.2 microns.
Optionally, the depth dimension of the buffer opening is: 0.99 to 1.01 microns.
Optionally, the passivation layer includes: a first passivation layer, and a second passivation layer on the first passivation layer.
Optionally, the material of the first passivation layer includes: silicon oxide; the material of the second passivation layer includes: silicon nitride and silicon oxide.
Optionally, the guard ring area is provided with a first blocking structure; the buffer area is internally provided with a second blocking structure.
Optionally, the first barrier structure and the second barrier structure each include: a plurality of conductive layers stacked repeatedly, and a plurality of conductive plugs positioned between adjacent conductive layers and respectively connected with the adjacent conductive layers.
Correspondingly, the technical scheme of the invention also provides a semiconductor structure, which comprises the following components: the wafer comprises a plurality of mutually separated main chip areas, guard ring areas surrounding the main chip areas and cutting channel areas positioned between the adjacent main chip areas, wherein the guard ring areas are positioned between the cutting channel areas and the main chip areas, the cutting channel areas comprise cutting areas and buffer areas positioned at two sides of the cutting areas, and the buffer areas are positioned between the cutting areas and the guard ring areas; and the passivation layer is positioned on the main chip region, the protection ring region and the cutting channel region, and a buffer opening is arranged in the passivation layer positioned on the buffer region and used for blocking crack extension of the cutting region.
Optionally, the plurality of main chip regions are arranged in an array along a first direction and a second direction, and the first direction and the second direction are different.
Optionally, the width dimension of the buffer opening is: 1.8-2.2 microns.
Optionally, the depth dimension of the buffer opening is: 0.99 to 1.01 microns.
Optionally, the passivation layer includes: a first passivation layer, and a second passivation layer on the first passivation layer.
Optionally, the material of the first passivation layer includes: silicon oxide; the material of the second passivation layer includes: silicon nitride and silicon oxide.
Optionally, the guard ring area is provided with a first blocking structure; the buffer area is internally provided with a second blocking structure.
Optionally, the first barrier structure and the second barrier structure each include: a plurality of conductive layers stacked repeatedly, and a plurality of conductive plugs positioned between adjacent conductive layers and respectively connected with the adjacent conductive layers.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a wafer, wherein the wafer comprises a plurality of mutually separated main chip areas, a protection ring area surrounding each main chip area and a cutting channel area positioned between the adjacent main chip areas, the protection ring area is positioned between the cutting channel area and the main chip area, the cutting channel area comprises a cutting area and buffer areas positioned at two sides of the cutting area, and the buffer areas are positioned between the cutting area and the protection ring area; forming passivation layers on the main chip region, the guard ring region and the dicing street region; and forming a buffer opening in the passivation layer on the buffer region, wherein the buffer opening blocks crack extension of the cutting region.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the chip in the technical scheme of the invention, the buffer opening is formed in the passivation layer on the buffer area, even if a crack appears in the passivation layer in the cutting process of the cutting area, when the crack is conducted to the buffer opening, the crack cannot continue to extend into the main chip area because no conducting medium exists in the buffer opening, so that the reliability and performance of the finally formed chip are improved.
Further, the depth dimension of the buffer opening is: 9.9 to 1.01 microns. When the depth dimension of the buffer opening is less than 0.99 microns, it is easy to cause cracks in the passivation layer to extend from below the buffer opening to the inside of the main chip region; when the depth dimension of the buffer opening is greater than 1.01 micrometers, the buffer opening has a greater loss on the passivation layer on the buffer region, thereby affecting the stability of the finally formed chip.
The chip of the technical scheme of the invention comprises: and the passivation layer is positioned on the main chip area, the protection ring area and the buffer area, a buffer opening is formed in the passivation layer positioned on the buffer area, and even if cracks appear in the passivation layer in the wafer dividing process, when the cracks are conducted to the buffer opening, the cracks cannot continue to extend into the main chip area due to the fact that no conducting medium is arranged in the buffer opening, so that the reliability and the performance of a finally formed chip are improved.
Further, the depth dimension of the buffer opening is: 9.9 to 1.01 microns. When the depth dimension of the buffer opening is less than 0.99 microns, it is easy to cause cracks in the passivation layer to extend from below the buffer opening to the inside of the main chip region; when the depth dimension of the buffer opening is greater than 1.01 micrometers, the buffer opening has a greater loss on the passivation layer on the buffer region, thereby affecting the stability of the finally formed chip.
The semiconductor structure of the technical scheme of the invention comprises the following components: and the passivation layer is positioned on the main chip area, the protection ring area and the cutting channel area, a buffer opening is formed in the passivation layer positioned on the buffer area, and even if cracks appear in the passivation layer in the wafer dividing process, when the cracks are conducted to the buffer opening, the cracks cannot continue to extend into the main chip area due to the fact that no conducting medium is arranged in the buffer opening, so that the reliability and the performance of the finally formed chip are improved.
Further, the depth dimension of the buffer opening is: 9.9 to 1.01 microns. When the depth dimension of the buffer opening is less than 0.99 microns, it is easy to cause cracks in the passivation layer to extend from below the buffer opening to the inside of the main chip region; when the depth dimension of the buffer opening is greater than 1.01 micrometers, the buffer opening has a greater loss on the passivation layer on the buffer region, thereby affecting the stability of the finally formed chip.
In the method for forming the semiconductor structure of the technical scheme of the invention, the buffer opening is formed in the passivation layer on the buffer area, and even if a crack appears in the passivation layer in the subsequent cutting process of the cutting area, when the crack is conducted to the buffer opening, the crack cannot continue to extend into the main chip area due to the fact that no conducting medium exists in the buffer opening, so that the reliability and the performance of a finally formed chip are improved.
Drawings
Fig. 1 to 3 are schematic structural views of steps of a method for forming a chip;
fig. 4 to 8 are schematic structural diagrams illustrating steps of a method for forming a chip according to an embodiment of the invention.
Detailed Description
As described in the background, the prior art methods still have problems in forming semiconductor structures. The following will make a detailed description with reference to the accompanying drawings.
Fig. 1 to 3 are schematic structural views of each step of a method for forming a chip.
Referring to fig. 1 and 2, fig. 2 is a schematic cross-sectional view taken along line A-A in fig. 1, and a wafer 100 is provided, wherein the wafer 100 includes a plurality of mutually separated main chip regions I, guard ring regions II surrounding each of the main chip regions I, and scribe line regions located between adjacent main chip regions I, the guard ring regions II are located between the scribe line regions and the main chip regions I, the scribe line regions include a scribe line region III and buffer regions IIII located at both sides of the scribe line region III, and the buffer regions IIII are located between the scribe line region III and the guard ring regions II; a passivation layer 101 is formed on the main chip region I, the guard ring region II, and the scribe line region.
Referring to fig. 3, the directions of the views in fig. 3 and fig. 2 are identical, and a first dicing process is performed on the wafer 100 along the dicing area III.
In this embodiment, the first cutting process adopts a laser cutting process, and since the main chip area I of the wafer 100 needs multiple layers of deposited dielectric materials in the process of forming the device structure, the dielectric materials are usually low-K dielectric materials, if the wafer 100 is directly cut by a blade, the low-K dielectric materials are easily broken, which further affects the reliability of the chips formed after the dicing, and even leads to electrical failure of the chips. Therefore, laser cutting is adopted before blade cutting, laser energy pulse with specific wavelength in the laser cutting process can only be absorbed by metal and silicon and gasified, other materials are passively heated and gasified and destroyed, so that the laser cutting process has less influence on the low-K dielectric material, and the metal structure formed in the cutting area III can be melted by laser cutting.
However, since the passivation layer 101 is mainly made of silicon oxide and silicon nitride, the passivation layer 101 is brittle like glass, and the passivation layer 101 is easily broken during the laser cutting process, and the crack 102 generated in the passivation layer 101 may even extend to the inside of the main chip area I through the buffer area IIII and the guard ring area II, so that the chip is reliable, and even the electrical failure of the chip is caused.
On the basis, the invention provides a chip, a forming method thereof, a semiconductor structure and a forming method thereof, wherein a buffer opening is formed in the passivation layer on the buffer region, and even if a crack appears in the passivation layer in the cutting process of the cutting region, when the crack is conducted to the buffer opening, the crack cannot continue to extend into the main chip region due to the fact that no conducting medium exists in the buffer opening, so that the reliability and performance of the finally formed chip are improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 4 to 8 are schematic structural diagrams illustrating steps of a method for forming a chip according to an embodiment of the present invention.
Referring to fig. 4 and 5, fig. 5 is a schematic cross-sectional view taken along line B-B in fig. 4, and a wafer 200 is provided, wherein the wafer 200 includes a plurality of mutually separated main chip regions I, guard ring regions II surrounding each of the main chip regions I, and scribe line regions between adjacent main chip regions I, the guard ring regions II are located between the scribe line regions and the main chip regions I, the scribe line regions include a scribe line region III and buffer regions IIII located at both sides of the scribe line region III, and the buffer regions IIII are located between the scribe line region III and the guard ring regions II; a passivation layer 201 is formed on the main chip region I, the guard ring region II, and the scribe line region.
In this embodiment, the main chip region I has a plurality of device structures and an electrical interconnection structure (not shown) electrically connected to the device structures.
In this embodiment, the passivation layer 201 includes: a first passivation layer 201a, and a second passivation layer 201b on the first passivation layer 201 a.
In this embodiment, the materials of the first passivation layer 201a include: silicon oxide; the materials of the second passivation layer 201b include: silicon nitride and silicon oxide.
In this embodiment, the guard ring region II has a first barrier structure 202 therein; the buffer area III has a second barrier structure 203 therein.
In this embodiment, the first blocking structure 202 and the second blocking structure 203 are formed in synchronization with the electrical interconnection structure in the main chip area I, and the first blocking structure 202 and the second blocking structure 203 play a role of peripheral stability, and can block the crack in the passivation layer 201 from extending to the inside of the main chip area I to a certain extent.
In this embodiment, the first barrier structure 202 and the second barrier structure 203 each include: a plurality of conductive layers stacked repeatedly, and a plurality of conductive plugs (not shown) located between and connected with the adjacent conductive layers, respectively.
In this embodiment, the cutting region III also has a metal structure 204 formed therein in synchronization with the electrical interconnection structure.
Referring to fig. 6, the directions of the views of fig. 6 and 5 are identical, and a buffer opening 205 is formed in the passivation layer 201 of the buffer region IIII.
In this embodiment, by forming the buffer opening 205 in the passivation layer 201 on the buffer area IIII, even if a crack occurs in the passivation layer 201 during the dicing process of the dicing area III, when the crack is conducted to the buffer opening 205, the crack cannot continue to extend into the main chip area I because the buffer opening 205 has no conductive medium, thereby improving the reliability and performance of the finally formed chip.
In this embodiment, the width d1 of the buffer opening 205 is: 1.8-2.2 microns.
In this embodiment, the depth d2 of the buffer opening 205 is: 9.9 to 1.01 microns. When the depth dimension d2 of the buffer opening 205 is less than 0.99 micrometers, it is easy to cause cracks in the passivation layer 201 to extend from below the buffer opening 205 to the inside of the main chip region I; when the depth d2 of the buffer opening 205 is greater than 1.01 μm, the buffer opening 204 consumes more passivation layer 201 on the buffer region IIII, thereby affecting the stability of the finally formed chip.
In this embodiment, after forming the buffer opening 205, the method further includes: and cutting in the cutting area. For a specific cutting process, please refer to fig. 7 and 8.
Referring to fig. 7, a first cutting process is performed on the cutting area III to form a cutting opening.
In this embodiment, the first cutting process uses a laser cutting process.
Since the main chip area I of the illustrated wafer 200 requires multiple layers of deposited dielectric materials in the process of forming the device structure, the dielectric materials are usually low-K dielectric materials, and if the illustrated wafer 200 is directly cut by a blade, the low-K dielectric materials are easily broken, so that the reliability of chips formed after the dicing is affected, and even the electrical failure of the chips is caused. Therefore, laser cutting is adopted before blade cutting, laser energy pulse with specific wavelength can only be absorbed by metal and silicon and gasified during laser cutting, other materials are passively heated and gasified and destroyed, so that the laser cutting process has less influence on the low-K dielectric material, and the metal structure 202 formed in the cutting channel region can be melted by laser cutting.
Referring to fig. 8, after the first dividing process, a second cutting process is performed in the cutting opening by using a second cutting process until the wafer 200 is penetrated.
In this embodiment, the second cutting process employs a blade cutting process.
In this embodiment, the second dicing process is used to completely penetrate the top and bottom surfaces of the wafer 200, so that the chips 206 are separated from each other.
Correspondingly, the embodiment of the present invention further provides a chip, please continue to refer to fig. 8, including: a main chip region I, a guard ring region II surrounding each of the main chip regions I, and a buffer region IIII surrounding the guard ring region II; and a passivation layer 201 positioned on the main chip region I, the guard ring region II and the buffer region IIII, wherein a buffer opening 205 is formed in the passivation layer 201 positioned on the buffer region IIII.
In this embodiment, since the passivation layer 201 on the buffer area IIII has the buffer opening 205 therein, even if a crack occurs in the passivation layer 201 during the subsequent dicing of the wafer 200, when the crack is conducted to the buffer opening 205, the crack cannot continue to extend into the main chip area I due to the absence of the conductive medium in the buffer opening 205, thereby improving the reliability and performance of the finally formed chip.
In this embodiment, the width d1 of the buffer opening 205 is: 1.8-2.2 microns.
In this embodiment, the depth d2 of the buffer opening 205 is: 0.99 to 1.01 microns. When the depth dimension d2 of the buffer opening 205 is less than 0.99 micrometers, it is easy to cause cracks in the passivation layer 201 to extend from below the buffer opening 205 to the inside of the main chip region I; when the depth d2 of the buffer opening 205 is greater than 1.01 μm, the buffer opening 204 is more lossy for the passivation layer 201 on the buffer region IIII, thereby affecting the stability of the finally formed chip
In this embodiment, the passivation layer 201 includes: a first passivation layer 201a, and a second passivation layer 201b on the first passivation layer 201 a.
In this embodiment, the material of the first passivation layer 201a is silicon oxide; the second passivation layer 201b is made of silicon nitride and silicon oxide.
In this embodiment, the guard ring region II has a first barrier structure 202 therein; the buffer region IIII has a second barrier structure 203 therein.
In this embodiment, the first barrier structure 202 and the second barrier structure 203 each include: a plurality of conductive layers stacked repeatedly, and a plurality of conductive plugs positioned between adjacent conductive layers and respectively connected with the adjacent conductive layers.
Accordingly, in an embodiment of the present invention, a method for forming a semiconductor structure is further provided, please continue to refer to fig. 4 to fig. 6, including: providing a wafer 200, wherein the wafer 200 comprises a plurality of mutually separated main chip areas I, a protection ring area II surrounding each main chip area I and a cutting channel area positioned between the adjacent main chip areas I, the protection ring area II is positioned between the cutting channel area and the main chip area I, the cutting channel area comprises a cutting area III and buffer areas IIII positioned at two sides of the cutting area III, and the buffer areas IIII are positioned between the cutting area III and the protection ring area II; forming a passivation layer 201 on the main chip region I, the guard ring region II, and the scribe line region; a buffer opening 205 is formed in the passivation layer 201 over the buffer region IIII.
In this embodiment, by forming the buffer opening 205 in the passivation layer 201 on the buffer area IIII, even if a crack appears in the passivation layer 201 during the dicing process of the dicing area III, when the crack is conducted to the buffer opening 205, the crack cannot continue to extend into the main chip area I because the buffer opening 205 has no conductive medium, thereby improving the reliability and performance of the finally formed chip.
Accordingly, in an embodiment of the present invention, a semiconductor structure is further provided, please continue to refer to fig. 6, which includes: the wafer 200 comprises a plurality of mutually separated main chip areas I, a protection ring area II surrounding each main chip area I and a cutting channel area positioned between the adjacent main chip areas I, wherein the protection ring area II is positioned between the cutting channel area and the main chip area I, the cutting channel area comprises a cutting area III and buffer areas IIII positioned at two sides of the cutting area III, and the buffer areas IIII are positioned between the cutting area III and the protection ring area II; passivation layer 201 on the main chip region I, guard ring region II, and scribe line region, and buffer opening 205 is provided in passivation layer 201 on buffer region IIII.
In this embodiment, since the passivation layer 201 on the buffer area IIII has the buffer opening 205 therein, even if a crack occurs in the passivation layer 201 during the subsequent dicing of the wafer 200, when the crack is conducted to the buffer opening 205, the crack cannot continue to extend into the main chip area I due to the absence of the conductive medium in the buffer opening 205, thereby improving the reliability and performance of the finally formed chip.
In this embodiment, the plurality of main chip regions I are arranged in an array along a first direction and a second direction, where the first direction and the second direction are different.
In this embodiment, the width d1 of the buffer opening 205 is: 1.8-2.2 microns.
In this embodiment, the depth d2 of the buffer opening 205 is: 0.99 to 1.01 microns. When the depth dimension d2 of the buffer opening 205 is less than 0.99 micrometers, it is easy to cause cracks in the passivation layer 201 to extend from below the buffer opening 205 to the inside of the main chip region I; when the depth d2 of the buffer opening 205 is greater than 1.01 μm, the buffer opening 204 is more lossy for the passivation layer 201 on the buffer region IIII, thereby affecting the stability of the finally formed chip
In this embodiment, the passivation layer 201 includes: a first passivation layer 201a, and a second passivation layer 201b on the first passivation layer 201 a.
In this embodiment, the material of the first passivation layer 201a is silicon oxide; the second passivation layer 201b is made of silicon nitride and silicon oxide.
In this embodiment, the guard ring region II has a first barrier structure 202 therein; the buffer region IIII has a second barrier structure 203 therein.
In this embodiment, the first barrier structure 202 and the second barrier structure 203 each include: a plurality of conductive layers stacked repeatedly, and a plurality of conductive plugs positioned between adjacent conductive layers and respectively connected with the adjacent conductive layers.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (26)

1. A method of forming a chip, comprising:
providing a wafer, wherein the wafer comprises a plurality of mutually separated main chip areas, a protection ring area surrounding each main chip area and a cutting channel area positioned between the adjacent main chip areas, the protection ring area is positioned between the cutting channel area and the main chip area, the cutting channel area comprises a cutting area and buffer areas positioned at two sides of the cutting area, and the buffer areas are positioned between the cutting area and the protection ring area;
forming passivation layers on the main chip region, the guard ring region and the dicing street region;
forming a buffer opening in the passivation layer on the buffer region;
after the buffer opening is formed, cutting is performed in the cutting region, and the buffer opening blocks crack extension of the cutting region.
2. The method of forming a chip of claim 1, wherein the buffer opening has a width dimension of: 1.8-2.2 microns.
3. The method of forming a chip of claim 1, wherein the buffer opening has a depth dimension of: 0.99 to 1.01 microns.
4. The method of forming a chip of claim 1, wherein the passivation layer comprises: a first passivation layer, and a second passivation layer on the first passivation layer.
5. The method of forming a chip of claim 4, wherein the material of the first passivation layer comprises: silicon oxide; the material of the second passivation layer includes: silicon nitride and silicon oxide.
6. The method of forming a chip of claim 1, wherein the guard ring region has a first barrier structure therein; the buffer area is internally provided with a second blocking structure.
7. The method of forming a chip of claim 6, wherein the first barrier structure and the second barrier structure each comprise: a plurality of conductive layers stacked repeatedly, and a plurality of conductive plugs positioned between adjacent conductive layers and respectively connected with the adjacent conductive layers.
8. The method of forming a chip of claim 1, wherein the method of dicing at the dicing area comprises: performing first cutting treatment on the cutting area by adopting a first cutting process to form a cutting opening; and after the first cutting process, performing a second cutting process in the cutting opening by adopting a second cutting process until the wafer is penetrated.
9. The method of forming a chip of claim 8, wherein the first cutting process comprises: and (5) a laser cutting process.
10. The method of forming a chip of claim 8, wherein the second dicing process comprises: blade cutting process.
11. A chip, comprising:
a main chip region, a guard ring region surrounding each of the main chip regions, and a buffer region surrounding the guard ring region;
and the passivation layer is positioned on the main chip region, the guard ring region and the buffer region, and a buffer opening is formed in the passivation layer positioned on the buffer region.
12. The chip of claim 11, wherein the buffer opening has a width dimension of: 1.8-2.2 microns.
13. The chip of claim 11, wherein the buffer opening has a depth dimension of: 0.99 to 1.01 microns.
14. The chip of claim 11, wherein the passivation layer comprises: a first passivation layer, and a second passivation layer on the first passivation layer.
15. The chip of claim 14, wherein the material of the first passivation layer comprises: silicon oxide; the material of the second passivation layer includes: silicon nitride and silicon oxide.
16. The chip of claim 11, wherein the guard ring region has a first barrier structure therein; the buffer area is internally provided with a second blocking structure.
17. The chip of claim 16, wherein the first barrier structure and the second barrier structure each comprise: a plurality of conductive layers stacked repeatedly, and a plurality of conductive plugs positioned between adjacent conductive layers and respectively connected with the adjacent conductive layers.
18. A semiconductor structure, comprising:
the wafer comprises a plurality of mutually separated main chip areas, guard ring areas surrounding the main chip areas and cutting channel areas positioned between the adjacent main chip areas, wherein the guard ring areas are positioned between the cutting channel areas and the main chip areas, the cutting channel areas comprise cutting areas and buffer areas positioned at two sides of the cutting areas, and the buffer areas are positioned between the cutting areas and the guard ring areas;
and the passivation layer is positioned on the main chip region, the protection ring region and the cutting channel region, and a buffer opening is arranged in the passivation layer positioned on the buffer region and used for blocking crack extension of the cutting region.
19. The semiconductor structure of claim 18, wherein a plurality of said main chip regions are arranged in an array along a first direction and a second direction, said first direction and said second direction being different.
20. The semiconductor structure of claim 18, wherein a width dimension of the buffer opening is: 1.8-2.2 microns.
21. The semiconductor structure of claim 18, wherein a depth dimension of the buffer opening is: 0.99 to 1.01 microns.
22. The semiconductor structure of claim 18, wherein the passivation layer comprises: a first passivation layer, and a second passivation layer on the first passivation layer.
23. The semiconductor structure of claim 22, wherein the material of the first passivation layer comprises: silicon oxide; the material of the second passivation layer includes: silicon nitride and silicon oxide.
24. The semiconductor structure of claim 18, wherein the guard ring region has a first barrier structure therein; the buffer area is internally provided with a second blocking structure.
25. The semiconductor structure of claim 24, wherein the first barrier structure and the second barrier structure each comprise: a plurality of conductive layers stacked repeatedly, and a plurality of conductive plugs positioned between adjacent conductive layers and respectively connected with the adjacent conductive layers.
26. A method of forming a semiconductor structure, comprising:
providing a wafer, wherein the wafer comprises a plurality of mutually separated main chip areas, a protection ring area surrounding each main chip area and a cutting channel area positioned between the adjacent main chip areas, the protection ring area is positioned between the cutting channel area and the main chip area, the cutting channel area comprises a cutting area and buffer areas positioned at two sides of the cutting area, and the buffer areas are positioned between the cutting area and the protection ring area;
forming passivation layers on the main chip region, the guard ring region and the dicing street region;
and forming a buffer opening in the passivation layer on the buffer region, wherein the buffer opening blocks crack extension of the cutting region.
CN202210871123.7A 2022-07-22 2022-07-22 Chip and forming method thereof, semiconductor structure and forming method thereof Pending CN117476556A (en)

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