CN117476484A

CN117476484A - Semiconductor test structure, forming method thereof and test result analysis system

Info

Publication number: CN117476484A
Application number: CN202210865727.0A
Authority: CN
Inventors: 郭帅
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-07-21
Filing date: 2022-07-21
Publication date: 2024-01-30

Abstract

The disclosure relates to the technical field of semiconductors, and relates to a semiconductor test structure, a forming method thereof and a test result analysis system, wherein the forming method comprises the following steps: providing a substrate; forming an isolation layer on a substrate; forming a capacitor structure on the surface of the isolation layer, which is far away from the substrate, wherein the capacitor structure comprises a lower electrode layer, a capacitor dielectric layer and an upper electrode layer which are sequentially stacked and distributed along the direction vertical to the substrate; forming a first lead and a second lead on one side of the capacitor structure far away from the substrate, wherein the first lead is in contact connection with the lower electrode layer, the second lead is in contact connection with the upper electrode layer, and orthographic projections of the first lead and the second lead on the substrate are not overlapped; and a first test pad and a second test pad which are arranged at intervals are formed on one side of the isolation layer away from the substrate, the first test pad is in contact connection with the first lead, and the second test pad is in contact connection with the second lead. The formation method can accelerate the development progress of the capacitor and improve the accuracy of the test result.

Description

Semiconductor test structure, forming method thereof and test result analysis system

Technical Field

The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor test structure, a forming method thereof and a test result analysis system.

Background

The dynamic random access memory (Dynamic Random Access Memory, DRAM) has the advantages of small volume, high integration degree, high transmission speed and the like, and is widely applied to mobile devices such as mobile phones, tablet computers and the like. The capacitor is used as a core component of the dynamic random access memory and is mainly used for storing charges.

In the DRAM manufacturing process, it is generally necessary to form a transistor first and then a capacitor, and to test the capacitor, it is necessary to manufacture the transistor first and then the capacitor, and then test the capacitor; however, the transistor manufacturing process occupies more than half of the whole manufacturing process period, so that the capacitor test period is longer, the capacitor research and development progress is slower, the test structure is easily interfered by other structures, and the test result accuracy is lower.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

In view of the above, the present disclosure provides a semiconductor test structure, a forming method thereof, and a test result analysis system, which can accelerate the development progress of the capacitor and improve the accuracy of the test result.

According to one aspect of the present disclosure, there is provided a method of forming a semiconductor test structure, comprising:

providing a substrate;

forming an isolation layer on the substrate;

forming a capacitor structure on the surface of the isolation layer, which is far away from the substrate, wherein the capacitor structure comprises a lower electrode layer, a capacitor dielectric layer and an upper electrode layer which are sequentially stacked and distributed along the direction perpendicular to the substrate;

forming a first lead and a second lead on one side of the capacitor structure far away from the substrate, wherein the first lead is in contact connection with the lower electrode layer, the second lead is in contact connection with the upper electrode layer, and orthographic projections of the first lead and the second lead on the substrate are not overlapped;

and forming a first test pad and a second test pad which are arranged at intervals on one side of the isolation layer away from the substrate, wherein the first test pad is in contact connection with the first lead, and the second test pad is in contact connection with the second lead.

In an exemplary embodiment of the present disclosure, the forming method further includes:

forming a plurality of capacitor structures on the surface of the isolation layer away from the substrate, wherein each capacitor structure is provided with a first lead and a second lead corresponding to the capacitor structures; the areas of the upper electrode layers of at least part of the capacitor structures are not equal in a direction parallel to the substrate.

In an exemplary embodiment of the present disclosure, areas of the upper electrode layers of the respective capacitor structures are not equal to each other in a direction parallel to the substrate.

In an exemplary embodiment of the present disclosure, each of the capacitor structures is arranged side by side, and an area of an upper electrode layer in each of the capacitor structures is sequentially increased or decreased in a direction parallel to the substrate.

In one exemplary embodiment of the present disclosure, the orthographic projection of the first lead on the substrate covers an edge of the orthographic projection of the lower electrode layer on the substrate for one week.

In an exemplary embodiment of the present disclosure, a capacitor structure is formed on a surface of the isolation layer away from the substrate, where the capacitor structure includes a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer sequentially stacked and distributed along a direction perpendicular to the substrate, and the capacitor structure includes:

sequentially forming a lower electrode material layer, a capacitance medium material layer and an upper electrode material layer on one side of the isolation layer away from the substrate;

etching the capacitance dielectric material layer and the upper electrode material layer to form a capacitance dielectric layer and an upper electrode layer;

forming a photoresist layer covering the upper electrode layer and the lower electrode material layer adjacent to the capacitance medium layer, wherein the orthographic projection of the photoresist layer on the substrate is within the orthographic projection of the lower electrode material layer on the substrate;

And removing the lower electrode material layer which is not covered by the photoresist layer to form a lower electrode layer.

In an exemplary embodiment of the present disclosure, forming a first lead and a second lead on a side of the capacitor structure away from the substrate, the first lead being in contact with the lower electrode layer, the second lead being in contact with the upper electrode layer, orthographic projections of the first lead and the second lead on the substrate not overlapping each other, includes:

forming an insulating layer covering the capacitor structure;

forming a mask layer on the surface of the insulating layer;

patterning the insulating layer by taking the mask layer as a mask to form a first contact hole exposing the lower electrode layer and a second contact hole exposing the upper electrode layer in the insulating layer, wherein the orthographic projection of the first contact hole on the substrate is not overlapped with the orthographic projection of the upper electrode layer on the substrate, and the orthographic projection of the second contact hole on the substrate is within the orthographic projection of the upper electrode layer on the substrate;

and filling conductive materials in the first contact hole and the second contact hole respectively to form a first lead in the first contact hole and a second lead in the second contact hole.

In an exemplary embodiment of the present disclosure, etching the capacitor dielectric material layer and the upper electrode material layer to form a capacitor dielectric layer and an upper electrode layer includes:

forming a first photoresist layer on the surface of the upper electrode material layer, wherein the orthographic projection of the first photoresist layer on the substrate is in the orthographic projection of the lower electrode material layer on the substrate;

and photoetching the capacitance dielectric material layer and the upper electrode material layer by taking the lower electrode material layer as an etching stop layer and taking the first photoresist layer as a photoresist so as to form the capacitance dielectric layer and the upper electrode layer.

In an exemplary embodiment of the present disclosure, patterning the insulating layer with the mask layer as a mask to form a first contact hole exposing the lower electrode layer and a second contact hole exposing the upper electrode layer in the insulating layer includes:

forming a second photoresist layer on the surface of the mask layer, wherein the second photoresist layer comprises a first development area and a second development area, the orthographic projection of the first development area on the substrate is not overlapped with the orthographic projection of the upper electrode layer on the substrate, and the orthographic projection of the second development area on the substrate is within the orthographic projection of the upper electrode layer on the substrate;

Etching the mask layer and the insulating layer in the first and second development regions to form a first contact hole exposing the lower electrode layer and a second contact hole exposing the upper electrode layer.

According to one aspect of the present disclosure, there is provided a semiconductor test structure comprising:

a substrate;

an isolation layer formed on the substrate;

the capacitor structure is formed on the surface, far away from the substrate, of the isolation layer and comprises a lower electrode layer, a capacitor dielectric layer and an upper electrode layer which are sequentially stacked and distributed along the direction perpendicular to the substrate;

the first lead and the second lead are formed on one side, far away from the substrate, of the capacitor structure, the first lead is in contact connection with the lower electrode layer, the second lead is in contact connection with the upper electrode layer, and orthographic projections of the first lead and the second lead on the substrate are not overlapped;

the first test pads and the second test pads are arranged at intervals on one side, far away from the substrate, of the isolation layer, the first test pads are in contact connection with the first lead wires, and the second test pads are in contact connection with the second lead wires.

In an exemplary embodiment of the present disclosure, the number of the capacitor structures is a plurality, the plurality of capacitor structures are each formed on a surface of the isolation layer away from the substrate, each of the capacitor structures has the first lead and the second lead corresponding thereto; the areas of the upper electrode layers of at least part of the capacitor structures are not equal in a direction parallel to the substrate.

According to one aspect of the present disclosure, there is provided a test result analysis system including:

a data importing unit for importing test data of the semiconductor test structure according to any one of the above; the test data comprise the area of the upper electrode layer of each capacitor structure and the storage capacity corresponding to each capacitor structure;

and the data generation component is used for generating test analysis results according to the area of the upper electrode layer of each capacitor structure and the storage capacity corresponding to each capacitor structure.

The semiconductor test structure and the forming method thereof can directly form a planar capacitor structure on a substrate, the lower electrode layer of the capacitor structure can be connected with a first test pad through a first lead wire, the upper electrode layer of the capacitor structure can be connected with a second test pad through a second lead wire, and the test probes are tied on the first test pad and the second test pad, so that the test of the capacitor structure is completed. In the process, on one hand, capacitor preparation and test are not required to be carried out after the transistor preparation is completed, so that the capacitor test period can be shortened, and the capacitor research and development progress can be accelerated; on the other hand, the influence of the technological process for forming the hole-shaped structure on the test result can be eliminated without manufacturing the hole-shaped structure with high depth-to-width ratio; meanwhile, as the capacitor structure is directly prepared on the substrate, other structures (such as transistors) are not arranged on the substrate, the influence of other structures on the capacitor test result can be eliminated, the test result is more accurate, and the accuracy of the test result can be improved; in addition, through setting up the isolation layer between electric capacity structure and substrate, and then through the inside impurity diffusion of isolation layer barrier substrate to the electric capacity structure in, can get rid of the influence of impurity in the substrate to electric capacity structure test result, further improve the rate of accuracy of test result.

According to the test result analysis system, test analysis results can be generated according to the area of the upper electrode layer of each capacitor structure and the storage capacity of each capacitor structure, the relation between the area of the capacitor structure and the storage capacity of the capacitor structure can be clearly seen, the monitoring board can be manufactured according to the test analysis results, and in the research and development process, the manufacturing process stability of the capacitor medium layer can be monitored through the monitoring board, so that when the storage capacity of the capacitor structure obtained by testing in the process is changed, the change of the storage capacity of the capacitor structure can be rapidly checked according to the test analysis results because of the change of the material of the capacitor medium layer or because of the change of the key size in the capacitor structure, and the research and development progress can be accelerated.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

FIG. 1 is a schematic diagram of a DRAM according to the related art;

FIG. 2 is a flow chart of a method of forming a semiconductor test structure in an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram after step S130 is completed in the embodiment of the present disclosure;

FIG. 4 is a flowchart of step S130 in an embodiment of the present disclosure;

FIG. 5 is a flowchart of step S220 in an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram after step S2210 is completed in the embodiment of the disclosure;

fig. 7 is a schematic structural diagram after step S2220 is completed in the embodiment of the present disclosure;

fig. 8 is a schematic structural diagram after step S230 is completed in the embodiment of the present disclosure;

fig. 9 is a schematic structural diagram after step S240 is completed in the embodiment of the present disclosure;

FIG. 10 is a top view of a photoresist layer in an embodiment of the present disclosure;

FIG. 11 is a top view of a first photoresist layer in an embodiment of the present disclosure;

FIG. 12 is a flowchart of step S140 in an embodiment of the present disclosure;

fig. 13 is a schematic structural diagram after step S310 is completed in the embodiment of the present disclosure;

fig. 14 is a schematic structural diagram after step S320 is completed in the embodiment of the present disclosure;

fig. 15 is a schematic structural diagram after step S330 is completed in the embodiment of the present disclosure;

fig. 16 is a schematic structural diagram after step S3310 is completed in the embodiment of the disclosure;

Fig. 17 is a schematic structural diagram after step S340 is completed in the embodiment of the present disclosure;

fig. 18 is a schematic view of a conductive material layer in an embodiment of the present disclosure;

FIG. 19 is a schematic diagram of a third photoresist layer in an embodiment of the present disclosure;

FIG. 20 is a schematic diagram of a third photoresist layer when forming a plurality of capacitor structures in an embodiment of the disclosure;

fig. 21 is a schematic structural diagram after step S150 is completed in the embodiment of the present disclosure;

FIG. 22 is a schematic view of a photomask when a plurality of first test pads and a plurality of second test pads are formed according to an embodiment of the present disclosure;

fig. 23 is a schematic diagram of overlay of various photomasks in an embodiment of the disclosure.

Reference numerals illustrate:

100. a transistor; 200. a capacitor structure 3; 1. a substrate; 2. an isolation layer; 3. a capacitor structure; 31. a lower electrode layer; 310. a lower electrode material layer; 32. a capacitance dielectric layer; 320. a layer of capacitive dielectric material; 33. an upper electrode layer; 330. an upper electrode material layer; 41. a first lead; 411. a first contact hole; 42. a second lead; 421. a second contact hole; 51. a first test pad; 52. a second test pad; 300. a photoresist layer; 400. an insulating layer; 500. a mask layer; 600. a conductive material layer; 700. a first photoresist layer; 800. a second photoresist layer; 801. a first development zone; 802. a second development region; 900. and a third photoresist layer.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first" and "second" and the like are used merely as labels, and are not intended to limit the number of their objects.

As shown in fig. 1, the dynamic random access memory (Dynamic Random Access Memory, DRAM) generally includes a transistor 100 and a capacitor structure 200, and in the DRAM manufacturing process, it is generally necessary to manufacture the transistor 100 and then manufacture the capacitor structure 200, so that in the process of testing the capacitor structure 200, the manufacturing process of the transistor 100 consumes a large part of time, so that the test period of the capacitor structure 200 is longer, resulting in slower development progress of the capacitor structure 200; in the process of testing the capacitor structure 200, the capacitor test structure is easily interfered by the transistor 100, and the accuracy of the test result is low; in addition, during the manufacturing process of the product, the storage capacity of the capacitor structure 200 is generally increased by increasing the surface area of the capacitor structure 200, and during the manufacturing process of the capacitor, it is required to form a hole-like structure with a high aspect ratio on the substrate, and then form the capacitor structure 200 in the hole-like structure. However, due to the limitation of the preparation process, the critical dimensions of each formed hole structure have errors, the problems of unclean etching of the hole structure and the like are easily caused, the whole process has more interference on the test result of the capacitor structure 200, and the accuracy of the test result is lower.

Based on this, the present disclosure provides a method for forming a semiconductor test structure to solve the above technical problems. Fig. 2 illustrates a flowchart of a method of forming a semiconductor test structure in an embodiment of the present disclosure, and referring to fig. 2, the method may include steps S110 to S150, wherein:

step S110, providing a substrate;

step S120, forming an isolation layer on the substrate;

step S130, forming a capacitor structure on the surface of the isolation layer, which is far away from the substrate, wherein the capacitor structure comprises a lower electrode layer, a capacitor dielectric layer and an upper electrode layer which are sequentially stacked and distributed along the direction perpendicular to the substrate;

step S140, forming a first lead and a second lead on one side of the capacitor structure far away from the substrate, wherein the first lead is in contact connection with the lower electrode layer, the second lead is in contact connection with the upper electrode layer, and orthographic projections of the first lead and the second lead on the substrate are not overlapped;

and step S150, forming a first test pad and a second test pad which are arranged at intervals on one side of the isolation layer away from the substrate, wherein the first test pad is in contact connection with the first lead, and the second test pad is in contact connection with the second lead.

According to the method for forming the semiconductor test structure, the planar capacitor structure can be directly formed on the substrate, the lower electrode layer of the capacitor structure can be connected with the first test pad through the first lead wire, the upper electrode layer of the capacitor structure can be connected with the second test pad through the second lead wire, and the test probes are respectively tied on the first test pad and the second test pad, so that the test of the capacitor structure is completed. In the process, on one hand, capacitor preparation and test are not required to be carried out after the transistor preparation is completed, so that the capacitor test period can be shortened, and the capacitor research and development progress can be accelerated; on the other hand, the influence of the technological process for forming the hole-shaped structure on the test result can be eliminated without manufacturing the hole-shaped structure with high depth-to-width ratio; meanwhile, as the capacitor structure is directly prepared on the substrate, other structures (such as transistors) are not arranged on the substrate, the influence of other structures on the capacitor test result can be eliminated, the test result is more accurate, and the accuracy of the test result can be improved; in addition, through setting up the isolation layer between electric capacity structure and substrate, and then through the inside impurity diffusion of isolation layer barrier substrate to the electric capacity structure in, can get rid of the influence of impurity in the substrate to electric capacity structure test result, further improve the rate of accuracy of test result.

The following describes in detail the steps of the method for forming a semiconductor test structure according to the embodiment of the present disclosure:

as shown in fig. 2, in step S110, a substrate is provided.

As shown in fig. 3, the substrate 1 may have a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular, and the material may be silicon or other semiconductor material, and the shape and material of the substrate 1 are not particularly limited.

As shown in fig. 2, in step S120, an isolation layer is formed on the substrate.

In an exemplary embodiment of the present disclosure, an isolation layer may be located on a surface of the substrate, and the substrate may be separated from other film layers by the isolation layer, so as to avoid diffusion of impurities in the substrate into the other film layers, which helps to ensure stability of the device.

The spacer layer 2 may be a thin film formed on the surface of the substrate 1 or a coating layer formed on the surface of the substrate 1, and is not particularly limited. In one embodiment, the isolation layer 2 may be formed on the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation, magnetron sputtering, or the like, and of course, the isolation layer 2 may be formed by other methods, which are not limited herein.

The material of the isolation layer 2 may be an insulating material, for example, silicon dioxide, a high-k dielectric material, or other dielectric material, or any combination thereof. The thickness of the isolation layer 2 may be set according to actual needs.

As shown in fig. 2, in step S130, a capacitor structure is formed on a surface of the isolation layer away from the substrate, where the capacitor structure includes a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer stacked in sequence along a direction perpendicular to the substrate.

In an exemplary embodiment of the present disclosure, the capacitor structure 3 may be a planar capacitor, and the capacitor structure 3 may include a lower electrode layer 31, a capacitor dielectric layer 32 and an upper electrode layer 33 stacked and distributed, where the lower electrode layer 31 may be located on a surface of the isolation layer 2, the capacitor dielectric layer 32 may be located on a surface of the lower electrode layer 31, the upper electrode layer 33 may be located on a surface of the capacitor dielectric layer 32, an area of the upper electrode layer 33 may be equal to an area of the capacitor dielectric layer 32, and an area of the upper electrode layer 33 may be equal to or unequal to an area of the lower electrode layer 31, which is not limited herein.

In one embodiment, the lower electrode layer 31 may have a circular, elliptical, rectangular or irregular shape, and the upper electrode layer 33 may have a circular, elliptical, rectangular or irregular shape. The shape of the capacitor dielectric layer 32 may be the same as the shape of the upper electrode layer 33, and the shape of the upper electrode layer 33 may be the same as the shape of the lower electrode layer 31, or may be different from the shape of the lower electrode layer 31, and is not particularly limited.

In an exemplary embodiment of the present disclosure, there may be a plurality of capacitor structures 3, and a plurality of capacitor structures 3 may be formed on the surface of the isolation layer 2 away from the substrate 1, where the manufacturing process of each capacitor structure 3 is the same, and a plurality of capacitor structures 3 may be formed by the same process of forming the capacitor structures 3.

For example, the number of the capacitor structures 3 may be 12 to 48, for example, 12, 24, 36 or 48, and of course, the number of the capacitor structures 3 may be other, and the number of the capacitor structures 3 is not limited specifically.

It should be noted that, the number of the capacitor structures 3 may be set according to the number of the test pin cards of the test device in the subsequent test process, for example, if the test device includes 24 test pin cards, 2 test pin cards are required for testing each capacitor structure 3, and the number of the capacitor structures 3 may be 12; if the test device includes 48 test pin cards, 2 test pin cards are required for testing each capacitor structure 3, the number of capacitor structures 3 may be 24; if the test device includes 72 test pin cards, 2 test pin cards are required for testing each capacitor structure 3, the number of capacitor structures 3 may be 36; if the test device includes 96 test pin cards, 2 test pin cards are required for testing each capacitor structure 3, the number of capacitor structures 3 may be 48, however, the number of test pin cards of the test device may be other, and correspondingly, the number of capacitor structures 3 may be other, which is not listed here.

In an embodiment, in a direction parallel to the substrate 1, areas of the upper electrode layers 33 of at least some of the capacitor structures 3 in the plurality of capacitor structures 3 are unequal, so that a plurality of capacitor structures 3 with unequal areas can be prepared at the same time, so that a test analysis result can be generated according to the areas of the capacitor structures 3 and the storage capacities of the capacitor structures 3 with different areas obtained by testing. For example, the number of the capacitor structures 3 may be 48, wherein the areas of the upper electrode layers 33 of the 36 capacitor structures 3 are not equal to each other; as another example, the number of the capacitor structures 3 may be 36, wherein the areas of the upper electrode layers 33 of the 24 capacitor structures 3 are not equal to each other; still alternatively, the number of the capacitor structures 3 may be 24, wherein the areas of the upper electrode layers 33 of 12 capacitor structures 3 are not equal to each other.

In an exemplary embodiment of the present disclosure, the areas of the lower electrode layers 31 in each capacitor structure 3 are all equal, and taking the shape of the lower electrode layers 31 as an example, the areas of the lower electrode layers 31 in each capacitor structure 3 may be 35um×286.76um.

In some embodiments of the present disclosure, the areas of the lower electrode layers 31 in each of the capacitor structures 3 are equal in a direction parallel to the substrate 1, and the areas of the upper electrode layers 33 of each of the capacitor structures 3 are different from each other. By testing the electrical properties of the capacitor structures 3 with the areas of the upper electrode layers 33 being different from each other, a test analysis result can be generated according to the areas of the upper electrode layers 33 of the capacitor structures 3 and the storage capacities of the capacitor structures 3, the relationship between the areas of the capacitor structures 3 and the storage capacities of the capacitor structures 3 can be clearly seen according to the test analysis result, a monitoring board can be manufactured according to the test analysis result, and in the research and development process, the manufacturing process stability of the capacitor dielectric layer 32 can be monitored through the monitoring board, so that when the storage capacities of the capacitor structures 3 obtained by testing in the manufacturing process are changed, whether the change of the storage capacities of the capacitor structures 3 is caused by the change of the materials of the capacitor dielectric layer 32 or caused by the change of the critical dimensions in the capacitor structures 3 can be rapidly checked according to the test analysis result, and the research and development progress can be accelerated.

In an embodiment, each capacitor structure 3 may be distributed on the surface of the isolation layer 2 side by side, and in a direction parallel to the substrate 1, the area of the upper electrode layer 33 in each capacitor structure 3 may be sequentially increased or decreased, so that the relationship between the capacitor area and the capacitor storage capacity can be clearly seen in the subsequent testing process, which is helpful for reducing the difficulty of data analysis.

The following describes in detail the process of manufacturing the capacitor structure 3, taking the manufacturing of the capacitor structure 3 as an example:

in an exemplary embodiment of the present disclosure, a capacitor structure 3 is formed on a surface of the isolation layer 2 away from the substrate 1, where the capacitor structure 3 includes a lower electrode layer 31, a capacitor dielectric layer 32, and an upper electrode layer 33 stacked and distributed in sequence along a direction perpendicular to the substrate 1 (i.e., step S130), and may include steps S210-S240, as shown in fig. 4, where:

step S210, sequentially forming a lower electrode material layer, a capacitor dielectric material layer and an upper electrode material layer on a side of the isolation layer away from the substrate.

In one embodiment, the lower electrode material layer 310, the capacitor dielectric material layer 320 and the upper electrode material layer 330 may be sequentially formed on the surface of the isolation layer 2. For example, the lower electrode material layer 310 may be formed on the surface of the isolation layer 2, the capacitance dielectric material layer 320 is formed on the surface of the lower electrode material layer 310, and the upper electrode material layer 330 is formed on the surface of the capacitance dielectric material layer 320. For convenience of process, the lower electrode material layer 310, the capacitance dielectric material layer 320 and the upper electrode material layer 330 may be flush with two ends of the isolation layer 2, that is: the front projection of the lower electrode material layer 310 on the substrate 1, the front projection of the capacitance dielectric material layer 320 on the substrate 1, and the front projection of the upper electrode material layer 330 on the substrate 1 can coincide with the front projection of the isolation layer 2 on the substrate 1.

For example, the lower electrode material layer 310, the capacitor dielectric material layer 320, and the upper electrode material layer 330 may be sequentially formed on the surface of the isolation layer 2 by vacuum evaporation, magnetron sputtering, thermal evaporation, chemical vapor deposition, physical vapor deposition, or atomic layer deposition, for example, although the forming manner of the lower electrode material layer 310, the capacitor dielectric material layer 320, and the upper electrode material layer 330 may be formed by other processes, and is not limited in particular.

The material of the lower electrode material layer 310 may be titanium, titanium nitride, tungsten, silicon germanium, or the like, or may be a combination of any two of the above materials. Of course, other materials that can be used as the electrode are also possible, and the material and the forming process of the lower electrode material layer 310 are not particularly limited. The capacitor dielectric material layer 320 may be a single-layer film structure made of the same material, or may be a mixed film structure made of film layers made of different materials. For example, it may comprise a material having a relatively high dielectric constant, such as aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, silicon nitride, or mixtures thereof, although other materials are also possible and are not listed herein. The material of the upper electrode material layer 330 may be titanium, titanium nitride, tungsten, silicon germanium, or the like, or a combination of any two of the above materials. Of course, other materials that can be used as the electrode are also possible, and the material of the upper electrode material layer 330 is not particularly limited.

Note that the material of the upper electrode material layer 330 may be the same as or different from the material of the lower electrode material layer 310, and is not particularly limited herein. For example, the material of the upper electrode material layer 330 and the material of the lower electrode material layer 310 may be a combination of titanium nitride and silicon germanium; for another example, the material of the upper electrode material layer 330 may be titanium nitride, and the material of the lower electrode material layer 310 may be tungsten; alternatively, the material of the upper electrode material layer 330 may be tungsten, and the material of the lower electrode material layer 310 may be titanium nitride.

Step S220, etching the capacitor dielectric material layer and the upper electrode material layer to form a capacitor dielectric layer and an upper electrode layer.

In an exemplary embodiment of the present disclosure, the area of the upper electrode layer 33 may be smaller than the area of the lower electrode material layer 310, and the area of the capacitive medium layer 32 may be equal to the area of the upper electrode layer 33. The capacitor dielectric material layer 320 and the upper electrode material layer 330 may be etched by a photolithography process to form the capacitor dielectric layer 32 and the upper electrode layer 33.

In an exemplary embodiment of the present disclosure, etching the capacitor dielectric material layer 320 and the upper electrode material layer 330 to form the capacitor dielectric layer 32 and the upper electrode layer 33 (i.e., step S220) may include step S2210 and step S2220, as shown in fig. 5, wherein:

In step S2210, a first photoresist layer is formed on the surface of the upper electrode material layer, and the orthographic projection of the first photoresist layer on the substrate is within the orthographic projection of the lower electrode material layer on the substrate.

The photoresist layer may be formed on the surface of the upper electrode material layer 330 by spin coating or other methods, and the material of the photoresist layer may be positive photoresist or negative photoresist, which is not particularly limited herein. For convenience of process, the surface of the upper electrode material layer 330 may be covered with a photoresist layer, a portion of the photoresist layer may be removed to form a first photoresist layer 700, and an area of the first photoresist layer 700 may be smaller than an area of the lower electrode material layer 310, and an orthographic projection of the first photoresist layer 700 on the substrate 1 may be located within an orthographic projection of the lower electrode material layer 310 on the substrate 1. The first photoresist layer 700 may have a circular, oval, fan-shaped, rectangular or irregular pattern in a direction parallel to the substrate 1, but of course, the first photoresist layer 700 may have other shapes, which are not listed here. The structure after step S2210 is completed in the embodiment of the disclosure is shown in fig. 6.

Step S2220, using the lower electrode material layer as an etching stop layer, and using the first photoresist layer as a photoresist to perform photolithography on the capacitor dielectric material layer and the upper electrode material layer, so as to form a capacitor dielectric layer and an upper electrode layer.

The upper electrode material layer 330 and the capacitor dielectric material layer 320, which are not overlapped with the first photoresist layer 700 in the direction perpendicular to the substrate 1, may be removed, thereby forming the capacitor dielectric layer 32 and the upper electrode layer 33. For example, the bottom electrode material layer 310 may be an etching stop layer for performing anisotropic etching on the top electrode material layer 330 and the capacitor dielectric material layer 320 that do not overlap with the first photoresist layer 700 in the direction perpendicular to the substrate 1, and in this process, the first photoresist layer 700 may be a photoresist, so that the top electrode material layer 330 and the capacitor dielectric material layer 320 that overlap with the first photoresist layer 700 in the direction perpendicular to the substrate 1 remain, namely: the upper electrode material layer 330 and the capacitor dielectric material layer 320 directly under the first photoresist layer 700 are reserved, and after etching is completed, the upper electrode material layer 330 directly under the first photoresist layer 700 is defined as an upper electrode layer 33, and at the same time, the capacitor dielectric material layer 320 directly under the first photoresist layer 700 is defined as a capacitor dielectric layer 32.

It should be noted that, after the etching is completed, the first photoresist layer 700 may be removed by ashing or other processes, so as to expose the upper electrode layer 33 formed by etching. The structure after step S2220 is completed in the embodiment of the present disclosure is shown in fig. 7.

In step S230, a photoresist layer is formed to cover the upper electrode layer and the lower electrode material layer adjacent to the capacitor dielectric layer, and the orthographic projection of the photoresist layer on the substrate is within the orthographic projection of the lower electrode material layer on the substrate.

The photoresist layer may be formed on the surfaces of the upper electrode layer 33 and the lower electrode material layer 310 by spin coating or other methods, and the material of the photoresist layer may be positive photoresist or negative photoresist, which is not particularly limited herein. For convenience of process, the photoresist layer may be spread over the surface of the structure formed by the upper electrode layer 33, the capacitor dielectric layer 32 and the lower electrode material layer 310, that is: the photoresist layer may fill the surface of the upper electrode layer 33, the sidewalls of the capacitor dielectric layer 32, and the surface of the structure of the lower electrode material layer 310 not covered by the capacitor dielectric layer 32. Portions of the photoresist layer may be removed to form the photoresist layer 300. The photoresist layer 300 may have an area larger than that of the upper electrode layer 33 and smaller than that of the lower electrode material layer 310; the front projection of the upper electrode layer 33 onto the substrate 1 may be located within the front projection of the photoresist layer 300 onto the substrate 1, and the front projection of the photoresist layer 300 onto the substrate 1 may be located within the front projection of the lower electrode material layer 310 onto the substrate 1.

The photoresist layer 300 may have a circular, oval, fan-shaped, rectangular or irregular pattern in a direction parallel to the substrate 1, however, the photoresist layer 300 may have other shapes, which are not illustrated herein. The structure after step S230 is completed in the embodiment of the present disclosure is shown in fig. 8.

And step S240, removing the lower electrode material layer which is not covered by the photoresist layer to form a lower electrode layer.

The lower electrode material layer 310 may be etched to form the lower electrode layer 31. For example, the lower electrode material layer 310, which is not overlapped with the photoresist layer 300 in the direction perpendicular to the substrate 1, may be removed, thereby forming the lower electrode layer 31. For example, the isolation layer 2 may be used as an etching stop layer to anisotropically etch the bottom electrode material layer 310 which is not overlapped with the photoresist layer 300 in the direction perpendicular to the substrate 1, and in this process, the photoresist layer 300 may be used as a photoresist, so that the bottom electrode material layer 310 overlapped with the photoresist layer 300 in the direction perpendicular to the substrate 1 is remained, namely: the bottom electrode material layer 310 directly under the photoresist layer 300 is remained, and the bottom electrode material layer 310 directly under the photoresist layer 300 may be defined as the bottom electrode layer 31 after etching is completed.

It should be noted that, after etching, the photoresist layer 300 may be removed by ashing or other processes, so as to expose the surface of the upper electrode layer 33, the sidewall of the capacitor dielectric layer 32, and the surface of the lower electrode layer 31 not covered by the capacitor dielectric layer 32. At this time, the area of the upper electrode layer 33 is smaller than that of the lower electrode layer 31. The structure after step S240 is completed in the embodiment of the present disclosure is shown in fig. 9.

It should be noted that, when forming the bottom electrode layers 31 of the plurality of capacitor structures 3 by the same patterning process, the photoresist layer 300 may have a shape as shown in fig. 10, and the photoresist layer 300 in fig. 10 is used as a mask to etch the bottom electrode material layer 310, so as to form a plurality of bottom electrode layers 31 with equal areas. When the upper electrode layers 33 of the plurality of capacitor structures 3 are formed by the same patterning process, as shown in fig. 11, the shape of the first photoresist layer 700 may be that the area of each region of the mask in fig. 11 is sequentially increased from left to right, and the photoresist layer 300 in fig. 11 is used as the mask to etch the upper electrode material layer 330 and the capacitor dielectric material layer 320, so that a plurality of upper electrode layers 33 with unequal areas may be formed, and the area of each upper electrode layer 33 is sequentially increased from left to right.

For example, in a direction parallel to the substrate 1, the area of the upper electrode layer 33 of each capacitor structure 3 may be 10um, 20um, 25um, 62um, 63um, 155um, 252um, respectively from left to right.

As shown in fig. 2, in step S140, a first lead and a second lead are formed on a side of the capacitor structure away from the substrate, the first lead is in contact connection with the lower electrode layer, the second lead is in contact connection with the upper electrode layer, and orthographic projections of the first lead and the second lead on the substrate do not overlap each other.

The first lead 41 and the second lead 42 may be made of conductive materials, and the lower electrode layer 31 and the upper electrode layer 33 may be electrically led out through the first lead 41 and the second lead 42, respectively, so that a test voltage may be applied to the lower electrode layer 31 and the upper electrode layer 33 of the capacitor structure 3 through the first lead 41 and the second lead 42, thereby completing an electrical performance test of the capacitor structure 3.

When the number of the capacitor structures 3 is plural, each capacitor structure 3 may have the first lead 41 and the second lead 42 corresponding thereto.

The process of forming the first lead 41 and the second lead 42 will be described in detail below taking the first lead 41 and the second lead 42 corresponding to the formation of one capacitor structure 3 as an example:

in an exemplary embodiment of the present disclosure, a first lead 41 and a second lead 42 are formed on a side of the capacitor structure 3 remote from the substrate 1, the first lead 41 is in contact with the lower electrode layer 31, the second lead 42 is in contact with the upper electrode layer 33, and orthographic projections of the first lead 41 and the second lead 42 on the substrate 1 do not overlap each other (i.e., step S140) may include steps S310 to S340, as shown in fig. 12, wherein:

In step S310, an insulating layer is formed to cover the capacitor structure.

In one exemplary embodiment of the present disclosure, the insulating layer 400 may cover the surface of the capacitor structure 3, which may simultaneously cover the surface of the isolation layer 2 not covered by the lower electrode layer 31, and the end of the insulating layer 400 may be flush with the end of the isolation layer 2.

The insulating layer 400 may be a thin film formed on the surfaces of the capacitor structure 3 and the lower electrode layer 31 and the upper electrode layer 33, or may be a coating formed on the surfaces of the capacitor structure 3 and the lower electrode layer 31 and the upper electrode layer 33, and is not particularly limited. In one embodiment, the insulating layer 400 may be formed on the surfaces of the capacitor structure 3 and the lower electrode layer 31 and the upper electrode layer 33 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation, magnetron sputtering, or the like, and of course, the insulating layer 400 may be formed by other methods, which are not limited herein.

The material of insulating layer 400 may be an insulating material, for example, silicon dioxide, a high-k dielectric material, or other dielectric material, or any combination thereof. The thickness of the insulating layer 400 may be set according to actual needs. The structure after step S310 is completed in the embodiment of the present disclosure is shown in fig. 13.

In step S320, a mask layer is formed on the surface of the insulating layer.

For example, the mask layer 500 may be formed on the surface of the insulating layer 400, and the mask layer 500 may be a single film layer or a composite film layer formed by multiple film layers, where the number of film layers in the mask layer 500 is not particularly limited, and when it is a multiple film layer, the materials of adjacent film layers may be different.

The mask layer 500 may be an anti-reflective coating, and the material may be an insulating material, for example, silicon nitride, silicon oxide, or carbide, and a specific material may be selected according to the design and requirements of the subsequent photolithography process, and in an embodiment, the mask layer 500 may have a lower dielectric constant and a certain hardness, and may meet the requirements of the subsequent etching process while reducing the coupling with the substrate 1, for example, the material may be carbon-doped silicon nitride. The structure after step S320 is completed in the embodiment of the present disclosure is shown in fig. 14.

And step S330, patterning the insulating layer by taking the mask layer as a mask to form a first contact hole exposing the lower electrode layer and a second contact hole exposing the upper electrode layer in the insulating layer, wherein the orthographic projection of the first contact hole on the substrate is not overlapped with the orthographic projection of the upper electrode layer on the substrate, and the orthographic projection of the second contact hole on the substrate is within the orthographic projection of the upper electrode layer on the substrate.

The first contact hole 411 and the second contact hole 421 may be formed in the insulating layer 400 through an etching process, and the first contact hole 411 may expose the lower electrode layer 31. The first contact hole 411 may be a circular hole, an elliptical hole, a rectangular hole, a ring-shaped hole, or a hole-like structure of other shape, and the shape of the first contact hole 411 is not particularly limited herein as long as the lower electrode layer 31 can be exposed.

In an embodiment, the front projection of the first contact hole 411 on the substrate 1 and the front projection of the lower electrode layer 31 on the substrate 1 overlap at least partially, and the front projection of the first contact hole 411 on the substrate 1 and the front projection of the upper electrode layer 33 on the substrate 1 do not overlap. Preferably, the first contact hole 411 may have a ring shape, and its orthographic projection on the substrate 1 may cover an edge of the orthographic projection of the lower electrode layer 31 on the substrate 1 for one circle, that is: the first contact hole 411 may expose an edge of the lower electrode layer 31 for one circumference.

The orthographic projection of the second contact hole 421 on the substrate 1 does not overlap with the orthographic projection of the first contact hole 411 on the substrate 1, and the orthographic projection of the second contact hole 421 on the substrate 1 is within the orthographic projection of the upper electrode layer 33 on the substrate 1. The first contact hole 411 and the second contact hole 421 are isolated by the insulating layer 400, so that the first lead 41 formed in the first contact hole 411 and the second lead 42 formed in the second contact hole 421 are prevented from shorting.

The second contact hole 421 may expose the upper electrode layer 33, and the second contact hole 421 may have a circular hole, an elliptical hole, a rectangular hole, or a hole-like structure having other shapes, and the shape of the second contact hole 421 is not particularly limited as long as the upper electrode layer 33 can be exposed. The structure after step S330 is completed in the embodiment of the present disclosure is shown in fig. 15.

In an exemplary embodiment of the present disclosure, patterning the insulating layer 400 with the mask layer 500 as a mask to form a first contact hole 411 exposing the lower electrode layer 31 and a second contact hole 421 exposing the upper electrode layer 33 in the insulating layer 400 (i.e., step S330) may include step S3310 and step S3320, wherein:

in step S3310, a second photoresist layer is formed on the surface of the mask layer, where the second photoresist layer includes a first developing region and a second developing region, where the orthographic projection of the first developing region on the substrate does not overlap with the orthographic projection of the upper electrode layer on the substrate, and the orthographic projection of the second developing region on the substrate is within the orthographic projection of the upper electrode layer on the substrate.

The second photoresist layer 800 may be formed on the surface of the mask layer 500 by spin coating or other methods, and the material of the second photoresist layer 800 may be a positive photoresist or a negative photoresist, which is not particularly limited herein. For convenience of process, the second photoresist layer 800 may be spread over the surface of the mask layer 500, and the second photoresist layer 800 may be exposed and developed using a reticle to form a first development region 801 and a second development region 802 in the second photoresist layer 800; wherein:

The first developing region 801 may be circular, elliptical, rectangular, annular, or other shape, and the shape of the first developing region 801 is not particularly limited herein. The front projection of the first development zone 801 onto the substrate 1 and the front projection of the lower electrode layer 31 onto the substrate 1 overlap at least partially, and the front projection of the first development zone 801 onto the substrate 1 does not overlap with the front projection of the upper electrode layer 33 onto the substrate 1.

The second development zone 802 may be circular, oval, rectangular, or other shape, and the shape of the second development zone 802 is not particularly limited herein. The orthographic projection of the second developing region 802 on the substrate 1 does not overlap with the orthographic projection of the first contact hole 411 on the substrate 1, and the orthographic projection of the second developing region 802 on the substrate 1 is within the orthographic projection of the upper electrode layer 33 on the substrate 1. The structure after step S3310 is completed in the embodiment of the disclosure is shown in fig. 16.

And step S3320, etching the mask layer and the insulating layer in the first development region and the second development region to form a first contact hole exposing the lower electrode layer and a second contact hole exposing the upper electrode layer.

The insulating layer 400 may be etched in the first and second development regions 801 and 802 by a dry etching process using the mask layer 500 as a mask, thereby forming a first contact hole 411 exposing the lower electrode layer 31 and a second contact hole 421 exposing the upper electrode layer 33.

The etching gas of the dry etching can comprise SF ₆ 、CF _x 、Cl ₂ Or Ar, which may include Ar, for example, and SF, for example ₆ 、CF _x Or Cl ₂ At least one gas of (a) and (b).

It should be noted that, after the first contact hole 411 and the second contact hole 421 are formed, the mask layer 500 is not required to be removed, for example, the remaining mask layer 500 may be remained, and thus the surface of the test structure may be protected by the mask layer 500, so that the surface damage of the test structure may be avoided; in addition, the tensile stress in the insulating layer 400 can be balanced by the compressive stress of the mask layer 500, so that the test structure reaches the stress balance.

And step S340, filling conductive materials in the first contact hole and the second contact hole respectively to form a first lead in the first contact hole and a second lead in the second contact hole.

The first contact hole 411 and the second contact hole 421 may be filled with a conductive material by electroplating, vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, or the like, and of course, the first contact hole 411 and the second contact hole 421 may be filled with a conductive material by other methods, so that the first lead 41 is formed in the first contact hole 411 and the second lead 42 is formed in the second contact hole 421, so that the lower electrode layer 31 and the upper electrode layer 33 are electrically led out through the first lead 41 and the second lead 42, respectively. The structure after step S340 is completed in the embodiment of the present disclosure is shown in fig. 17.

It should be noted that, when the first contact hole 411 is annular, and the front projection of the first contact hole on the substrate 1 covers a circle of the front projection edge of the lower electrode layer 31 on the substrate 1, the first lead 41 may also be annular, and the front projection of the first lead 41 on the substrate 1 may cover a circle of the front projection edge of the lower electrode layer 31 on the substrate 1, so that when the electrical performance test of the capacitor structure 3 is performed subsequently, a uniform electric field distribution may be realized, and the accuracy of the test structure is ensured.

In an exemplary embodiment of the present disclosure, the conductive material may be a metal material, for example, it may be tungsten or titanium nitride, and of course, other materials with better conductive properties may also be used, which are not listed here.

In some embodiments of the present disclosure, as shown in fig. 18, in the process of filling the conductive material, for convenience of process, the conductive material may be simultaneously deposited on the surface of the mask layer 500, and then the conductive material layer 600 is formed on the surface of the mask layer 500, and the deposition is stopped after the conductive material fills the first contact hole 411 and the second contact hole 421, at this time, the conductive material in the first contact hole 411 and the conductive material in the second contact hole 421 are connected together through the conductive material layer 600; the conductive material layer 600 on the surface of the mask layer 500 may be etched through a patterning process (e.g., a photolithography process), thereby breaking the first lead 41 in the first contact hole 411 and the second lead 42 in the second contact hole 421.

For example, as shown in fig. 19, a third photoresist layer 900 may be formed on the surface of the conductive material layer 600, and the third photoresist layer 900 may be exposed and developed to form a developing region, where the developing region may be located between the first contact hole 411 and the second contact hole 421, and the developing region may be formed in a ring shape around the periphery of the first contact hole 411, and when the second contact hole 421 is formed in a ring shape, the ring shape of the developing region may be located within the ring shape of the second contact hole 421; the orthographic projection of the third photoresist layer 900 on the substrate 1 at least partially overlaps with the orthographic projection of the first lead 41 on the substrate 1, and at the same time, the orthographic projection of the third photoresist layer 900 on the substrate 1 at least partially overlaps with the orthographic projection of the second lead 42 on the substrate 1.

In addition, when the first leads 41 and the second leads 42 corresponding to the plurality of capacitor structures 3 are formed by the same patterning process, the third photoresist layer 900 may be shaped as shown in fig. 20, and the conductive material layer 600 may be etched using the third photoresist layer 900 in fig. 20 as a mask, so that the plurality of first leads 41 connected to the lower electrode layers 31 of the respective capacitor structures 3 and the plurality of second leads 42 connected to the upper electrode layers 33 of the respective capacitor structures 3 may be formed.

As shown in fig. 2, in step S150, a first test pad and a second test pad are formed on a side of the isolation layer away from the substrate, where the first test pad is in contact connection with the first lead, and the second test pad is in contact connection with the second lead.

Each capacitor structure 3 may be correspondingly provided with a first test pad 51 and a second test pad 52, each of the first test pad 51 and the second test pad 52 may be made of a conductive material, each of the first test pad 51 and each of the second test pad 52 may be respectively located at two sides of the capacitor structure 3 corresponding thereto, and the first lead 41 and the second lead 42 corresponding to the capacitor structure 3 may be respectively connected through the first test pad 51 and the second test pad 52 so as to transmit a test voltage to the lower electrode layer 31 and the upper electrode layer 33 of the capacitor structure 3 through the first test pad 51 and the second test pad 52, respectively, so as to complete an electrical performance test of the capacitor structure 3.

In some embodiments of the present disclosure, the first and second test pads 51 and 52 may be formed on the surface of the separation layer 2 and may be spaced apart from each other on the surface of the separation layer 2; the first and second test pads 51 and 52 may be formed on the surface of the insulating layer 400 and may be arranged at intervals on the surface of the insulating layer 400; the first test pad 51 and the second test pad 52 may also be formed on the surface of the mask layer 500, and may be arranged at intervals on the surface of the mask layer 500; of course, the first test pad 51 and the second test pad 52 may be formed on the surface of other film layers on the side of the isolation layer 2 away from the substrate 1, and specific positions of the first test pad 51 and the second test pad 52 are not particularly limited herein, so long as the first test pad 51 and the second test pad 52 can communicate with the first lead 41 and the second lead 42, respectively, and can transmit the test voltage to the first lead 41 and the second lead 42.

For example, the first test pad 51 and the second test pad 52 may be formed on the side of the isolation layer 2 facing away from the substrate 1 by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or thermal evaporation, or the like, however, the first test pad 51 and the second test pad 52 may be formed by other methods, and the forming manner of the first test pad 51 and the second test pad 52 is not particularly limited.

The material of the first test pad 51 may be a metal material, for example, tungsten or titanium nitride, but of course, other materials with better conductivity may be used, which are not listed here. In some embodiments, the materials of the first test pad 51 and the second test pad 52 may be the same or different, and are not particularly limited herein. For example, the materials of the first test pad 51 and the second test pad 52 may be the same, for example, the materials of the first test pad 51 and the second test pad 52 may be tungsten, or the materials of the first test pad 51 and the second test pad 52 may be titanium nitride, or one of the materials of the first test pad 51 and the second test pad 52 may be tungsten, and the other material may be titanium nitride.

Each capacitor structure 3 and the corresponding first lead 41, second lead 42, first test pad 51 and second test pad 52 together form a test unit, and the space between the test units can be set according to the space between the pins in the test device, which is not particularly limited herein. The structure after step S150 is completed in the embodiment of the present disclosure is shown in fig. 21.

It should be noted that, when the first test pads 51 and the second test pads 52 corresponding to the plurality of capacitor structures 3 are formed by the same patterning process, the photoresist layer 300 in fig. 22 may be used as a mask as shown in fig. 22 to etch the metal material layer, so as to form a plurality of first test pads 51 respectively connected to the first leads 41 of the capacitor structures 3 and a plurality of second test pads 52 respectively connected to the second leads 42 of the capacitor structures 3.

During each patterning process, the mask used to form the lower electrode layer 31, the mask used to form the upper electrode layer 33, the mask used to form the first and second leads 41 and 42, and the mask used to form the first and second test pads 51 and 52 are stacked as shown in fig. 23, in which the mask regions between two adjacent test cells are used for alignment, minimizing alignment errors.

In the testing process, two test probes in the testing device can be respectively tied on the first test pad 51 and the second test pad 52, so as to complete the testing of the capacitor structure 3. The semiconductor test structure has higher test sensitivity, and can detect weak ferroelectric or antiferroelectric effect signals existing in the capacitor structure 3 through the semiconductor test structure.

It should be noted that although the various steps of the method of forming a semiconductor test structure in the present disclosure are depicted in the drawings in a particular order, this is not required or implied that these steps be performed in the particular order or that all of the illustrated steps be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.

The disclosed embodiments also provide a semiconductor test structure, which may include a substrate 1, an isolation layer 2, a capacitor structure 3, first and second leads 41 and 42, and first and second test pads 51 and 52, as shown in fig. 17 and 21, wherein:

an isolation layer 2 may be formed on the substrate 1;

the capacitor structure 3 may be formed on a surface of the isolation layer 2 away from the substrate 1, and the capacitor structure 3 may include a lower electrode layer 31, a capacitor dielectric layer 32, and an upper electrode layer 33 stacked in sequence along a direction perpendicular to the substrate 1;

the first lead 41 and the second lead 42 may be formed on a side of the capacitor structure 3 away from the substrate 1, the first lead 41 being in contact with the lower electrode layer 31, the second lead 42 being in contact with the upper electrode layer 33, the orthographic projections of the first lead 41 and the second lead 42 on the substrate 1 not overlapping each other;

The first test pad 51 and the second test pad 52 may be arranged at intervals on a side of the isolation layer 2 away from the substrate 1, the first test pad 51 is in contact connection with the first lead 41, and the second test pad 52 is in contact connection with the second lead 42.

In the semiconductor test structure disclosed by the disclosure, the planar capacitor structure 3 can be directly formed on the substrate 1, the lower electrode layer 31 of the capacitor structure 3 can be connected with the first test pad 51 through the first lead 41, the upper electrode layer 33 of the capacitor structure 3 can be connected with the second test pad 52 through the second lead 42, and the test probe can be tied on the first test pad 51 and the second test pad 52, so that the test of the capacitor structure 3 is completed. In the process, on one hand, capacitor preparation and test are not required to be carried out after the transistor preparation is completed, so that the capacitor test period can be shortened, and the capacitor research and development progress can be accelerated; on the other hand, the influence of the technological process for forming the hole-shaped structure on the test result can be eliminated without manufacturing the hole-shaped structure with high depth-to-width ratio; meanwhile, as the capacitor structure 3 is directly prepared on the substrate 1, other structures (such as transistors) are not arranged on the substrate 1, the influence of other structures on the capacitor test result can be eliminated, the test result is more accurate, and the accuracy of the test result can be improved; in addition, through setting up isolation layer 2 between capacitance structure 3 and substrate 1, and then through isolation layer 2 blocking the inside impurity diffusion of substrate 1 to capacitance structure 3, can get rid of the influence of impurity in the substrate 1 to capacitance structure 3 test result, further improve the rate of accuracy of test result.

Specific details of the semiconductor test structure in the embodiments of the present disclosure are described below:

The isolation layer 2 may be located on the surface of the substrate 1, and the substrate 1 may be separated from other film layers by the isolation layer 2, so as to avoid the impurity in the substrate 1 from diffusing into the other film layers, which helps to ensure the stability of the device.

The spacer layer 2 may be a thin film formed on the surface of the substrate 1 or a coating layer formed on the surface of the substrate 1, and is not particularly limited. The material of the isolation layer 2 may be an insulating material, for example, silicon dioxide, a high-k dielectric material, or other dielectric material, or any combination thereof. The thickness of the isolation layer 2 may be set according to actual needs.

The capacitor structure 3 may be a planar capacitor, and the capacitor structure 3 may include a lower electrode layer 31, a capacitor dielectric layer 32 and an upper electrode layer 33 that are stacked and distributed, where the lower electrode layer 31 may be located on the surface of the isolation layer 2, the capacitor dielectric layer 32 may be located on the surface of the lower electrode layer 31, the upper electrode layer 33 may be located on the surface of the capacitor dielectric layer 32, the area of the upper electrode layer 33 may be equal to the area of the capacitor dielectric layer 32, and the area of the upper electrode layer 33 may be equal to or unequal to the area of the lower electrode layer 31, which is not limited herein.

The material of the upper electrode layer 33 may be a material with good conductivity, for example, it may include titanium, titanium nitride, tungsten, silicon germanium, or the like, or a combination of any two of the above materials. Preferably, the material of the upper electrode layer 33 may be a combination of titanium nitride and silicon germanium. The material of the lower electrode layer 31 may be a material having a good electrical conductivity, and may be the same as that of the upper electrode layer 33 or may be different from that of the upper electrode layer 33, and is not particularly limited. Preferably, the material of the lower electrode layer 31 is the same as the material of the upper electrode layer 33, for example, the material of the lower electrode layer 31 and the material of the upper electrode layer 33 are both a combination of titanium nitride and silicon germanium. The material of the capacitor dielectric layer 32 may be a material with a high dielectric constant, for example, it may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, silicon nitride, or a mixture thereof, but may be other materials, which are not listed here.

In some embodiments of the present disclosure, the areas of the lower electrode layers 31 in each of the capacitor structures 3 are equal in a direction parallel to the substrate 1, and the areas of the upper electrode layers 33 of each of the capacitor structures 3 are different from each other. Through testing the electrical properties of the capacitor structures 3 with the areas of the upper electrode layers 33 being different from each other, more effective data can be obtained, databases for data analysis can be enriched, the accuracy of data analysis is improved, and further the influence of parasitic capacitance on the capacitance can be rapidly eliminated in the process of subsequent analysis.

In an embodiment, each capacitor structure 3 may be distributed on the surface of the isolation layer 2 side by side, and in a direction parallel to the substrate 1, the area of the upper electrode layer 33 in each capacitor structure 3 may be sequentially increased or decreased, so that the relationship between the capacitor area and the capacitor storage capacity can be clearly seen in the subsequent testing process, which is helpful for reducing the difficulty of data analysis. After the test is completed, a relation curve of the area size of the capacitor structure 3 and the storage capacity of the capacitor structure 3 can be drawn according to the test result, and abnormal data can be rapidly removed according to the relation curve.

The first lead 41 and the cross section may be circular, elliptical, rectangular, annular, or other shapes, and the shape of the first lead 41 is not particularly limited herein. Preferably, the cross section of the first lead 41 may be annular, and the orthographic projection of the first lead 41 on the substrate 1 may cover a circumference of the edge of the orthographic projection of the lower electrode layer 31 on the substrate 1, so that when the electrical performance test of the capacitor structure 3 is performed subsequently, uniform electric field distribution may be realized, and the accuracy of the test structure is ensured.

The material of the first lead 41 may be a metal material, for example, tungsten or titanium nitride, but of course, other materials with better conductivity may be used, which are not listed here.

The second lead 42 and the cross section may be circular, oval, rectangular or other shapes, and the shape of the second lead 42 is not particularly limited herein. The material of the second lead 42 may be a metal material, for example, tungsten or titanium nitride, but of course, other materials with better conductivity may be used, which are not listed here.

In some embodiments, the material of the second lead 42 may be the same as the material of the first lead 41, or may be different from the material of the first lead 41, which is not particularly limited herein. For example, the material of the second lead 42 and the first lead 41 may be the same, which may be tungsten.

Each of the capacitor structures 3 may be provided with a first test pad 51 and a second test pad 52, and each of the first test pad 51 and the second test pad 52 may be made of a conductive material, as shown in fig. 21, and each of the first test pad 51 and each of the second test pad 52 may be located at two sides of the capacitor structure 3 corresponding thereto, and may be in communication with the first lead 41 and the second lead 42 corresponding to the capacitor structure 3 through the first test pad 51 and the second test pad 52, respectively, so that a test voltage may be transmitted to the lower electrode layer 31 and the upper electrode layer 33 of the capacitor structure 3 through the first test pad 51 and the second test pad 52, respectively, so as to complete an electrical performance test of the capacitor structure 3.

Each capacitor structure 3 and the corresponding first lead 41, second lead 42, first test pad 51 and second test pad 52 together form a test unit, and the space between the test units can be set according to the space between the pins in the test device, which is not particularly limited herein.

The disclosed embodiments also provide a test result analysis system, which can be used to analyze weak ferroelectric and antiferroelectric effect signals, the area of the upper electrode layer 33 of the capacitor structure 3, and the storage capacity of each capacitor structure 3 in the semiconductor test structure in any of the above embodiments, and includes a data importing component and a data generating component, wherein:

the data importing component may be used to import test data of the semiconductor test structure in some of the embodiments described above; the test data comprise the area of the upper electrode layer 33 of each capacitor structure 3 and the corresponding storage capacity of each capacitor structure 3;

The data generating component may be configured to generate a test analysis result according to the area of the upper electrode layer 33 of each capacitor structure 3 and the storage capacity corresponding to each capacitor structure 3.

According to the test result analysis system disclosed by the disclosure, test analysis results can be generated according to the area of the upper electrode layer 33 of each capacitor structure 3 and the storage capacity of each capacitor structure 3, the relation between the area of the capacitor structure 3 and the storage capacity of the capacitor structure can be clearly seen, a monitoring plate can be manufactured according to the test analysis results, and in the research and development process, the manufacturing process stability of the capacitor medium layer 32 can be monitored through the monitoring plate, so that when the storage capacity of the capacitor structure 3 obtained by testing in the process is changed, the change of the storage capacity of the capacitor structure 3 can be rapidly checked according to the test analysis results because of the change of the material of the capacitor medium layer 3 or because of the change of the key size in the capacitor structure 3, and the research and development progress can be accelerated.

In an exemplary embodiment of the present disclosure, the semiconductor test structure may be subjected to an electrical performance test to obtain test data, where the test data may be an area of the upper electrode layer 33 of each capacitor structure 3 and a storage capacity corresponding to each capacitor structure 3, and the test data may be imported into a test result analysis system through a data importing component so as to perform data analysis. In one embodiment, the data importing component may be a data interface, which may be a hardware interface or a software calling program, where no special limitation is made, and of course, may be other forms of data importing components, as long as the test data can be imported into the test analysis system, where no special limitation is made to the specific type of the data importing component.

The data generation component can invoke test data within the data import component and can generate test analysis results based on the test data. For example, a graph of the area of the upper electrode layer 33 and the storage capacity corresponding to the area of the upper electrode layer 33 can be generated by the test data generating component, and during the development process, the developer can quickly exclude abnormal data according to the graph. Of course, the area of the upper electrode layer 33 and the storage capacity corresponding to the area of the upper electrode layer 33 may be plotted as a table, and in the subsequent development process, whether the data has an abnormality may be determined by looking up a table.

For example, when the change relation diagram drawn by the capacitance storage capacity and the area of the capacitance upper electrode layer 33 is a straight line, in the subsequent development process, whether the test data is normal can be quickly determined by looking up the change relation diagram, for example, if the storage capacity of a certain capacitance structure 3 and the area of the upper electrode layer 33 are obtained by the subsequent test, the storage capacity and the area of the upper electrode layer 33 are put into the change relation diagram for comparison, and if the data is coincident with the change relation diagram, the test data of the capacitance structure 3 is determined to be authentic; if the data is deviated, it is determined that the test data of the capacitor structure 3 is problematic and has no reliability.

It should be noted that, the data analysis system of the present disclosure may also be used to analyze the relationship between the dielectric constant of the material of the capacitive dielectric layer 32 and the storage capacity of the capacitor, and the analysis principle is similar to the analysis process of the relationship between the capacitance area and the storage capacity, so that the description thereof is omitted herein.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A method of forming a semiconductor test structure, comprising:

providing a substrate;

forming an isolation layer on the substrate;

2. The forming method according to claim 1, characterized in that the forming method further comprises:

3. The method of forming of claim 2, wherein areas of upper electrode layers of each of the capacitor structures are not equal to each other in a direction parallel to the substrate.

4. A forming method according to claim 3, wherein each of the capacitor structures is arranged side by side, and an area of an upper electrode layer in each of the capacitor structures is sequentially increased or decreased in a direction parallel to the substrate.

5. The method of claim 1, wherein the orthographic projection of the first lead on the substrate covers an edge of the orthographic projection of the lower electrode layer on the substrate for one revolution.

6. The method of any one of claims 1-5, wherein forming a capacitor structure on a surface of the isolation layer away from the substrate, the capacitor structure including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer stacked in order along a direction perpendicular to the substrate, includes:

7. The method of forming of any one of claims 1-5, wherein forming a first lead and a second lead on a side of the capacitive structure remote from the substrate, the first lead being in contact with the lower electrode layer, the second lead being in contact with the upper electrode layer, the orthographic projections of the first lead and the second lead on the substrate not overlapping each other, comprises:

forming an insulating layer covering the capacitor structure;

forming a mask layer on the surface of the insulating layer;

8. The method of forming of claim 6, wherein etching the capacitor dielectric material layer and the upper electrode material layer to form a capacitor dielectric layer and an upper electrode layer comprises:

9. The method of forming of claim 7, wherein patterning the insulating layer with the mask layer as a mask to form a first contact hole exposing the lower electrode layer and a second contact hole exposing the upper electrode layer in the insulating layer comprises:

10. A semiconductor test structure, comprising:

a substrate;

an isolation layer formed on the substrate;

11. The test structure of claim 10, wherein the number of the capacitor structures is a plurality, the plurality of capacitor structures each being formed on a surface of the isolation layer remote from the substrate, each of the capacitor structures having the first lead and the second lead corresponding thereto; the areas of the upper electrode layers of at least part of the capacitor structures are not equal in a direction parallel to the substrate.

12. The test structure of claim 11, wherein the areas of the upper electrode layers of each of the capacitor structures are not equal to each other in a direction parallel to the substrate.

13. The test structure of claim 12, wherein each of the capacitor structures is arranged side by side and an area of an upper electrode layer in each of the capacitor structures is sequentially increased or decreased in a direction parallel to the substrate.

14. The test structure of claim 10, wherein the orthographic projection of the first lead on the substrate covers an edge of the orthographic projection of the lower electrode layer on the substrate for one revolution.

15. A test result analysis system, comprising:

a data importing component for importing test data of the semiconductor test structure of claim 11; the test data comprise the area of the upper electrode layer of each capacitor structure and the storage capacity corresponding to each capacitor structure;