CN117476471A - Method of manufacturing semiconductor device and corresponding semiconductor device - Google Patents

Abstract

The present disclosure relates to a method of manufacturing a semiconductor device and a corresponding semiconductor device. Semiconductor devices, currently known as package-level-System (SiP) types and having a transformer embedded therein, are produced by embedding at least one semiconductor chip in an insulating encapsulation at a first portion thereof. A stacked structure is formed over a second portion thereof that is at least partially non-overlapping with the first portion, the stacked structure including a respective pattern of electrically conductive material and a plurality of layers of electrically insulating material. Corresponding pattern of conductive material: having a planar coil geometry for providing a conductive coil (such as the windings of a transformer); and has a geometric distribution of conductive connections provided to one or more semiconductor chips.

Description

Method of manufacturing semiconductor device and corresponding semiconductor device

Cross Reference to Related Applications

The present application claims the benefit of priority from italian patent application No. 102022000016011 filed at 28, 7, 2022, the contents of which are incorporated herein by reference in their entirety to the maximum extent allowed by law.

Technical Field

The present description relates to the fabrication of semiconductor devices including electrical coils, for example in transformers.

The solutions described herein may be applied to, for example, DC/DC converters, current insulators (galvanic insulator), and are generally applied to semiconductor device packages having coils embedded therein.

Background

Semiconductor devices of the type currently known as package-level Systems (SiP) may have a (high performance) transformer embedded therein.

These transformers may be formed starting from a core laminate. This approach can be quite expensive; additionally, the presence of the portion of the leadframe on which the transformer is placed may result in coupling with the metal (e.g., copper) of the leadframe, with associated losses. These losses are mainly due to the fact that the metal frame acts as a shield, thereby adversely affecting the mutual coupling of the coils.

For example, a transformer integrated with a so-called fan-out panel level package (Fan Out Panel Level Package, FOPLP) formed over silicon is described in "A transformer using two RDL metal layers based on Fan-Out Panel Level Package Technology (a transformer using two RDL metal layers based on fan-out panel level package technology) published in J Phys: conf. Ser.1971, 012041, by z.wang et al, incorporated by reference. This approach also results in coupling with silicon and the consequent loss. It is noted that the transformer has a size comparable to the size of the die, which makes it unsuitable for power applications.

Accordingly, there is a need in the art to adequately address the problems discussed previously.

Disclosure of Invention

One or more embodiments relate to a method.

One or more embodiments may also relate to a corresponding semiconductor device in which a coil (e.g., a transformer) is embedded.

One or more embodiments provide a circuit layout in which coils are integrated in a package level System (SiP) using panel embedded packaging (Panel Embedded Package, PEP) technology.

In various embodiments, the coils may be formed at a metallization level of PEP technology, resulting in a package-level system layout in which the die/dies and the coil/coils do not (at least substantially) overlap each other.

The advantages of the solution described herein can be summarized as follows: for example, one or more coils for a transformer may be created using metal (e.g., copper) plating, thereby avoiding the installation of the coils in a package; since there are no metal pads for one or more coils, electrical performance is improved with increasing inductance; since the wires are replaced via, for example, DCI interconnects, which also have advantages in terms of coupling coefficient and Q factor, the resistance is also reduced; the overall package thickness may decrease as the package footprint may decrease; and flexibility in package layout is improved with possible cost reduction.

The solution described herein utilizes LDS/DCI technology and envisages forming the coil/transformer directly in encapsulation molding (molding).

In this way, the provision of a support frame, transformer substrate and related processes (wire bonding/die/substrate attachment) can be avoided.

The solutions described herein may also help reduce package size (in terms of both footprint and thickness) while improving electrical performance.

Drawings

One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

fig. 1 is a perspective view of a conventional System In Package (SiP) with a transformer embedded therein;

FIG. 2 is a side view of a conventional System In Package (SiP) taken along line II-II of FIG. 1;

fig. 3 is a perspective view of a System In Package (SiP) according to an embodiment of the present description;

fig. 4 is a plan view of the System In Package (SiP) of fig. 3;

FIG. 5 is a side view of a System In Package (SiP) according to an embodiment of the present description taken along line V-V of FIG. 4;

fig. 6 is a perspective view of another System In Package (SiP) in accordance with an embodiment of the present description;

fig. 7 is a plan view of the System In Package (SiP) of fig. 6;

FIG. 8 is a side view of a System In Package (SiP) according to an embodiment of the present description taken along line VIII-VIII of FIG. 7; and

fig. 9A to 9L illustrate a sequence of steps according to an embodiment of the present description.

Detailed Description

It is noted that in fig. 1-8, various elements are represented as "transparent" so as not to obscure the presence of other elements in the figures. This applies, for example, to the side views of fig. 2, 5 and 8.

The drawings are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

Corresponding numerals and symbols in the various drawings generally indicate corresponding parts unless otherwise indicated: accordingly, like parts or elements are indicated by like reference numerals in the various figures, and corresponding descriptions will not be repeated for each figure. The edges of features depicted in the drawings do not necessarily indicate the termination of the feature's range.

In the following description, one or more specific details are set forth in order to provide a thorough understanding of examples of the described embodiments. Embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

References in the framework of the present description to "an embodiment" or "one embodiment" are intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may be present in one or more points of the present description do not necessarily refer to the same embodiment.

Furthermore, the particular structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Headings/references used herein are provided for convenience only and thus do not limit the scope of protection or the scope of the embodiments.

For simplicity and ease of explanation, throughout this description, the fabrication of a single device will be described, except that it is understood that the current fabrication process of semiconductor devices involves the concurrent fabrication of multiple devices that are separated into individual devices in a final singulation (singulation).

Fig. 1 and 2 are exemplary conventional System In Package (SiP) 10, the system in package 10 including a substrate (leadframe) 12, the substrate 12 including a die mounting area (die pad) 12A and an array of conductive leads 12B distributed on a side of the die pad 12A. One or more semiconductor die or chips 14 are mounted at the die pad 12A.

The name "leadframe" (or "leadframe") is currently used (see, for example, the USPC integrated vocabulary of the united states patent and trademark office) to indicate a metal frame that provides support for an integrated circuit chip or die, as well as electrical leads that interconnect the integrated circuit in the die or chip with other electrical components or contacts.

Essentially, the leadframe includes an array of conductive features (or leads, e.g., 12B) that extend inwardly from the outline location in the direction of the semiconductor chip or die (e.g., 14), thus at least one semiconductor integrated circuit chip or die is attached to the die pad (e.g., 12A) from an array configured to form conductive features from the die pad (e.g., 12A).

The package 10 further includes a transformer 18, the transformer 18 being placed on a support portion 1200 formed in the lead frame 12.

The transformer 18 may include primary and secondary windings (coils) connected to the die or chip 14 via wiring 20.

An encapsulant 22 of insulating material (e.g., epoxy) is molded onto the assembly thus formed, leaving leads 12B (shown in a transparent manner so as not to obscure other elements of package 10) protruding from encapsulant 22.

The encapsulant 22 surrounds the circuit material to protect it from corrosion or physical damage while facilitating the mounting of the electrical contacts, connecting the package to a mounting substrate, such as a Printed Circuit Board (PCB), not visible in the drawings.

During operation, the coils in the transformer 18 generate magnetic fields that inevitably interact with the metallic (e.g., copper) material of the leadframe 12 (at the portion designated 1200), which undesirably affects electrical performance.

The wiring pattern 20 may also create constraints in terms of electrical performance and package footprint size. It was observed that with packages having embedded coils such as transformer 18, standard wire interconnections lead to (very) poor layout flexibility.

Embedding such coils in standard leadframe-based packages also results in a rather complex assembly process. Conventional solutions for implementing transformers in packages may actually involve building the transformer on a dielectric substrate (e.g., of the type using ball grid array/land grid array (BGA/LGA) arrangement) that is connected to the silicon die by conventional wire bonding. A leadframe with a custom design may be required in order to adhere to galvanic isolation constraints and reduce the presence of metal parts.

In summary: the substrate of the transformer (which may be a 6-layer substrate with a thickness of, for example, 0.4 mm) is placed on one or more metal pads 1200 in the leadframe, which results in a reduction of electrical performance; standard interconnects using wires such as 20 also adversely affect electrical performance because they may introduce undesirable resistance; coils such as the transformer coil 18 illustrated in fig. 1 and 2 mounted on a substrate may have high costs; a "dedicated" lead frame 12 may be required to accommodate one or more coils; the substrate housing the coil occupies a certain space in the package 10, resulting in an increase in the footprint; and may involve additional and rather complex assembly steps.

Laser Direct Structuring (LDS) is a laser-based processing technology that has now been widely used in various industries in the industrial and consumer electronics markets, for example for high performance antenna integration, where antenna designs can be formed directly on molded plastic parts. In an exemplary process, the molded part may be produced with a commercially available insulating resin that includes additives suitable for the LDS process; a wide range of resins (such as polymeric resins, e.g., PC/ABS, ABS, LCP) are currently available for this purpose. The laser beam may be used to transfer ("structure") the desired conductive pattern onto the plastic molding, which is then metallized to ultimately form the desired conductive pattern. Metallization may involve electroless plating followed by electrolytic plating. Electroless plating (also known as electroless plating) is a class of industrial chemical processes that create metal coatings on various materials by autocatalytic chemical reduction of metal cations in a liquid bath. In electrolytic plating, the electric field between the anode and the workpiece acts as a cathode, forcing positively charged metal ions to move to the cathode where they give up charge and deposit themselves as metal on the surface of the workpiece.

LDS is also commonly referred to as Direct Copper Interconnect (DCI). This is mainly referred to the package family, where conventional wire bonding is replaced with copper plated vias and lines (traces). Laser induced ribbonized interconnect (LISI) and panel embedded encapsulation (PEP) are names of possible subfamilies of DCI encapsulation.

U.S. patent publication nos. 2018/0342453A1, 2019/0115287A1, 2020/0203264A1, 2020/031274 A1, 2021/0050226A1, 2021/0050299A1/2021/0183748A1 or 2021/0305203A1 (all of which are incorporated herein by reference) are exemplary possibilities for applying LDS technology in the manufacture of semiconductor devices.

The solutions described herein may utilize LDS/DCI technology as a solution to provide device interconnections with a substrate via a metal (such as copper) grown (directly) with additive processes.

A Ti/Cu sputtering process can be used to create a seed layer for both the coil and the interconnect. A metallization (e.g., growing a metal such as copper via a plating process) may then be performed to grow thicker conductive structures.

Thus simplifying the provision of coils embedded in the package while improving overall electrical performance.

Two possible embodiments of the solution described herein are illustrated in fig. 3 to 5 and fig. 6 to 8, respectively.

For simplicity and to facilitate understanding of the advantages of the solutions described herein, similar parts or elements to those already discussed in connection with fig. 1 and 2 are indicated (at least in part) with similar reference numerals in fig. 3-8.

It will be appreciated that the use of similar reference signs for certain portions or elements in fig. 1 and 2 and in fig. 3-8 does not necessarily imply that these portions or elements are implemented in the same manner.

Generally, in fig. 3-8, reference numeral 14 denotes a semiconductor chip coupled to the coils (primary and secondary sides) of the transformer 18, while conductive pins or leads providing electrical contacts for the package 10 are indicated as 12B.

As better understood in the side views of fig. 5 and 8, in the solutions described herein, both coils 181, 182 (located on the primary and secondary sides of the transformer 18) may be formed using PEP technology.

This results in a sandwich structure comprising (from bottom to top in fig. 5): a substrate 180 (e.g., an insulating layer of molding material 180, such as an epoxy, such as the encapsulant 22 of fig. 1 and 2) having a thickness of, for example, 450 microns, in which the integrated circuit chip or die 14 is embedded (in a manner known per se to those skilled in the art); and a stacked arrangement of (e.g., four) layers L1, L2, L3, L4 of electrically insulating material having primary winding 181 and secondary winding 182 of transformer 18 and associated wiring (designated 120) formed therein as respective patterns of electrically conductive material.

Accordingly, a drawing such as fig. 5 is exemplary, at least one semiconductor chip 14 is embedded in an insulating encapsulation 180 at a first portion, and one or more conductive coils 181, 182 are formed over a second portion of the insulating encapsulation 180 that is at least partially non-overlapping with the first portion of the insulating encapsulation 180. These coils have a planar coil geometry and a geometric distribution of conductive connections 120 to the semiconductor chip 14.

The drawings such as fig. 5 are also exemplary, in which the semiconductor chip 14 is embedded in a stacked structure of layers over the insulating encapsulation 180 in a first portion thereof. The layers in the stacked structure include respective patterns 1006, 1008, 12B of electrically insulating material L1, L2, L3, L4 and electrically conductive material.

These patterns of conductive material have: providing a planar coil geometry of the conductive coils 181, 182; or thereby provide a geometric distribution of the conductive connections 120.

As discussed further below, these layers L1 through L4 may be laminated on top of a base layer (referred to as L0 in fig. 9A through 9L) at the "panel" level, which may be laminated at the "wafer" level.

Advantageously, these layers may comprise sheets/films (films) of LDS/DCI molding compound, which are suitable for the processing discussed below.

The laminated film may be a flavoured element(Ajinomoto Build-up/>ABF), an organic thermosetting film commercialized by a monosodium glutamate group.

By way of example only, the layers in question may have the following thicknesses: l1:50 microns, L2:100 micrometers, L3:50 microns and L4:150 microns.

Of course, the quantitative values reported above are merely exemplary and are not limiting on the embodiments.

As further detailed in the description of the sequence of steps of fig. 9A-9L, the processing of the substrate 180 and layers L0, L1, L2, L3, L4 involves forming conductive patterns therein, such as vias and conductive lines, to provide: the coils (primary winding 181 and secondary winding 182) of the transformer 18; and wiring 120, and vias that facilitate (see primarily fig. 4 and 7) electrical connection of die or chip 14 with the coils or windings of transformer 18, and possibly (see reference numeral 120' in fig. 4 and 7) conductive traces between die or chip 14 and associated leads 12B.

In the solution described herein, one or more semiconductor chips 14 are thus arranged at a first portion of the substrate 180, and one or more conductive coils 181, 182 are formed over a second portion of the substrate 180. The second portion is at least partially non-overlapping with the first portion.

The one or more coils 181, 182 have: planar coil geometry; and the geometric distribution of conductive connections 120 to one or more semiconductor chips 14.

The solution described herein includes forming a stacked structure of electrically insulating material layers L0, L1, L2, L3, L4 over a second portion of the substrate 180, wherein respective patterns of electrically conductive material are formed (see e.g., 1000, 1006, 1008, 12B in fig. 9A-9L), as further detailed in connection with fig. 9A-9L.

These corresponding patterns of conductive material have: the planar coil geometry of the one or more coils 181, 182, thereby providing such one or more coils (transformer windings); or a geometric distribution of conductive connections 120 to one or more semiconductor chips 14, thereby providing such conductive connections 120.

As is understood in fig. 3 to 8, the chip 14 advantageously does not overlap with the coils of the transformer 18.

It was found to be advantageous that there is (at least substantially) no overlap between the chip 14 and the windings of the transformer 18, as this minimizes undesirable interactions between the two.

The comparison of fig. 3-5 (on one side) and fig. 6-8 (on the other side) highlights the possibility of optimizing the layout (and length) of the conductive traces 120 coupling the die 14 to the transformer 18.

Fig. 3 to 5 are basically exemplary "appearances" of the SiP of fig. 1 that are possible when implemented using PEP technology. The design of the transformers 181, 182 is substantially unchanged; die 14 are identical and are placed at the same distance from the transformer: the performance is improved by omitting most of the wiring and lead frame.

Fig. 6-8 are exemplary (possible) optimizations of the solutions of fig. 3-5, showing how the flexibility provided by PEP technology can further improve performance.

As illustrated in fig. 6-8, the shorter die-to-transformer connection helps reduce the overall size of package 10.

For example (and by way of non-limiting example), the system layout illustrated in fig. 4 may be implemented on a 6mm x 8mm rectangular-sized substrate, while the system layout illustrated in fig. 7 may be implemented on a 5.5x 7mm rectangular-sized substrate 180.

Again, these values are merely exemplary and are not limiting on the embodiments.

The embodiments illustrated in fig. 3-8 have been found to provide significant advantages over the conventional arrangements illustrated in fig. 1 and 2 in terms of inductance, resistance and coupling coefficient, and Q factor of the transformer arrangement.

This improvement can be attributed primarily to two factors, namely: the portion of the metal lead frame under transformer 18, such as portion 1200 in fig. 1, may be omitted; and/or replace the conventional wiring 120 with conductive lines (traces) formed at layers L0 and L1 to L4.

Modulating the thickness of the conductive trace helps to reduce the associated resistance and increase the Q factor. This approach is nearly impossible in the presence of a leadframe having a fixed thickness.

Advantageously, a corresponding pattern of electrically conductive material is grown on the electrically insulating material of the layers L0, L1, L2, L3, L4, for example via plating.

As illustrated in fig. 3-8, a sequence that may be applied to manufacture the package 10 will now be described in connection with fig. 9A-9L.

It is to be understood that the sequence of steps of fig. 9A-9L is merely exemplary, as: one or more of the steps illustrated in fig. 9A-9L may be omitted, performed differently (e.g., using other tools), and/or replaced with other steps; additional steps may be added; and one or more steps may be performed in a different sequence than illustrated.

Fig. 9A is an exemplary lamination (at the "wafer" level) of a first layer L0 on a semiconductor chip or die 14.

It is noted that the solution described herein is applicable to arrangements where there are multiple chips or dies 14 and arrangements that include a single chip or die 14.

Likewise, although an arrangement comprising a plurality of coils (e.g. primary winding 181 and secondary winding 182 of transformer 18) is shown in the figures, the solutions described herein are also applicable to arrangements where a single coil is present.

Fig. 9B is an exemplary via 1000 formed through layer L0 (in a manner known per se to those skilled in the art, e.g., via laser beam processing).

Fig. 9C is an exemplary wafer grinding and dicing (e.g., via a dicing blade) indicated at B.

Fig. 9D is an exemplary (re) construction of a panel using a carrier 1002, the structure obtained in fig. 9C being "inverted" mounted to the carrier 1002 via an intermediate layer (e.g., tape) 1004.

Fig. 9E is an exemplary encapsulant material (intended to form the support 180) molded with subsequent molding grinds. Starting with fig. 9E, a single chip or die 14 is shown for simplicity.

Accordingly, fig. 9A-9E are exemplary semiconductor chips 14 embedded at a first portion of the insulating encapsulation 180 via steps comprising: singulating a semiconductor wafer comprising a plurality of semiconductor chips 14 into a plurality of individual semiconductor chips comprising the semiconductor chips 14; the plurality of individual semiconductor chips 14 thus obtained are arranged on temporary carriers 1002, 1004; and molding an encapsulant material over the plurality of (individual) semiconductor chips, thereby embedding the plurality of individual semiconductor chips in the insulating encapsulant 180.

Fig. 9A-9E are exemplary advantageous arrangements in which a base layer (base layer) is formed on the surface of the semiconductor chip 14, such base layer comprising an electrically insulating material L0, and a corresponding pattern 1000 of electrically conductive material having a desired geometrical distribution.

After the step of fig. 9E, in fig. 9F, the arrangement obtained in fig. 9E is released and transferred (inverted again) onto a further carrier 1002 'by the panel via an associated layer, such as a tape 1004'.

It is noted that the carrier 1002 'and the layer 1004' may be the same type of carrier 1002 and layer 1004, although indicated with different reference numerals for clarity.

Fig. 9G and 9H are an exemplary sub-sequence of steps for making the via 1000 (fully) conductive.

These steps may include: forming a "seed" layer, e.g., applying Ti/Cu into the drilled via 1000 via a sputtered SP; laminating a dry film; laser Direct Imaging (LDI) and development; copper current growth; and Cu/Ti etching to complete the formation of the conductive contact at the via 1000.

These steps may be performed in a manner known per se to the person skilled in the art, but also with respect to possible alternatives for forming the seed layer.

The foregoing is followed by lamination of layer L1 discussed in the foregoing.

That is, the processing of the base layer L0 in the stacked structure includes: a corresponding pattern of locations promoting the growth of the electrically conductive material is formed in the electrically insulating material of the base layer L0 in the stacked structure (e.g. via deposition-by sputtering SP, e.g. an electrically conductive material such as copper or titanium).

Conductive material 1000 is then grown at those locations that promote the growth of the conductive material.

Fig. 9I is an exemplary step (i.e., dry film Lamination (LDI) and development, cu current growth, cu/Ti etching) as previously discussed as well, such that conductive lines and contacts (collectively indicated by 1006 for simplicity) are formed, providing, for example, one of the coils 181, 182 of the transformer 18 and the associated wiring 120, followed by lamination of yet another layer L2.

It is noted that the formation of a seed layer (e.g., a Ti/Cu layer applied into the drilled via 1000 via a sputtered SP) is no longer required in subsequent steps following fig. 9I, so long as plating of, e.g., cu can be performed on a homogenous (homologo) base layer (e.g., electrolytically plated copper) in these subsequent steps.

Fig. 9J is an exemplary step of repeating the foregoing discussion (i.e., dry film Lamination (LDI) and development, cu current growth, cu/Ti etching) again such that conductive lines and contacts (collectively indicated by 1008 for simplicity) are formed, providing, for example, another of the coils 181, 182 of the transformer 18 and the associated wiring 120, and then laminating a further layer L3.

As illustrated in fig. 9K, the same sequence of steps may be repeated to provide additional contacts to provide contacts suitable for functioning as leads 12B of package 10 in the case of final layer L4.

Finally, fig. 9L is an exemplary release of the panel thus formed from carrier 1002' and subsequent finishing steps, such as Electroless Nickel Immersion Gold (ENIG) finishing and singulation of leads 12B indicated at P12.

Devices contemplated herein may include one or more conductive coils, such as, for example, a first conductive coil 181 having a first planar coil geometry and a second conductive coil 182 having a second planar coil geometry, facilitating inductive coupling to the first conductive coil 181 to provide a transformer circuit.

The stacked structure of layers may thus comprise a first layer (e.g. L2) of electrically insulating material having a first pattern (e.g. 1006) of electrically conductive material. The first pattern has a first planar coil geometry and provides a first conductive coil, such as 181: this may be a primary winding or a secondary winding of the transformer.

The stacked structure of layers may then include a second layer (e.g., L3) of electrically insulating material having a second pattern (e.g., 1008) of electrically conductive material at the second layer (L3). The second pattern has a second planar coil geometry and provides a second conductive coil, such as 182:

this may be a secondary winding or a primary winding of the transformer.

In addition to the two conductive coils 181, 182, the device illustrated herein (fig. 3 and beyond) also includes a first semiconductor chip and a second semiconductor chip 14 disposed at a first portion of the substrate 180.

In this case, the stacked structure of layers includes: a third layer (e.g., L0) of electrically insulating material having a third pattern (e.g., 1000) of electrically conductive material, providing a geometric distribution of electrically conductive connections of the first semiconductor chip to the first electrically conductive coil 181 of the transformer circuit; and a fourth layer (e.g., L4) of electrically insulating material having a fourth pattern (e.g., 12B) of electrically conductive material, providing a geometric distribution of the conductive connections 120 of the second semiconductor chip 14 to the second conductive coils 182 of the transformer circuits 181, 182.

Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the scope of the protection.

The scope of protection is determined by the appended claims.

Claims (16)

1. A method, comprising:

embedding at least one semiconductor chip in a first portion of an insulating encapsulation; and

forming at least one conductive coil over a second portion of the insulating encapsulation embedded in the at least one semiconductor chip, the second portion being at least partially non-overlapping with the first portion of the insulating encapsulation, wherein the at least one conductive coil has a planar coil geometry and a geometric distribution of conductive connections to the at least one semiconductor chip;

wherein forming comprises: forming a stacked structure of layers over the insulating encapsulation, wherein the layers in the stacked structure comprise respective patterns of electrically conductive material and electrically insulating material;

wherein the respective pattern of conductive material:

having the planar coil geometry to provide the at least one conductive coil; and

with the geometric distribution to provide the conductive connection.

2. The method of claim 1, wherein embedding comprises:

singulating a semiconductor wafer comprising a plurality of semiconductor chips into a plurality of individual semiconductor chips, the plurality of individual semiconductor chips comprising the at least one semiconductor chip;

disposing the plurality of individual semiconductor chips on a temporary carrier;

an encapsulant material is molded over the plurality of individual semiconductor chips to embed the plurality of individual semiconductor chips in the insulating encapsulant.

3. The method of claim 2, wherein forming the stacked structure of layers comprises: a base layer is formed on a surface of the at least one semiconductor chip, the base layer comprising an electrically insulating material and at least one pattern of an electrically conductive material having the geometric distribution.

4. A method according to claim 3, further comprising: the respective pattern of electrically conductive material is grown on the electrically insulating material.

5. The method of claim 4, wherein growing the respective pattern of electrically conductive material on the electrically insulating material comprises plating.

6. The method of claim 3, wherein forming the stacked structure of layers comprises:

forming a corresponding pattern of locations in the electrically insulating material of the base layer that promote the growth of electrically conductive material, an

The conductive material is grown at the locations that promote growth of the conductive material.

7. The method of claim 6, wherein forming the respective pattern of locations comprises: where the conductive material is sputtered.

8. The method of claim 6, wherein forming the respective pattern of locations comprises depositing copper or titanium.

9. A method according to claim 3, wherein the layers in the stacked structure of layers are a monosodium glutamate stacked film layer.

10. The method according to claim 3, wherein the base layer formed on the surface of the semiconductor chip is a monosodium glutamate stacked film layer.

11. A device, comprising:

at least one semiconductor chip embedded in the first portion of the insulating encapsulation; and

at least one conductive coil over a second portion of the insulating encapsulation that is at least partially non-overlapping with the first portion of the insulating encapsulation, the at least one conductive coil having a planar coil geometry and a geometric distribution of conductive connections to the at least one semiconductor chip;

a stack of layers over the insulating encapsulation, the insulating encapsulation having the semiconductor chip embedded in the first portion of the insulating encapsulation, wherein the layers in the stack of layers comprise respective patterns of electrically conductive material and electrically insulating material;

wherein the respective pattern of conductive material:

having the planar coil geometry to provide the at least one conductive coil; and

with the geometric distribution to provide the conductive connection.

12. The device of claim 11, wherein the stacked structure of layers comprises a base layer on a surface of the semiconductor chip, the base layer comprising an electrically insulating material and at least one corresponding pattern of electrically conductive material having the geometric distribution.

13. The device of claim 12, wherein the at least one conductive coil comprises:

a first conductive coil having a first planar coil geometry; and

a second conductive coil having a second planar coil geometry and inductively coupled to the first conductive coil to provide a transformer circuit; and is also provided with

Wherein the stacked structure of layers comprises:

a first layer of electrically insulating material having a first pattern of electrically conductive material at the first layer, the first pattern having the first planar coil geometry and providing the first electrically conductive coil of the transformer circuit; and

a second layer of electrically insulating material having a second pattern of electrically conductive material at the second layer, the second pattern having the second planar coil geometry and providing the second electrically conductive coil of the transformer circuit.

14. The device of claim 13, wherein the at least one semiconductor chip comprises a first semiconductor chip and a second semiconductor chip, and wherein the stacked structure of layers comprises:

a further layer of electrically insulating material has a further pattern of electrically conductive material providing a geometrical distribution of conductive connections of the first semiconductor chip to at least one of the first and second conductive coils of the transformer circuit.

15. The device of claim 13, wherein the layers in the stacked structure of layers comprise a monosodium glutamate stacked film layer.

16. The device of claim 13, wherein the base layer comprises a flavourant film stack.