CN117472826A - Control of skew between multiple data channels - Google Patents

Control of skew between multiple data channels Download PDF

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Publication number
CN117472826A
CN117472826A CN202310932862.7A CN202310932862A CN117472826A CN 117472826 A CN117472826 A CN 117472826A CN 202310932862 A CN202310932862 A CN 202310932862A CN 117472826 A CN117472826 A CN 117472826A
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data channel
clock
data
reset signal
control stage
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Chinese (zh)
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R·辛格
A·巴尔
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STMicroelectronics International NV Switzerland
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STMicroelectronics International NV Switzerland
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Priority claimed from US18/348,899 external-priority patent/US20240039545A1/en
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Publication of CN117472826A publication Critical patent/CN117472826A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Embodiments of the present disclosure relate to control of skew between multiple data lanes. Methods and apparatus for controlling skew between a plurality of data channels are provided. In the method and apparatus, a first data channel control stage controls output of first data through a first data channel based on a first data channel clock, and a second data channel control stage controls output of second data through a second data channel based on a second data channel clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate first and second data for output over first and second data channels. The clock control stage shifts the first and second data channel clocks from each other by a fixed duration, which is an integer part of the period duration of the system clock.

Description

Control of skew between multiple data channels
Technical Field
The present disclosure relates to control of skew between multiple data lanes, and in particular, to controlling skew by shifting a data transmission timing in a data lane by a fraction of a system clock period.
Background
Multiple data channels are used to transfer data between two devices. The use of multiple data channels increases the data rate at which communications are performed between devices. However, the offset between the multiple data lanes may have a negative impact on the data merge at the receiving device. In particular, the deviation may increase beyond the amount by which the synchronizer can synchronize the data to merge the data.
Disclosure of Invention
Techniques for controlling skew between data channels in a multi-channel transmission are provided. In serial communications, multiple data lanes are used to increase bandwidth and achieve high data bandwidth. To ensure proper transmission and reception of data, it is necessary to limit the data skew between the multiple data channels. The deviation is limited to one clock period of the system clock (symbol clock). The system clock may represent the rate at which one symbol is added to the transmit buffer, whereby symbols may be added to the transmit buffer every system clock cycle. Bits of the symbol may be serially drawn from the buffer at a higher rate and using a faster data channel clock.
Repair of delays or deviations between multiple data channels is provided. Specifically, the data channel clock signal is offset by a portion of the system clock. For example, when two data channels are used, there is a half-period delay of the system clock between the data channel clock signals. Thus, the serial data is retrieved from the corresponding buffer of the data channel offset by half the system clock. The synchronizer synchronizes the serial data as it is transmitted and combined at the receiver. Setting the offset to be less than one system clock cycle enables synchronization and mitigates packet corruption at merging (packet corruption).
Drawings
Fig. 1 shows data transmission from a first system to a second system.
Fig. 2 shows a clock reset stage that resets the clocks of the first and second data channel control stages.
Fig. 3A and 3B show timing diagrams of the signals described with reference to fig. 1 and 2.
Detailed Description
Fig. 1 illustrates data transmission from a first system 102 to a second system 104. The first system 102 may be an electronic device, a controller, a circuit, a system on a chip (SoC), a processor, or the like. The second system 104 may be an electronic device, a controller, a circuit, a SoC, a processor, or the like. The first system 102 may generate data on one or both of the two data channels including the first data channel 106a and the second data channel 106b and send the data to the second system 104. The first and second data channels 106a, 106b are paths or connections for transferring data from the first system 102 to the second system 104. Note that although two data lanes are shown in fig. 1, the first system 102 may transmit data to the second system 104 over any number of data lanes (such as four, six, or eight data lanes).
The first and second data lanes 106a, 106b have first and second first-in-first-out (FIFO) buffers 108a, 108b and first and second serializers 109a, 109b, respectively. The first and second FIFO buffers 108a, 108b may each be memories or registers. Furthermore, the FIFO buffers 108a, 108b may each be Static Random Access Memory (SRAM), flip-flop, latch, or the like.
The first and second serializers 109a, 109b each have an input and an output. The first and second serializers 109a, 109b each receive data from the first and second FIFO buffers 108a, 108b through an input and serialize and output the data at a higher clock frequency through an output. The first FIFO buffer 108a has a data input for receiving first data from the first system 102, a data output for outputting the first data to the first serializer 109a (for serializing and outputting to the second computer 104), a control input and a clock input. The second FIFO buffer 108b has a data input for receiving second data from the first system 102, a data output for outputting the second data to the second serializer 109b (for serializing and outputting to the second computer 104), a control input and a clock input. The first and second FIFO buffers 108a, 108b may receive the first and second data as symbols.
The first system 102 outputs first and second start signals to control inputs of the first and second FIFO buffers 108a, 108b, respectively. The first FIFO buffer 108a receives the first start signal via its control input and the second FIFO buffer 108b receives the second start signal via its control input. The first start signal indicates a time when the first data is output from the first system 102 to the first FIFO buffer 108a, and the second start signal indicates a time when the second data is output from the first system 102 to the second FIFO buffer 108b.
Note that the first system 102 may have a system clock. The system clock may be the symbol clock of the first system 102. The first and second FIFO buffers 108a, 108b may each store symbols comprising a plurality of bits, respectively. The first and second FIFO buffers 108a, 108b may each output multiple bits of a symbol. The first start signal and the second start signal may be timed according to a system clock. The first start signal may be asserted or de-asserted (or set to a logic zero or a logic one) according to an agreement (convention) indicating that the first data is output to the first FIFO buffer 108 a. The first start signal may be clocked to the system clock. The time at which the first start signal is asserted may be a rising edge (or falling edge) of the system clock. The second start signal may also be asserted or de-asserted to indicate that the second data is output to the second FIFO buffer 108b. The second start signal may be clocked to the system clock.
The first and second data channels 106a, 106b are associated with first and second data channel control stages 110a, 110b, respectively. The first and second data channel control stages 110a, 110b may be physical layer entities. The first and second data channel control stages 110a, 110b may each be a circuit comprising digital logic. Digital logic includes gates, flip-flops, and the like. The first and second serializers 109a, 109b may be part of the first and second data lanes 106a, 106b, respectively. The first data channel control stage 110a outputs a first data channel clock signal to the first FIFO buffer 108 a. The first FIFO buffer 108a receives the first data channel clock signal through a clock input. The first FIFO buffer 108a outputs the first data according to the first data channel clock signal. The first serializer 109a has a clock input. The first serializer 109a receives a first serial clock from the first data channel control stage 110a through a clock input. The serial clock may be faster than the first data channel clock signal. The first serializer 109a serializes the first data according to the first serial clock. For example, the first FIFO buffer 108a may output one symbol to the first serializer 109a, and the first serializer 109a may serialize bits of the symbol and serially output the bits during one clock cycle of the first data channel clock signal.
The second data channel control stage 110b outputs a second data channel clock signal to the second FIFO buffer 108b. The second FIFO buffer 108b receives the second data channel clock signal through the clock input of the second FIFO buffer 108b. The second FIFO buffer 108b outputs second data according to the second data channel clock signal. The second serializer 109b has a clock input. The second serializer 109b receives a second serial clock from the second data channel control stage 110b through a clock input. The second serial clock may be faster than the second data channel clock signal. The first serializer 109b serializes the second data according to the second serial clock. The second FIFO buffer 108b may output one symbol of the second data held in the second FIFO buffer 108b through a data output (data output of the second FIFO buffer 108 b) during one clock cycle of the first data channel clock signal.
The first and second data channel clock signals may be in different phases than the system clock. The frequencies of the first and second serial clocks may be integer multiples of the frequency of the first and second data channel clock signals, respectively, or multiples of a power of 2 (e.g., 8, 16, 32, etc.). For example, if the system clock is clocked at one gigahertz (1 GHz), the first and second data channel clocks are 1GHz, but the phases may be different. The frequency of the high frequency clock (hs_clk) of the first and second data channel control stages 110a, 110b may be 32GHz or 16GHz (e.g., if the controller has a 32 bit sign). Thus, the first and second serial data are retrieved from the first and second FIFO buffers 108a, 108b at a rate of 32 gigabits per second (Gbps). Further, the first and second FIFO buffers 108a, 108b may have a buffer size, a storage size, or a depth. The depth may be three or four symbol sizes, etc. Depth 4 and symbol size 32 bits, corresponding to storing 32 x 4 = 128 bits, for handling phase mismatch between the first and second data channel clock signals and the system clock.
The data outputs of the first and second FIFO buffers 108a, 108b are coupled to respective inputs of the second system 104 via first and second serializers 109a, 109b, respectively. The second system 104 receives the first and second serial data from the first and second serializers 109a, 109b, respectively, at twice the data rate compared to the data rate using one data channel. Adding additional data channels further increases the rate at which data is sent from the first system 102 to the second system 104 by a multiple.
Fig. 2 shows a system 111, the system 111 resetting (or enabling) the clocks of the first and second data channel control stages 110c, 110 d. The first and second data channel control stages 110c, 110d each have a clock reset input. The clock reset input is coupled to a clock reset stage 112. The clock reset stage 112 has a clock input for receiving the system clock of the first system 102 and an enable input for receiving the second channel enable signal. The clock reset stage 112 has a first clock output for outputting a first data channel clock reset signal and a second clock output for outputting a second data channel clock reset signal. The first and second clock outputs of the clock reset stage 112 are coupled to the clock inputs of the first and second data channel control stages 110c, 110d, respectively.
The first and second data channel clock reset signals are operative to set the first and second data channel clock signals and the first and second serial clocks, respectively. The clock reset stage 112 configures the first and second data channel clock reset signals such that the first and second data channel clock signals are offset by a duration less than one period of the system clock. This configuration results in the first serial data (output by the first serializer 109 c) and the second serial data (output by the second serializer 109 d) having the greatest deviation from each other within one period of the system clock. The synchronizer may be used, for example, at the second system 104 to synchronize the first and second serial data. Synchronizing the first and second serial data may eliminate skew. In order for the synchronizer to effectively eliminate the skew, the skew between the first and second data channel clock signals (and, therefore, the first and second serial data) is shorter than one period of the system clock. The skew is limited to one period of the system clock so that the post-transmission synchronization effectively eliminates the skew. If the duration of the skew between the first and second serial data is greater than one period of the system clock, the synchronization may not eliminate the skew. Furthermore, the first and second serial data may not be effectively combined. If the data between the data lanes deviates more than one system (symbol) clock period, the data may be corrupted at the receiver end, resulting in a packet failure.
The clock reset stage 112 includes first and second flip-flops 114, 116 and a logic connection gate 118. The first flip-flop 114 has a data input for receiving a first reset signal, a clock input for receiving a system clock, and a data output for outputting a first data channel clock reset signal. Logic connection gate 118 has a first input coupled to the data output of first flip-flop 114, a second input for receiving a second channel enable signal, and an output for outputting a second reset signal. The second flip-flop 116 has a data input coupled to the output of the logic connection gate 118 for receiving a second reset signal. The second flip-flop 116 has a clock input for receiving the inverted system clock and a data output for outputting a second data channel clock reset signal. Note that while clock reset stage 112 is shown with an agreement to assert by setting the signal to a logic one and to de-assert by setting the signal to a logic zero, the agreement may be inverted and the signal may be asserted by setting the signal to a logic zero and de-assert by setting the signal to a logic one.
When the first reset signal is asserted, the first flip-flop 114 asserts the first data channel clock reset signal at the next rising edge of the system clock. The first data channel control stage 110c generates the first data channel clock signal based on the timing of the rising edge of the first data channel clock reset signal. The first data channel control stage 110c may have circuitry including digital logic such as one or more shift registers and one or more clock dividers. The first data channel control stage 110c may use the first data channel clock reset signal to reset the digital logic and the clock divider logic. For example, the first data channel control stage 110c may use a first data channel clock reset signal to reset the flip-flops of the digital logic. Due to the operation of the first data channel control stage 110c, the start of the first data channel clock signal (and the first serial clock) may be delayed with respect to the first data channel clock reset signal.
The clock reset stage 112 receives the second channel enable signal. The second channel enable signal indicates whether the second data channel 106b is being used to transmit data from the first system 102. For example, the second channel enable signal may be asserted to indicate that the second data channel 106b is being used to transmit data from the first system 102.
When the second channel enable signal is asserted, the logic connection gate 118 passes the first data channel clock reset signal to the data input of the second flip-flop 116. At the same time, the second flip-flop 116 receives the inverted system clock. The falling edge of the system clock is half the duration of the system clock after the rising edge of the system clock. When the system clock has a falling edge, the inverted system clock has a rising edge. At the falling edge of the system clock, the second flip-flop 116 outputs a second data channel clock reset signal. Thus, the second data channel clock reset signal is asserted half the system clock period after the first data channel clock reset signal.
The second data channel control stage 110d may be constructed similarly to the first data channel control stage 110 c. The second data channel control stage 110d receives a second data channel clock reset signal. The second data channel control stage 110d generates a second data channel clock signal based on the timing of the rising edge of the second data channel clock reset signal. Due to the operation of the second data channel control stage 110d, the start of the second data channel clock signal and the start of the second serial clock may be delayed with respect to the second data channel clock reset signal. The delay between the second data channel clock signal and the second data channel clock reset signal may be similar or identical to the delay between the first data channel clock signal and the first data channel clock reset signal.
The clock reset stage 112 fixes or sets the delay or offset between the first and second data channel clock signals (and thus, between the first and second serial data retrieved from the first and second FIFO buffers 108a, 108b, respectively) to a specified value. When two data channels are used, the specified value is half of the system clock period. For a number n of data channels, a first data channel is reset using rising edge sampling and the remaining data channels are reset using falling edge sampling, or vice versa, depending on the delay between the reset and the channel clock output. For example, if four data lanes are used and the delay between the reset input and the rising edge of the lane clock is about one symbol clock, then the first lane reset is generated on the rising edge of the system clock and the remaining lanes are generated on the falling edge of the system clock. In other cases, when the delay between the reset and the rising edge of the channel clock is substantially half of the symbol clock, the reset of the first channel is generated on the falling edge of the system clock and the remaining channel resets are generated on the rising edge of the system clock. In this way, the offset between the first channel clock and the other channel clocks is half a clock period. Similarly, the offset between the serialized data is half the symbol clock.
The first and second serial data are combined by the second system 104 described with reference to fig. 1. The synchronizer may synchronize the first and second serial data when merging the data. The fact that the deviation is less than one system clock period enables synchronization at merging. As described herein, the skew between the data channels is controlled using a clock reset stage 112, the clock reset stage 112 having a small footprint and may be implemented while taking up relatively little area on the circuit. By actively controlling the offset, offset drift and duration increase can be prevented.
Fig. 3 and 3B show timing diagrams of the signals described with reference to fig. 1 and 2. In fig. 3A and 3B, a system clock 302, a start signal 304, first and second data channel clock reset signals 306, 308, and first and second data channel clocks 310, 312 of the first and second data channel control stages 110a, 110B, respectively, are shown. The first and second data channel clocks 310, 312 are each divided by a corresponding clock divider based on a high speed input clock (hs_clk). The high speed clock (hs_clk) is used to generate the first and second serial clocks based on the first and second data channel clocks 310, 312, respectively. The first and second data channel clocks 310, 312 have the same rate as the system clock 302, but may have delays associated with circuitry and operation of the first and second data channel control stages 110a, 110b, respectively. Fig. 3A and 3B also show first and second start signals 314, 316 and first and second serial data 318, 320.
As shown in fig. 3A and 3B, first and second data channel clock reset signals 306, 308 are generated based on the system clock 302. At a first time instance 322 corresponding to a rising edge of the system clock 302, the first data channel clock reset signal 306 is asserted. Further, at a second time instance 324 corresponding to a falling edge of the system clock 302, the second data channel clock reset signal 308 is asserted. Assertion of the first data channel clock reset signal 306 causes the first data channel clock 310 of the first data channel control stage 110c to begin at the third time instance 326. Further, assertion of the second data channel clock reset signal 308 causes the second data channel clock 312 of the second data channel control stage 110d to begin at the fourth time instance 328. The first and second data channel clocks 310, 312 have a delay relative to the system clock 302. The first and second data channel clocks 310, 312 have the same rate as the system clock 302.
At a fifth time instance 330, the start signal 304 is asserted, indicating that a data transfer is to be initiated. At a sixth time instance 332 in the second data channel 106b and corresponding to the next rising edge of the second data channel clock 312, the start signal 304 is captured. At the subsequent rising edge of the second data channel clock 312 corresponding to the seventh time instance 334, the second start signal 316 is asserted. Data retrieval from the second FIFO buffer 108b and serialization is initiated after half the system clock at the eighth time instance 336.
For the first data channel 106a, the start signal 304 is captured at a ninth time instance 338 corresponding to the next rising edge of the first data channel clock 310. At a subsequent rising edge of the first data channel clock 310 corresponding to the sixth time instance 332, the first start signal 314 is asserted. The data retrieval from the first FIFO buffer 108a is initiated after half the system clock of the tenth time instance 340. As can be seen from fig. 3A and 3B, the offset between the retrieval of the first serial data at tenth time instance 340 and the retrieval of the second serial data at eighth time instance 336 is half of the system clock 302.
The various embodiments described above may be combined to provide further embodiments.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims (20)

1. A system, comprising:
a first data channel control stage configured to:
controlling output of the first data through the first data channel based on the first data channel clock;
a second data channel control stage configured to:
controlling output of the second data through the second data channel based on the second data channel clock;
a first device associated with a system clock and configured to generate the first data and the second data for output over the first data channel and the second data channel; and
a clock control stage configured to shift the first data channel clock and the second data channel clock from each other by a fixed duration, the fixed duration being an integer portion of a period duration of the system clock.
2. The system of claim 1, wherein the system clock is a symbol clock of the first device that represents a duration of time that the first device outputs symbols included in the first data or the second data.
3. The system of claim 1, wherein the integer portion is the inverse of the number of data channels.
4. The system of claim 3, wherein the fixed duration is half the period duration of the system clock when the number of data lanes is two.
5. The system of claim 1, wherein the clock control stage is configured to:
outputting a first data channel clock reset signal to the first data channel;
outputting a second data channel clock reset signal to the second data channel; and
the first data channel clock and the second data channel clock are offset from each other by at least the fixed duration by:
the first data channel clock reset signal is asserted for the fixed duration after the second data channel clock reset signal is asserted or the second data channel clock reset signal is asserted for the fixed duration after the second data channel clock reset signal is asserted.
6. The system of claim 5, wherein the first data channel control stage is configured to generate the first data channel clock based on the first data channel clock reset signal and the second data channel control stage is configured to generate the second data channel clock based on the second data channel clock reset signal.
7. The system of claim 5, wherein the clock control stage comprises:
a first flip-flop configured to assert the first data channel clock reset signal at one of a falling edge or a rising edge of the system clock; and
a second flip-flop configured to assert the second data channel clock reset signal at the other of the falling edge or the rising edge of the system clock.
8. The system of claim 5, wherein the first data channel control stage is configured to reset a plurality of flip-flops of the first data channel control stage in response to the first data channel clock reset signal being asserted, and the second data channel control stage is configured to reset a plurality of flip-flops of the second data channel control stage in response to the second data channel clock reset signal being asserted.
9. The system of claim 1, wherein a first serial clock has a first frequency that is an integer multiple of a frequency of the system clock and a second serial clock has a second frequency that is the integer multiple of the frequency of the system clock.
10. The system of claim 9, wherein the first data lane control stage comprises a first serializer configured to serially retrieve the first data from a first-in first-out FIFO buffer at a rate of the first serial clock, the second data lane control stage comprises a second serializer configured to serially retrieve the second data from a second FIFO buffer at a rate of the second serial clock, and the first device is configured to input symbols representing the first data and the second data into the first FIFO and the second FIFO, respectively, at a rate of the system clock.
11. An apparatus, comprising:
a first trigger configured to:
generating a first data channel clock reset signal; and
outputting the first data channel clock reset signal to a first data channel control stage, the first data channel clock reset signal operative to set a timing of a first data channel clock of the first data channel control stage, the first data channel clock being used to control output of first data through a first data channel; and
a second trigger configured to:
generating a second data channel clock reset signal, the second data channel clock reset signal offset from the first data channel clock reset signal by an integer portion of a cycle duration of a system clock; and
the second data channel clock reset signal is output to a second data channel control stage, the second data channel clock reset signal operative to set a timing of a second data channel clock of the second data channel control stage, the second data channel clock being used to control output of second data through a second data channel.
12. The device of claim 11, wherein the system clock is a symbol clock of a first device, the symbol clock of the first device representing a duration of time that the first device outputs symbols included in the first data or the second data.
13. The apparatus of claim 11, wherein the integer portion is the inverse of the number of data channels.
14. The apparatus of claim 13, wherein the second data channel clock reset signal is offset from the first data channel clock reset signal by half the period duration of the system clock when the number of data channels is two.
15. The apparatus of claim 11, wherein the first flip-flop is configured to assert the first data channel clock reset signal at one of a falling edge or a rising edge of the system clock, and the second flip-flop is configured to assert the second data channel clock reset signal at the other of the falling edge or the rising edge of the system clock.
16. The device of claim 11, wherein the first data channel control stage is configured to reset a plurality of flip-flops of the first data channel control stage in response to the first data channel clock reset signal being asserted, and the second data channel control stage is configured to reset a plurality of flip-flops of the second data channel control stage in response to the second data channel clock reset signal being asserted.
17. The apparatus of claim 11, wherein a first serial clock has a first frequency that is an integer multiple of a frequency of the system clock and a second serial clock has a second frequency that is the integer multiple of the frequency of the system clock.
18. The device of claim 17, wherein the first data lane control stage comprises a first serializer configured to retrieve the first data from a first-in first-out FIFO buffer at a rate of the first serial clock, the second data lane control stage comprises a second serializer configured to retrieve the second data from a second FIFO buffer at a rate of the second serial clock, and the first device is configured to input symbols representing the first data and the second data into the first FIFO and the second FIFO, respectively, at a rate of the system clock.
19. A method, comprising:
generating a first data channel clock reset signal;
setting a timing of a first data channel clock based on the first data channel clock reset signal;
outputting first data through a first data channel based on the first data channel clock;
generating a second data channel clock reset signal, the second data channel clock reset signal offset from the first data channel clock reset signal by an integer portion of a cycle duration of a system clock;
setting a timing of a second data channel clock based on the second data channel clock reset signal; and
and outputting second data through a second data channel based on the second data channel clock.
20. The method of claim 19, wherein a first data channel control stage resets a plurality of flip-flops of the first data channel control stage in response to the first data channel clock reset signal being asserted, and a second data channel control stage is configured to reset a plurality of flip-flops of the second data channel control stage in response to the second data channel clock reset signal being asserted.
CN202310932862.7A 2022-07-28 2023-07-27 Control of skew between multiple data channels Pending CN117472826A (en)

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US63/393,093 2022-07-28
US18/348,899 US20240039545A1 (en) 2022-07-28 2023-07-07 Control of skew between multiple data lanes
US18/348,899 2023-07-07

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