WO2006025768A2 - Read latency minimisation using frame offset - Google Patents

Abstract

The invention relates to a communications receiver with reduced latency and method that offsets the receiver framing alignment to minimize the decode latency for return data. The receiver comprises transceiver cells for deserialising data received in frames from a host computer into a parallel output data word of width equal to the number of bits in the frame; and a memory interface controller for decoding the parallel frame data from the transceiver cells and generating control signals and data signals to a memory device. The phase of the deserialised output data is adjusted to offset the parallel output data word to the frame control clock, so that the parallel output data word is aligned to the frame control clock such that the output data becomes valid when the command field has been deserialised. This provides improved clocking alignment for any downstream components operating on the data contained within the frame structure.

Description

READ LATENCY MINIMISATION USING FRAME OFFSET

Technical Field

The present invention relates to the communication of signals, in particular, to the transmission and reception of digital signals. More specifically, the present invention relates to control and data transfer within a serial framing system.

The present invention is particularly applicable to interfaces between integrated circuits and for high-speed communications.

Background of the Invention One common form of communication system involves digital signals representing data, which is sent over wires or other communication media, called a communication channel.

In a communication channel this data can be sent as frames, where an embedded structure is applied in time, with an appropriate method of imparting the frame start to the receiver.

Figure 1 shows the block diagram of a communications system typically used in a high performance, high-speed memory system where a memory controller transmits data to a memory system and receives data back from a memory system. In such a system the receiver is required to return information, and minimizing the round trip latency is of the greatest importance.

The communications system comprises a plurality of serial communication channels, or lanes, both receiving serial data from the memory controller and transmitting serial data to the memory controller. Further the communications system handles the conversion of the serial data from the memory controller into parallel data for the memory system and conversion of the parallel data from the memory system to serial data for the host controller.

The communications system shown in figure 1 is mesochronous, that is, a clock is received that is synchronous to the received serial data 10 although not in phase with the received serial data and may be used to aid in sampling and re- timing the same received serial data.

Serial data lanes 10 contain bits of data that are transmitted from a memory controller, typically formatted into a frame structure such as shown in figure 2. The serial data is received in transceiver cells 30 where a clock is recovered from the data and subsequently samples the data in the middle of the received serial data bit period to ensure a low bit error rate and reliable communications across the serial interface between the memory controller and memory system. Phase locked loop 40 locks to external reference clock 20, typically multiplying up the clock frequency to the same frequency as the frequency of the received serial data generating re-timing clock 41. Re-timing clock 41 is distributed from the PLL to all transceivers 20 to aid in the recovery of the clock from the received serial data 10. PLL 40 also generates a frame clock 42 at the frame rate that is distributed to memory interface circuit 100.

Transceiver 20 deserialises the received serial data 10 on a lane-by-lane basis into a parallel data word, typically at the frame rate. Further, transceiver 20 performs lane-to lane deskew of the data compensating for different data path lengths which introduce skew between lanes. Circuit CAL CONTROL 200 generates calibrations signals 202 when the system is placed into reset mode through the signal RESET 201.

An example of such a serial communications transceiver is described by the present inventors in US patent applications 60/588,993 for A Re-timer Circuit for Data Recovery with Fast Recovery from a Low Power Mode and US 60/ for De-skew and De-serialiser Circuit for Low Latency.

Parallel data words from transceivers 20 are received in memory controller 100 across bus 102 where the data words are recombined into data frames and processed outputting signals in bus 101 to the memory.

A typical frame structure is shown in Figure 2 and, by means of an example, comprises "n" lanes of "m" data bits. Quantities "n" and "m" having been chosen as part of the protocol to ensure efficient coding of commands, data and status that are to be transferred to the memory system.

The organisation of the data bits in a frame is called the protocol and each data bit within the frame may comprise a command data bit, a data bit to be written or read from the memory system or a control/status bit. A typical grouping of the data bits in a frame containing both data and a command is shown in figure 3 where the command is incorporated into the first art of the frame and the data payload is incorporated into the second part of the frame. It is often the case that command bits may be spread across multiple frames, requiring memory controller 100 to store the contents of multiple frames before a full command decode may be performed. This may increase the latency of, for example, a read of data from the memory system by the memory controller. Typically, transceivers 20 deserialise the received serial data 10 into parallel words of "m" data bits at the frame rate. Further it is common practice to align the data from each transceiver so that each parallel output data word in bus 102 to memory controller 100 contains data bits 0 to "m-1" of the frame. Subsequently, in a system where commands are split across two or more frames, memory controller 100 must wait until complete frames of data have been received before decoding the command. This introduces latency into the memory system data access and reduces the overall performance of the memory system and possibly the performance of the whole communications or computing system.

Fig.3 shows this end-of-frame alignment where the frame clock would be used to latch the data after deserialisation, sending the data to memory interface circuit 100. Figure 3 further shows two consecutive frames where the command is split across the two frames. Frame 300 contains a command part A 301 and a data part 302 such that the command part A 301 is transmitted across all lanes in the first few bit periods of the frame. Frame 320 contains a command part B 321 and a data part 322, again where the command part B 321 is transmitted first across the all lanes in the first few bits of the frame. It can be seen that the time elapsed from the transmission of the first bit of data in frame 300 to the last bit of data in frame 320 is 2xm bit periods or two frame periods.

Fig.4 shows the timing diagram of a conventional deserialisation process up to and including the command decoding and latching. In Figure 4 the command decode is shown to take less than one frame, resulting in a total latency of three frames from receipt of the first serial data bit. Note that lane-lane skew and deskew is not considered here. US Provisional patent application 60/ "A deskew and deserialiser circuit for low latency" describes a means of alignment of the frame sampling clock to an arbitrary position within the frame.

When decoding a frame it is most often the case that the control content requires greater processing than the data portion. This may result in the decoding of a command taking more than one frame. Using a single clock for the frame sampling, command decoding and latching process can then result in increased latency when the command decoding takes slightly more than a multiple number of frames, basically quantizing this portion of the total system latency to multiple frames. Figure 5 shows a timing diagram where the command decode takes just 1 Ul more than a frame period, resulting in the total delay from the receipt of the first serial data bit to the latched decoded command of four frames.

One approach to reducing delay in logic circuits is to use self-clocking structures. However, such structures are difficult to implement and are poorly handled by current commercially available CAD simulation tools. It has thus been shown that it would be highly advantageous in a communications receiver to reduce the latency of decoding of commands within a frame.

Object of the present invention

It is therefore a primary object of the present invention to provide an improved system read latency when communicating control within a frame structure.

It is therefore a primary object of the present invention to provide an improved clocking alignment for any downstream components operating on the data contained within the frame structure. Summary of The Invention

The present invention relates to a device and method that offsets the receiver framing alignment to minimize the decode latency for return data.

In one aspect of the invention, a communications receiver with reduced latency is provided comprising: a plurality of transceiver cells for receiving frames of serial data from a host controller and transmitting frames of serial data back to the host controller, the transceiver cells deserialising the data into a parallel output data word of width equal to the number of bits in a frame;a memory interface controller for decoding the parallel frame data from the transceiver cells and generating control signals and data signals to a memory device, the controller performing write operations and formatting read data and status information from the memory device to the transceiver cells for onwards transmission across the serial interface; wherein the receiver further comprises a means for adjustment of the phase of the deserialised output data to offset the parallel output data word to the frame control clock, wherein the parallel output data word is aligned to the frame control clock such that the parallel output data becomes valid when the command field has been deserialised.

The frame can comprise multiple segments of information fields, including a command field and a data field, the bits in each field spread across at least one or more serial lanes, or across all serial lanes. Preferably, the command field is split across multiple frames and contained within the first part of each frame. In another aspect of the invention, a method of communication is provided using a communications receiver with reduced latency as stated above.

Brief Description of The Drawings

For a better understanding of the present invention and the advantages thereof and to show how the same may be carried into effect, reference will now be made, by way of example, without loss of generality to the accompanying drawings in which:

Fig. 1 shows a block diagram of a communications receiver as used between a memory controller and a memory system.

Fig. 2 shows the generic structure of a frame of data. Fig. 3 shows consecutive frames of transmitted data with command and data fields and alignment of a frame clock to the end of the frame.

Fig. 4 shows a timing diagram from the received serial data to the output of the command decoder for a conventional communications receiver.

Fig. 5 shows a timing diagram from the received serial data to the output of the command decoder for a conventional communications receiver, specifically where the command decoding takes slightly more than one frame.

Fig. 6 shows consecutive frames of transmitted data with command and data fields and alignment of a frame clock to the end of the command field within the frame. Fig. 7 shows a timing diagram from the received serial data to the output of the command decoder for the present invention. Fig. 8 shows a timing diagram from the received serial data to the output of the command decoder for the present invention with a command decoder output clock.

Fig. 9 shows a block diagram of the memory interface circuit employed in the communications receiver.

Fig. 10 shows a block diagram of the command decoder employed in the memory interface.

Fig. 11 shows a block diagram of the vernier delaying the frame clock in the memory interface. Detailed Description of the Invention

The invention will now be described in detail without limitation to the generality of the present invention with the aid of example embodiments and accompanying drawings.

This invention applies to framing structures that are fixed or at least consistent in period.

Within a receiver with a clock vernier or similar system, the alignment of the frame-sampling clock is chosen such that it is offset to the original frame alignment.

This allows the latching edge of the clock to be aligned such that it is coincident with the end of the control section of the frame payload.

This in effect adds latency equal to the transmit time of the control section to the latching of any write data to the receiver associated with the original frame.

The benefit is that read commands are processed without the delay associated with waiting for the data payload. The novelty to this method is that we need not align on this command decode clock to interface with any register or memory element or device. We can choose the phase relationship between the command latch and the data latch to match the pipeline latency of the command decode.

In essence, the read pipeline to the register element has been reduced to the minimum logic delay plus the minimum set of latching delays. Figure 6 shows the alignment of the frame clock for two consecutive frames 300 and 320 where the frame clock is aligned to the end of the command rather than the end of the frame. Hereby, the command is latched and decoded as soon as it is received, reducing the delay. Fig.7 shows a timing diagram of the frame clock aligned to the end of the command with a resulting improvement in delay of m-4 Ul.

A further improvement in delay is also presented in this invention. The frame clock is typically used to clock all parts of the command decoder, and, in the case where the command decode takes more that one period, results in increased delay or latency. It is the intention of the present invention to reduce the delay by introducing a second clock into the command decoder. The second clock is aligned to the output signals in the command decoder. Fig. 8 shows a timing diagram where a second clock, MEMCLK, is introduced to coincide with valid data being made available at the output of the command decoder. This second clock latches the data instead of FRCLK, resulting in a potential delay improvement of up to m-1 Ul.

Fig.9 shows the preferred implementation of memory interface circuit 100 with improved latency and comprises input register 110 for receiving deserialised data on bus 102 from the individual transceivers 20, command decoder 120 for decoding commands in received serial data, memory control 130 for converting commands into signals suitable for the memory device attached to memory bus 101 , write buffer 140 for buffering data to be written into the memory device attached to memory bus 101 , memory status circuit 150 for reporting status of memory reads and writes back to the memory controller across bus 151 , read buffer 160 holding data read from the memory device attached to bus 101 , output register 170 where the data is aligned to the domain of clock FRCLK 42, clock vernier 180 for adjusting the phase of the memory control clock MEMCLK 181 , and offset control 190 for adjusting the phase of the frame clock for each lane.

To someone skilled in the art, several implementations of vernier 180 may be thought possible. One implementation of vernier 180 could be a delay line with programmable taps. The delay line could consist of analogue elements such as discrete inductors and capacitors, active buffers with the property of time delay or digital elements with delay properties. An alternative implementation could comprise logic cells forming a path which is equivalent to the worst-case delay path through the command decoder with FRCLK 42 connected to the input of this series of logic gates. The output of the vernier 180 would then effectively align the delayed version of FRCLK 42 to the signals at the output of the command decoder. An additional small delay would be inserted to ensure adequate setup and hold margin in following synchronization elements. The delay clock would then track the delay through the command decoder over process, temperature and supply voltage variations. In a complex command decoder this approach may result in a long sequence of gates that are required to be connected in the same manner as the gates in the command decoder in order to obtain matching parasitic capacitance and may result in a difficult piece of design and layout. In either case the delayed version of FRCLK 42 would be selected by some calibration process generating MEMCLK 181. The preferred implementation of the generation of MEMCLK 181 is now described in conjunction with Fig. 10 and Fig. 11. The present invention introduces a data selector into the data path to the command decoder to insert a known, worst-case data pattern into the command decoder during part of the serial interface calibration process. The phase of MEMCLK is adjusted to match the delay of the worst-case pattern through the command decoder.

The preferred implementation of command decoder 120 is shown in figure 10 and comprises register 123, data selector 124, decoder 125, register 126, comparator 127 and D-type flip-flop 128. Data selector 124 selects as input to decoder 125 either the data input to the command decoder or the output of register 123. In normal operation the data derived from bus 102 is input to decoder 125, generating the decoded command output 121. In calibration the output of register 123 is selected by data selector 124, register 123 containing a preset pattern or a pattern loaded at power up of the communications system from another memory location in the system, the pattern generating the worst-case delay path though the decoder 125. The output of decoder 125 is compared against the expected result, held in register 126. The contents of register 126 containing a preset pattern or pattern loaded at power up from another memory location in the system are compared against the output of decoder 125 in comparator 127, the result of the comparison being latched by MEMCLK 181 in D- type flip-flop 128.

Fig. 11 shows the preferred implementation of vernier 180, comprising FSM 182, data selector 183 and shift register 184. Shift register 184 comprises a plurality of flip-flops connected in series with a common clock connection. Shift register 184 has connected to its data input FRCLK while connected to its clock input RTCLK 201 , a clock at a higher speed than FRCLK, and in the preferred implementation a clock at the same frequency as the received serial data rate. The outputs of the serially connected flip-flops in shift register 184 provide delayed versions of FRCLK 42. The delayed versions of FRCLK42 are gathered in bus 185 and are inputs to data selector 183. Data selector 183, under control of FSM 182, selects one of the delayed versions of FRCLK 42 outputting it as MEMCLK 181. FSM 182 is first initialised to select the longest delay from shift register 185 by setting address lines 186 to the appropriate state. The signal COMP then is used to step the FSM through a well-defined sequence that results in address lines 186 being modified to select ever-decreasing delayed versions of the signals in bus 185. While signal COMP is true, indicating that the delay period though command decoder 125 is shorter than the delay between FRCLK 42 and MEMCLK 181 , the address lines select ever-decreasing delayed versions of FRCLK 42. When signal COMP becomes false, indicating that the delay through command decoder 125 is longer than the delay between FRCLK 42 and MEMCLK 181 , FSM 182 stops decrementing address lines 186 and increments address lines 186 till COMP becomes true again. At this point FSM halts and the calibration process is complete. It should be obvious to someone skilled in the art that other calibration sequences may be implemented that result in the same result.

Although the present invention does not show any lane-to-lane skew removal, it is obvious to someone skilled in the art that such circuitry would be required at very high speed operation but such deskew removal introduces additional delay to the overall serial communications process and does not impact the validity of the proposed invention. Although the present invention is described in relation to an application between a host controller and a memory interface, it is obvious to someone skilled in the art that the methods described in the invention are applicable to other applications involving transmission of data between one system and another system where reduced latency may increase the overall performance.

Claims

WE CLAIM:

1. A Communications receiver with reduced latency comprising: a plurality of transceiver cells for receiving frames of serial data from a host controller and transmitting frames of serial data back to the host controller, the transceiver cells deserialising the data into a parallel output data word of width equal to the number of bits in a frame; a memory interface controller for decoding the parallel frame data from the transceiver cells and generating control signals and data signals to a memory device, the controller performing write operations and formatting read data and status information from the memory device to the transceiver cells for onwards transmission across the serial interface; wherein the receiver further comprises a means for adjustment of the phase of the deserialised output data to offset the parallel output data word to the frame control clock, wherein the parallel output data word is aligned to the frame clock such that the output data becomes valid when the command field has been deserialised.

2. A communications receiver according to claim 1 wherein the frame comprises multiple segments of information fields, including a command field and a data field, the bits in each field spread across one or more serial lanes.

3. A communications receiver according to claim 2 wherein the frame comprises multiple segments of information fields, including a command field and a data field, the bits in each field spread across all serial lanes.

4. A communications receiver according to any one of claims 1 to 3 wherein the command field is split across multiple frames and contained within the first part of each frame.

5. A communications receiver according to claim 1 , wherein the memory interface controller comprises a command decoder and a vernier wherein the vernier generates a clock offset from the frame clock and timed to coincide with the worst-case delay data path in the command decoder.

6. A Communications receiver according to claim 5, wherein the command decoder comprises a first register to hold a pre-defined data pattern exercising the worst-case delay path through the command decoder.

7. A communications receiver according to claim 5, wherein the command decoder comprises a data selector for selecting between the parallel data word from the transceiver cells or the first register.

8. A communications receiver according to claim 5, wherein the command decoder comprises a decoder for translating the commands embedded in the frames of received data.

9. A communications receiver according to claim 6, wherein the command decoder further comprises a second register to hold a pre-defined data pattern corresponding to the expected result of applying the data pattern held in the first register to the decoder.

10. A communications receiver according to claim 9, wherein the command decoder comprises a comparator for comparing the output of the decoder against the second register when the data contents of the first register are selected by the data selector as input to the decoder.

11. A communications receiver according to claim 10, wherein the command decoder further comprises a latch to store the results of the comparator.

12. A communications receiver according to claim 5, wherein the clock vernier adjusts the input clock in phase to provide an output clock that is aligned to the output of the command decoder.

13. A communications receiver according to claim 12, wherein the clock vernier comprises a shift register, the input to the shift register being the frame clock and the clock to the shift register being a clock of substantially higher frequency than the frame clock;

14. A communications receiver according to claim 13, wherein the clock vernier further comprises a data selector for selecting one output of the shift register.

15. A Communications receiver according to claim 13, wherein the clock vernier comprises a finite state machine for controlling the calibration of the delay path through the command decoder.

16. A communications receiver according to claim 15, wherein the finite state machine outputs address signals to the data selector selecting delayed frame clock outputs from the shift register in a pre-defined sequence to determine the optimum sampling point of the data at the output of the command decoder.

17. A method of latency reduction comprising the following steps: receiving frames of serial data from a host controller and transmitting frames of serial data back to the host controller through a plurality of transceiver cells for deserialising the data into a parallel output data word of width equal to the number of bits in a frame; decoding the parallel frame data from the transceiver cells and generating control signals and data signals to a memory device; performing write operations and formatting read data and status information from the memory device to the transceiver cells for onwards transmission across the serial interface;

18. the method further comprising a step of adjusting the phase of the deserialised parallel output data to offset the parallel output data word to the frame control clock, wherein the parallel output data word is aligned to the frame clock such that the output data becomes valid when the command field has been deserialised. A method of claim 17 wherein the frame comprises multiple segments of information fields, including a command field and a data field, the bits in each field spread across one or more serial lanes.

19. A method of claim 17 wherein the command field is split across multiple frames and contained within the first part of each frame.

20. A method of claim 17, wherein a clock offset from the frame clock is generated and timed to coincide with the worst-case delay data path in the command decoder.

21. A method of claim 20, wherein a pre-defined data pattern is used to exercise the worst-case delay path.

22. A method of claim 17, further comprising a step of translating the commands embedded in the frames of received data.

23. A method of claim 21 , further comprising a step of holding a pre-defined data pattern corresponding to the expected result of applying the data pattern.