CN117472676A - Efficient register fault injection method for embedded processor - Google Patents

Abstract

The invention relates to an embedded processor-oriented high-efficiency register fault injection method, which comprises the following steps: analyzing an instruction structure of an instruction set of a processor, and extracting an instruction related to register operation; classifying instructions related to register operation according to injection time sequences, constructing a tree diagram structure between the instructions and the injection time sequences, and obtaining a fault injection model of an instruction set related to the register operation; acquiring a user program instruction, and constructing a register fault injection vector adapting to the user program according to a fault injection model; when the program is executed to the instruction, fault injection is performed according to the fault injection vector. The invention realizes accurate injection time, and can more accurately simulate the real situation when the hardware resource is affected by irradiation and overturned, thereby improving injection efficiency; meanwhile, the invention can be used for application occasions such as design verification of a single event upset protection scheme.

Description

Efficient register fault injection method for embedded processor

Technical Field

The invention belongs to the technical field of reliability evaluation, and relates to an efficient register fault injection method for an embedded processor.

Background

The instruction set of an embedded processor is load/store, i.e., most instructions in the instruction set can only process data in registers, and the processing results are put back into registers. However, the register used as the core memory unit is a radiation sensitive unit, so that a single event upset effect is easy to generate, and the function execution of the processor program instruction is seriously affected.

In the traditional fault injection mode, a fault tree program instruction is implanted into a tested system, and the execution result of a hardware system is judged through task execution, so that the influence of a dynamic response fault tree on the system is realized; or simulating a hardware bottom fault driving mode through a tested system hardware bus interface, so as to simulate the influence of a fault execution result in system hardware; or the fault injection is performed by random time, so that the directivity of the fault injection is insufficient, and the fault injection with low efficiency and low accuracy is caused. Therefore, the fault injection method cannot achieve the aim of efficient injection in terms of injection mode, efficiency and effect.

Disclosure of Invention

The invention solves the technical problems that: the defect of the prior art is overcome, and an efficient register fault injection method for an embedded processor is provided.

The solution of the invention is as follows:

an efficient register fault injection method for an embedded processor, comprising:

analyzing an instruction structure of an instruction set of a processor, and extracting an instruction related to register operation;

classifying instructions related to register operation according to injection time sequences, constructing a tree diagram structure between the instructions and the injection time sequences, and obtaining a fault injection model of an instruction set related to the register operation;

acquiring a user program instruction, and constructing a register fault injection vector adapting to the user program according to a fault injection model;

when the program is executed to the instruction, fault injection is performed according to the fault injection vector.

Preferably, the processor instruction set includes the general classes of data processing instructions, data load and store instructions, branch instructions, program state register processing instructions, coprocessor instructions, and exception generation instructions 6.

Preferably, the instruction architecture format of the processor instruction set is as follows:

＜opcode＞{cond}{S}{Rd},{Rn},{＜OP2＞}

wherein opcode represents an operation code; cond represents a condition field of instruction execution; s represents whether the execution result of the instruction affects the program state register, and the suffix is used for representing that the execution result affects the program state register; rd represents a destination register; rn represents a first operand, typically a register; OP2 represents a second operand, which is an immediate, register, or register shift operand.

Preferably, when the fault injection model is constructed, firstly, an operation code < opcode > in an instruction set is analyzed, a register used by the operation code is analyzed, and a register to be injected in the instruction is defined; for ordered injection instructions, the operation code has unique and definite injection time; if the unordered instruction is injected, fault injection can be performed before and after the operation code is executed.

Preferably, when constructing a tree graph structure between instructions and injection timings, the injection timings of instructions in the same class are consistent.

Preferably, the instruction injection timing classification set includes three main classes, namely a post-execution injection set RA, a pre-execution injection set RB and a pre-execution and post-execution injectable set RR.

Preferably, the fault injection model is as follows:

r is an instruction injection time sequence classification set, and is divided into three main types, namely an injection set RA after execution, an injection set RB before execution and an injection set RR before and after execution, wherein Ra, rb and Rc represent instructions in the three main types of sets; r is R _ij Refers to somethingThe injection characteristic vector of the instruction, i represents the injection time sequence classification set number, j represents the instruction number in the injection time sequence classification set, INS is the instruction name, position is the injection time, and resource is the register of the fault to be injected; mask is an abnormal data mask, consisting of '0' and '1', wherein the bit position of 1 represents the fault injection position, a, b and c respectively represent the subset numbers of the injection time sequence classification set, and x, y and z respectively represent the instruction sequence numbers in the subsets of the classification set; the abnormal data mask performs exclusive OR operation with the original data of the register to realize the bit overturn of the original data and complete the fault injection.

Preferably, the instruction related to the register operation is fetched, and the fetching method is as follows:

compiling the program, analyzing the compiled instruction structure to obtain a compiled instruction sequence, and extracting the instruction name related to the register operation and the register in the instruction from the instruction sequence.

Preferably, instructions related to register operations are classified according to injection timing, the method is as follows:

and modifying the register manipulated in the instruction before and after executing the instruction, taking whether the result generates faults as a classification basis, determining proper injection time according to the analysis classification result of the instruction set according to each instruction and the register related to the instruction, and then turning the data of the register in units at the time.

A terminal device, comprising:

a memory for storing instructions for execution by the at least one processor;

and the processor is used for executing the instructions stored in the memory to realize the method.

The invention provides a design method of a fault injection model based on a tree diagram structure aiming at the soft error influence generated by single event upset generated by internal resources of a microprocessor in an irradiation environment. According to the method, injection is performed at the fine time granularity of the program instruction, the register is injected to simulate the condition that different hardware resources are affected by irradiation when a specific instruction is executed, so that accurate injection time is realized, the real condition when the hardware resources are affected by irradiation and are overturned can be simulated more accurately, and the injection efficiency is improved; meanwhile, the method can be used for application occasions such as design verification of a single event upset protection scheme. The advantages are as follows:

(1) The invention designs a tree structure fault injection model of a hardware structure related to an instruction set, the instruction set is divided into six instruction trees with different functions according to functions and tree data structures, and nodes of the instruction tree are related to hardware resources in a graph form, so that the situation when a plurality of different hardware resources are overturned is simulated by injecting registers, and different soft error occurrence rates of the hardware resources are better simulated.

(2) According to the invention, by means of instruction meaning and register injection, the time for injecting the register when executing the instruction is divided into three types, namely before instruction execution, after instruction execution and before and after instruction execution, so that the most suitable fault injection time is selected for each instruction, the condition that injection errors are covered can be effectively avoided, and accurate and effective fault injection is ensured.

Drawings

FIG. 1 is a schematic diagram of the correspondence between instructions and injection timing;

FIG. 2 is a flow chart of the method of the present invention;

FIG. 3 is a diagram illustrating an instruction actually to be executed according to an embodiment;

FIG. 4 is a state of a register before instruction execution in an embodiment;

FIG. 5 is a diagram showing the result of normal execution of an instruction according to an embodiment;

FIG. 6 is a state of the post-injection registers in the embodiment;

FIG. 7 is a diagram illustrating the result of executing an instruction after injection in an embodiment.

Detailed Description

The invention is further illustrated below with reference to examples.

The method aims at analyzing the effective fault injection characteristics of hardware resources and program instructions, designing fault injection methods for different types of program instructions, searching the matching relation between the hardware resources and the program instructions, and constructing a fault injection model of a tree diagram structure of the program instructions and the hardware resources. In the implementation process, the invention takes a general embedded ARM processor instruction set as an example, and divides the general embedded ARM processor instruction set into a data processing instruction, a data loading and storing instruction, a branch instruction, a program state register processing instruction, a coprocessor instruction and an exception generating instruction 6.

The following is a design architecture of a fault injection model method based on a tree graph structure of the method of the present invention.

Step one: instruction structure resolution of ARM processor instruction set for fault injection

An embedded processor performs a specified task by executing a program that is comprised of a sequence of ordered instructions, a collection of instructions called an instruction system, that direct the processor to perform some operation. Microprocessors of different families differ in their instruction systems because of their different core architectures.

For an ARM processor, the general format of the instruction structure is shown below.

＜opcode＞{cond}{S}{Rd},{Rn},{＜OP2＞}

Where opcode is denoted as an opcode, e.g., ADD denotes arithmetic addition; cond represents a condition field for instruction execution, e.g., EQ represents equal conditions; s, determining whether an execution result of the instruction affects the program state register, and using the suffix to represent the execution result to affect the program state register; rd represents a destination register; rn represents a first operand, typically a register; OP2 represents a second operand, which may be an immediate, a register, or a register shift operand. In addition, the content in { may be omitted, as is indispensable. It is necessary that < opcode > is an instruction mnemonic. And { < cond > } is an execution condition of the instruction, is optional, and indicates unconditional execution by default.

Functionally, the instruction set of an embedded ARM processor is load/store, i.e., most instructions in the instruction set can only process data in registers, and the processing results are put back into registers. The ARM instruction set may be divided into the general categories of data processing instructions, data load and store instructions, branch instructions, program status register processing instructions, coprocessor instructions, and exception generation instructions 6, as shown in Table 1.

Table 1 instruction set attribute classification

In the present invention, mainly register fault injection is oriented, so that instructions related to register operation in an instruction set need to be extracted to be used as a data basis for constructing a register injection model.

The extraction method comprises the following steps: compiling the program, analyzing the compiled instruction structure to obtain a compiled instruction sequence, and extracting the instruction name related to the register operation and the register in the instruction from the instruction sequence.

Step two: constructing fault injection model based on tree graph structure

Different hardware resources carry different processor functions, and before building a tree structure of hardware resources and program instructions, the type of hardware resources in the processor should be specified first. The central processing unit comprises an arithmetic unit and a controller. The arithmetic unit receives the command sent from the controller and executes corresponding actions to process and treat the data. The arithmetic unit is a center for processing data by the processor, and mainly comprises an arithmetic logic unit, a temporary storage register, an accumulation register, a general register group, a program state register, a shifter and a counter. The controller works on the principle that control signals to be used by each component of the current processor are formed according to instruction operation codes, execution steps (micro command sequences) of the instructions and condition signals. The controller is composed of a program counter, an instruction register, an instruction decoder, a memory address register, a memory data register, a timing system and a micro-operation signal generator. The memory is the storage component of the processor for storing program instructions and data.

In fault injection, the effective fault injection type is destination register injection and operand injection, and the operand injection type is divided into an immediate and a register according to a data source.

Through analysis of hardware resources and program instructions, different hardware resources only use centralized and fixed types of program instructions, and single-event soft errors of the hardware resources are often reflected in data of registers or memories. Therefore, according to the effective fault injection type and the time-space relation of the effective fault injection, the registers in the six classes of instructions of the instruction set of the processor are classified according to injection time sequences (according to the registers manipulated in the instructions before and after executing the instructions, whether faults are generated as a classification basis or not is judged according to the results of analysis and classification of the instruction set according to each instruction and the registers related to the instructions, and then the data of the registers are turned over in units at the time), so that a tree diagram structure between the instructions and the injection time sequences is constructed, and the injection time sequences of the instructions in the same class are consistent, as shown in fig. 1.

Wherein I in the figure _i I is more than or equal to 1 and less than or equal to N, R is an instruction injection time sequence classification set, and is divided into three main types, namely RA injection after execution, RB injection before execution and RR injection before and after execution; r is R _ij Is a feature vector injected into the model. By analyzing the spatiotemporal relationship of the register and program instruction, a register fault injection model suitable for the instruction set can be constructed.

Based on the above-described ideas, an injection model for an instruction set may be constructed as follows:

wherein, R is a command injection time sequence classification set, and is divided into three main classes, namely, injection after RA, injection before RB and injection before RR and injection after RR, ra., rb. and Rc. represent commands in the three main classes; rij refers to an injection feature vector of an instruction, i represents an injection time sequence classification set number, j represents an instruction number in the injection time sequence classification set, INS is an instruction name, position is an injection time, resource is a register to be injected with a fault, mask is an abnormal data mask, and consists of 0 and 1, wherein the bit position of 1 represents a fault injection position, a, b and c respectively represent subset numbers of the injection time sequence classification set, and x, y and z respectively represent instruction sequence numbers in subsets of the classification set. The abnormal data mask performs exclusive OR operation with the original data of the register to realize the bit overturn of the original data and complete the fault injection.

When the injection model is constructed, the operation code < opcode > in the instruction set needs to be primarily analyzed. In practice, the registers used by the operation code are analyzed in detail, the registers to be injected in the instruction are defined, and the ARM instruction set is taken as an analysis object and is divided into three major classes and ten minor class subsets. The indication in table 2 indicates that for ordered injection instructions, the operation code has unique and definite injection timing; if out-of-order instructions are injected, fault injection can be performed before and after execution of the opcodes, but the effective injection positions are different.

Therefore, after analyzing each instruction according to the instruction list in the instruction set, a complete space-time relation table is constructed according to the table 2, and a register fault injection model of the instruction set is formed.

Table 2 fault injection ordered instruction subset

Step three: injection vectors are generated for the user program.

Instructions of the user function program are obtained, and a register fault injection vector adapting to the user program is constructed according to the space-time relationship shown in table 2, as shown in table 3.

Table 3 fault injection vector table

And according to the timing and the target position appointed by the injection vector, performing exclusive OR operation on the mask and the original register value, modifying the register value, and realizing fault injection on the register.

And generating a corresponding fault injection vector according to the instruction executed in the program flow through the constructed tree diagram structure model, so as to execute fault injection.

Examples:

the add instruction in the program execution flow needs to be injected, if the add instruction is currently add x1, x0, #0x390, specifically meaning that the value of the x0 register is added with the immediate 0x390 and the added result is stored in the x1 register. According to the second table, the fault injection subset type of the add instruction in the tree diagram structure is judged first, the second table can be known that the add instruction corresponds to the pre-execution injection, and the injection resource is the second register. Therefore, assuming that the fault injection vector is generated as < add according to the random single bit fault injection, the pre-execution injection, x0,0x0001>, i.e. the single event upset occurs at the lowest bit of the analog register x0, the fault injection is realized. The specific injection process and the achieved injection effect are shown below:

(1) According to the add instruction, the value of x1 will change to the result of adding the immediate 0x390 to the value of the x0 register after executing the instruction, that is, x1=0x390+x0, so the executing instruction is add x1, x0#0x390 shown in fig. 3, specifically meaning that the value of the x0 register is added to the immediate 0x390 and the result is stored in the x1 register.

(2) In fig. 4, a command is input: p/x$x1 looks at the value of register x1 to be 0xd540 before the instruction is executed; input naming: p/x$ x0 looks at the value of register x0 to be 0x2000 before the instruction is executed. In fig. 5, as a result of normal execution of the instruction, the value stored in the register x1 is 0x2390, which is identical to the value calculated by x1=0x390+x0.

(3) In fig. 5, the command is again input: p/x$ x1 looks at the value stored in register x1 after execution as 0x2390, as calculated by the aforementioned instruction x1=0x390+x0.

(4) Executing the generated fault injection vector<add, perform pre-implant, x0,0x0001>The value of register x1 after execution will change to the value of register x0 exclusive-ored with fault mask 0x0001 and then add the value of immediate 0x390, i.e. the execution instruction isThereby simulating single event upset, and the specific fault injection effect is as follows. Post-injection register value change as shown in fig. 6, single bit flipped fault injection is achieved using p/x$x0 to see the change of the value of register x0 to 0x2001 before execution of the instruction. The result of the instruction execution after injection is shown in FIG. 7, the value of the x1 register is again checked using p/x$x1 and displayed in 16-ary fashion, the end result being just as +.>The calculated agreement, the value after the instruction has been run after injection becomes 0x2391, changing the state of only one bit compared to the normal result shown in fig. 5.

When fault injection is executed, the effective fault injection type is destination register injection and operand injection, and the operand injection type is divided into an immediate and a register according to a data source. By analyzing the hardware resources and the program instructions, the hardware resources of different operation applications are concentrated in the program instructions of a fixed type, single-particle soft errors of the hardware resources are often reflected in data of a storage unit, the data access process under different execution states is simulated through a register, six major classes of a processor instruction set are subdivided into a plurality of subsets according to the space-time relationship of fault injection effectiveness, and a tree diagram structure associated with the hardware resources and the program instructions is constructed, so that the purpose of efficiently simulating fault injection is achieved.

Although the present invention has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present invention by using the methods and technical matters disclosed above without departing from the spirit and scope of the present invention, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present invention are within the scope of the technical matters of the present invention.

Claims (10)

1. An efficient register fault injection method for an embedded processor is characterized by comprising the following steps:

analyzing an instruction structure of an instruction set of a processor, and extracting an instruction related to register operation;

classifying instructions related to register operation according to injection time sequences, constructing a tree diagram structure between the instructions and the injection time sequences, and obtaining a fault injection model of an instruction set related to the register operation;

acquiring a user program instruction, and constructing a register fault injection vector adapting to the user program according to a fault injection model;

when the program is executed to the instruction, fault injection is performed according to the fault injection vector.

2. An embedded processor oriented high efficiency register fault injection method as claimed in claim 1, wherein the processor instruction set comprises a data processing instruction, a data load and store instruction, a branch instruction, a program status register processing instruction, a coprocessor instruction and an exception generation instruction 6 major classes.

3. An efficient register fault injection method for an embedded processor as claimed in claim 2, wherein the instruction structure format of the processor instruction set is as follows:

＜opcode＞{cond}{S}{Rd},{Rn},{＜OP2＞}

wherein opcode represents an operation code; cond represents a condition field of instruction execution; s represents whether the execution result of the instruction affects the program state register, and the suffix is used for representing that the execution result affects the program state register; rd represents a destination register; rn represents a first operand, typically a register; OP2 represents a second operand, which is an immediate, register, or register shift operand.

4. The method for efficiently injecting faults into registers of an embedded processor according to claim 3, wherein when a fault injection model is constructed, an operation code < opcode > in an instruction set is analyzed, a register used by the operation code is analyzed, and a register to be injected in the instruction is defined; for ordered injection instructions, the operation code has unique and definite injection time; if the unordered instruction is injected, fault injection can be performed before and after the operation code is executed.

5. The method of claim 4, wherein the same type of internal instruction injection sequences are identical when constructing a tree structure between the instructions and the injection sequences.

6. The method of claim 5, wherein the instruction injection timing classification set includes three main classes, namely a post-execution injection set RA, a pre-execution injection set RB, and a pre-execution and post-execution injectable set RR.

7. The method for efficient register fault injection for embedded processors of claim 6, wherein the fault injection model is as follows:

r is an instruction injection time sequence classification set, and is divided into three main types, namely an injection set RA after execution, an injection set RB before execution and an injection set RR before and after execution, wherein Ra, rb and Rc represent instructions in the three main types of sets; r is R _ij The injection characteristic vector of a certain instruction is represented by i representing the injection time sequence classification set number, and j representing the injection time sequence classification setIn the instruction number, INS is the instruction name, position is the injection time, and resource is the register to be injected with fault; mask is an abnormal data mask, consisting of '0' and '1', wherein the bit position of 1 represents the fault injection position, a, b and c respectively represent the subset numbers of the injection time sequence classification set, and x, y and z respectively represent the instruction sequence numbers in the subsets of the classification set; the abnormal data mask performs exclusive OR operation with the original data of the register to realize the bit overturn of the original data and complete the fault injection.

8. An efficient register fault injection method for an embedded processor as claimed in claim 1, wherein the instruction associated with the register operation is fetched by:

compiling the program, analyzing the compiled instruction structure to obtain a compiled instruction sequence, and extracting the instruction name related to the register operation and the register in the instruction from the instruction sequence.

9. The method for efficient register fault injection for embedded processors of claim 1, wherein the instructions related to register operations are classified according to injection timing, the method comprising:

and modifying the register manipulated in the instruction before and after executing the instruction, taking whether the result generates faults as a classification basis, determining proper injection time according to the analysis classification result of the instruction set according to each instruction and the register related to the instruction, and then turning the data of the register in units at the time.

10. A terminal device, comprising:

a memory for storing instructions for execution by the at least one processor;

a processor for executing instructions stored in a memory to implement the method of any one of claims 1-8.