CN116450431A - Instruction function test system of CPU reference model, method thereof, computer equipment and storage medium - Google Patents
Instruction function test system of CPU reference model, method thereof, computer equipment and storage medium Download PDFInfo
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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Abstract
The invention discloses a system and a method for testing instruction functions of a CPU reference model, computer equipment, a computer readable storage medium and a computer program product, wherein the system comprises: CPU references the model; the test case interface module is connected with the CPU reference model and is used for providing functions required by generating test instructions and configuring the state of the CPU reference model; the test case module is connected with the test case interface module and is used for writing test cases of instructions according to functions provided by the test case interface module; and the result comparison module is used for acquiring the execution result of the test instruction from the CPU reference model through the test case interface module, and comparing the execution result with the expected result set by the test case so as to check whether the instruction function of the CPU reference model is correct. The invention can solve the problems of low test efficiency and more dependence caused by the need of supporting new development instructions in the prior art.
Description
Technical Field
The present invention relates to computer testing technology, and in particular, to a system and a method for testing instruction functions of a CPU reference model, a computer device, a computer readable storage medium, and a computer program product.
Background
In the process of chip verification, the reference model needs to be developed and maintained, the workload required by functional test on the reference model in the process of developing the reference model is large, more labor cost is generally consumed, cost and efficiency cannot be reduced, and the functional test on the reference model is performed through the self-checking test case written by assembly instructions, so that the labor cost can be saved, but the test efficiency is low.
In the prior reference model test flow, after the development of the reference model is completed, executing self-checking test cases written by assembly instructions by the reference model, and testing the functions of the reference model; or the reference model and the third party model execute the test cases generated by the random instruction generator, and the result of the reference model is compared with the result of the third party model, so that the test of the function of the reference model is realized.
Whether writing self-test cases or test cases generated using a random instruction generator, support of tool chains such as assembler is required. When writing the self-test case, the self-test value needs to be constructed, and the efficiency is low. When the random instruction generator and the third party model are used, the random instruction generator and the third party model are required to support newly developed instructions, and are more dependent.
In view of the above, it is necessary to provide a system and a method for testing instruction functions of a CPU reference model, so as to solve the problems of low testing efficiency and more dependence caused by the need of supporting newly developed instructions.
Disclosure of Invention
The invention aims to provide an instruction function test system and method of a CPU reference model, computer equipment, a computer readable storage medium and a computer program product, which are used for solving the problems of low test efficiency and more dependence caused by the need of supporting newly developed instructions in the prior art.
In order to achieve the above object, the present invention provides an instruction function test system of a CPU reference model, comprising:
CPU references the model;
the test case interface module is connected with the CPU reference model and is used for providing functions required by generating test instructions and configuring the state of the CPU reference model;
the test case module is connected with the test case interface module and is used for writing test cases of instructions according to functions provided by the test case interface module; and
The result comparison module is connected with the test case interface module and the test case module and is used for acquiring an execution result of a test instruction from the CPU reference model through the test case interface module and comparing the execution result with an expected result set by the test case so as to check whether the instruction function of the CPU reference model is correct.
In an embodiment of the present invention, the instruction function test system of the CPU reference model, wherein the CPU reference model includes:
the interface function module is used for setting an interface function of the CPU reference model;
the instruction set module is used for acquiring an instruction set formed by all instruction objects of the CPU;
the instruction execution module is connected with the interface function module and the instruction set module and is used for realizing the function of executing instructions by the CPU reference model according to the interface function and the instruction set; and
And the CPU state module is connected with the instruction execution module and the instruction set module and used for defining the CPU state and storing the execution result obtained by the instruction execution module.
In an embodiment of the present invention, the function provided by the test case interface module includes an instruction parameter configuration function, an instruction generation function, a reference model state configuration function, and an instruction execution function.
In an embodiment of the present invention, the instruction function test system of the CPU reference model, wherein the test case module writes the test cases in the following manner:
invoking the reference model state configuration function and initializing the state of the CPU reference model; and
Determining a test scene of an instruction, calling the instruction parameter configuration function to set test parameters of the instruction, calling the instruction generation function to generate a test instruction according to the test parameters, calling the reference model state configuration function to set a reference model state expected by the test instruction, transmitting the test instruction to a CPU reference model through the instruction execution function, and executing the test instruction by the CPU reference model.
In an embodiment of the invention, the instruction function test system of the CPU reference model, wherein the test case module adopts a C++ language function to realize the writing of the test case.
In an embodiment of the invention, the instruction function test system of the CPU reference model, wherein the instruction function test system further includes:
the instruction test module is a top layer module and is used for scheduling test cases, starting instruction function test, counting test information and reporting test results.
On the other hand, the invention also provides a method for testing the instruction function of the CPU reference model, which comprises the following steps:
providing a function required for generating test instructions and configuring the state of the CPU reference model;
writing a test case of an instruction according to the function;
and executing the test instruction by the CPU reference model, acquiring an execution result, and comparing the execution result with an expected result set by the test case so as to check whether the instruction function of the CPU reference model is correct.
In an embodiment of the present invention, the instruction function test method of a CPU reference model, wherein in the step of providing a function required to generate a test instruction and configure a state of the CPU reference model, the CPU reference model is configured to:
setting an interface function of the CPU reference model by an interface function module;
the instruction set module acquires an instruction set formed by all instruction objects of the CPU;
the instruction execution module realizes the function of executing instructions by the CPU reference model according to the interface function and the instruction set; and
And defining a CPU state by a CPU state module, and storing an execution result obtained by the instruction execution module.
In an embodiment of the present invention, the method for testing instruction functions of the CPU reference model, wherein in the step of providing a function required for generating a test instruction and configuring a state of the CPU reference model, the function at least includes: an instruction configuration function, an instruction generation function, a reference model state configuration function, and an instruction execution function.
In an embodiment of the present invention, the method for testing an instruction function of the CPU reference model, wherein the step of writing the test case of the instruction according to the function includes: test cases were written as follows:
invoking the reference model state configuration function and initializing the state of the CPU reference model; and
Determining a test scene of an instruction, calling the instruction parameter configuration function to set test parameters of the instruction, calling the instruction generation function to generate a test instruction according to the test parameters, calling the reference model state configuration function to set a reference model state expected by the test instruction, transmitting the test instruction to a CPU reference model through the instruction execution function, and executing the test instruction by the CPU reference model.
In an embodiment of the present invention, the method for testing an instruction function of the CPU reference model, wherein the step of writing the test case of the instruction according to the function includes: repeating the step of writing the test cases of the instructions according to the functions, obtaining the test cases of all the instructions, forming a functional test set of a CPU reference model, and operating the functional test set after each change of the CPU reference model.
In addition, the present invention also provides a computer device, including:
at least one processor; and
and a memory for storing computer instructions executable on the processor, which when executed by the processor implement the instruction function test method of the CPU reference model as described above.
Furthermore, the present invention provides a computer-readable storage medium storing a computer program, wherein the computer program when executed implements the instruction function test method of the CPU reference model as described above.
Furthermore, the present invention provides a computer program product comprising computer instructions for instructing a computer device to execute the method for testing the instruction function of the CPU reference model as described above.
Compared with the prior art, the invention has the beneficial technical effects that:
the CPU reference model can simplify the function test flow of the CPU reference model and improve the stability and development efficiency of the CPU reference model.
In the development process of the CPU reference model, the invention can also perform functional test on the newly added instruction of the CPU reference model.
Drawings
Fig. 1A is a block diagram of an instruction function test system of a CPU reference model of the present invention.
Fig. 1B is a diagram showing a reference model of a CPU in the instruction function test system of the present invention.
FIG. 2 is a flow chart of a method for testing instruction functions of a CPU reference model according to the present invention.
Wherein, the reference numerals:
instruction function test system 100 of 100 … CPU reference model
101 … test case interface module
102 … test case module
103 … result comparison module
104 … instruction test module
105 … CPU reference model
151 … model interface module
152 … instruction execution module
153 … CPU status module
154 … instruction set module
S201-S206 … steps
Detailed Description
In order to better understand the technical solutions in the embodiments of the present application, the following descriptions will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the embodiments of the present application shall fall within the scope of protection of the embodiments of the present application.
First, for a better understanding of the present invention, some terms or nouns appearing in the course of describing the embodiments of the present application are applicable as follows:
reference model: refers to a functional model in the verification process for implementing the function of executing the test instruction.
Test cases: refers to a function of a set of test inputs, execution conditions, and expected results programmed for a particular target to verify that a particular requirement is met.
Referring to FIG. 1A, a block diagram of an instruction function test system of a CPU reference model according to the present invention is shown. In fig. 1A, the instruction function test system 100 of the CPU reference model is mainly composed of the following modules: the test case interface module 101, the test case module 102, the result comparison module 103, the instruction test module 104, and the CPU reference model 105 are disposed in the instruction test module 104 in one embodiment. The CPU reference model 105 refers to a functional model of the CPU in the process of CPU verification, and is used for implementing the function of the CPU executing the test instruction.
The CPU reference model 105 is mainly composed of a model interface module 151, an instruction execution module 152, a CPU state module 153, an instruction set module 154, and the like.
The model interface module 151 is mainly used for setting various interface functions of the CPU reference model 105. Specifically, the interface functions include, but are not limited to, one or more of the following functions:
(1) Initializing an interface function: the state of the CPU reference model 105 is initialized.
(2) Instruction execution interface function: the CPU reference model 105 is driven to execute instructions.
(3) Access interface function: the CPU references the model 105 to access the memory model.
(4) Interface function to interact with a module under test (DUT, device Under Testing): such as to obtain an interrupt signal for the DUT.
(5) Verifying an environment interface function: the interface functions of the CPU reference model 105 interacting with the verification environment, such as the functions that obtain the instruction execution results, are interface functions that are used to test the instruction functions of the CPU reference model 105.
The instruction execution module 152 is connected to the model interface module 151, and is mainly used for implementing the function of executing instructions by the CPU reference model 105. Specifically, the instruction execution module 152 executes instructions mainly in the following steps:
(1) the finger taking step: and accessing the memory model through the memory access interface function to acquire the instruction codes.
(2) Decoding: the instruction code is decoded and the instruction object corresponding to the instruction code is found from the instruction set 154.
(3) The instruction execution step: and calling an execution function of the instruction object to finish the operation corresponding to the instruction.
(4) Interrupt and exception steps are handled.
The CPU state module 153 is mainly used for defining the states of the CPU, such as a register file of the CPU, a privilege model of the CPU, and the like, and storing the execution result obtained by the instruction execution module 152 executing the instruction.
The instruction set module 154 is mainly used for acquiring an instruction set formed by all instruction objects of the CPU. Specifically, instruction set module 154 is configured to:
modeling all instructions supported by the target CPU using a c++ class (but not limited to this approach), defining and implementing instruction classes, different instructions corresponding to different instruction classes.
Creating instruction objects from the instruction class, all of which constitute the instruction set of the CPU.
With reference to fig. 1A and 1B, a test case interface module 101, a test case module 102, a result comparison module 103, and an instruction test module 104 in the instruction function test system 100 are further described in detail.
The test case interface module 101 mainly realizes some interface functions for generating test instructions and configuring the states of a CPU reference model, and is used for writing test cases, and is divided into an instruction parameter configuration function, an instruction generation function, a reference model state configuration function, an instruction execution function and the like.
In some embodiments of the present invention, the instruction parameter configuration function mainly configures values of different fields in the instruction code, such as values of instruction operands and operation codes of instructions.
In some embodiments of the present invention, the instruction generating function mainly configures parameters configured by the function according to instruction parameters, generates a test instruction, and returns instruction codes.
In some embodiments of the present invention, the reference model state configuration function is primarily configured to configure the state of the CPU reference model 105. The CPU references the state of model 105, including, but not limited to, the values of general purpose registers and control registers, such as the state of MMU (Memory Manage Unit, memory management unit) and PMP (Physical Memory Protection ), and the like. After the instruction parameter configuration function determines the operand registers of the instruction, the configuration of the instruction operand values may be achieved by configuring the values of the operand registers in the CPU reference model 105 by reference model state configuration functions. In addition, the reference model state configuration function may also configure other reference model states, such as privilege modes, and the like.
In some embodiments of the present invention, the instruction execution function is to pass the code of the instruction to be tested to the CPU reference model 105, and the CPU reference model 105 executes the instruction to be tested. The original instruction execution step of the CPU reference model 105 is modified, the instruction fetching step is skipped, the instruction to be tested is directly transmitted to the CPU reference model 105, and the CPU reference model 105 is enabled to execute the instruction to be tested.
The test case module 102 is a collection of test cases for instructions. The basic unit of the test case is an instruction to be tested, each instruction to be tested has one test case, and the function of the instruction is tested in the test case. Each test case comprises a plurality of test instructions, and each test instruction corresponds to one test scene of the instruction to be tested. The test case is actually a function of the test instruction object, and the test of the instruction function is implemented inside the function. The test cases were written as follows:
2.1, calling a reference model state configuration function, and initializing the state of the CPU reference model 105.
2.2, firstly determining a test scene of the instruction, calling an instruction parameter configuration function, setting parameters such as an operand, an immediate and the like of the instruction, and then calling an instruction generation function to generate a test instruction. And calling a reference model state configuration function, and setting the expected reference model state of the test instruction. Then, the instruction execution function is called to transfer the test instruction to the CPU reference model 105, so that the CPU reference model 105 executes a test instruction. The result comparison module 103 is then invoked to set the expected value of the result of the instruction, and the result comparison module 103 checks whether the CPU reference model 105 performs correctly.
And 2.3, repeating the step 2.2 to obtain a test instruction of the to-be-tested instruction in different test scenes.
The result comparison module 103 is responsible for acquiring the execution result of the test instruction from the CPU reference model 105 and comparing with the expected result set by the test case, thereby checking whether the instruction function of the CPU reference model 105 is correct.
The instruction testing module 104 is configured to configure an instruction to be subjected to a functional test according to parameters of the instruction test, call a test case function of the instruction to be tested, and perform the instruction functional test by executing the test case of the instruction.
In the instruction function test system 100, a test case module 102 implements a test case of an instruction, which communicates with a CPU reference model 105 and a result comparison module 103 through a test case interface module 101. Specifically, parameters of a test instruction are configured through an instruction parameter configuration function of the test case interface module 101, and the test instruction is generated through an instruction generation function; the instruction execution function of the test case interface module 101 is also used for calling the CPU reference model 105 to execute the test instruction and calling the result comparison module 103 to check whether the instruction function of the CPU reference model 105 is correct.
In the instruction function test system 100, the instruction test module 104 is a top module of an instruction function test scheme, and is responsible for scheduling test cases in the test case module 102, starting instruction function test, counting test information, and reporting test results.
As shown in FIG. 2, a flow chart of the instruction function test method of the CPU reference model is provided. With reference to fig. 1A and 1B, the specific steps of the flow of the method are as follows:
s201, determining an instruction test space.
In some embodiments of the present invention, in this step, the instruction test space refers to a test parameter set of an instruction, and the test parameter refers to a parameter affecting an instruction execution result, including an instruction parameter and a CPU reference model state. Such as the operands of the instructions, the values of the control registers of the CPU reference model 105, etc. The instruction test space, i.e. the test parameters of the instruction and the range of values of these parameters, are determined.
S202, determining a test scene.
In some embodiments of the invention, in this step, one test scenario refers to a combination of instruction test parameter values. Different test scenes, the value combinations of the instruction test parameters are different. And determining a test scene, namely determining the value of each test parameter of the instruction, wherein the value of the test parameter is within the range of the value of the test parameter. And each test scene is tested through one test instruction.
S203, generating a test instruction.
In some embodiments of the present invention, after determining the instruction test scenario, this step invokes the interface function provided by the test case interface module 101 according to the determined instruction test parameter, sets the initial state of the CPU reference model 105, and generates the test instruction. An expected result of the test instruction is determined. If so, an exception occurs, a result is calculated, etc.
S204, the CPU refers to the model 105 to execute the test instruction.
In some embodiments of the present invention, this step is performed by the instruction execution module 152 of the CPU reference model 105 to cause the CPU reference model 105 to execute test instructions via an instruction execution function.
S205, comparing the execution result of the test instruction.
In some embodiments of the present invention, this step is performed by the result comparison module 103 obtaining the execution result of the test instruction from the CPU reference model 105, comparing with the execution result expected by the test case, and checking whether the instruction function of the CPU reference model 105 is correct.
S206, judging whether to end the test.
In this step, if the result comparing module 103 generates that the execution result of the test instruction is different from the expected result given by the test case, the test is ended and the test result is reported. If the result comparison passes, a check is started to see if all test spaces have been traversed. If not traversing all the test spaces, selecting a new test scene and continuing the test. If all test spaces have been traversed, the test is ended.
In view of the above object, another aspect of an embodiment of the present invention provides a computer apparatus, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executed by the processor to perform the steps of the method as described above.
The invention also provides a computer readable storage medium storing a computer program which when executed by a processor performs the method as above.
The present invention further provides a computer program product comprising computer instructions for instructing a computer device to execute the method for testing the instruction function of the CPU reference model as described above.
It should be noted that, it will be understood by those skilled in the art that all or part of the processes in the above-described embodiments may be implemented by a computer program to instruct related hardware, and the program of the instruction function test method of the CPU reference model 105 may be stored in a computer readable storage medium, and the program may include the processes in the above-described embodiments of the methods when executed. The storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (RAM), or the like.
Embodiments of the computer program may achieve the same or similar effects as any of the method embodiments previously described.
Furthermore, the method disclosed according to the embodiment of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. The above-described functions defined in the methods disclosed in the embodiments of the present invention are performed when the computer program is executed by a processor.
Furthermore, the steps of the method and elements of the assembly described above may also be implemented using a controller and a computer readable storage medium storing a computer program for causing the controller to implement the functions of the steps or elements described above.
Those of skill would further appreciate that the various illustrative modules, circuits, and process steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The foregoing is a description of exemplary embodiments of the invention disclosed herein, but it should be noted that various changes and modifications could be made without departing from the spirit and substance of the invention.
Compared with the prior art, the invention has the advantages that:
1. the instruction function test scheme provided by the invention is characterized in that the test case interface module 101, the result comparison module 103 and the instruction test module 104 are all universal modules except the test case module 102. When a to-be-tested instruction is newly added, only a test case of the to-be-tested instruction is needed to be realized. The test case is written in three steps of setting instructions and reference model states, running the test instructions by the reference model and comparing results, and the test case is written simply and conveniently.
2. The instruction function test scheme provided by the invention can be used as a function test module of a reference model, and is developed by using C++ language as the reference model. The whole test environment is a C++ program, the running speed is high, tens of thousands of test instructions can be executed in one second by the reference model, so that a large number of test scenes can be covered by the test cases, and the test time is short.
3. According to the instruction function test scheme provided by the invention, the programming of test cases is realized through the C++ function, a assembler and a third party model which are not dependent on newly added instructions are not needed, the function test can be performed in the process of programming model development, and the reference model development mode of test drive development is realized. And the test is carried out while the development is carried out, so that the functional faults of the reference model are quickly found, and the development and debugging efficiency of the reference model is improved.
4. The invention can make the test cases of all instructions into the function test set of the reference model, and after each time the reference model is changed, the function test set is operated for one time, thereby helping to find faults introduced by modifying the reference model and improving the stability of the reference model. The instruction function test scheme provided by the invention has high test speed, so that the function test set can comprise a large number of test cases.
Of course, those of ordinary skill in the art will appreciate that: the description of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of disclosure of embodiments of the invention (including the claims) is limited to these examples; combinations of features of the above embodiments or of the various embodiments are possible within the spirit of the embodiments of the invention and there are many other variations on the various aspects of the embodiments of the invention as described above, to the extent they are not provided in detail in this disclosure. Accordingly, it is intended that all such alterations and modifications as fall within the spirit and principles of this invention, including such omissions, modifications, equivalents, and improvements as may be made within the spirit and scope of the embodiments of the invention.
Claims (14)
1. An instruction function test system of a CPU reference model, comprising:
CPU references the model;
the test case interface module is connected with the CPU reference model and is used for providing functions required by generating test instructions and configuring the state of the CPU reference model;
the test case module is connected with the test case interface module and is used for writing test cases of instructions according to functions provided by the test case interface module; and
The result comparison module is connected with the test case interface module and the test case module and is used for acquiring an execution result of a test instruction from the CPU reference model through the test case interface module and comparing the execution result with an expected result set by the test case so as to check whether the instruction function of the CPU reference model is correct.
2. The instruction function test system of a CPU reference model according to claim 1, wherein the CPU reference model includes:
the interface function module is used for setting an interface function of the CPU reference model;
the instruction set module is used for acquiring an instruction set formed by all instruction objects of the CPU;
the instruction execution module is connected with the interface function module and the instruction set module and is used for realizing the function of executing instructions by the CPU reference model according to the interface function and the instruction set; and
And the CPU state module is connected with the instruction execution module and the instruction set module and used for defining the CPU state and storing the execution result obtained by the instruction execution module.
3. The system according to claim 1 or 2, wherein the functions provided by the test case interface module include an instruction parameter configuration function, an instruction generation function, a reference model state configuration function, and an instruction execution function.
4. The system for testing the instruction function of the CPU reference model according to claim 3, wherein the test case module writes the test case in the following manner:
invoking the reference model state configuration function and initializing the state of the CPU reference model; and
Determining a test scene of an instruction, calling the instruction parameter configuration function to set test parameters of the instruction, calling the instruction generation function to generate a test instruction according to the test parameters, calling the reference model state configuration function to set a reference model state expected by the test instruction, transmitting the test instruction to a CPU reference model through the instruction execution function, and executing the test instruction by the CPU reference model.
5. The instruction function test system of a CPU reference model according to claim 1, characterized in that the instruction function test system further comprises:
the instruction test module is a top layer module and is used for scheduling test cases, starting instruction function test, counting test information and reporting test results.
6. The instruction function test method of the CPU reference model is characterized by comprising the following steps of:
providing a function required for generating test instructions and configuring the state of the CPU reference model;
writing a test case of an instruction according to the function;
and executing the test instruction by the CPU reference model, acquiring an execution result, and comparing the execution result with an expected result set by the test case so as to check whether the instruction function of the CPU reference model is correct.
7. The instruction function test method of a CPU reference model according to claim 6, wherein in the step of providing a function required to generate a test instruction and configure a state of the CPU reference model, the CPU reference model is configured to:
setting an interface function of the CPU reference model by an interface function module;
the instruction set module acquires an instruction set formed by all instruction objects of the CPU;
the instruction execution module realizes the function of executing instructions by the CPU reference model according to the interface function and the instruction set; and
And defining a CPU state by a CPU state module, and storing an execution result obtained by the instruction execution module.
8. The instruction function test method of a CPU reference model according to claim 6 or 7, wherein in the step of providing a function required for generating a test instruction and configuring a state of the CPU reference model, the function includes at least: an instruction configuration function, an instruction generation function, a reference model state configuration function, and an instruction execution function.
9. The method for testing the instruction function of the CPU reference model according to claim 8, wherein the step of writing the test case of the instruction according to the function comprises: test cases were written as follows:
invoking the reference model state configuration function and initializing the state of the CPU reference model; and
Determining a test scene of an instruction, calling the instruction parameter configuration function to set test parameters of the instruction, calling the instruction generation function to generate a test instruction according to the test parameters, calling the reference model state configuration function to set a reference model state expected by the test instruction, transmitting the test instruction to a CPU reference model through the instruction execution function, and executing the test instruction by the CPU reference model.
10. The method for testing the instruction function of the CPU reference model according to claim 9, wherein in the step of writing the test cases of the instructions according to the function, the c++ language function is adopted to implement the writing of the test cases.
11. The method for testing the instruction function of the CPU reference model according to claim 9, wherein the step of writing the test case of the instruction according to the function comprises: repeating the step of writing the test cases of the instructions according to the functions, obtaining the test cases of all the instructions, forming a functional test set of a CPU reference model, and operating the functional test set after each change of the CPU reference model.
12. A computer device, comprising:
at least one processor; and
a memory for storing computer instructions executable on the processor, which when executed by the processor implement the method of instruction function testing of a CPU reference model according to any one of claims 6-11.
13. A computer readable storage medium storing a computer program, wherein the computer program when executed implements the method of instruction function testing of a CPU reference model according to any one of claims 6-11.
14. A computer program product comprising computer instructions for instructing a computer device to execute the method of instruction function testing of a CPU reference model according to any of claims 6-11.
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| CN117313595B (en) * | 2023-11-30 | 2024-02-23 | 杭州登临瀚海科技有限公司 | Random instruction generation method, equipment and system for function verification |
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