CN117472452A - High-reliability loading starting system and method in satellite-borne software definition function - Google Patents

Abstract

A high-reliability loading starting system and method in a satellite-borne software definition function belong to the technical field of satellite effective load. Aiming at the characteristics of high reliability requirement of software loading in a software defined satellite load, the invention develops the construction of a system and a method for realizing the high reliability loading and starting of the satellite-borne software, and realizes the system and the method for realizing the high reliability loading and starting in the satellite-borne software defined function. The invention solves the problem of high reliability of software definition functions in the satellite-borne computing storage resource equipment based on the high-performance FPGA, DSP, CPU, AI chip, particularly improves the high-reliability loading capacity of the software, and remarkably improves the reliability and flexibility of the satellite-borne equipment.

Description

High-reliability loading starting system and method in satellite-borne software definition function

Technical Field

The invention relates to a high-reliability loading starting system and method in a satellite-borne software definition function, and belongs to the technical field of satellite payloads.

Background

When the traditional satellite payload system is designed, a plurality of different function subsystems are adopted to jointly complete the whole satellite function according to convention, so that the defects of large quantity of satellite-borne equipment, large weight, complex equipment connection relationship, long system test time and the like are brought, the whole satellite size, quality, power consumption and cost are high, and the development requirements of miniaturization, high integration, batch production and the like of the satellite-borne equipment are restricted.

The software-defined satellite technology aims at relieving the tight coupling relation between satellite application software and satellite hardware, and is beneficial to reducing development cost, shortening development period, improving application efficiency, developing on-orbit tests, facing future demands and expanding the number of users. With the rapid development of microelectronic technology, high-performance microprocessors are continuously emerging, and the whole satellite function can be realized by combining high-functional density ratio hardware with software-defined satellite functions. The software defined satellite is a satellite adopting a novel open system architecture, supports the loading of payload software according to the requirement, and can redefine the satellite function conveniently by updating the software, thereby flexibly adapting to the requirements of various tasks and various users.

Aiming at the problem of high reliability of software loading in a software-defined satellite, if a bit file loaded is wrong, an FPGA (field programmable gate array) cannot be loaded normally, and system loading failure or abnormal functions can be caused; for CPU, DSP, AI chips, if the loaded program file is wrong, the software cannot be loaded normally, and the system is abnormal in function and even crashed.

Disclosure of Invention

The invention solves the technical problems that: the system and the method for starting the high-reliability loading in the space-borne software definition function are provided, and the problem of high-reliability loading of chips such as FPGA, CPU, DSP, AI and the like in space-borne environments such as single particles and other space radiation is solved.

The technical scheme of the invention is as follows: a high-reliability loading starting system in a satellite-borne software definition function comprises a control unit and a calculation unit;

the control unit comprises a control unit CPU module, a control unit PROM module, a control unit FPGA module and a control unit Norflash module; the control unit PROM module is used for storing a starting program of the control unit CPU module; the control unit Norflash module is used for storing an application program of the control unit CPU module and a bit file of the calculation unit; the control unit CPU module is powered on, sequentially reads and loads a starting program stored in the control unit PROM module and an application program stored in the control unit Norflash module, receives an input signal through the first control interface after starting, generates a first remote control telemetry signal after processing according to the preset remote control telemetry requirement in the control unit CPU module, and sends the first remote control telemetry signal to the control unit FPGA module through the second control interface signal; the control unit FPGA module processes the first remote control telemetry signal according to the preset remote control telemetry requirement in the control unit FPGA module, generates a second remote control telemetry signal and sends the second remote control telemetry signal to the calculation unit through the third control interface;

the computing unit comprises a computing unit FPGA module, a computing control module and a computing storage module; the calculation storage module is used for storing a calculation program of the calculation control module; the computing unit FPGA module is used for reading bit files stored in the Norflash module of the control unit after power-on for interface control and logic calculation, receiving a second remote control and telemetry signal sent by the FPGA module of the control unit by receiving a third control interface, generating various frame format signals after processing according to the preset remote control and telemetry requirements in the computing unit FPGA module, and respectively sending the frame format signals to the computing control module through corresponding interfaces; the calculation control module carries out corresponding processing on the input frame format signal by loading the program stored in the calculation storage module.

Further, the number of the computing units is configured according to the system computing power requirement; the computing control module comprises a computing unit CPU module, a computing unit DSP module and a computing unit AI module, which are respectively used for executing control tasks, computing tasks and AI computing tasks according to input signals;

the number and types of the CPU module, the DSP module and the AI module are selected and configured according to the performance requirement of the computing unit.

Further, the interface type design of the control unit CPU module, the first control interface and the control unit PROM module.

Further, after the start program of the control unit CPU module is read, a CPU application program stored in the control unit Norflash module is read through a control unit Norflash module interface of the control unit FPGA module; the capacity of the control unit Norflash module is determined by the application program capacity of the control unit CPU module and the bit file capacity of the calculation unit FPGA module in the calculation unit.

Further, the types of the computing unit FPGA modules are selected according to the performance requirements of the computing units, and the number of the computing unit FPGA modules is selected and configured according to the capacity of the control unit Norflash module and the program capacity of the computing unit FPGA modules.

Further, the computing storage module is configured according to loading interfaces of the computing unit CPU module, the computing unit DSP module and the computing unit AI module, and includes: selecting and configuring a computing unit QSPI Flash module when a QSPI interface exists, selecting and configuring a computing unit Norflash module when a Norflash interface exists, and selecting and configuring a computing unit NANDflash module when a NANDflash interface exists.

Further, the first control interface comprises a CAN bus, a 1553B bus, a SpaceWire bus, an RS422 interface and the like, and is selectively configured according to satellite bus requirements.

Further, the second control interface comprises an RS422 bus, an RS485 bus, a control unit Norflash module interface and the like, and is selectively configured according to the control unit CPU module;

further, the third control interface comprises an RS422 bus, an RS485 bus, an LVDS interface and the like, and is selectively configured according to interconnection requirements of the control unit and the computing unit.

According to the loading starting method realized by the high-reliability loading starting system in the satellite-borne software definition function, the method comprises the following steps:

the control unit CPU module is powered on, sequentially reads and loads a starting program stored in the control unit PROM module and an application program stored in the control unit Norflash module, receives an input signal through the first control interface after starting, generates a remote control telemetry signal after processing according to the preset remote control telemetry requirement in the control unit CPU module, and sends the remote control telemetry signal to the control unit FPGA module through the second control interface signal;

the control unit FPGA module automatically operates after power-on, processes the remote control telemetry signal sent by the control unit CPU module according to the preset remote control telemetry requirement in the control unit FPGA module, generates the remote control telemetry signal and sends the remote control telemetry signal to the calculation unit FPGA module of the calculation unit through a third control interface;

the computing unit FPGA module is used for completing interface control and logic computation functions after the bit file stored in the control unit Norflash module is powered on and read, receiving a remote control telemetry signal sent by the control unit FPGA module through a third control interface, generating various frame format signals after processing according to the preset remote control telemetry requirement in the computing unit FPGA module, and respectively sending the frame format signals to the computing control module through corresponding interfaces;

the calculation control module carries out corresponding processing on the input frame format signal by loading the program stored in the calculation storage module.

Compared with the prior art, the invention has the advantages that:

(1) Aiming at the problem of high reliability of software loading in a software defined satellite, compared with the prior method system, the method solves the problem of the loading reliability of an on-orbit FPGA, CPU, DSP, AI chip, adopts a three-level controllable loading mechanism, ensures that a first-level control unit CPU module and a control unit FPGA module finish the loading of the control unit software, and ensures the loading correctness of a control core unit;

(2) The method is simple and reliable, after the first-level reliable loading is ensured, the loading process of the second-level computing unit FPGA module can monitor the reconfigurable and repeated loading, the second-level loading process can monitor the correctness of the verification of each bit file comprising the high-performance FPGA, the correctness of the verification of 1-N bit files is supported, the loading is started from the first bit file by default and carried out for 3 times, if the corresponding bit loading is not successfully returned, the loading of the 2 nd bit file is continuously carried out for 3 times until the current loading is successful, or the loading is successfully carried out until the nth bit loading or the loading is exited.

(3) The method is simple and reliable, ensures the first-level and second-level reliable loading, the third-level calculation control module loading process can monitor the reconfigurability, and the third level is used for selectively loading according to different requirements because of software definition requirements, and the default loading is carried out for 3 times or the loading is carried out according to the appointed maximum loading times;

(4) The method is based on different computing unit configurations, and the high-reliability loading success of the computing unit FPGA module is ensured through the control unit Norflash module; after the loading of the computing unit FPGA module is successful, the loading of the computing unit CPU module, the computing unit DSP module and the computing unit AI module is monitored through the computing unit FPGA module, and the system is started after the loading is successful; if the loading is unsuccessful, the loading may be repeated; if the maximum number of loads is still unsuccessful according to the preset number, the system exits the loading and returns corresponding telemetry; after the system is started after exiting loading, the program storage space which is unsuccessfully loaded in the first stage, the second stage and the third stage can be checked in a targeted mode, and telemetry information is returned.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

FIG. 1 is a general design of the method of the present invention;

fig. 2 shows an embodiment of the method according to the invention.

FIG. 3 is a functional block diagram of an antifuse FPGA in a control unit in accordance with the present invention.

FIG. 4 is a functional block diagram of a programmable high performance FPGA program in a computing unit in accordance with the present invention.

Detailed Description

In order to better understand the technical solutions described above, the following detailed description of the technical solutions of the present application is provided through the accompanying drawings and specific embodiments, and it should be understood that the specific features of the embodiments and embodiments of the present application are detailed descriptions of the technical solutions of the present application, and not limit the technical solutions of the present application, and the technical features of the embodiments and embodiments of the present application may be combined with each other without conflict.

In the scheme provided by the embodiment of the application, the number of control units is 1, the number of calculation units is 2, the control units are mainly responsible for functions such as system core management and the like, and the calculation units 1 and 2 are mainly responsible for functions such as high-performance calculation and the like as high-performance computing facilities.

As shown in fig. 1, the control unit comprises a control unit CPU module, a control unit PROM module, a control unit FPGA module and a control unit NorFlash module; the control unit PROM module is used for storing a starting program of the control unit CPU module; the control unit Norflash module is used for storing an application program of the control unit CPU module and a bit file of the calculation unit; the control unit CPU module is powered on, sequentially reads and loads a starting program stored in the control unit PROM module and an application program stored in the control unit Norflash module, receives an input signal through the first control interface after starting, generates a first remote control telemetry signal after processing according to the preset remote control telemetry requirement in the control unit CPU module, and sends the first remote control telemetry signal to the control unit FPGA module through the second control interface signal; the control unit FPGA module processes the first remote control telemetry signal according to the preset remote control telemetry requirement in the control unit FPGA module, generates a second remote control telemetry signal and sends the second remote control telemetry signal to the calculation unit through the third control interface; the computing unit comprises a computing unit FPGA module, a computing control module and a computing storage module; the calculation storage module is used for storing a calculation program of the calculation control module; the computing unit FPGA module is used for reading bit files stored in the Norflash module of the control unit after power-on for interface control and logic calculation, receiving a second remote control and telemetry signal sent by the FPGA module of the control unit by receiving a third control interface, generating various frame format signals after processing according to the preset remote control and telemetry requirements in the computing unit FPGA module, and respectively sending the frame format signals to the computing control module through corresponding interfaces; the calculation control module carries out corresponding processing on the input frame format signal by loading the program stored in the calculation storage module.

Further, the number of the calculation units is configured to be 2 according to the system calculation force demand; the computing control module comprises a computing unit CPU module, a computing unit DSP module and a computing unit AI module, which are respectively used for executing control tasks, computing tasks and AI computing tasks according to input signals;

the computing unit CPU module is an 8-core CPU module and is provided with a QSPI Flash interface and a NorFlash interface; the computing unit DSP module is an 8-core DSP module and is provided with a Norflash interface; the computing unit AI module is a 12TOPS AI module and is provided with a NANDflash interface; the number is 1 each, and the domestic modules are adopted.

In one possible implementation manner, the interface type design of the control unit CPU module, the first control interface and the control unit PROM module adopts a domestic anti-radiation CPU module and a domestic anti-radiation 256Kbit PROM module, the first interface adopts a CAN A/B bus, the control unit FPGA module adopts a domestic anti-radiation antifuse FPGA module, and the control unit Norflash module adopts a domestic anti-radiation 2Gbit Norflash module.

Further, in one possible implementation manner, after the starting program of the domestic anti-radiation CPU module is read, reading the domestic anti-radiation CPU module application program stored in the domestic anti-radiation 2Gbit Norflash module through a domestic anti-radiation 2Gbit Norflash module interface of the domestic anti-radiation anti-fuse FPGA module; the capacity of the domestic irradiation-resistant 2Gbit Norflash module is determined by the application program capacity of the domestic irradiation-resistant CPU module and the bit file capacity of the computing unit FPGA module in the 2 computing units.

In one possible implementation manner, the type of the computing unit FPGA module selected by the computing unit performance requirement is a domestic 6900 ten thousand gate FPGA module, and the number is selected and configured to be 1 according to the capacity of the domestic irradiation-resistant 2Gbit Norflash module and the program capacity of the domestic 6900 ten thousand gate FPGA module.

Optionally, in one possible implementation manner, the computing unit QSPI Flash module in the computing storage module is configured to have 1 512Mbit QSPI Flash, the computing unit NorFlash module is configured to have 12 Gbit NorFlash, and the computing unit NANDFlash module is configured to have 1 256Gbit NANDFlash.

The first control interface is a CAN A/B bus.

The second control interface is a domestic irradiation-resistant 2Gbit NorFlash interface and an RS485A/B bus;

the third control interface comprises an RS485A/B bus and a slave select MAP interface, wherein the RS485A/B bus is in bus interconnection, and the slave select MAP interface is respectively interconnected with related signal lines of a domestic anti-radiation antifuse FPGA module and a domestic anti-radiation 2Gbit Norflash module in 6900 ten thousand gate FPGA modules produced in China in a computing unit 1 and a computing unit 2.

According to a loading starting method realized by a high-reliability loading starting system in a satellite-borne software definition function, the method comprises the following steps:

the system comprises a domestic anti-radiation CPU module, a domestic anti-radiation anti-fuse FPGA module, a domestic anti-radiation 2Gbit Norflash interface and a domestic anti-radiation CPU module, wherein a starting program stored in the domestic anti-radiation 256 KBT PROM module and an application program stored in the domestic anti-radiation 2Gbit Norflash module are sequentially read and loaded after the domestic anti-radiation CPU module is powered on, an input signal is received through a CAN A/B bus after the starting is finished, a remote control telemetry signal is generated after the remote control telemetry signal is processed according to the internal preset remote control telemetry requirement of the internal remote control telemetry signal, the remote control telemetry signal is sent to the domestic anti-radiation anti-fuse FPGA module through the RS485A/B bus, and the interconnection of the interfaces of the domestic anti-radiation CPU module is finished through the domestic anti-radiation 2Gbit Norflash interface;

the domestic anti-radiation anti-fuse FPGA module automatically operates after power-on, processes a remote control telemetry signal sent by the domestic anti-radiation CPU module according to the preset remote control telemetry requirement in the domestic anti-radiation anti-fuse FPGA module, generates a remote control telemetry signal, sends the remote control telemetry signal to the computing unit FPGA module of the computing unit through an RS485A/B bus, and completes interface interconnection of 2 domestic 6900 ten-thousand-gate FPGA modules and the domestic anti-radiation 2Gbit Norflash module through a slave select MAP interface;

the system comprises a domestic 6900 ten-thousand-gate FPGA module, a digital control module and a digital control module, wherein after a bit file stored in the domestic irradiation-resistant 2Gbit Norflash module is powered on and read, interface control and logic calculation functions based on the domestic 6900 ten-thousand-gate FPGA module are completed, remote control and telemetry signals sent by the domestic irradiation-resistant anti-fuse FPGA module are received through a receiving RS485A/B bus, and after being processed according to the preset remote control and telemetry requirements in the domestic irradiation-resistant anti-fuse FPGA module, various frame format signals are generated and are respectively sent to a calculation control module through corresponding interfaces;

the 8-core CPU module in the computing control module is provided with a QSPI Flash interface and a NorFlash interface, and can select and read CPU programs in appointed positions in 512Mbit QSPI Flash or 2Gbit NorFlash according to appointments; the 8-core DSP module is provided with a Norflash interface and reads a DSP program of an appointed position in the 2Gbit Norflash according to the appointed; the 12TOPS AI module is provided with an NANDflash interface, and reads AI programs of appointed positions in 256Gbit NANDflash according to the appointed.

FIG. 3 is a functional block diagram of a domestic anti-fuse FPGA program in a control unit of the present invention, wherein CAN A/B management functions mainly complete the functions of data receiving, processing, transmitting, etc. on a CAN A/B bus; the RS485A/B management function mainly completes the functions of data receiving, processing, transmitting and the like on an RS485A/B bus; the slave selecting MAP management function is mainly used for completing the communication function of related signals on a slave selecting MAP interface and is used for completing and judging the loading state of a domestic 6900 ten thousand gate FPGA module; the domestic 6900 ten thousand-gate FPGA module loading, refreshing and reconstructing functions comprise a loading function and other functions, wherein the loading function realizes high-performance loading configuration management, the loading times, the loading sequence and the like, and the other functions realize functions of correcting and detecting errors and the like in the loading process; the domestic CPU module management function comprises a loading function and other functions, wherein the loading function is mainly the loading control of a Norflash interface of the domestic CPU, the Norflash interface protocol function is realized through FPGA logic, and the other functions realize the functions of error correction, error detection and the like in the loading process.

FIG. 4 is a functional block diagram of a domestic 6900 ten thousand gate FPGA program in a computing unit, wherein the RS485A/B management function mainly completes the functions of data receiving, processing, transmitting and the like on an RS485A/B bus; the memory management function is used for realizing interface protocol realization with QSPI Flash and NorFlash, NANDFlash devices; the CPU/DSP/AI management function is used for realizing interface protocol realization with CPU, DSP, AI devices, etc.; the 8-core CPU module management function comprises a loading function and other functions, wherein the loading function realizes a QSPI Flash interface, a Norflash interface protocol and the like of the 8-core CPU; other functions realize functions such as error correction and detection in the loading process; the 8-core DSP module management function comprises a loading function and other functions, wherein the loading function realizes an EMIF interface protocol of the 8-core DSP and the like; other functions realize functions such as error correction and detection in the loading process; the 12TOPS AI module management function comprises a loading function and other functions, wherein the loading function realizes NANDflash interface protocol of AI and the like; other functions realize functions such as error correction and detection in the loading process.

The invention can release the tight coupling relation between the satellite application software and the specific satellite hardware, and can ensure that the corresponding core device has high reliable loading, thereby being beneficial to reducing the development cost, shortening the development period, improving the application efficiency, developing the on-orbit test, facing the future requirement and expanding the number of users.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

What is not described in detail in the present specification is a well known technology to those skilled in the art.

Claims (10)

1. The high-reliability loading starting system in the satellite-borne software definition function is characterized by comprising a control unit and a calculation unit;

the control unit comprises a control unit CPU module, a control unit PROM module, a control unit FPGA module and a control unit Norflash module; the control unit PROM module is used for storing a starting program of the control unit CPU module; the control unit Norflash module is used for storing an application program of the control unit CPU module and a bit file of the calculation unit; the control unit CPU module is powered on, sequentially reads and loads a starting program stored in the control unit PROM module and an application program stored in the control unit Norflash module, receives an input signal through the first control interface after starting, generates a first remote control telemetry signal after processing according to the preset remote control telemetry requirement in the control unit CPU module, and sends the first remote control telemetry signal to the control unit FPGA module through the second control interface signal; the control unit FPGA module processes the first remote control telemetry signal according to the preset remote control telemetry requirement in the control unit FPGA module, generates a second remote control telemetry signal and sends the second remote control telemetry signal to the calculation unit through the third control interface;

the computing unit comprises a computing unit FPGA module, a computing control module and a computing storage module; the calculation storage module is used for storing a calculation program of the calculation control module; the computing unit FPGA module is used for reading bit files stored in the Norflash module of the control unit after power-on for interface control and logic calculation, receiving a second remote control and telemetry signal sent by the FPGA module of the control unit by receiving a third control interface, generating various frame format signals after processing according to the preset remote control and telemetry requirements in the computing unit FPGA module, and respectively sending the frame format signals to the computing control module through corresponding interfaces; the calculation control module carries out corresponding processing on the input frame format signal by loading the program stored in the calculation storage module.

2. The system of claim 1, wherein the number of computing units is configured according to system power requirements; the computing control module comprises a computing unit CPU module, a computing unit DSP module and a computing unit AI module, which are respectively used for executing control tasks, computing tasks and AI computing tasks according to input signals;

the number and types of the CPU module, the DSP module and the AI module are selected and configured according to the performance requirement of the computing unit.

3. The system of claim 1, wherein the control unit CPU module is configured to interface with the first control interface and the control unit PROM module.

4. The system according to claim 1, wherein after the start-up procedure of the control unit CPU module is read, the CPU application program stored in the control unit NorFlash module is read through the control unit NorFlash module interface of the control unit FPGA module; the capacity of the control unit Norflash module is determined by the application program capacity of the control unit CPU module and the bit file capacity of the calculation unit FPGA module in the calculation unit.

5. The system for starting up the highly reliable loading in the satellite-borne software definition function according to claim 1, wherein the type of the calculation unit FPGA modules is selected according to the performance requirements of the calculation unit, and the number of the calculation unit FPGA modules is selectively configured according to the capacity of the control unit NorFlash module and the program capacity of the calculation unit FPGA modules.

6. The high reliability loading initiation system in a satellite-borne software defined function of claim 1, wherein: the calculation storage module is configured according to loading interfaces of a calculation unit CPU module, a calculation unit DSP module and a calculation unit AI module, and comprises: selecting and configuring a computing unit QSPI Flash module when a QSPI interface exists, selecting and configuring a computing unit Norflash module when a Norflash interface exists, and selecting and configuring a computing unit NANDflash module when a NANDflash interface exists.

7. The high reliability loading initiation system in a satellite-borne software defined function of claim 1, wherein: the first control interface comprises a CAN bus, a 1553B bus, a SpaceWire bus, an RS422 interface and the like, and is selectively configured according to satellite bus requirements.

8. The high reliability loading initiation system in a satellite-borne software defined function of claim 1, wherein: the second control interface comprises an RS422 bus, an RS485 bus, a control unit Norflash module interface and the like, and is selectively configured according to the control unit CPU module.

9. The high reliability loading initiation system in a satellite-borne software defined function of claim 1, wherein: the third control interface comprises an RS422 bus, an RS485 bus, an LVDS interface and the like, and is selectively configured according to the interconnection requirements of the control unit and the computing unit.

10. A method for loading and starting up a highly reliable loading and starting up system implementation in a satellite borne software defined function according to any of claims 1-9, comprising:

the control unit CPU module is powered on, sequentially reads and loads a starting program stored in the control unit PROM module and an application program stored in the control unit Norflash module, receives an input signal through the first control interface after starting, generates a remote control telemetry signal after processing according to the preset remote control telemetry requirement in the control unit CPU module, and sends the remote control telemetry signal to the control unit FPGA module through the second control interface signal;

the control unit FPGA module automatically operates after power-on, processes the remote control telemetry signal sent by the control unit CPU module according to the preset remote control telemetry requirement in the control unit FPGA module, generates the remote control telemetry signal and sends the remote control telemetry signal to the calculation unit FPGA module of the calculation unit through a third control interface;

the computing unit FPGA module is used for completing interface control and logic computation functions after the bit file stored in the control unit Norflash module is powered on and read, receiving a remote control telemetry signal sent by the control unit FPGA module through a third control interface, generating various frame format signals after processing according to the preset remote control telemetry requirement in the computing unit FPGA module, and respectively sending the frame format signals to the computing control module through corresponding interfaces;

the calculation control module carries out corresponding processing on the input frame format signal by loading the program stored in the calculation storage module.