CN117472273A

CN117472273A - Data reading and writing method, device and storage medium

Info

Publication number: CN117472273A
Application number: CN202311180378.XA
Authority: CN
Inventors: 李舒; 李以恒
Original assignee: Hangzhou Alibaba Cloud Feitian Information Technology Co ltd
Current assignee: Hangzhou Alibaba Cloud Feitian Information Technology Co ltd
Priority date: 2023-09-12
Filing date: 2023-09-12
Publication date: 2024-01-30

Abstract

The embodiment of the application provides a data reading and writing method, equipment and a storage medium. When a read instruction for the storage device connected with the host occurs, whether a target write instruction which needs to be associated with the read instruction is existed or not can be judged, so that the condition of additional read after write is timely detected; and such read instructions and write instructions to be executed in association therewith may be scheduled to the same instruction queue in accordance with a specified association format. In this way, the storage device can correctly sense the condition of additional read after writing in a plurality of instruction queues provided by the host side, temporarily suspend the sensed read instructions, and restore the corresponding read instructions after determining that the related write instructions have completed execution. Therefore, in a multi-queue concurrent read-write scene, the association execution relation between the instructions under the condition of additional read after write can still be correctly maintained, so that the latest data can be read from the storage device by the read instruction, the read-write consistency of the data is ensured, and the performance of the storage device is improved.

Description

Data reading and writing method, device and storage medium

Technical Field

The present disclosure relates to the field of storage technologies, and in particular, to a data reading and writing method, device, and storage medium.

Background

Compared with a mechanical Hard Disk (HDD), the Solid-state Drive (SSD) not only saves complex mechanical design and reduces power consumption volume, but also realizes performance improvement such as delay, throughput and the like. Therefore, SSDs have been widely used in various fields of cloud services.

Among them, SSD supporting multiple queues high concurrency read/write can effectively alleviate IO performance bottleneck, and thus is favored by high performance applications (e.g., database, etc.). However, with the increasing write parallelism and read parallelism, when a write operation to an address is not completed, a read operation to the address is often added, and the read operation does not read the latest data, which causes a problem of data inconsistency.

Disclosure of Invention

Aspects of the present application provide a data read/write method, apparatus, and storage medium for improving data consistency in a case of performing multi-queue read/write on a storage device.

The embodiment of the application provides a data reading and writing method, which is applicable to a host end, wherein the host end is connected with storage equipment, and the method comprises the following steps:

judging whether a target write instruction to be executed in association with the read instruction exists or not under the condition that the read instruction aiming at the storage equipment is monitored;

If the read instruction and the target write instruction exist, scheduling the read instruction and the target write instruction into a target queue according to a specified association format, wherein the target queue is any one of a plurality of instruction queues used for transmitting the read/write instruction to the storage equipment;

and providing the read instruction and the target write instruction to the storage device through the target queue, so that the storage device perceives the write instruction influencing the read instruction based on the association format and executes the read instruction after the corresponding write instruction is completed.

The embodiment of the application also provides a data reading and writing method, which is suitable for a storage device, wherein the storage device is connected to a host end, and the method comprises the following steps:

for any read instruction contained in a plurality of instruction queues provided by the host side, if the read instruction is determined to have a write instruction to be executed in a correlated manner, temporarily suspending the read instruction;

searching target write instructions to be executed in association with the read instructions in the instruction queues according to a specified association format;

and after the completion of the execution of the target write instruction is monitored, restoring the read instruction so that the read instruction reads the data written by the target write instruction.

The embodiment of the application also provides electronic equipment, which comprises a memory, a processor and a communication component;

the memory is used for storing one or more computer instructions;

the processor is coupled to the memory and the communication component for executing the one or more computer instructions for performing the aforementioned data read-write method.

Embodiments also provide a computer-readable storage medium storing computer instructions that, when executed by one or more processors, cause the one or more processors to perform the aforementioned data read-write method.

In the embodiment of the application, when a read instruction for the storage device connected with the host occurs at the host, whether a target write instruction to be executed in association with the read instruction exists or not can be judged, and the condition of additional reading after writing is detected in time; based on this, such read instructions and write instructions to be executed in association with them may be scheduled to the same instruction queue according to a specified association format. In this way, the storage device can correctly sense the condition of additional read after writing in a plurality of instruction queues provided by the host side, temporarily suspend the sensed read instructions, and restore the corresponding read instructions after determining that the related write instructions have completed execution. Accordingly, through the cooperation between the host end and the storage device connected with the host end, in a multi-queue concurrent read-write scene, the association execution relationship between the instructions under the condition of additional read after write can still be correctly maintained, so that the read instruction can read the latest data from the storage device, the data read-write consistency is ensured, and the performance of the storage device is improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

FIG. 1 is a schematic diagram of a conventional method for performing concurrent reading and writing on a solid state disk with multiple queues;

FIG. 2 is a schematic diagram of an address mapping table for supporting data reading and writing;

fig. 3 is a flowchart of a data read-write method at a host side according to an exemplary embodiment of the present application;

FIG. 4 is an exemplary operational logic diagram of a host side in an exemplary embodiment of the present application;

FIG. 5 is a flow diagram of an exemplary implementation of a host side adding specified tags for read instructions and target write instructions;

FIG. 6 is an exemplary flow diagram of an exemplary scheduling scheme;

fig. 7 is a flowchart of a data read-write method on a storage device side according to another exemplary embodiment of the present application;

FIG. 8 is a schematic diagram of the logic of operation in a memory device in an exemplary embodiment of the present application;

FIG. 9a is a flow chart of an exemplary data read-write scheme on the storage device side;

FIG. 9b is a logical schematic of an exemplary data read-write scheme on the storage device side;

fig. 10 is a schematic structural diagram of an electronic device according to another exemplary embodiment of the present application.

Detailed Description

For the purposes, technical solutions and advantages of the present application, the technical solutions of the present application will be clearly and completely described below with reference to specific embodiments of the present application and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

The technical scheme provided by the application is described below with reference to the accompanying drawings.

Fig. 1 is a logic schematic diagram of a conventional solid state disk for performing multiple-queue concurrent reading and writing. As shown in fig. 1, in the process of reading and writing data from and to the solid state disk, the host side may transmit a read/write instruction to the solid state disk in a multi-queue concurrent manner. Referring to fig. 1, a host may place read/write instructions for a solid state disk into a plurality of instruction queues, and the solid state disk sequentially executes instructions in the plurality of instruction queues according to a first-in-first-out order.

With the increasing write parallelism and read parallelism, the probability of address overlap between the read instruction and the write instruction is higher and higher, and according to the conventional processing scheme shown in fig. 1, when the write instruction for a certain access address is not completed yet, if the read instruction for the access address is added, the problem of data inconsistency may occur. Fig. 2 is a schematic diagram of an address mapping table for supporting data reading and writing. The address mapping table may also be referred to as a page table, and is used to translate an access address in a read/write instruction into a physical address to access a corresponding physical storage location. Referring to fig. 2, the address mapping table includes a mapping relationship between an access address (also referred to as a logical address, logical block address, LBA) and a physical address (physical block address, PBA), and when a write instruction is not completed, whether a read instruction added to the same access address can read correct data depends on the execution state of the corresponding write instruction when the read instruction is resolved.

If the write instruction has not reached the solid state disk, then there may be several cases illustrated in fig. 2 when the read instruction is parsed: the access address pointed to by the read instruction is not mapped to a valid physical address in the address mapping table, then the read instruction will read invalid data (e.g., all zeros, etc.); the access address pointed by the read instruction is mapped to a valid physical address in the address mapping table, and the read instruction reads old data. In either case, the read command cannot read correct new data, and the problem of inconsistent data reading and writing occurs. If the write command reaches the solid state disk, the read command still has high probability of failing to read correct new data under the influence of factors such as queue depth, reading time interval and the like.

Therefore, in this embodiment, a data read-write scheme is proposed, which is used to ensure that the read command can read the data written by the write command when additional read is performed after write. The write-after-append read refers to that the read command for the same access address is appended and generated in a short time after the write command is generated.

The data read-write scheme proposed in this embodiment may be implemented by the host side in conjunction with the storage device connected thereto, and the working logic of the host side and the working logic of the storage device will be described below, respectively. Considering that the reading accuracy of the read command is focused in this embodiment, in order to facilitate the explanation of the solution, the technical solution will be explained from the perspective of any read command occurring in the host side in this embodiment.

Fig. 3 is a flowchart of a data read-write method at a host side according to an exemplary embodiment of the present application. Referring to fig. 3, the method may include:

step 300, judging whether a target write instruction to be executed in association with a read instruction exists or not under the condition that the read instruction aiming at the storage device is monitored;

step 301, if so, scheduling a read instruction and a target write instruction into a target queue according to a specified association format, wherein the target queue is any one of a plurality of instruction queues for transmitting the read/write instruction to a storage device;

Step 302, providing a read instruction and a target write instruction to a storage device through a target queue.

It should be noted that, the storage device in this embodiment may be the aforementioned solid state disk, or may be other storage devices capable of supporting concurrent reading and writing of multiple queues and connected to the host, which is not limited in this embodiment. In this embodiment, a Queue Pair (QP) technique may be used in the host to support multiple concurrent read and write queues. Wherein QP is a virtual interface between hardware and software. In the queue structure provided by QP, tasks (WQEs) issued by software to hardware are stored in order, and the WQEs contain information of where to fetch how long data from and to which destination, etc. In this embodiment, the QP queues are used for the instruction queues, and the QP queues carry the read/write instructions to be transferred to the storage device side.

In addition, a storage engine for processing storage transactions may be installed in the host side in this embodiment, and a drive component (e.g., NVMe (Non Volatile Memory Express, nonvolatile storage device) drive component, etc.) corresponding to the storage device to which the storage engine is connected may be included in the storage engine. Based on this, in this embodiment, the storage engine in the host may be modified, so that the host may execute the data read-write method provided in this embodiment.

Referring to fig. 3, in step 300, the host side may monitor a read command for the storage device and determine whether there is a target write command to be executed in association with the read command. Wherein, the need to be executed in association with the read instruction means that the correctness of the read result of the read instruction is affected if the read instruction is not executed in association with the read instruction. In this embodiment, the host side may monitor, in real time, a read instruction initiated by an application program on the host side for the storage device, where the host side may support concurrent reading and writing of a single application program on the storage device, and may support concurrent reading and writing of multiple application programs on the storage device. Thus, in step 300, whenever a new read instruction is detected, it may be determined whether there is a target write instruction to be executed in association with the read instruction. Here, from the write instruction that occurs before the currently monitored read instruction and has not been processed, it is searched whether there is a target write instruction that needs to be executed in association with the read instruction, so it may be determined in step 300 whether the currently monitored read instruction belongs to the case of additional read after write.

FIG. 4 is an exemplary operational logic diagram of a host side in an exemplary embodiment of the present application. Referring to FIG. 4, in an alternative implementation, the host side may record the access address to which the write instruction is directed upon monitoring the write instruction for the storage device, such that a write address record may be formed. In practical applications, the write address record may be maintained by means of a data table or the like. Moreover, the write address record may be updated dynamically, i.e. the access address to which it relates may be recorded in time after the occurrence of a new write instruction is detected, and the access address to which it relates may be deleted in time after the write instruction has been processed. Based on this, in this implementation, the host side may determine, when a read instruction for the storage device is monitored, an access address to which the read instruction is directed; if the access address exists in the write address record, the write instruction to be processed pointing to the access address is determined to be a target write instruction to be executed in association with the read instruction. Thus, based on the dynamically maintained write address record, when the read instruction is monitored, whether a target write instruction needing to be associated with the read instruction is needed or not can be determined through address comparison.

Referring to FIG. 3, if there is a target write instruction to be executed in association with a read instruction, then in step 301, the read instruction and the target write instruction may be dispatched to a target queue according to a specified association format. The target queue may be any one of a plurality of instruction queues. As mentioned above, multiple instruction queues may be employed between the host side and the storage device for transferring read/write instructions. In step 301, a read instruction and its corresponding target write instruction may be written to the same instruction queue in a specified association format.

The specified association format can be used for reflecting the association execution relationship between the read instruction and the corresponding target write instruction. In this embodiment, various association formats may be used to embody the association execution relationship between the read instruction and the corresponding target write instruction.

In an alternative implementation: a designated mark for representing that the instructions needing to be executed in a correlated way exist can be respectively added for the read instruction and the target write instruction; and scheduling the read instruction and the target write instruction into a target queue according to the specified relative position relation.

Illustratively, the designated marker may employ a marker bit. In some implementations, a value, e.g., 1, may be configured for the tag bit that may be used to characterize the presence of an instruction for associated execution. In this case, the flag bit may be added for the relevant read instruction and write instruction, respectively, only in the case where there is a target write instruction to be executed in association with the read instruction, and no flag bit may be added for the read instruction and write instruction that do not need to be executed in association. Of course, in other practical applications, two types of data may be configured for the flag bit, one of which is used to indicate that there is an instruction to be executed in association with the flag bit, and the other of which is used to indicate that there is no instruction to be executed in association with the flag bit. For example, 1 and 0, where 1 is used to characterize that there are instructions to be executed in association and no instructions to be executed in association. In this case, a flag bit may be added for each read instruction and each write instruction, but whether there is an instruction to be executed in association is marked by a different value of the flag bit.

In addition, the designation of the tag may take other forms besides a tag bit, such as adding a special field, etc., and no further examples are presented herein. By adding the specified mark, one type of instructions with the instructions needing to be executed in a correlated manner and the other type of instructions without the instructions needing to be executed in a correlated manner can be effectively distinguished.

FIG. 5 is a flow diagram of an exemplary implementation of a host side adding specified tags for read instructions and target write instructions. Referring to FIG. 5, write instructions to the storage device that occur at the host side may be placed directly into the write queue by a scheduler in the storage engine, while read instructions have to be compared with the pending write instructions for access addresses. If the access addresses are different, scheduling according to independent read-write events; if the access addresses are the same, the specified marks are added to the read instruction and the corresponding target write instruction in the read-write queue respectively.

In this alternative implementation, in addition to adding a specified tag to each of the read instruction and its corresponding target write instruction, the read instruction and the target write instruction may also be scheduled to the target queue in a specified relative positional relationship. As mentioned above, the host transmits the read/write command to the storage device through a plurality of command queues, that is, all the pending read commands and pending write commands monitored by the host need to be scheduled into the command queues. In this alternative implementation, it is specified that the read instruction and its corresponding target write instruction are scheduled for location in the instruction queue. On the one hand, the read instruction and the corresponding target write instruction are required to be located in the same instruction queue, and on the other hand, the read instruction and the corresponding target write instruction also need to meet the specified relative position relationship in the same instruction queue.

The specified relative position relationship can be used for correctly indicating the write instruction which should be associated with the read instruction in the target queue, so that the association execution relationship between the read instruction and the corresponding target write instruction can be correctly transferred to the storage device.

Preferably, the specified relative positional relationship may be: the read command is located at a subsequent location of its corresponding target write command. That is, a read instruction is adjacent to and subsequent to its corresponding target write instruction in the target queue. It should be understood that the relative positional relationship is merely exemplary, and the present embodiment is not limited thereto, and for example, the read command and the corresponding target write command may be placed at a predetermined number of placement positions apart from each other, or the like. More specific examples are not presented here.

To ensure that read instructions and their corresponding target write instructions can be dispatched to the target queue according to a specified relative positional relationship, in one exemplary dispatch scheme: the scheduling time of the read command with the additional read condition after writing can be adjusted on the premise of not interfering the scheduling process of the write command.

In this exemplary scheduling scheme: the target write instruction may be dispatched to the target queue when the target write instruction reaches an exit of the write queue; determining a target placement position for a read instruction in a target queue according to the relative position relation; and scheduling the read instruction to a target placement position in the target queue. The write queue is used for placing the write instruction to be processed in the host end, and the write instruction to be processed contained in the write queue is scheduled to a plurality of instruction queues according to the first-in first-out sequence.

Fig. 6 is an exemplary flow diagram of the exemplary scheduling scheme. Referring to fig. 6, in this exemplary scheduling scheme: the host side can respectively fetch instructions from the read queue and the write queue for processing and check the flag bit of the current instruction. If the flag bit is not 1, scheduling and distributing to a QP (queue pair) queue; if the flag bit is 1, dividing into read/write instructions; if the read command is the read command, the read command is put into a read command temporary storage queue of a host end and is treated together when the subsequent associated write command is scheduled; if the read instruction is a write instruction, checking whether the associated read instruction of the same LBA is in the read instruction temporary storage queue. If the read instruction is temporarily stored in the queue, the associated write instruction and the read instruction are fetched and put into the same QP queue according to the sequence of writing before reading. If the associated read instruction is not found in the read instruction temporary storage queue, the associated read instruction is found in the current read queue, and after the associated read instruction is found, the associated read instruction and the associated write instruction are placed in a QP queue according to the read-before-write sequence. If the system error cannot be found in the read queue, the system error can be reported, and the current processing flow is exited.

In practical application, after the host side monitors a new write instruction, the write instruction can be placed into a write queue for queuing, and the write instruction to be processed reaching the outlet of the queue is scheduled to a plurality of instruction queues. It should be noted that, for the aforementioned target write instruction, a specific flag is added during the period of the write queue, and based on this exemplary scheduling scheme, the host side may sense whether there is an instruction to be executed in association with the pending write instruction currently reaching the queue exit by identifying the specific flag. Naturally, when the target write instruction arrives at the queue exit, it can be identified that there is an instruction to be executed in association, and the scheduling of the related read instruction can be additionally triggered for the target write instruction; for other pending write instructions without instructions to be executed in association, the scheduling of the related read instructions is not additionally triggered, and only conventional write instruction scheduling is completed.

Here, there is a possibility that: the read instruction has reached a scheduling opportunity before its corresponding target write instruction reaches the write queue exit. In this case, read instructions may be scheduled prematurely into the multiple instruction queues without satisfying the specified relative positional relationship. In this regard, referring to fig. 4, in a modification, a read queue and a read instruction scratch queue are also provided in the host side. The method comprises the steps that a to-be-processed read instruction contained in a read queue is scheduled to a plurality of instruction queues according to a first-in first-out sequence; and the read command contained in the read command temporary storage queue needs to be scheduled after waiting for triggering. Based on this, in this modification: and if the read instruction reaches the outlet of the read queue before the target write instruction reaches the outlet of the write queue, scheduling the read instruction into the read instruction temporary storage queue. In this way, if the read instruction is inquired from the read instruction temporary storage queue, the dispatch of the read instruction is triggered so as to dispatch the read instruction to the target placement position in the target queue; if the read instruction is not queried from the read instruction temporary storage queue, the read instruction is extracted from the read queue and is scheduled to a target placement position in the target queue.

That is, in the improvement scheme, the write instruction to be processed can be scheduled in sequence based on the write queue, so that whether the read instruction reaching the exit of the read queue is the read instruction with the condition of additional read after write can be accurately identified through the specified identifier, if so, the read instruction can be scheduled to the read instruction temporary storage queue first, and the corresponding target write instruction is scheduled to the target queue together with the target write instruction after reaching the exit of the write queue; if not, the read instruction can be directly dispatched to a plurality of instruction queues without first dispatching to the read instruction temporary storage queue.

Therefore, the scheduling time of the read instruction with the additional read condition after writing can be effectively adjusted through the read instruction temporary storage queue, and the read instruction can be ensured to be scheduled to the target queue together with the corresponding target write instruction, so that the association execution relationship between the read instruction and the corresponding target write instruction is ensured to be correctly transferred to the storage device.

In connection with fig. 4, an exemplary application scenario is provided below, and data read-write logic of a host side is illustrated in the application scenario.

Referring to fig. 4, the host side may place read instructions and write instructions from a plurality of applications in the read queue and the write queue, respectively, in the received order, and perform processing in a first-in-first-out manner. After recording the write LBA (i.e., access address) for each new write instruction for its desired operation, it can be placed in the write queue. For each new read instruction, the read LBA (i.e., access address) of its request may be compared to the LBA to which the respective write instruction in the write queue refers before entering the read queue. If the LBAs are not the same, the read command enters a read queue; conversely, if the same LBA exists, that is, if the write-after-read occurs, the write LBA (lba_wr m in fig. 4) and the read LBA (lba_rdx in fig. 4) are linked and marked in the read queue. The specific mode may be to place a flag bit in each of the corresponding read instruction and write instruction. If there is an association, the flag bit of the read LBA is set to 1. Write instructions in the write queues may be distributed to the various instruction queues according to scheduling rules (e.g., first-in first-out); when a write instruction of an instruction to be executed in association enters an instruction queue, an associated read instruction (namely, the same LBA of operation) is required to be searched in a read instruction cache queue; if the read instruction is not found, the read instruction is sent to the read queue to continue to find the required read instruction. After the required read instruction is found, it can be scheduled to the same instruction queue as the write instruction and placed at the later placement location of the write instruction. When each read instruction in the read queue is scheduled, the exit of the read queue needs to be checked for a flag bit, and if the flag bit is 0, the scheduler can allocate the read instruction into each instruction queue. If the flag bit is 1, indicating that the read instruction at the outlet has a write instruction which needs to be associated and pointed, and the write instruction is still queued in a write queue; at this time, the read instruction may be placed in the read temporary queue until the write instruction associated with the read instruction arrives at the write queue exit and is processed, and then placed in the same instruction queue. In this way, in the application scenario provided in fig. 4, the write instruction and the read instruction that may need to be executed in association can be transferred to the storage device according to the correct associated execution sequence, so as to ensure that both can be executed by the storage device according to the correct execution sequence.

Fig. 7 is a flowchart of a data read-write method on a storage device side according to another exemplary embodiment of the present application.

Referring to fig. 7, the method may include:

step 700, for any one read instruction contained in the multiple instruction queues provided by the host, if it is determined that the read instruction has a write instruction to be executed in association, suspending the read instruction temporarily;

step 701, searching a target write instruction to be executed in association with a read instruction in a plurality of instruction queues according to a specified association format;

step 702, after it is monitored that the execution of the target write instruction is completed, restoring the read instruction, so that the read instruction reads the data written by the target write instruction.

FIG. 8 is a schematic diagram of the working logic in a memory device according to an exemplary embodiment of the present application. Referring to fig. 8, a front-end process that communicates with a storage engine in a host may be executed in the storage device in this embodiment, and based on this, the front-end process may be modified in this embodiment, so that the storage device executes the data read-write method provided in this embodiment. The front-end process can access a plurality of instruction queues provided by the host end and receive read/write instructions from the plurality of instruction queues. The instruction queues are generated by the host according to the data reading and writing method.

In this embodiment, the data read/write logic on the storage device side will be described also from the viewpoint of any one of the read instructions. Referring to fig. 7, in step 700, for any read instruction contained in the plurality of instruction queues provided by the host side, if it is determined that there is a write instruction to be executed in association with the read instruction, the read instruction is temporarily suspended.

As mentioned above, the host side can distinguish between the type of instruction in which the post-write append read condition occurs and the type of instruction in which the post-write append read condition does not occur by adding a specified flag, etc., so that in step 700: whether the read instruction carries a designated mark or not can be detected, and the designated mark is used for representing that the instruction needing to be executed in a correlated way exists; if the read command is carried and points to the same access address, determining that a write command which needs to be associated with the read command for execution exists; the specified mark is added by the read instruction after the host side determines that the write instruction to be executed in association with the read instruction exists. The specific implementation of the specific mark is not repeated here.

Of course, as mentioned above, the implementation of the specified mark used by the host may be varied, so that the storage device and the host agree on the required identification mode. The storage device can recognize whether the current read instruction has a write instruction which needs to be executed in a correlated manner according to the recognition mode agreed with the host side. If so, the read instruction will be temporarily suspended. Here, a temporary suspension is understood as suspending execution, and then waiting for a trigger before resuming execution.

In an alternative implementation, such read instructions may be dispatched from the instruction queue in which they reside to a read staging queue; the read instruction in the read temporary storage queue needs to wait for the trigger condition to be reached and then is executed, and the trigger condition comprises that the write instruction needing to be executed in association with the read instruction is executed. Referring to fig. 8, in this implementation, a read scratch queue is added to the storage device for storing read instructions that need to be suspended temporarily. It should be appreciated that with reference to FIG. 8, for write instructions read from a plurality of instruction queues, the memory device may place the write instructions into the write execution queue and execute in first-in-first-out order as shown in FIG. 8; for read instructions that do not need to be suspended temporarily, they will also be placed in the read execution queue and executed in first-in-first-out order.

Of course, other implementations may be employed in this embodiment to suspend such read instructions temporarily, and no further examples are provided herein.

With continued reference to FIG. 7, in step 701, a target write instruction to be executed in association with a read instruction may be looked up in a plurality of instruction queues according to a specified association format. The storage device can accurately find out a target write instruction to be executed in association with the read instruction from the plurality of instructions according to the agreed association format.

One exemplary scheduling scheme in the accepting host side: the host end adds a specified mark for a read instruction and a target write instruction which need to be executed in a correlated manner respectively; and scheduling the read instruction and the target write instruction into the same instruction queue according to the specified relative position relation. In step 701: the storage device can search a write instruction conforming to the relative position relation in an instruction queue where the read instruction is located according to the specified relative position relation; if the searched write instruction carries the designated mark and points to the same access address as the read instruction, the searched write instruction is determined to be the target write instruction. Through the checking operation, the storage device can accurately find out a target write instruction which needs to be associated for execution for a read instruction from a plurality of instruction queues.

It should be appreciated that during execution of step 701, the read instruction is still in a temporarily suspended state. The storage device can monitor the execution condition of the target write instruction when the target write instruction is found for the read instruction. Referring to FIG. 7, in step 702, after the completion of the execution of the target write instruction is monitored, the read instruction may be resumed such that the read instruction reads the data written by the target write instruction.

In step 702, after the completion of the execution of the target write instruction is monitored, the execution of the corresponding read instruction in the read cache queue may be triggered to recover the read instruction.

In addition, in the process of executing the target writing instruction, the storage device can write target data to be written into the memory of the storage device; and updating the physical address corresponding to the target data into an address pointing to the storage position of the target data in the memory in the address mapping table so as to complete the associated write instruction. Preferably, the storage device may employ a low power memory (low power doubledata rate, LPDDR).

That is, the storage device does not directly write the target data into the final storage location, but writes the target data into the memory first, and because the read-write speed of the memory is generally higher than that of the final storage location of the storage device, the read command can be responded with lower delay through the memory of the storage device in combination with updating the address mapping table, so that the read command can read the data written by the write command executed in association with the read command more quickly.

Here, a memory address conversion table may be further added to the storage device, and a mapping relationship between a memory logical address and a memory physical address is recorded in the memory address conversion table, so that, in the address mapping table, a physical address corresponding to the target data may be updated to a memory logical address corresponding to the target data in the memory of the storage device. In this way, in the process of executing the read instruction, the storage device can map the access address pointed by the read instruction to the memory logical address of the target data in the memory based on the address conversion table, and then convert the memory logical address into the memory physical address based on the memory address conversion table, so that the read instruction can read the required data from the memory physical address.

Further, the storage device may asynchronously write the target data from the memory of the storage device into the flash memory of the storage device; after the target data is written into the flash memory of the storage device, the physical address corresponding to the target data is updated into the physical address of the target data in the flash memory in the address mapping table. That is, the target data may be transferred from the memory to the final storage location in an asynchronous manner, and the address mapping table may be updated to the physical address corresponding to the final storage location for later use.

For example, FIG. 8 is a logical schematic of an exemplary execution of a write instruction at the storage device side. Referring to FIG. 8, during execution of a write instruction by a memory device, data may now be written to the LPDDR data cache (i.e., memory) and then asynchronously written to the NAND flash memory, and the address map updated. After the data is written into the LPDDR, a short LDPPR address conversion table is maintained besides the address mapping table. As shown in fig. 8, the physical address PBA mapped by the entry of the mapping table corresponding to the access address lba=w is a memory logical address in the LPDDR address table, and based on the LPDDR address conversion table, the memory physical address ddrp=b of the LPDDR can be read out to the memory logical address (for example, ddr=w), and correct data can be obtained by reading the LPDDR memory using the memory physical address and returning to the host side. After the SSD background uses the physical address PBA distributed by the address mapping table to successfully write the data into the NAND flash memory, the entry in the address mapping table is updated to the NAND physical address. For data after an asynchronous write is completed, the read instruction may read the NAND physical PBA directly from the address mapping table (e.g., pba=t) and proceed to the NAND physical PBAPBA to retrieve the desired data.

Fig. 9a is a flow chart of an exemplary data read/write scheme on the storage device side, and fig. 9b is a logic diagram of an exemplary data read/write scheme on the storage device side. The foregoing related alternative implementations are presented centrally in fig. 9a and 9 b. Referring to fig. 9a and 9b, after the front end process of the storage device receives the read/write instructions transmitted by the plurality of instruction queues, it may first determine that the read/write instruction is a read or write instruction. If the command is a write command, the command is put into a write execution queue to start writing operation. The write operation includes writing data to the memory of the storage device and updating the address mapping table. At this time, the data is still in the memory of the storage device, so the corresponding access address in the address mapping table will be mapped to the address pointing to the storage location of the data in the memory, i.e. the physical address of the memory. After data is asynchronously written into the flash memory from the memory of the storage device, the address mapping table is continuously updated, and the corresponding access address is mapped to the physical address of the data in the flash memory. The storage device will execute as soon as it receives the write instruction. When a read instruction is received, whether the flag bit is 1 is checked.

If the flag bit of the read instruction is not 1, executing according to the independent read instruction, putting the read instruction into a read execution queue, and executing in a first-in-first-out mode. In execution, the physical address (memory physical address or flash memory physical address) mapped by the access address in the address mapping table is searched, and the data is read to the corresponding physical address. Of course, the storage device may also perform error correction on the read data during this period and perform data verification; after the verification is passed, the data is sent back to the host side to complete the read instruction.

If the flag bit of the read instruction is 1, the read instruction has a write instruction to be executed in association. Checking whether a flag bit of a write instruction before a read instruction is 1 in an instruction queue where the read instruction is located, and whether the read instruction and the read instruction point to the same access address; if yes, determining that the association is correct, putting the read instruction into a read cache queue, and starting to execute the read instruction after the associated write instruction is successfully executed. If the association is wrong, the association error may be reported.

In summary, when a read instruction for the storage device connected to the host occurs, whether a target write instruction to be executed in association with the read instruction exists or not can be judged, and the condition of additional read after write is detected in time; based on this, such read instructions and write instructions to be executed in association with them may be scheduled to the same instruction queue according to a specified association format. In this way, the storage device can correctly sense the condition of additional read after writing in a plurality of instruction queues provided by the host side, temporarily suspend the sensed read instructions, and restore the corresponding read instructions after determining that the related write instructions have completed execution. Accordingly, through the cooperation between the host end and the storage device connected with the host end, in a multi-queue concurrent read-write scene, the association execution relationship between the instructions under the condition of additional read after write can still be correctly maintained, so that the read instruction can read the latest data from the storage device, the data read-write consistency is ensured, and the performance of the storage device is improved.

It should be noted that, in some of the above embodiments and the flows described in the drawings, a plurality of operations appearing in a specific order are included, but it should be clearly understood that the operations may be performed out of the order in which they appear herein or performed in parallel, the sequence numbers of the operations such as 301, 302, etc. are merely used to distinguish between the various operations, and the sequence numbers themselves do not represent any order of execution. In addition, the flows may include more or fewer operations, and the operations may be performed sequentially or in parallel.

Fig. 10 is a schematic structural diagram of an electronic device according to another exemplary embodiment of the present application. As shown in fig. 10, the electronic device may include: memory 10, processor 11, and communication component 12.

In some possible designs, the electronic device provided in fig. 10 is implemented as the host side in the foregoing embodiments. In this case, a storage device may be connected to the host side, and a processor 11 coupled to the memory 10 and the communication component 12 for executing a computer program in the memory 10 for:

In an alternative embodiment, the processor 11 may be specifically configured to, when determining whether there is a target write instruction to be executed in association with the read instruction:

determining an access address pointed by the read instruction;

if the access address exists in the write address record, determining a write instruction to be processed pointing to the access address as the target write instruction;

the write address record contains an access address identified from a write instruction to be processed.

In an alternative embodiment, the processor 11 may be specifically configured to, when scheduling the read instruction and the target write instruction into the target queue according to a specified association format:

Adding a specified mark for representing that the instruction needing to be executed in a correlated way exists for the read instruction and the target write instruction respectively;

and dispatching the read instruction and the target write instruction to the target queue according to the specified relative position relation.

In an alternative embodiment, when the processor 11 schedules the read instruction and the target write instruction into the target queue according to a specified relative positional relationship, the method may specifically be used to:

when the target write instruction reaches the outlet of a write queue, scheduling the target write instruction into the target queue;

determining a target placement position for the read instruction in the target queue according to the relative position relation;

scheduling the read instruction to the target placement position in the target queue;

and the write instructions to be processed contained in the write queues are scheduled to the instruction queues according to the first-in first-out sequence.

In an alternative embodiment, the processor 11 may be further configured to:

if the read instruction reaches the outlet of the read queue before the target write instruction reaches the outlet of the write queue, scheduling the read instruction into a read instruction temporary storage queue, wherein the read instruction contained in the read instruction temporary storage queue needs to be scheduled after waiting for triggering;

Scheduling the read instruction to the target placement location in the target queue includes:

if the read instruction is inquired from the read instruction temporary storage queue, triggering the dispatch of the read instruction so as to dispatch the read instruction to the target placement position in the target queue;

if the read instruction is not queried from the read instruction temporary storage queue, extracting the read instruction from the read queue and scheduling the read instruction to the target placement position in the target queue;

and the read instructions to be processed contained in the read queues are scheduled to the instruction queues according to the first-in first-out sequence.

In an alternative embodiment, the relative positional relationship includes the read instruction being located at a subsequent placement location for its corresponding target write instruction.

In other possible designs, the electronic device in fig. 10 may be implemented as the storage device in the foregoing embodiment, in which case the storage device may be connected to a host side, and the processor 11 is coupled to the memory 10 and the communication component 12, for executing the computer program in the memory 10 for:

In an alternative embodiment, the processor 11 may be specifically configured to, when the read instruction is temporarily suspended:

scheduling the read instruction from the instruction queue in which the read instruction is positioned to a read temporary storage queue;

the read instruction in the read temporary storage queue needs to wait for a trigger condition to be reached and then is executed, wherein the trigger condition comprises that a write instruction needing to be executed in association with the read instruction is executed.

In an alternative embodiment, the processor 11 may be further configured to:

detecting whether the read instruction carries a specified mark or not, wherein the specified mark is used for representing that an instruction needing to be executed in a correlated way exists;

if the read instruction is carried, determining that a write instruction to be executed in association with the read instruction exists;

the specified mark is added by the read instruction after the host side determines that the write instruction needing to be associated with the read instruction for execution exists.

In an alternative embodiment, when the processor 11 searches the plurality of instruction queues for the target write instruction to be executed in association with the read instruction according to the specified association format, the method may be specifically used for:

Searching a write instruction conforming to the relative position relation in an instruction queue where the read instruction is located according to the specified relative position relation;

if the searched write instruction carries the specified mark and points to the same access address as the read instruction, determining the searched write instruction as the target write instruction;

the specified mark is added by the host side to the target write instruction after the host side determines that the target write instruction needs to be associated with the read instruction for execution.

In an alternative embodiment, the processor 11 may be further configured to:

in the execution process of the target writing instruction, writing target data to be written into the memory of the storage device;

updating a physical address corresponding to the target data into an address pointing to a storage position of the target data in the memory in an address mapping table so as to complete the associated write instruction;

in an alternative embodiment, the processor 11 may be further configured to:

asynchronously writing the target data from the memory of the storage device into the flash memory of the storage device;

after the target data is written into the flash memory of the storage device, the physical address corresponding to the target data is updated into the physical address of the target data in the flash memory in the address mapping table.

Further, as shown in fig. 10, the electronic device further includes: power supply assembly 13, and the like. Only some of the components are schematically shown in fig. 10, which does not mean that the electronic device only comprises the components shown in fig. 10.

It should be noted that, for the technical details of the embodiments of the electronic device, reference may be made to the descriptions related to the host side and the storage device in the foregoing method embodiments, which are not repeated herein for the sake of brevity, but should not cause a loss of protection scope of the present application.

Accordingly, the present application further provides a computer readable storage medium storing a computer program, where the computer program is executed to implement the steps executable by the electronic device in the above method embodiments.

The memory of FIG. 10 described above is used to store a computer program and may be configured to store various other data to support operations on a computing platform. Examples of such data include instructions for any application or method operating on a computing platform, contact data, phonebook data, messages, pictures, videos, and the like. The memory may be implemented by any type of volatile or nonvolatile memory device or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.

The communication assembly of fig. 10 is configured to facilitate wired or wireless communication between the device in which the communication assembly is located and other devices. The device where the communication component is located can access a wireless network based on a communication standard, such as a mobile communication network of WiFi,2G, 3G, 4G/LTE, 5G, etc., or a combination thereof. In one exemplary embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component further comprises a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.

The power supply assembly shown in fig. 10 provides power to various components of the device in which the power supply assembly is located. The power components may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for the devices in which the power components are located.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.

Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Disks (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and changes may be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. that fall within the spirit and principles of the present application are intended to be included within the scope of the present application.

Claims

1. A data read-write method, suitable for a host end, the host end being connected with a storage device, the method comprising:

2. The method of claim 1, determining whether there is a target write instruction to be executed in association with the read instruction, comprising:

determining an access address pointed by the read instruction;

3. The method of claim 1, scheduling the read instruction and the target write instruction into a target queue according to a specified association format, comprising:

4. The method of claim 3, scheduling the read instruction and the target write instruction into the target queue according to a specified relative positional relationship, comprising:

5. The method of claim 4, further comprising:

6. A method according to claim 3, said relative positional relationship comprising said read instruction being located at a subsequent placement location for its corresponding target write instruction.

7. A data read-write method, suitable for a storage device, where the storage device is connected to a host, the method comprising:

8. The method of claim 7, the temporarily suspending the read instruction, comprising:

9. The method of claim 7, further comprising:

10. The method of claim 7, looking up in the plurality of instruction queues a target write instruction to be executed in association with the read instruction in a specified association format, comprising:

11. The method of claim 7, further comprising:

and updating a physical address corresponding to the target data into an address pointing to a storage position of the target data in the memory in an address mapping table so as to complete the associated write instruction.

12. The method of claim 11, further comprising:

13. An electronic device comprising a memory, a processor, and a communication component;

the memory is used for storing one or more computer instructions;

the processor is coupled to the memory and the communication component for executing the one or more computer instructions for performing the data read-write method of any of claims 1-12.

14. A computer-readable storage medium storing computer instructions that, when executed by one or more processors, cause the one or more processors to perform the data read-write method of any of claims 1-12.