CN113641614A - Single-channel multi-service parallel processing method and chip based on SPI - Google Patents
Single-channel multi-service parallel processing method and chip based on SPI Download PDFInfo
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- CN113641614A CN113641614A CN202110767579.4A CN202110767579A CN113641614A CN 113641614 A CN113641614 A CN 113641614A CN 202110767579 A CN202110767579 A CN 202110767579A CN 113641614 A CN113641614 A CN 113641614A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Abstract
The invention relates to the technical field of service processing, and provides a single-channel multi-service parallel processing method and a chip based on SPI (Serial peripheral interface). The single-channel multi-service parallel processing method based on the SPI comprises the following steps: caching data acquired from an SPI channel to a first random access memory of the SPI equipment, and transferring the data in the first random access memory to a second random access memory of the SPI equipment by adopting a data receiving thread; processing the data in the second random access memory by adopting a service processing thread, and storing a processing result into the second random access memory; transferring a processing result in the second random access memory to the first random access memory by adopting a data sending thread; the data receiving thread, the service processing thread and the data sending thread are in a parallel relation. The embodiment provided by the invention improves the response speed and the processing efficiency of the system of the SPI interface to the data received from the SPI interface.
Description
Technical Field
The invention relates to the technical field of service processing, in particular to a single-channel multi-service parallel processing method based on SPI and a chip adopting an SPI interface.
Background
The SPI interface chip can meet the requirements of service fusion gradually by continuously improving the memory capacity, the CPU processing capacity, the process level and the like. In the existing scheme, according to different services, the SPI chip sets different instruction lists, does not limit the contents of the instruction lists, allows a plurality of lists to use the same instruction, and sequentially executes the instructions in the lists according to the received sequence.
Fig. 1 schematically shows a multi-service processing flow diagram of an SPI chip according to the prior art. As shown in fig. 1, communication is easily blocked in the current SPI chip because the communication mode is a serial mode, and the instruction processing efficiency is low because the chip core uses a single-task operating system. Even if a multitask operating system is used in a chip to process instructions in parallel, the processing efficiency of the whole chip cannot be improved due to communication blockage.
Disclosure of Invention
The embodiment of the invention aims to provide a single-channel multi-service parallel processing method based on SPI and a chip adopting the method, so as to provide a communication mode adaptive to a multitask operating system, avoid the problem of instruction blocking, improve the efficiency of the whole chip and make quick response to emergency processing instructions.
In order to achieve the above object, a first aspect of the present invention provides a single-channel multi-service parallel processing method based on SPI, where the processing method includes: buffering data acquired from an SPI channel to a first random access memory of the SPI device, wherein the processing method further comprises the following steps:
adopting a data receiving thread to transfer the data in the first random access memory to a second random access memory of the SPI equipment; the second random access memory comprises a plurality of service lists, and the data transferred from the first random access memory are distributed to the corresponding service lists in the second random access memory according to services;
processing the data in the second random access memory by adopting a service processing thread, and storing a processing result into the second random access memory;
transferring a processing result in the second random access memory to the first random access memory by adopting a data sending thread;
the data receiving thread, the service processing thread and the data sending thread are in a parallel relation.
Preferably, processing the data in the second random access memory by using a service processing thread includes: and the service processing thread processes the data in the service list according to the priority.
Preferably, the buffering data obtained from the SPI channel to the first random access memory of the SPI device includes: the acquired data is cached into a first random access memory of the SPI equipment in a first-in first-out mode.
Preferably, after buffering data acquired from the SPI channel to the first random access memory of the SPI device, the processing method further includes: determining the acquired data as an emergency instruction; and then the emergency instruction is not stored in the second random access memory any more, an emergency instruction processing function is called to process the emergency instruction, and a processing result is stored in the first random access memory.
Preferably, the processing result in the first random access memory is sent through the SPI channel in a first-in first-out manner.
Preferably, the data acquired from the SPI channel includes instructions; the instruction is used in cooperation with a corresponding query instruction.
Preferably, the instruction and the corresponding query instruction both adopt a preset format.
Preferably, the trigger mode for acquiring data from the SPI channel of the SPI device is hardware trigger.
Preferably, after acquiring data from the SPI channel of the SPI device, the processing method further includes: and carrying out data verification on the acquired data.
Preferably, the data transmission between the first random access memory and the second random access memory adopts system direct memory access.
Preferably, the data transmission between the first random access memory and the first-in first-out storage position adopts SPI direct memory access.
Preferably, the first random access memory is an SPI random access memory, and the second random access memory is a user random access memory.
In a second aspect of the present invention, a chip using an SPI interface is further provided, where the chip includes an RAM, and the chip uses the above single-channel multi-service parallel processing method based on SPI.
A third aspect of the present invention provides a computer-readable storage medium, which stores instructions that, when executed on a computer, cause the computer to execute the aforementioned SPI-based single-channel multi-service parallel processing method.
A fourth aspect of the present invention provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the computer program implements the SPI-based single-channel multi-service parallel processing method.
The technical scheme has the following beneficial effects:
(1) by adopting different threads for processing, the receiving and sending processes of the application layer and the processing process of the service instruction can be simultaneously carried out, and the working efficiency of the whole system is improved.
(2) By setting the storage modes of different random access memories, the sending process is not influenced by the instruction receiving sequence, and the executed faster instruction can be sent in advance, so that instruction blocking is effectively reduced, and the sending efficiency is improved.
(3) Through service differentiation, processing of a plurality of services received from the same SPI channel is processed in a multi-task system in a thread mode in parallel, and for the services which are time-consuming (such as an algorithm, Flash write operation and the like), simultaneous operation of processing of the plurality of services is realized, and the processing efficiency of the services is improved.
(4) The instructions needing urgent processing can be quickly responded by respectively processing the judgment of the urgency of the instructions, and the waiting time of the instructions is reduced.
As used herein, terms are used in their conventionally understood sense in the art, including:
SPI, Serial Peripheral Interface;
RAM, Random Access Memory;
FIFO, First Input First Output, First in First out;
DMA, Direct Memory Access.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 schematically illustrates a multi-service processing flow diagram of an SPI chip according to the prior art;
fig. 2 is a schematic diagram illustrating an implementation of a single-channel multi-service parallel processing method for SPI according to an embodiment of the present invention;
FIG. 3 schematically illustrates a thread design diagram according to an embodiment of the invention;
FIG. 4 is a schematic diagram illustrating the structures of an SPI RAM and a user RAM according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating a process flow of SPI transaction processing according to an embodiment of the present invention;
fig. 6 is a schematic diagram illustrating steps of an SPI-based single-channel multi-service parallel processing method according to an embodiment of the present invention;
FIG. 7 is a schematic representation of a downstream measured data waveform according to an embodiment of the present invention;
fig. 8 schematically shows a waveform diagram of measured data upstream according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
Fig. 2 schematically shows an implementation diagram of a single-channel multi-service parallel processing method of SPI according to an embodiment of the present invention. As shown in fig. 2, the present embodiment provides a single-channel multi-service parallel processing method based on SPI, where the processing method includes:
caching data acquired from an SPI channel to a first random access memory of the SPI equipment, and transferring the data in the first random access memory to a second random access memory of the SPI equipment by adopting a data receiving thread; the second random access memory comprises a plurality of service lists, and the data transferred from the first random access memory are distributed to the corresponding service lists in the second random access memory according to services; processing the data in the second random access memory by adopting a service processing thread, and storing a processing result into the second random access memory; transferring a processing result in the second random access memory to the first random access memory by adopting a data sending thread; the data receiving thread, the service processing thread and the data sending thread are in a parallel relation.
And the data receiving party receives data through an SPI channel provided by an external SPI pin of the SPI equipment. The first random access memory is configured to buffer the received data, and has a data read-write path and a preset data read-write relationship with other random access memories in the device. The first random access memory in the present embodiment is preferably an SPI random access memory (hereinafter also simply referred to as an SPI RAM or an SRAM). The second random access memory in the present embodiment is preferably a USER random access memory (hereinafter also simply referred to as USER RAM or URAM). The second random access memory differs from the first random access memory in that the second random access memory comprises a number of service lists by which data is stored by means of services. Meanwhile, the embodiment is provided with three parallel processing threads which are a data receiving thread, a service processing thread and a data sending thread. Although the three threads are described sequentially and temporally related to the processing of the same data, the parallel actions of the three threads on different data processing are not limited by the sequential description.
By the implementation mode, a processing mode of data according to the receiving sequence is avoided, and parallel processing of the data by a plurality of parallel service processes can be realized, so that parallel processing of a plurality of services is realized.
FIG. 3 schematically shows a thread design according to an embodiment of the invention. As shown in fig. 3, the data is described as an SPI service command. The SPI service command is read from the SPI FIFO queue to the SPI RAM, and then the process of the SPI service command to the user RAM is processed by the data reading thread; the response result of the SPI service instruction is read from the user RAM to the SPI RAM, and the process of the response result to the SPI FIFO queue is processed by a data sending thread; the data reading thread and the data sending thread are in parallel relation. The data receiving thread and the data sending thread in fig. 3 do not perform actual transceiving work, but refer to two data unloading processes from the SPI RAM to the USER RAM, and from the USER RAM to the SPI RAM. The receiving operation of the data receiving thread comprises the following steps: (1) fetching data in a protocol channel (SPI RAM); (2) and copying the service to a cache USER RAM area to which the application belongs according to the service, and informing the application corresponding to the service. The sending operation of the data sending thread comprises the following steps: and putting the application execution result into a USER RAM, wherein an area in the USER RAM can be configured to correspond to the application, a semaphore and a mutex are juxtaposed (judgment is made when the protocol layer sends data), and the data of the USER RAM is transferred to the SPI RAM. Only the case with two traffic handling threads is shown in fig. 3, the actual number of traffic handling threads corresponding to the aforementioned traffic. The above threads are in parallel relationship. And a plurality of parallel threads are adopted in the same operating system to process the data unloading process, so that the processing efficiency can be improved. The two unloading processes in the above embodiment are designed as two threads of a multitasking operating system, which are the aforementioned data receiving thread and data sending thread.
Fig. 4 schematically shows the structural diagrams of the SPI ram and the user ram according to the embodiment of the present invention, as shown in fig. 4. In both SPI RAM and USERRAM, buffering for SPI service command and SPI service command response is provided, but the difference of USERRAM is that SPI service command is stored in service list, where only the case of 3 service lists is shown, the number of them is only schematic and does not constitute a practical limitation.
Through the implementation mode, single-channel multi-service parallel processing of the SPI is achieved. The embodiment adopts a different cache scheme than that in the prior art, and achieves the technical effect of multi-service parallel processing by setting different functions of the first random access memory and the second random access memory to be matched with each other.
In an optional implementation manner provided by the present invention, processing the data in the second random access memory by using a service processing thread includes: and the service processing thread processes the data in the service list according to the priority. The priority is adopted to determine the processing sequence of the data in the second random access memory, and therefore the importance degree of the data in different service lists is distinguished, and the response to the distinguishing degree of different service is achieved.
In an optional embodiment of the present invention, the obtained data is buffered in a first-in first-out manner to a first random access memory of the SPI device. In this embodiment, the acquired data is stored in the SPI FIFO queue first, and the data in the first random access memory is from the SPI FIFO queue. In the embodiment, the buffer queue is added to the first random access memory in a first-in first-out mode, so that data can be better buffered.
In the application of the SPI device, some emergency instructions are often required to respond immediately, such as serious faults and the like, and alarm information needs to be given at the first time. However, the communication mode of the existing scheme has the problem of instruction blocking, so that the emergency instruction cannot be immediately executed and response is given. In an embodiment provided by the present invention, the processing method further includes: and calling an emergency instruction processing function if the acquired data is determined to be an emergency instruction, and storing a processing result into a sending area of the second random access memory. The embodiment can judge whether the data is an emergency instruction or not, thereby further shunting. For instructions requiring urgent processing, the separate design in a multitasking operating system is a higher priority thread. After receiving the instruction, whether the instruction is an emergency instruction needs to be identified, if the instruction is the emergency instruction, the processing function is directly called to process, and instruction data does not need to be transferred to a service list of the USER RAM. Namely, the identification work of the emergency command is carried out in the SPIRAM, the processing function is called after the identification, the result is sent back to the FIFO, and the unloading process from the SRAM to the URAM is not carried out. Through the implementation mode, the command needing emergency processing can be quickly responded, the command does not need to be processed after the previous command is processed, and the response speed is improved.
In an optional implementation manner provided by the present invention, the processing method further includes: determining that a second random access memory in the random access memories has a processing result to be sent; and after the processing result is transferred to the first random access memory, the processing result is sent through the SPI channel. The embodiment discloses a step of passing data in the second random access memory through the SPI channel, thereby realizing bidirectional transmission of data on the basis of the aforementioned embodiment.
In an optional embodiment of the present invention, the processing result in the first random access memory is sent through the SPI channel in a first-in first-out manner. The first random access memory and the SPI channel are provided with buffer queues so as to realize the buffer of processing results.
In an optional implementation provided by the present invention, the data obtained from the SPI channel includes an instruction; the instruction is used in cooperation with a corresponding query instruction. The instructions and corresponding query instructions appear as command pairs. The corresponding query instruction is configured to: and returning the writing result, the service status word and the service data of the SPI service instruction. Because the lower computer is limited by the space of the RAM, the upper computer needs to acquire the instruction receiving condition of the lower computer in time and extract the service data. The upper computer instruction preferably consists of a command (inquiry) command pair. The lower computer can store a plurality of service instructions and then process the service instructions. The SPI driver of the lower computer is not responsible for distinguishing the service numbers, is only responsible for receiving data to a specified cache region of the service layer, returns instruction status words according to the pointer content of the cache region (for example, the instruction is normally received, the instruction buffer region is full, and the like), and returns the service status words and the service data according to the query instruction. In the embodiment, the writing-in of the SPI business instruction is realized by the command, and the integrity and the correctness of the writing-in process of the SPI business instruction can be ensured.
In an optional implementation manner provided by the present invention, the instruction and the corresponding query instruction adopt a preset format. For example: the following bytes are first defined: 9F 55: valid instruction identification Bytes, 2 Bytes; LenH LenL: packet length (unit: Byte); PACKET 1: a service instruction packet (upper computer downlink); PACKET 2: a service instruction receives a state packet (the lower computer is uplink); PACKET 3: and (4) service response data packet (lower computer uplink). Correspondingly, the command format is: and (4) service instructions: 9F55 LenH LenL PACKET 1; return instruction status word: 9F55 LenH LenL PACKET 2; and (3) query instructions: 9F 55000351 CC LRC (where 51CC is a fixed query); service status words and data: 9F55 LenH LenL PACKET 3.
In an optional embodiment provided by the present invention, a trigger mode for acquiring data from an SPI channel of an SPI device is a hardware trigger. Specifically, the SPI data reception is triggered to start to be interrupted when the SSN chip selection of the SPI device is from high to low, and the SPI data reception is triggered to end to be interrupted when the SSN chip selection is from low to high. The communication Mode in this embodiment is implemented by using SPI Mode3 and a half-duplex Mode (i.e., the transmission and reception communication is completed in the process of one chip select high, low, and high). After the instruction of the upper computer is sent out, the chip selection needs to be kept low continuously, clk is given out until the identification heads (2Bytes) + Len (2Bytes) returned by the lower computer are obtained, and then according to Len, the corresponding number of clk is given out, and the returned data are obtained.
In an optional implementation, the processing method further includes: and carrying out data verification on the acquired data. Its checking step of the acquired data may be implemented by different logical layers of the SPI device (e.g., driver layer and service layer, etc.). For example: the driver layer determines the LRC (longitudinal redundancy check) of the received data and returns an instruction status word to the application layer. The application layer needs to calculate the LRC (exclusive or negation value) value of the application return data, takes the LRC as the last byte effective data, and counts the length value, and returns the last byte effective data to the driving layer for uplink. The data transmission correctness can be quickly judged by setting the data check.
Fig. 5 schematically shows a process flow diagram of SPI service processing according to an embodiment of the present invention. As shown in fig. 5, in the present embodiment, the data transmission between the first random access memory and the second random access memory is a system direct memory access, and the data transmission between the first random access memory and the first-in first-out data queue is an SPI direct memory access. Specifically, when the upper computer issues data and the lower computer starts to receive the data, the data is transferred from the SPI FIFO to the SPI RAM by using the DMA _ SPI, and then is transferred from the SPI RAM to the designated USER RAM area by using the DMA _ SYS mode. When the lower computer uploads data, the DMA _ SYS is used for transferring to the SPI RAM, and then the DMA _ SPI is used for moving to the SPI FIFO to upload the data. Through the embodiment, the efficiency of data unloading can be improved.
As mentioned above, the first ram is an SPI ram, and the second ram is a user ram. Those skilled in the art do not limit the functions implemented by the first random access memory and the second random access memory to the names thereof.
Fig. 6 is a schematic diagram illustrating steps of an SPI-based single-channel multi-service parallel processing method according to an embodiment of the present invention, and as shown in fig. 6, the method includes the following steps:
(1) and the upper computer sends a service instruction.
(2) Judging whether a cache SPI RAM of the lower computer for receiving data has an idle position: if not, the lower computer returns that the receiving is failed; if so, the process continues.
(3) Judging whether the data check byte is correct: if not, the lower computer returns that the receiving is failed; if so, the process continues.
(4) The lower computer drives and judges whether the command is an emergency command: if so, directly calling an emergency instruction processing function, and storing a processing result into the SPI RAM to be sent; if not, the process continues to be executed.
(5) The lower computer stores the instruction into the SPI RAM and returns the success of receiving.
(6) The receiving thread of the application transfers the service instruction in the SPI RAM to different service lists in the USER RAM according to the service; the service processing thread processes the instruction of each service list according to the priority, and the response result is stored in the USER RAM; and the sending thread of the application moves the response data in the USER RAM to the SPI RAM. The above three operations are performed in parallel in a multitasking operating system.
(7) And the upper computer sends a query command.
(8) And the lower computer sends the instruction processing result and the data in the SPI RAM to the upper computer.
Fig. 7 schematically shows a data downstream measured waveform diagram according to an embodiment of the present invention, and fig. 8 schematically shows a data upstream measured waveform diagram according to an embodiment of the present invention. The following two figures show that: the above embodiment that this application provided has promoted the response speed of the data on the SPI interface.
In an embodiment provided by the present invention, a chip using an SPI interface is further provided, where the chip includes an RAM, and the chip uses the above single-channel multi-service parallel processing method based on the SPI. The chip adopting the SPI interface and adopting the single-channel multi-service parallel processing method based on the SPI can realize the parallel processing of multiple services through the set SPI RAM and the user RAM, has the advantage of being capable of making quick response to emergency instructions, and improves the operating efficiency of the whole chip. The specific implementation of the chip using the SPI interface may refer to the definition of the SPI-based single-channel multi-service parallel processing method in the foregoing, and is not described herein again.
In an embodiment of the present invention, there is also provided a computer-readable storage medium having stored therein instructions which, when executed on a computer, cause the processor to be configured to perform the SPI-based single-channel multi-service parallel processing method described above.
In one embodiment provided by the present invention, a computer program product is provided, which includes a computer program, and when the computer program is executed by a processor, the computer program implements the SPI-based single-channel multi-service parallel processing method described above.
Through the implementation mode, multiple service processes can be simultaneously operated under the scene of the SPI single channel, the service processing efficiency is improved, the command needing emergency processing can be quickly responded, and the sending efficiency is improved.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). The memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (14)
1. A single-channel multi-service parallel processing method based on SPI is characterized in that the processing method comprises the following steps:
caching data acquired from the SPI channel to a first random access memory of the SPI equipment;
adopting a data receiving thread to transfer the data in the first random access memory to a second random access memory of the SPI equipment; the second random access memory comprises a plurality of service lists, and the data transferred from the first random access memory are distributed to the corresponding service lists in the second random access memory according to services;
processing the data in the second random access memory by adopting a service processing thread, and storing a processing result into the second random access memory;
transferring a processing result in the second random access memory to the first random access memory by adopting a data sending thread;
the data receiving thread, the service processing thread and the data sending thread are in a parallel relation.
2. The processing method according to claim 1, wherein processing the data in the second random access memory with a business processing thread comprises:
and the service processing thread processes the data in the service list according to the priority.
3. The processing method according to claim 1, wherein buffering data obtained from an SPI channel to a first random access memory of the SPI device comprises:
the acquired data is cached into a first random access memory of the SPI equipment in a first-in first-out mode.
4. The processing method according to claim 1, wherein after buffering data obtained from an SPI channel to a first random access memory of the SPI device, the processing method further comprises:
determining the acquired data as an emergency instruction;
and then the emergency instruction is not stored in the second random access memory any more, an emergency instruction processing function is called to process the emergency instruction, and a processing result is stored in the first random access memory.
5. The processing method according to claim 1, wherein the processing result in the first random access memory is sent through the SPI channel in a first-in first-out manner.
6. The processing method according to claim 1, wherein the data obtained from the SPI channel includes an instruction; the instruction is used in cooperation with a corresponding query instruction.
7. The processing method according to claim 6, wherein the instruction and the corresponding query instruction both adopt a preset format.
8. The processing method according to claim 1, wherein a trigger manner for acquiring data from the SPI channel of the SPI device is hardware trigger.
9. The processing method according to claim 1, wherein after acquiring data from an SPI channel of an SPI device, the processing method further comprises: and carrying out data verification on the acquired data.
10. The processing method of claim 1, wherein data transfer between the first random access memory and the second random access memory employs system direct memory access.
11. The processing method according to claim 1, wherein data transmission between the first random access memory and the first-in first-out data queue adopts SPI direct memory access.
12. The processing method according to any one of claims 1 to 11, characterized in that the first random access memory is an SPI random access memory and the second random access memory is a user random access memory.
13. A chip using an SPI interface, the chip comprising a random access memory, wherein the chip uses the SPI-based single channel multi-service parallel processing method according to any one of claims 1 to 12.
14. A computer-readable storage medium having stored therein instructions that, when executed on a computer, cause the computer to perform the SPI-based single channel multi-service parallel processing method according to any one of claims 1 to 12.
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