CN117461257A

CN117461257A - Power amplifying circuit

Info

Publication number: CN117461257A
Application number: CN202280039260.2A
Authority: CN
Inventors: 本多悠里
Original assignee: Murata Manufacturing Co Ltd
Current assignee: Murata Manufacturing Co Ltd
Priority date: 2021-10-22
Filing date: 2022-10-21
Publication date: 2024-01-26
Also published as: WO2023068360A1

Abstract

A power amplification circuit that operates in a linear mode and a saturation mode, the power amplification circuit comprising: a signal output unit to which a control voltage is input and which outputs an adjustment signal based on the linear mode or the saturation mode; at least one amplifier of the driving stage, which is an amplifier to which the adjustment signal is supplied, to which an RF input signal is input, and which amplifies the input RF input signal; and an amplifier of an output stage to which a power supply voltage is supplied, the amplifier amplifying the amplified RF input signal output from the amplifier of the drive stage and outputting an RF output signal, the signal output unit including: a voltage output unit to which the power supply voltage and the control voltage are supplied and which outputs the adjustment signal; and a switching unit that controls the voltage output unit so that the power supply voltage is output as the adjustment signal in the linear mode, and a voltage substantially proportional to the control voltage is output as the adjustment signal in the saturation mode.

Description

Power amplifying circuit

Technical Field

The present disclosure relates to power amplification circuits.

Background

A power amplifier capable of operating in a linear mode and a saturation mode so as to cope with different modulation standards is known (for example, refer to patent document 1).

Prior art literature

Patent literature

Patent document 1: U.S. patent No. 7605651 specification

Disclosure of Invention

Problems to be solved by the invention

The power amplifier described in patent document 1 controls the collector of the driver amplifier by an LDO (Low Drop Output), and drives the collector of the power amplifier by a power supply voltage that is a power supply different from the LDO. Thus, the power amplifier can prevent degradation of characteristics. The power amplifier detects output power at the time of saturation operation. The power amplifier controls the output of the LDO based on the detected output power and the voltage Vdet. The power amplifier controls the output of the LDO based on the control voltage Vcntl during linear operation.

However, the power amplifier described in patent document 1 has a problem in that a circuit for detecting and feeding back the output power is required, and thus the circuit scale is increased.

Accordingly, an object of the present disclosure is to provide a power amplification circuit configured with a simple circuit and capable of coping with different modulation standards.

Means for solving the problems

A power amplification circuit according to an aspect of the present invention is a power amplification circuit that operates in a linear mode and a saturation mode, the power amplification circuit including: a signal output unit to which a control voltage is input and which outputs an adjustment signal based on the linear mode or the saturation mode; at least one amplifier of the driving stage, which is an amplifier to which the adjustment signal is supplied, to which an RF input signal is input, and which amplifies the input RF input signal; and an amplifier of an output stage to which a power supply voltage is supplied, the amplifier amplifying the amplified RF input signal output from the amplifier of the drive stage and outputting an RF output signal, the signal output unit including: a voltage output unit to which the power supply voltage and the control voltage are supplied and which outputs the adjustment signal; and a switching unit that controls the voltage output unit so that the power supply voltage is output as the adjustment signal in the linear mode, and a voltage substantially proportional to the control voltage is output as the adjustment signal in the saturation mode.

Effects of the invention

According to the present disclosure, a power amplification circuit configured with a simple circuit and capable of coping with different modulation standards can be provided.

Drawings

Fig. 1 is a diagram showing a configuration example of a power amplification circuit.

Fig. 2 is a diagram showing a configuration example of the bias circuit.

Fig. 3 is a diagram showing an example of a relationship between the control voltage Vramp and the voltage of the node 100a in the saturation mode.

Fig. 4 is a diagram showing an example of a relationship between the control voltage Vramp and the current Ic supplied from the bias control circuit in the saturation mode.

Fig. 5 is a diagram showing an example of a relationship between the power supply voltage Vcc and the current Ic supplied from the bias control circuit in the saturation mode.

Fig. 6 is a diagram showing a configuration example of a power amplification circuit according to a modification.

Fig. 7 is a diagram showing an example of a relationship between the control voltage Vramp and the current Ic supplied from the bias control circuit in the saturation mode.

Detailed Description

The power amplifying circuit 100= = = = =

Structure

A communication device such as a mobile phone is provided with a power amplifying circuit that operates in a saturated mode (Gaussian Minimum Shift Keying: GMSK, gaussian minimum shift keying) in which the output power is controlled by the input power, and a linear mode (Enhanced Data rates for GSM Evolution: EDGE, enhanced data rates for GSM evolution) in which the input power is fixed and the output power is controlled. In order to cope with different modulation standards such as GMSK and EDGE, it is desirable that the power amplifier circuit of a communication device such as a mobile phone can operate in either a saturation mode or a linear mode. The power amplifier circuit 100 of the present embodiment is a circuit capable of operating in a saturation mode and a linear mode, respectively. As described later, the power amplifier circuit 100 may be a circuit that operates (can operate) in a saturation mode and a linear mode, respectively, or may not be a circuit that switches between the saturation mode and the linear mode during operation. In other words, the power amplification circuit 100 may be a circuit as follows: in the operation, only either the saturation mode or the linear mode is operated, but the operation is switched between the operation in the saturation mode and the operation in the linear mode by the portable terminal mounted on the portable terminal.

The power amplification circuit 100 is mounted in, for example, a mobile phone, and amplifies power of a signal transmitted to a base station. The power amplification circuit 100 can amplify, for example, the power of signals of different modulation standards such as GSM digital communication standards modulated with an RF carrier using GMSK and EDGE obtained by expanding the GSM digital communication standards. Note that, the standard of the signal amplified by the power amplification circuit 100 is not limited thereto. The power amplifying circuit 100 amplifies an input signal RFin and outputs an output signal RFout. The input signal is a Radio-Frequency (RF) signal, and the Frequency of the input signal is, for example, in the order of several hundred MHz to several GHz.

A configuration example of the power amplifier circuit 100 will be described with reference to fig. 1. Fig. 1 is a diagram showing a configuration example of a power amplification circuit 100. As shown in fig. 1, the power amplification circuit 100 includes, for example, an amplification circuit 110 and a signal output section 120.

The amplifying circuit 110 includes, for example, an amplifier 111, an amplifier 112, an amplifier 113, a bias circuit 114, a bias circuit 115, and a bias circuit 116. As an example, the case where the amplifying circuit 110 includes three stages of amplifiers is described, but the present invention is not limited thereto. For example, the amplifier circuit 110 may include two or more stages of amplifiers.

The amplifier 111 and the amplifier 112 are, for example, amplifiers of a driving stage that amplifies the input signal RFin. The amplifiers 111 and 112 receive the input signal RFin received from the input terminal 110a, amplify the input signal RFin, and output the amplified input signal RFin to the amplifier 113.

The amplifier 113 is, for example, an amplifier that amplifies the input signal RFin amplified by the amplifiers 111 and 112. The amplifier 113 outputs the output signal RFout to the output terminal 110 b.

The bias circuit 114 is a circuit for supplying bias to the amplifier 111. Here, a configuration example of the bias circuit 114 will be described with reference to fig. 2. Fig. 2 is a diagram showing a configuration example of the bias circuit 114. As shown in fig. 2, the bias circuit 114 includes, for example, transistors 114a to 114c, a capacitor 344, and a resistor 341.

Transistors 114a to 114c are heterojunction bipolar transistors (Heterojunction Bipolar Transistor: HBT), but are not limited thereto. For example, the transistors 114a to 114c may be field effect transistors (Field Effect Transistor: FETs). The transistors 114a, 114b are diode connected. The collector of the transistor 114a is connected to the terminal 114f through a resistor 341.

The emitter of transistor 114a is connected to the collector and base of transistor 114 b. The base of transistor 114a is connected to the base of transistor 114 c. The emitter of the transistor 114b is connected to a reference potential. The emitter of transistor 114b may also be connected to the base of transistor 114c through capacitor 114 d.

The terminal 114f is connected to, for example, a bias power supply circuit 124 of the signal output unit 120. Further, a bias current is supplied from the bias power supply circuit 124 to the terminal 114 f. The terminal 114f is connected to the base of the transistor 114c through a resistor 114 e. That is, the transistor 114c of the bias circuit 114 is supplied with the base current from the bias power supply circuit 124 through the terminal 114 f.

The terminal 114g is connected to, for example, the bias control circuit 123 of the signal output unit 120. Terminal 114g is connected to the collector of transistor 114 c. That is, the transistor 114c of the bias circuit 114 is supplied with collector current from the bias control circuit 123 through the terminal 114 g.

The terminal 114h is connected to the amplifier 111, for example. Terminal 114h is connected to the emitter of transistor 114 c. That is, the transistor 114c of the bias circuit 114 supplies a bias current to the amplifier 111 through the terminal 114 h.

That is, the transistor 114c supplies an emitter current obtained based on a bias current supplied to the base and a collector current supplied to the collector to the amplifier 340.

The bias circuit 115 has the same structure as the bias circuit 114, and therefore, a description thereof is omitted. The bias circuit 115 supplies a bias current to the amplifier 112 through a terminal 114h shown in fig. 2.

The bias circuit 116 has the same structure as the bias circuit 114, and therefore, a description thereof is omitted. The bias circuit 116 supplies a bias current to the amplifier 113 through a terminal 114h shown in fig. 2.

The signal output unit 120 outputs a signal (hereinafter referred to as "adjustment signal S") based on the linear mode or the saturation mode to the amplifiers 111 and 112, for example. As shown in fig. 1, the signal output unit 120 includes, for example, a voltage output unit 121, a switching unit 122, a bias control circuit 123, and a bias power supply circuit 124.

The voltage output unit 121 supplies, for example, an adjustment signal S obtained based on a control signal output from a switching unit 122 described later to the amplifiers 111 and 112. The adjustment signal S is a voltage or current supplied to the amplifiers 111, 112. The adjustment signal S outputted from the voltage output unit 121 will be described later.

The voltage output unit 121 is, for example, a low dropout linear regulator. The voltage output unit 121 includes, for example, a transistor 121a, a driver circuit 121b, a filter 121c, a limiter 121d, and resistors 121e and 121f. The constituent elements of the voltage output unit 121 are not particularly limited.

The transistor 121a is, for example, a P-type transistor. The source of the transistor 121a is connected to the power supply 101 that supplies the power supply voltage Vcc. The drain of the transistor 121a is connected to the amplifiers 111 and 112 via, for example, an inductor. The drain of the transistor 121a is grounded through resistors 121e and 121f. The gate of the transistor 121a is connected to an output terminal of a switching unit 122 and a driver circuit 121b, which will be described later.

The driver circuit 121b is, for example, a differential amplifier. Hereinafter, the driver circuit 121b will be described as a differential amplifier as an example, but the driver circuit 121b is not limited to a differential amplifier. The driver circuit 121b may have, for example, an inverting input terminal (-terminal), a non-inverting input terminal (+terminal), and a standby terminal 121b1. The driver circuit 121b outputs, for example, a voltage substantially proportional to the control voltage Vramp. The term "substantially proportional" may include, for example, a case where a proportionality constant of a voltage outputted from the driver circuit 121b in proportion to the control voltage Vramp varies within ±20%. For example, when the driver circuit 121b outputs a voltage obtained by multiplying the control voltage by the proportionality constant a, the proportionality constant a may be a value in the range of 0.8×a to 1.2×a. In the driver circuit 121b, for example, a filter 121c is connected to an inverting input terminal (-terminal), and a node 121g is connected to a non-inverting input terminal (+terminal). The control voltage Vramp is supplied to the inverting input terminal through the filter 121 c. The noninverting input terminal is grounded through a resistor 121f connected to a node 121g. The spare terminal 121b1 is connected to the switching unit 122, and a control signal is input from the switching unit 122. The standby terminal 121b1 is, for example, a terminal for switching the operation state and the stop state of the driver circuit 121b based on a control signal described later. The driver circuit 121b adjusts, for example, the drain current of the transistor 121a so that the potential of the output of the filter 121c applied to the inverting input terminal is equal to the potential of the node 121g applied to the non-inverting input terminal.

The filter 121c is, for example, an RC filter or the like, and removes noise of the control voltage Vramp.

The limiter 121d is, for example, an RC filter or the like, and removes a spike voltage mixed into the control voltage Vramp.

The switching unit 122 controls the adjustment signal S output from the voltage output unit 121 based on, for example, a linear mode or a saturation mode. The switching unit 122 includes, for example, a switch 122a and a control unit 122b.

In the switch 122a, for example, one end is grounded, and the other end is connected to the gate of the transistor 121 a. The switching unit 122 may switch the connection state of the switch 122a based on a serial signal indicating a saturation mode or a linear mode, which is obtained from a predetermined circuit (for example, CPU (Central Processing Unit: central processing unit)). Specifically, when a serial signal (for example, a low voltage) indicating the saturation mode is obtained, the switching unit 122 sets the switch 122a to the off state (off). Thus, the voltage output unit 121 outputs the adjustment signal S as a voltage substantially proportional to the control voltage Vramp. When a serial signal (for example, a high voltage) indicating the linear mode is obtained, the switching unit 122 sets the switch 122a to the on state (on). In this case, the gate potential of the transistor 121a becomes "0V". Thus, the voltage output unit 121 outputs the adjustment signal S as the power supply voltage Vcc irrespective of the control voltage Vramp.

The control unit 122b outputs a control signal to the standby terminal 121b1 of the driver circuit 121b based on the operation of the switch 122 a. For example, the control signal is a signal for stopping the driver circuit 121 b. The control unit 122b may output a control signal to the terminal 210 in the linear mode. That is, the voltage output unit 121 receives the control signal from the control unit 122b in the linear mode, and stops the driver circuit 121 b. Thus, the power amplifier circuit 100 can stop the voltage output unit 121 that does not need to operate in the linear mode, and thus can reduce power consumption.

The bias control circuit 123 supplies a bias control signal to, for example, the terminals 114g of the bias circuits 114 to 116. The bias control circuit 123 may be a constant current source or a constant voltage source. The bias control circuit 123 may be a bias-based variable current source and a bias-based variable voltage source. The bias control circuit 123 may be a variable current source that supplies a current (bias control signal) that varies substantially square with respect to the control voltage Vramp to at least one of the bias circuits 114 to 116 in the saturation mode. The "substantially square" may include, for example, a case where a proportionality constant of a current outputted by the bias control circuit 123 in proportion to the control voltage Vramp in a square manner varies within ±20%. For example, when the bias control circuit 123 supplies a current obtained by multiplying the control voltage by the proportionality constant a, the proportionality constant a may be a value in the range of 0.8×a to 1.2×a. The bias control circuit 123 may generate a current that varies in a substantially square manner using a digital circuit, or may generate a current that varies in a substantially square manner using analog determination of a transistor. The bias control circuit 123 may determine a bias circuit that supplies a current that varies substantially square among the bias circuits 114 to 116 based on a serial signal obtained from a predetermined circuit (for example, CPU). Specifically, as an example, the bias control circuit 123 may determine whether the mode is the saturation mode or the linear mode based on the serial signal, and in the case of the saturation mode, supply a current that varies substantially in a square manner to the bias circuit 116.

The bias power supply circuit 124 supplies bias to, for example, the terminals 114f of the bias circuits 114 to 116. The bias power supply circuit 124 may be a constant current source or a constant voltage source. The bias power supply circuit 124 may be a bias-based variable current source and a bias-based variable voltage source. The bias power supply circuit 124 may be a variable current source that supplies a current that is substantially proportional to the control voltage Vramp or that varies substantially square to at least one of the bias circuits 114 to 116 in the saturation mode. The bias power supply circuit 124 may use digital circuitry to generate a substantially proportional or substantially square-varying current, or may use analog determination of transistors to generate a substantially proportional or substantially square-varying current. The bias power supply circuit 124 may determine a bias circuit that supplies a current that is substantially proportional or substantially square to the bias circuits 114 to 116 based on a serial signal obtained from a predetermined circuit (for example, CPU). Specifically, as an example, the bias power supply circuit 124 may determine whether the mode is the saturation mode or the linear mode based on the serial signal, and in the case of the saturation mode, supply a current that varies substantially in a square manner to the bias circuit 116. In addition, as an example, when the saturation mode is determined based on the serial signal, the bias power supply circuit 124 may supply a current substantially proportional to the control voltage Vramp to the bias circuits 114 and 115. The switching of the output of the adjustment signal S according to the linear mode and the saturation mode by the switching unit 122 may not necessarily be performed during the operation of the amplifying circuit 110. For example, when it is necessary to switch between the linear mode and the saturation mode according to the portable terminal equipped with the power amplifier circuit 100, the output switching of the adjustment signal S by the switching unit 122 may not be performed during the operation of the amplifier circuit 110. Specifically, the switching unit 122 may start outputting either the adjustment signal S, which is a voltage substantially proportional to the control voltage Vramp, or the adjustment signal S, which is the power supply voltage Vcc, according to a mode shown by a serial signal that is initially acquired in the portable terminal in which the power amplifier circuit 100 is mounted, and may not necessarily switch the adjustment signal S to be outputted during the operation of the amplifier circuit 110. That is, the operation of "outputting the power supply voltage Vcc as the adjustment signal S in the linear mode and outputting the voltage substantially proportional to the control voltage Vramp as the adjustment signal S in the saturation mode" includes both an operation of switching the adjustment signal S and outputting the adjustment signal S in accordance with switching the linear mode and the saturation mode in the operation of the power amplification circuit 100 and an operation of switching the adjustment signal S and outputting the adjustment signal S for each portable terminal in accordance with whether the mode used by the portable terminal in which the power amplification circuit 100 is mounted is the linear mode or the saturation mode. Therefore, the switching unit 122 includes a mechanism that, when the switching unit performs an operation of "outputting the power supply voltage Vcc as the adjustment signal S in the linear mode and outputting the voltage substantially proportional to the control voltage Vramp as the adjustment signal S in the saturation mode", even if the adjustment signal S output in the operation of the power amplification circuit 100 is only one of the signal of the voltage substantially proportional to the control voltage Vramp and the signal of the power supply voltage Vcc, the switching unit can switch the adjustment signal S from the signal of the voltage substantially proportional to the control voltage Vramp to the signal of the power supply voltage Vcc or from the signal of the power supply voltage Vcc to the signal of the voltage substantially proportional to the control voltage Vramp according to the linear mode or the saturation mode.

Action

The operation of the power amplifier circuit 100 will be described with reference to fig. 1 to 5. First, with reference to fig. 1 to 5, the operation of the power amplifier circuit 100 in the saturation mode (GMSK mode) will be described. Next, an operation of the power amplifier circuit 100 in the linear mode (EDGE mode) will be described.

Fig. 3 is a diagram showing an example of a relationship between the control voltage Vramp and the voltage of the node 100a in the saturation mode. In fig. 3, the X-axis is set to the control voltage Vramp, and the Y-axis is set to the voltage of the node 100 a.

Fig. 4 is a diagram showing an example of a relationship between the control voltage Vramp and the current Ic supplied by the bias control circuit 123 in the saturation mode. In fig. 4, the X-axis is set to the control voltage Vramp, and the Y-axis is set to the current Ic supplied from the bias control circuit 123.

Fig. 5 is a diagram showing an example of the relationship between the power supply voltage Vcc and the current Ic supplied by the bias control circuit 123 in the saturation mode. In fig. 5, the X-axis is set to the power supply voltage Vcc, and the Y-axis is set to the current Ic supplied from the bias control circuit 123.

First, an operation of the power amplifier circuit 100 in the saturation mode will be described. The power amplification circuit 100 turns off (turns off) the switch 122a of the switching unit 122, for example, based on a serial signal input from a predetermined circuit (not shown). The driver circuit 121b outputs a voltage substantially proportional to the input control voltage Vramp. The transistor 121a outputs an adjustment signal S based on the voltage output from the driver circuit 121 b. As shown in fig. 3, the adjustment signal S makes the voltage at the node 100a voltage substantially proportional to the control voltage Vramp (here, the maximum voltage is the voltage Vcc). That is, the amplifiers 111, 112 of the driving stage are supplied with a voltage substantially proportional to the control voltage Vramp. The amplifier 113 of the output stage is supplied with a voltage Vcc as a fixed voltage from the power supply 101.

As shown in fig. 4, the bias control circuit 123 supplies a current Ic that varies substantially square with respect to the control voltage Vramp to the bias circuit 116, for example, based on a serial signal input from a predetermined circuit. The bias control circuit 123 supplies the power supply voltage Vcc as a fixed voltage to the bias circuits 114 and 115, independently of the control voltage Vramp. Here, as shown in fig. 5, the maximum value of the current Ic is inversely proportional to the power supply voltage Vcc. Specifically, as shown in fig. 4 and 5, the current Ic is limited to a predetermined current Ic1 in the power supply voltage Vcc1, and is limited to a predetermined current Ic2 in the power supply voltage Vcc2 smaller than the power supply voltage Vcc 1.

The bias power supply circuit 124 supplies a current Id1 substantially proportional to the control voltage Vramp to the bias circuits 114 and 115 based on, for example, a serial signal input from a predetermined circuit (not shown). The bias power supply circuit 124 supplies a current Id2, which varies substantially square with respect to the control voltage Vramp, to the bias circuit 116 based on, for example, a serial signal input from a predetermined circuit.

In the above description, the bias power supply circuit 124 supplies the current Id1 proportional to the control voltage Vramp to the bias circuits 114 and 115 based on, for example, a serial signal input from a predetermined circuit (not shown), but the present invention is not limited thereto. The bias power supply circuit 124 may supply the bias circuits 114 and 115 with a current Id1 that varies substantially square with respect to the control voltage Vramp, for example, based on a serial signal input from a predetermined circuit (not shown).

According to the above, the power amplifying circuit 100 can be adapted to the switching spectrum of the modulation standard of the saturation mode (GMSK). Since the modulation standard of GMSK is a standard for time burst, the switching spectrum is a standard indicating whether or not a waveform at the time of burst enters a predetermined spectrum mask (spectral mask). In the modulation standard of the saturation mode (GMSK), it is necessary to adapt the inclination on the graph of the output voltage Pout with respect to the control voltage Vramp to the switching spectrum. In the case of steep gradients on the graph of the output voltage Pout, it is no longer suitable for switching spectra. The inclination is determined by the current Ic output from the bias control circuit 123, and the currents Id1 and Id2 output from the bias power supply circuit 124. Therefore, the power amplifier circuit 100 changes the current Ic, the current Id1, and the current Id2 to be substantially square with respect to the control voltage Vramp, thereby reducing the gradient on the graph of the output power Pout.

Next, an operation of the power amplification circuit 100 in the linear mode will be described. The power amplification circuit 100 sets the switch 122a of the switching unit 122 to an on state (on) based on a serial signal input from a predetermined circuit (not shown), for example. The control unit 122b of the switching unit 122 outputs a control signal to the standby terminal 121b1 of the driver circuit 121b by the switch 122a being turned on. The driver circuit 121b stops operating. Thus, the power amplifier circuit 100 can stop the driver circuit 121b that does not need to operate in the linear mode, and thus can reduce power consumption. Further, since the base of the transistor 121a is grounded, the base potential becomes "0V". Thus, as shown in fig. 5, the adjustment signal S sets the voltage at the node 100a to the power supply voltage Vcc, which is a fixed voltage, regardless of the control voltage Vramp.

The bias control circuit 123 operates as a voltage source that outputs a fixed voltage regardless of the control voltage Vramp, for example, based on a serial signal input from a predetermined circuit.

The bias power supply circuit 124 operates as a current source that outputs a fixed current regardless of the control voltage Vramp, for example, based on a serial signal input from a predetermined circuit.

Variation of

A modification of the power amplifier circuit 100 will be described with reference to fig. 6 and 7. Fig. 6 is a diagram showing a configuration example of a power amplification circuit 100 according to a modification. Fig. 7 is a diagram showing an example of a relationship between the control voltage Vramp and the current Ic supplied by the bias control circuit 123a in the saturation mode. In fig. 7, the X-axis is set to the control voltage Vramp, and the Y-axis is set to the current Ic supplied from the bias control circuit 123 a.

As shown in fig. 6, the power amplifier circuit 100 outputs the same bias control signal from the bias control circuit 123a to the bias circuits 114 to 116, as compared with the power amplifier circuit of fig. 1.

The following describes operations different from those of the power amplifier circuit 100 of fig. 1.

In the saturation mode, the bias control circuit 123a supplies a fixed voltage (e.g., the power supply voltage Vcc) to the bias circuits 114 to 116 irrespective of the control voltage Vramp. Here, as shown in fig. 5, the maximum value of the current Ic is inversely proportional to the power supply voltage Vcc.

In the saturation mode, the bias power supply circuit 124 supplies a current Id1 substantially proportional to the control voltage Vramp to the bias circuits 114 and 115 based on, for example, a serial signal input from a predetermined circuit (not shown). The bias power supply circuit 124 may supply the bias circuit 116 with a current Id2 that varies substantially square with respect to the control voltage Vramp, for example, based on a serial signal input from a predetermined circuit.

In the above description, the case where the bias control circuit 123a supplies a fixed voltage (for example, the power supply voltage Vcc) to the bias circuits 114 to 116 irrespective of the control voltage Vramp has been described, but the present invention is not limited thereto. As shown in fig. 7, the bias control circuit 123a may supply the bias circuits 114 to 116 with a current Ic that varies substantially square with respect to the control voltage Vramp.

In the above description, the bias power supply circuit 124 supplies the current Id1 substantially proportional to the control voltage Vramp to the bias circuits 114 and 115 based on, for example, a serial signal input from a predetermined circuit (not shown), but the present invention is not limited thereto. The bias power supply circuit 124 may supply the bias circuits 114 and 115 with a current Id1 that varies substantially square with respect to the control voltage Vramp, for example, based on a serial signal input from a predetermined circuit (not shown).

= = summary= =

The power amplification circuit 100 is a power amplification circuit that operates in a linear mode and a saturation mode, and includes: a signal output unit 120 to which the control voltage Vramp is input, and which outputs an adjustment signal S that is a signal based on the linear mode or the saturation mode; at least one driver stage amplifier 111, 112 to which the adjustment signal S is supplied, to which the RF input signal is input, and which amplifies the input RF input signal RFin; and an amplifier 113 of the output stage, which is an amplifier supplied with the power supply voltage Vcc, amplifies the amplified RF input signals outputted from the amplifiers 111, 112 of the driving stage, and outputs an RF output signal RFout, the signal output section 120 having: a voltage output unit 121 to which a power supply voltage Vcc and a control voltage Vramp are supplied and which outputs an adjustment signal S; and a switching unit 122 that controls the voltage output unit 121 so that the power supply voltage Vcc is output as the adjustment signal S in the linear mode, and a voltage substantially proportional to the control voltage Vramp is output as the adjustment signal S in the saturation mode. Thus, a power amplifier circuit which can cope with different modulation standards and is constituted by a simple circuit is provided.

In the power amplification circuit 100, the voltage output unit 121 includes: a transistor 121a that outputs an adjustment signal S; and a driver circuit 121b to which a control voltage Vramp is input and which outputs a signal based on the control voltage Vramp to a gate of the transistor 121a, the switching unit 122 having: a switch 122a having one end connected to the reference potential and the other end connected to the gate of the transistor 121 a; and a control unit 122b that controls the driver circuit 121b so as not to output a signal based on the control voltage Vramp from the driver circuit 121b, based on the switch 122a being in an on state. Thus, the power amplifier circuit 100 can stop the voltage output unit 121 that does not need to operate in the linear mode, and thus can reduce power consumption.

The power amplifier circuit 100 further includes a bias circuit 116 for supplying a bias to the amplifier 113 of the output stage, and the signal output section 120 further includes a bias control circuit 123, and the bias control circuit 123 supplies a current that changes substantially square with respect to a change in the control voltage Vramp to the collector of the bias circuit 116 in the saturation mode. Thus, the power amplification circuit 100 can be adapted to a modulation standard of a saturation mode (GMSK) by a simple structure.

The power amplifier circuit 100 further includes a bias circuit 116 for supplying a bias to the amplifier 113 of the output stage, and the signal output section 120 further includes a bias power supply circuit 124, and the bias power supply circuit 124 supplies a current that changes substantially square with respect to a change in the control voltage Vramp to the base of the bias circuit 116 in the saturation mode. Thus, the power amplification circuit 100 can be more reliably adapted to the modulation standard of the saturation mode (GMSK) by a simple structure.

The power amplification circuit 100 further includes: bias circuits 114, 115 (first bias circuits) that supply bias to the amplifiers 111, 112 of at least one driving stage; and a bias circuit 116 (second bias circuit) for supplying bias to the amplifier 113 of the output stage, the signal output section 120 further having: a bias control circuit 123a that supplies a constant current to the collectors of the bias circuits 114 and 115 (first bias circuits) and the collector of the bias circuit 116 (second bias circuits) in the saturation mode, irrespective of a change in the control voltage Vramp; and a bias power supply circuit 124 that supplies a current that changes substantially square with respect to a change in the control voltage Vramp to the base of the bias circuit 116 (second bias circuit) in the saturation mode. Thus, the power amplification circuit 100 can be adapted to a modulation standard of a saturation mode (GMSK) by a simple structure.

The power amplification circuit 100 further includes: bias circuits 114, 115 (first bias circuits) that supply bias to the amplifiers 111, 112 of at least one driving stage; and a bias circuit 116 (second bias circuit) for supplying bias to the amplifier 113 of the output stage, the signal output section 120 further having: a bias control circuit 123a that supplies a current that changes substantially square with respect to a change in the control voltage Vramp to the collectors of the bias circuits 114 and 115 (first bias circuits) and the collector of the bias circuit 116 (second bias circuit) in the saturation mode; and a bias power supply circuit 124 that supplies a current that changes substantially square with respect to a change in the control voltage Vramp to the base of the bias circuit 116 (second bias circuit) in the saturation mode. Thus, the power amplification circuit 100 can be more reliably adapted to the modulation standard of the saturation mode (GMSK) by a simple structure.

In addition, the bias power supply circuit 124 of the power amplification circuit 100 supplies a current that changes substantially square with respect to a change in the control voltage Vramp to the bases of the bias circuits 114, 115 (first bias circuits) in the saturation mode. Thus, the power amplification circuit 100 can be adapted to a modulation standard of a saturation mode (GMSK) by a simple structure.

In addition, the bias power supply circuit 124 of the power amplification circuit 100 supplies a current substantially proportional to a change in the control voltage Vramp to the bases of the bias circuits 114, 115 (first bias circuits) in the saturation mode. Thus, the power amplification circuit 100 can be adapted to a modulation standard of a saturation mode (GMSK) by a simple structure.

The embodiments described above are intended to facilitate understanding of the present disclosure, and are not intended to be limiting in interpreting the present disclosure. The present disclosure can be modified or improved within a range not departing from the gist thereof, and equivalents thereof are also included in the present disclosure. That is, those skilled in the art can appropriately design and modify the embodiments, and the embodiments are also included in the scope of the present disclosure as long as they have the features of the present disclosure. The elements and the arrangement thereof in the embodiment are not limited to the examples, and can be appropriately changed.

Description of the reference numerals

A power amplifying circuit, a 110..an amplifying circuit, a 120..a signal output section, a 121..a voltage output section, a 122..a switching section, a 123..a bias control circuit, and a 124..a bias power supply circuit.

Claims

1. A power amplifying circuit operating in a linear mode and a saturation mode, wherein,

the power amplification circuit includes:

a signal output unit to which a control voltage is input and which outputs an adjustment signal based on the linear mode or the saturation mode;

at least one amplifier of the driving stage, which is an amplifier to which the adjustment signal is supplied, to which an RF input signal is input, and which amplifies the input RF input signal; and

an amplifier for outputting an RF output signal by amplifying the RF input signal outputted from the amplifier of the driving stage,

the signal output unit includes:

a voltage output unit to which the power supply voltage and the control voltage are supplied and which outputs the adjustment signal; and

and a switching unit that controls the voltage output unit so that the power supply voltage is output as the adjustment signal in the linear mode, and a voltage substantially proportional to the control voltage is output as the adjustment signal in the saturation mode.

2. The power amplification circuit of claim 1, wherein,

the voltage output unit includes:

a transistor that outputs the adjustment signal; and

a driver circuit to which the control voltage is input, outputting a signal based on the control voltage to a gate of the transistor,

the switching unit includes:

a switch, one end of which is connected with a reference potential, and the other end of which is connected with the grid electrode of the transistor; and

and a control unit that controls the driver circuit so that a signal based on the control voltage is not output from the driver circuit, based on the switch being turned on.

3. The power amplification circuit according to claim 1 or 2, wherein,

the power amplification circuit further comprises a bias circuit for supplying a bias to an amplifier of the output stage,

the signal output unit further includes a bias control circuit that supplies a current that changes substantially square with respect to a change in the control voltage to a collector of the bias circuit in the saturation mode.

4. A power amplifying circuit according to any one of claims 1 to 3, wherein,

the signal output unit further includes a bias power supply circuit that supplies a current that changes substantially square with respect to a change in the control voltage to a base of the bias circuit in the saturation mode.

5. The power amplification circuit according to claim 1 or 2, wherein,

the power amplification circuit further includes:

a first bias circuit that supplies a bias to an amplifier of the at least one driving stage; and

a second bias circuit for supplying bias to the amplifier of the output stage,

the signal output unit further includes:

a bias control circuit that supplies a constant current to a collector of the first bias circuit and a collector of the second bias circuit in the saturation mode regardless of a change in the control voltage; and

and a bias power supply circuit that supplies a current that changes substantially square with respect to a change in the control voltage to a base of the second bias circuit in the saturation mode.

6. The power amplification circuit according to claim 1 or 2, wherein,

the power amplification circuit further includes:

a second bias circuit for supplying bias to the amplifier of the output stage,

the signal output unit further includes:

a bias control circuit that supplies a current that changes substantially square with respect to a change in the control voltage to a collector of the first bias circuit and a collector of the second bias circuit in the saturation mode; and

7. The power amplification circuit of claim 5 or 6, wherein,

the bias power supply circuit supplies a current that changes in a substantially square manner with respect to a change in the control voltage to a base of the first bias circuit in the saturation mode.

8. The power amplification circuit of claim 5 or 6, wherein,

the bias power supply circuit supplies a current substantially proportional to a change in the control voltage to a base of the first bias circuit in the saturation mode.