CN117460334A - Array substrate and display panel - Google Patents
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- CN117460334A CN117460334A CN202311597943.2A CN202311597943A CN117460334A CN 117460334 A CN117460334 A CN 117460334A CN 202311597943 A CN202311597943 A CN 202311597943A CN 117460334 A CN117460334 A CN 117460334A
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- 239000000758 substrate Substances 0.000 title claims abstract description 123
- 239000004065 semiconductor Substances 0.000 claims abstract description 108
- 229910052751 metal Inorganic materials 0.000 claims abstract description 76
- 239000002184 metal Substances 0.000 claims abstract description 76
- 239000000463 material Substances 0.000 claims description 18
- 239000010410 layer Substances 0.000 description 134
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000010408 film Substances 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 150000002739 metals Chemical class 0.000 description 7
- 239000010409 thin film Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- -1 IGZO) Chemical compound 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000003086 colorant Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The application provides an array substrate and a display panel, wherein the array substrate comprises a substrate, a first metal layer, a semiconductor layer and a second metal layer, wherein the first metal layer, the semiconductor layer and the second metal layer are positioned on one side of the substrate, the first metal layer comprises a data line, the semiconductor layer is positioned on one side of the first metal layer, which is far away from the substrate, and comprises a semiconductor part, the second metal layer is positioned on one side of the semiconductor layer, which is far away from the first metal layer, and comprises a scanning line, the orthographic projections of the data line and the scanning line on the substrate are provided with overlapping areas, and the orthographic projection of the semiconductor part on the substrate at least covers the overlapping areas; in this way, by arranging the semiconductor part between the data line and the scanning line, the semiconductor characteristics of the semiconductor part correspond to the overlapping area of the data line and the scanning line, and the problem that the crossing line crossing position of the data line and the scanning line is short-circuited can be improved, so that the problem that the overlapping line crossing position of the data line and the scanning line in the traditional OLED panel is easy to short-circuit is solved.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a display panel.
Background
At present, organic light emitting diode display (Organic Light emitting Display, OLED) panels are increasingly used in the fields of use and vision of people, and are widely applied to smart wear, mobile phones, displays and large-sized televisions and commercial displays. OLED panels are also increasingly being used in the panel market due to their bright color, high contrast, high refresh rate, low power consumption, and many other advantages. However, OLED panels face yield problems during manufacturing as conventional liquid crystal display (Liquid Crystal Display, LCD) panels. For example, in the design of an OLED panel, there are a Data (Data) signal line and a scan (Gate) signal line arranged perpendicular to the Data (Data) signal line, so in the overlapping position of the two metal signal lines, a short circuit occurs at the position of the crossing metal due to dropping of some particles (particles) or foreign matters during film forming in the panel manufacturing process, and sometimes a short circuit occurs due to breakdown of the metal at the crossing caused by static electricity generated in the panel production line, thereby resulting in rejection of the OLED panel and lowering the yield. The thickness of the insulating layer between the two metals is increased to prevent such a short circuit, but the excessive thickness of the insulating layer is disadvantageous for driving the panel.
Disclosure of Invention
The application provides an array substrate and a display panel to alleviate the technical problem that short circuit is easy to occur at the overlapping overline position of a data line and a scanning line in the existing OLED panel.
In order to solve the problems, the technical scheme provided by the application is as follows:
the embodiment of the application provides an array substrate, which comprises:
a substrate;
a first metal layer located at one side of the substrate and including a data line;
a semiconductor layer located on one side of the first metal layer away from the substrate and including a semiconductor portion;
the second metal layer is positioned on one side of the semiconductor layer away from the first metal layer and comprises scanning lines;
the front projection of the data line and the scanning line on the substrate is provided with an overlapping area, and the front projection of the semiconductor part on the substrate at least covers the overlapping area.
In the array substrate provided by the embodiment of the application, the first metal layer further comprises a light shielding part, the light shielding part is located at one side of the data line and is arranged at intervals with the data line, and the light shielding part and the data line are arranged on the same layer.
In the array substrate provided in the embodiment of the present application, the light shielding portion and the data wire are the same in quality.
In the array substrate provided by the embodiment of the application, the semiconductor layer further comprises an active part, and the active part is located at one side of the semiconductor part and is arranged at intervals with the semiconductor part;
the active part comprises a channel part and a source electrode area and a drain electrode area which are positioned at two sides of the channel part;
wherein the semiconductor portion is arranged in the same layer as the active portion.
In the array substrate provided in the embodiment of the present application, the semiconductor portion, the active portion and the channel portion are made of the same material.
In the array substrate provided by the embodiment of the application, the second metal layer further includes a gate portion, the gate portion is opposite to the channel portion, and the scan line and the gate portion are arranged on the same layer.
In the array substrate provided in the embodiment of the present application, the material of the scan line is the same as that of the gate portion.
In the array substrate provided by the embodiment of the application, the array substrate further comprises a buffer layer, the buffer layer is located between the first metal layer and the semiconductor layer, and the data line and the semiconductor portion are separated by a part of the buffer layer.
In the array substrate provided by the embodiment of the application, the array substrate further comprises a gate insulating layer, the gate insulating layer is located between the second metal layer and the semiconductor layer, and the scan line and the semiconductor portion are separated by a part of the gate insulating layer.
The embodiment of the application also provides a display panel, which comprises the array substrate of one of the embodiments.
The beneficial effects of this application are: in the array substrate and the display panel provided by the application, the array substrate comprises a substrate, and a first metal layer, a semiconductor layer and a second metal layer which are positioned on one side of the substrate, wherein the first metal layer comprises a data line, the semiconductor layer is positioned on one side of the first metal layer far away from the substrate and comprises a semiconductor part, the second metal layer is positioned on one side of the semiconductor layer far away from the first metal layer and comprises a scanning line, the orthographic projection of the data line and the scanning line on the substrate is provided with an overlapping area, and the orthographic projection of the semiconductor part on the substrate at least covers the overlapping area; therefore, by arranging the semiconductor part between the data line and the scanning line, the semiconductor characteristics of the semiconductor part correspond to the overlapping area of the data line and the scanning line, and the problem that the crossing line crossing position of the data line and the scanning line is short-circuited can be solved, so that the technical problem that the overlapping line crossing position of the data line and the scanning line in the traditional OLED panel is easy to short-circuit is solved.
Drawings
In order to more clearly illustrate the embodiments or the technical solutions in the prior art, the following description will briefly introduce the drawings that are needed in the embodiments or the description of the prior art, it is obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic plan view of an array substrate according to an embodiment of the present application.
FIG. 2 is a schematic cross-sectional view of the structure of FIG. 1 along the directions M-M 'and N-N'.
Fig. 3 is a schematic diagram of a partial film layer structure of an array substrate according to an embodiment of the present application.
FIG. 4 is a schematic view of another cross-sectional structure along the directions M-M 'and N-N' in FIG. 1.
Fig. 5 is a schematic cross-sectional structure of a display panel according to an embodiment of the disclosure.
Detailed Description
The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. The directional terms mentioned in this application, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., are only referring to the directions of the attached drawings. Accordingly, directional terminology is used to describe and understand the application and is not intended to be limiting of the application. In the drawings, like elements are designated by like reference numerals. In the drawings, the thickness of some layers and regions are exaggerated for clarity of understanding and ease of description. I.e., the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited thereto.
Referring to fig. 1 to 3, fig. 1 is a schematic plan view of an array substrate according to an embodiment of the present application, fig. 2 is a schematic sectional view of the array substrate along the directions M-M 'and N-N' in fig. 1, and fig. 3 is a schematic partial film structure of the array substrate according to an embodiment of the present application. Referring to fig. 1, the array substrate 100 includes a substrate 10, and a plurality of data lines DL and a plurality of scan lines GL disposed on the substrate 10, the scan lines GL being located at a side of the data lines DL away from the substrate 10. The data lines DL are arranged at intervals along the first direction X, and each data line DL extends along the second direction Y. The plurality of scanning lines GL are arranged at intervals along the second direction Y, and each scanning line GL extends along the first direction X. The first direction X and the second direction Y are different, for example, the first direction X is a row direction, the second direction Y is a column direction, and the first direction X is perpendicular to the second direction Y.
The data lines DL and the scan lines GL are insulated and cross to define a plurality of pixel areas PD, each of which may be provided with one sub-pixel, so that the plurality of sub-pixels are arranged on the substrate 10 in an array. Each adjacent three sub-pixels form a pixel, and each pixel comprises three sub-pixels with different colors, for example, three sub-pixels with different colors are respectively a red sub-pixel, a green sub-pixel and a blue sub-pixel. The subpixels of the same color are arranged in a subpixel row, and the subpixels of different colors are arranged in a subpixel column.
The insulating crossing position of the data line DL and the scanning line GL is an overlapping cross line area of the data line DL and the scanning line GL, that is, an overlapping area OL exists between the orthographic projection of the data line DL on the substrate 10 and the orthographic projection of the scanning line GL on the substrate 10, and the overlapping area OL is an area where the orthographic projection of the overlapping cross line area of the data line DL and the scanning line GL on the substrate 10 is located.
Specifically, referring to fig. 2, the array substrate 100 includes a first metal layer 20, a semiconductor layer 30, and a second metal layer 40 disposed on the substrate 10. The first metal layer 20 is located at one side of the substrate 10, and the first metal layer 20 includes the data line DL. The semiconductor layer 30 is located on a side of the first metal layer 20 remote from the substrate 10, and the semiconductor layer 30 includes a semiconductor portion 31. The second metal layer 40 is located at a side of the semiconductor layer 30 away from the first metal layer 20, and the second metal layer 40 includes a scan line GL. That is, the semiconductor layer 30 is located between the first metal layer 20 and the second metal layer 40, and accordingly, the semiconductor portion 31 is located between the data line DL and the scan line GL.
Specifically, the semiconductor portion 31 is disposed at least corresponding to the overlapping cross line region of the data line DL and the scan line GL, that is, the orthographic projection of the semiconductor portion 31 on the substrate 10 covers at least the overlapping region OL of the data line DL and the scan line GL to isolate the data line DL and the scan line GL corresponding to the overlapping region OL. Optionally, the orthographic projections of the data line DL and the scan line GL on the substrate 10 cover the orthographic projection of the semiconductor portion 31 on the substrate 10, that is, the orthographic projection of the semiconductor portion 31 on the substrate 10 is within the orthographic projection of the data line DL on the substrate 10, and the orthographic projection of the semiconductor portion 31 on the substrate 10 is also within the orthographic projection of the scan line GL on the substrate 10. In other words, the width of the data line DL in the first direction X is equal to the width of the semiconductor portion 31 in the first direction X, and the width of the scanning line GL in the second direction Y is equal to the width of the semiconductor portion 31 in the second direction Y. Of course, it should be noted that, due to the process accuracy, the width equality of the two structures described in the present application is not limited to the strict equality, and the width equality is understood to mean that the widths of the two structures are substantially equal, and may include a smaller range of process errors.
In this embodiment, by disposing the semiconductor portion 31 between the data line DL and the scan line GL, the semiconductor portion 31 corresponds to the overlapping area OL of the data line DL and the scan line GL, the semiconductor portion 31 has semiconductor characteristics, and the conductivity and the dielectric constant of the semiconductor portion 31 are different from those of the data line DL and the scan line GL, so that the data line DL and the scan line GL corresponding to the overlapping area OL are isolated and insulated from each other by the semiconductor portion 31, thereby improving the problem that the short circuit occurs at the crossing line position of the data line DL and the scan line GL, and further solving the technical problem that the short circuit easily occurs at the overlapping line position of the data line DL and the scan line GL in the conventional OLED panel. Meanwhile, the semiconductor portion 31 is disposed in the overlapping area OL of the data line DL and the scan line GL, and no additional film layer is required, and the thickness of the insulating layer between the data line DL and the scan line GL is not increased, so that the problem that the driving of the panel is not facilitated due to the excessively thick insulating layer is avoided.
The film structure on the array substrate 100 will be specifically described below.
Referring to fig. 3, the array substrate 100 further includes a thin film transistor T1 disposed on the substrate 10, the thin film transistor T1 includes an active portion 32, a gate portion 41, a source 51 and a drain 52, the data line DL is electrically connected to the source 51 of the thin film transistor T1, and the scan line GL is electrically connected to the gate portion 41 of the thin film transistor T1. The substrate 10 may be a rigid substrate or a flexible substrate; when the substrate 10 is a rigid substrate, the substrate may include a glass substrate, a quartz substrate, a silicon wafer, or other rigid substrates; when the substrate 10 is a flexible substrate, the flexible substrate may include a Polyimide (PI) film, an ultrathin glass film, or the like, and the embodiment of the present application uses the substrate 10 as a dual-layer Polyimide as an example.
Specifically, the first metal layer 20 is disposed on one side of the substrate 10, the first metal layer 20 further includes the light shielding portion 21, the light shielding portion 21 is disposed on one side of the data line DL and is spaced from the data line DL, and the light shielding portion 21 is disposed on the same layer as the data line DL. It should be noted that the term "same layer setting" in the present application refers to that, in a preparation process, a film layer formed by the same material is subjected to patterning treatment to obtain at least two different structures, and the at least two different structures are set in the same layer. For example, in this embodiment, the light shielding portion 21 and the data line DL are patterned by the same conductive film layer, and then the light shielding portion 21 and the data line DL are arranged on the same layer, that is, the light shielding portion 21 and the data line DL are made of the same material.
Alternatively, the first metal layer 20 may be formed of one or more metals selected from molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or the like, or one or more alloys formed by any combination of the above metals, or other suitable materials. In addition, the first metal layer 20 may have a single-layer or multi-layer structure.
The semiconductor layer 30 is disposed on a side of the first metal layer 20 away from the substrate 10, the semiconductor layer 30 further includes the active portion 32, and the active portion 32 is disposed on a side of the semiconductor portion 31 and spaced apart from the semiconductor portion 31. The active portion 32 includes a channel portion and source and drain regions located on both sides of the channel portion. The light shielding portion 21 is provided at least corresponding to the channel portion to shield the channel portion from light.
The semiconductor portion 31 and the active portion 32 are provided in the same layer, and the semiconductor portion 31 and the active portion 32 are made of the same material as the channel portion. For example, the semiconductor layer 30 may have a single-layer structure or a multi-layer structure formed of indium gallium zinc oxide (indium gallium zinc oxide, IGZO), indium tin zinc oxide (indium tin zinc oxide, ITZO), indium gallium zinc tin oxide (indium gallium zinc tin oxide, IGZTO), or the like. The semiconductor portion 31 and the channel portion have semiconductor characteristics, and the source region and the drain region are formed by conducting a semiconductor material of the semiconductor layer 30, so that the semiconductor material is changed from semiconductor to semiconductor.
The array substrate 100 further includes a buffer layer 11, the buffer layer 11 is located between the first metal layer 20 and the semiconductor layer 30, and the data line DL and the semiconductor portion 31 are separated by a portion of the buffer layer 11. The buffer layer 11 covers the data line DL, the light shielding portion 21, and the substrate 10. The buffer layer 11 may prevent unwanted impurities or contaminants (e.g., moisture, oxygen, etc.) from diffusing from the substrate 10 into devices that may be damaged by such impurities or contaminants, while also providing a planar top surface. The buffer layer 11 may be silicon nitride (SiNx), silicon oxide (SiOx), or a stack of silicon nitride and silicon oxide.
The second metal layer 40 is disposed on a side of the first metal layer 20 away from the substrate 10, the second metal layer 40 further includes a gate portion 41, the gate portion 41 is opposite to the channel portion, the scan line GL and the gate portion 41 are disposed on the same layer, and the scan line GL and the gate portion 41 are the same material. For example, the second metal layer 40 may be formed of one or more metals selected from molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or the like, or one or more alloys formed by any combination of the above metals, or other suitable materials. In addition, the second metal layer 40 may have a single-layer or multi-layer structure.
The array substrate 100 further includes a gate insulating layer 12, the gate insulating layer 12 is located between the second metal layer 40 and the semiconductor layer 30, and the scan line GL and the semiconductor portion 31 are separated by a portion of the gate insulating layer 12. The buffer layer 11 may be silicon nitride (SiNx), silicon oxide (SiOx), or a stack of silicon nitride and silicon oxide. The gate portion 41 and the scanning line GL are provided on the gate insulating layer 12.
Since the front projection of the scanning line GL on the substrate 10 covers the front projection of the semiconductor portion 31 on the substrate 10, the scanning line GL can shield the semiconductor portion 31 when the semiconductor layer 30 is made conductive, and prevent the semiconductor portion 31 from being made conductive, so that the semiconductor portion 31 can maintain the semiconductor characteristics of the semiconductor material. Accordingly, when the semiconductor layer 30 is made conductive, the gate portion 41 can shield the channel portion from being made conductive, and the channel portion can be made to maintain the semiconductor characteristics of the semiconductor material as a channel of the thin film transistor T1.
Further, the array substrate 100 further includes a third metal layer disposed on a side of the second metal layer 40 away from the semiconductor layer 30. The third metal layer includes a source electrode 51 and a drain electrode 52 of the thin film transistor T1, the source electrode 51 being electrically connected to a source region of the active portion 32, and the drain electrode 52 being electrically connected to a drain region of the active portion 32. The third metal layer may be formed of one or more metals selected from molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or the like, or one or more alloys formed by any combination of the above metals, or other suitable materials. In addition, the third metal layer may have a single-layer or multi-layer structure.
The array substrate 100 further includes an interlayer insulating layer 13 between the second metal layer 40 and the third metal layer, and the interlayer insulating layer 13 covers the gate portion 41, the scan line GL, a portion of the active portion 32, and the buffer layer 11. The interlayer insulating layer 13 may be silicon nitride (SiNx), silicon oxide (SiOx), or a stack of silicon nitride and silicon oxide.
Further, the array substrate 100 further includes a planarization layer 14 and a pixel electrode 60. The planarization layer 14 is covered on the third metal layer and the interlayer insulating layer 13, and the pixel electrode 60 is disposed on the planarization layer 14 and electrically connected to the drain electrode 52 of the thin film transistor T1. Optionally, the array substrate 100 further includes a pixel defining layer 15 covering the pixel electrode 60 and the planarization layer 14, and the pixel defining layer 15 is provided with a pixel opening 151 at a position corresponding to the pixel electrode 60. The materials of the planarization layer 14 and the pixel defining layer 15 may be organic materials, and the material of the pixel electrode 60 may include a transparent conductive material or a conductive material having reflective properties.
In one embodiment, referring to fig. 1 to 4, fig. 4 is a schematic cross-sectional structure along the directions M-M 'and N-N' in fig. 1. Unlike the above embodiment, the orthographic projection of the semiconductor portion 31 on the substrate 10 covers other portions of the orthographic projection of the scanning line GL on the substrate 10 in addition to the overlapping area OL of the orthographic projections of the data line DL and the scanning line GL on the substrate 10. In other words, the front projection of the scanning line GL on the substrate 10 covers the front projection of the semiconductor portion 31 on the substrate 10, but the front projection of the data line DL on the substrate 10 does not completely cover the front projection of the semiconductor portion 31 on the substrate 10, i.e. the front projection of the semiconductor portion 31 on the substrate 10 is within the range of the front projection of the scanning line GL on the substrate 10, but the front projection of the semiconductor portion 31 on the substrate 10 is beyond the front projection range of the data line DL on the substrate 10. More specifically, the width of the data line DL in the first direction X is smaller than the width of the semiconductor portion 31 in the first direction X.
In this embodiment, since the arrangement area of the semiconductor portion 31 exceeds the overlapping area OL of the data line DL and the scan line GL, the data line DL and the scan line GL corresponding to the overlapping area OL can be better isolated, and the problem of short circuit at the crossing line crossing position of the data line DL and the scan line GL can be further better improved. The other descriptions refer to the above embodiments, and are not repeated here.
Based on the same inventive concept, the embodiment of the present application further provides a display panel, please refer to fig. 1 to 5, and fig. 5 is a schematic cross-sectional structure of the display panel according to the embodiment of the present application. The display panel includes the array substrate 100 of one of the foregoing embodiments. The display panel includes an organic Light Emitting Diode (Organic Light Emitting Display) panel, a Light-Emitting Diode (LED) display panel, a Micro-Light-Emitting Diode (Micro-LED) display panel, a sub-millimeter LED (Mini Light-Emitting Diode), or the like. The display panel can be applied to electronic equipment with display functions such as mobile phones, tablet personal computers, notebooks, game machines, digital cameras, vehicle-mounted navigator, electronic billboards, automatic teller machines and the like.
The embodiment of the application takes the display panel as an OLED panel as an example. Referring to fig. 5, the display panel 1000 includes a light emitting layer 70 disposed in a pixel opening 151 of the array substrate 100 and a cathode electrode 80 disposed on a side of the light emitting layer 70 remote from the pixel electrode 60. The light emitting layer 70 emits light by the combined action of the pixel electrode 60 and the cathode electrode 80. Optionally, the display panel 1000 further includes an encapsulation layer 90 covering the cathode 80, where the encapsulation layer 90 is used to protect the light emitting layer 70 to block water and oxygen and prevent the light emitting layer 70 from being disabled due to water and oxygen intrusion.
Of course, the display panel 1000 of the present application may further integrate functional elements having functions of touch control, fingerprint recognition, image capturing, and the like, and will not be described herein.
As can be seen from the above embodiments:
in the array substrate 100 and the display panel 1000 provided by the application, the array substrate 100 includes a substrate 10, a first metal layer 20, a semiconductor layer 30 and a second metal layer 40, which are positioned on one side of the substrate 10, the first metal layer 20 includes a data line DL, the semiconductor layer 30 is positioned on one side of the first metal layer 20 away from the substrate 10 and includes a semiconductor portion 31, the second metal layer 40 is positioned on one side of the semiconductor layer 30 away from the first metal layer 20 and includes a scanning line GL, the orthographic projection of the data line DL and the scanning line GL on the substrate 10 has an overlapping region OL, and the orthographic projection of the semiconductor portion 31 on the substrate 10 at least covers the overlapping region OL; in this way, by disposing the semiconductor portion 31 between the data line DL and the scan line GL, the semiconductor characteristics of the semiconductor portion 31 corresponding to the overlapping area OL of the data line DL and the scan line GL can improve the problem that the crossing line crossing position of the data line DL and the scan line GL is short-circuited, thereby solving the technical problem that the overlapping line crossing position of the data line DL and the scan line GL in the conventional OLED panel is easy to short-circuit.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The foregoing embodiments of the present application have been described in detail, and specific examples have been employed herein to illustrate the principles and embodiments of the present application, the above embodiments being provided only to assist in understanding the technical solutions of the present application and their core ideas; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. An array substrate, characterized by comprising:
a substrate;
a first metal layer located at one side of the substrate and including a data line;
a semiconductor layer located on one side of the first metal layer away from the substrate and including a semiconductor portion;
the second metal layer is positioned on one side of the semiconductor layer away from the first metal layer and comprises scanning lines;
the front projection of the data line and the scanning line on the substrate is provided with an overlapping area, and the front projection of the semiconductor part on the substrate at least covers the overlapping area.
2. The array substrate of claim 1, wherein the first metal layer further comprises a light shielding portion, the light shielding portion is located at one side of the data line and is spaced apart from the data line, and the light shielding portion is arranged at the same layer as the data line.
3. The array substrate of claim 2, wherein the light shielding portion is the same as the data line material.
4. The array substrate of claim 1, wherein the semiconductor layer further comprises an active portion located on one side of the semiconductor portion and spaced apart from the semiconductor portion;
the active part comprises a channel part and a source electrode area and a drain electrode area which are positioned at two sides of the channel part;
wherein the semiconductor portion is arranged in the same layer as the active portion.
5. The array substrate of claim 4, wherein the semiconductor portion and the active portion are the same material as the channel portion.
6. The array substrate of claim 4, wherein the second metal layer further comprises a gate portion positioned opposite the channel portion, the scan line being disposed in the same layer as the gate portion.
7. The array substrate of claim 6, wherein the scan lines are made of the same material as the gate portions.
8. The array substrate of any one of claims 1-7, further comprising a buffer layer between the first metal layer and the semiconductor layer, the data line and the semiconductor portion being separated by a portion of the buffer layer.
9. The array substrate of any one of claims 1-7, further comprising a gate insulating layer between the second metal layer and the semiconductor layer, the scan line and the semiconductor portion being separated by a portion of the gate insulating layer.
10. A display panel comprising an array substrate according to any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311597943.2A CN117460334A (en) | 2023-11-27 | 2023-11-27 | Array substrate and display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311597943.2A CN117460334A (en) | 2023-11-27 | 2023-11-27 | Array substrate and display panel |
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| Publication Number | Publication Date |
|---|---|
| CN117460334A true CN117460334A (en) | 2024-01-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311597943.2A Pending CN117460334A (en) | 2023-11-27 | 2023-11-27 | Array substrate and display panel |
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| Country | Link |
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| CN (1) | CN117460334A (en) |
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- 2023-11-27 CN CN202311597943.2A patent/CN117460334A/en active Pending
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