CN117460249A - Semiconductor device, manufacturing method of semiconductor device and electronic equipment - Google Patents

Abstract

The present disclosure relates to a semiconductor device, a method for manufacturing the semiconductor device, and an electronic apparatus, the semiconductor device including: a substrate; vertical ring channel type transistors and planar type transistors. According to the method, the channel full-surrounding structure and the planar metal oxide semiconductor device are combined to form the 2T0C structure with the zero capacitance of the two transistors, the grid electrode, the first source electrode layer, the second source electrode layer and the second drain electrode layer in the 2T0C structure correspond to four metal layers respectively, the internal stress of the semiconductor device is reduced by reducing the number of the metal layers, the possibility of failure of the semiconductor device is reduced, and meanwhile the yield of the semiconductor device is improved; in addition, because the second source electrode layer, the second drain electrode layer and the second channel layer form a capacitor structure, the purpose of changing the area of the storage area can be achieved by adjusting the distance between the second source electrode layer and the second drain electrode layer, namely the length of the second channel layer, to change the capacitance.

Description

Semiconductor device, manufacturing method of semiconductor device and electronic equipment

Technical Field

The disclosure relates to the technical field of semiconductors, and in particular relates to a manufacturing method of a semiconductor device, the semiconductor device and electronic equipment.

Background

Currently, a dynamic random access memory (Dynamic Random Access Memory, DRAM) structure formed by a Channel-All-Around structure or a planar semiconductor structure has a large number of metal layers, generally five layers, and is affected by the number of metal layers, so that the internal stress of the existing DRAM structure is large and easy to fail.

Disclosure of Invention

The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

In order to overcome the problems in the related art, the present disclosure provides a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus.

Embodiments of the present disclosure provide a semiconductor device including: a substrate; a vertical ring channel type transistor disposed on the substrate, the vertical ring channel type transistor including a gate electrode, a first gate oxide layer surrounding the gate electrode, a first channel layer surrounding the first gate oxide layer, a first source layer in contact with a bottom end of the first channel layer, and a first drain layer in contact with a top end of the first channel layer; the planar transistor is arranged on the vertical annular channel transistor and comprises a second gate oxide layer covering the first drain electrode layer, a second channel layer covering the second gate oxide layer, a second source electrode layer contacted with one side of the second channel layer and a second drain electrode layer contacted with the other side of the second channel layer, wherein the first drain electrode layer forms a grid electrode of the planar transistor.

According to some embodiments of the disclosure, the second source layer covers a portion of the top surface of one side of the second channel layer, the second drain layer covers a portion of the top surface of the other side of the second channel layer, and a predetermined distance is provided between the second source layer and the second drain layer.

According to some embodiments of the present disclosure, the semiconductor device further includes an oxide semiconductor material layer disposed between the first source layer and the first drain layer, the second gate oxide layer further covers the exposed top surface of the oxide semiconductor material layer, and the second source layer and the second drain layer are both located in regions corresponding to the exposed top surface of the oxide semiconductor material layer.

According to some embodiments of the present disclosure, the area of the first drain layer is smaller than the area of the first source layer, and a projection of the first drain layer onto the first source layer is located within an outer contour of the first source layer.

According to some embodiments of the present disclosure, a top surface of the oxide semiconductor material layer, which is covered by the second gate oxide layer, is lower than a top surface of the oxide semiconductor material layer, which is covered by the first drain layer.

According to some embodiments of the present disclosure, the semiconductor device further includes a channel hole penetrating the first drain layer and a bottom surface of the channel hole being located between a top surface and a bottom surface of the first source layer, the first channel layer covering the side surfaces and the bottom surface of the channel hole.

According to some embodiments of the present disclosure, the semiconductor device further includes a first bit line, a first word line, a second bit line, and a second word line, wherein the first bit line is co-layer with and in contact with the first source layer; the first word line is connected with the grid electrode through a first through silicon via; the second bit line is arranged on the same layer as the second source electrode layer and is in contact with the second source electrode layer, and the second word line is connected with the second drain electrode layer through a second silicon through hole; or the second bit line is connected with the second source electrode layer through a third through silicon via, and the second word line is arranged in the same layer as the second drain electrode layer and is contacted with the second drain electrode layer.

According to some embodiments of the present disclosure, the first bit line is parallel to the first word line and disposed at an angle to the second bit line, and the second word line is parallel to the second bit line and disposed at an angle to the first word line; the first word line is located between the second bit line and the second word line.

In a second aspect of the embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, the method for manufacturing a semiconductor device including: providing a substrate; forming a vertical ring channel type transistor on the substrate, the vertical ring channel type transistor including a gate electrode, a first gate oxide layer surrounding the gate electrode, a first channel layer surrounding the first gate oxide layer, a first source layer in contact with a bottom end of the first channel layer, and a first drain layer in contact with a top end of the first channel layer; and forming a planar transistor on the vertical ring channel transistor, wherein the planar transistor comprises a second gate oxide layer covering the first drain electrode layer, a second channel layer covering the second gate oxide layer, a second source electrode layer contacted with one side of the second channel layer and a second drain electrode layer contacted with the other side of the second channel layer, and the first drain electrode layer forms a grid electrode of the planar transistor.

According to some embodiments of the present disclosure, the forming a vertical ring channel transistor on the substrate includes: sequentially stacking a first dielectric layer, a first source electrode layer, a second dielectric layer, a first drain electrode layer and a third dielectric layer on the substrate; forming a channel hole, wherein the channel hole penetrates through the third dielectric layer, the first drain electrode layer and the second dielectric layer and extends into the first source electrode layer; forming an unpatterned first channel layer, a first gate oxide layer and a gate electrode, wherein the first channel layer covers the top surface of the third dielectric layer, the side surface and the bottom surface of the channel hole, the first gate oxide layer covers the first channel layer, and the gate electrode covers the first gate oxide layer and fills a space surrounded by the first gate oxide layer in the channel hole; and performing grinding treatment on the top surface of the grid electrode to remove the third dielectric layer, part of the grid electrode, part of the first gate oxide layer and part of the first channel layer until the top surface of the first drain electrode layer is exposed, so as to obtain the first channel layer, the first gate oxide layer and the grid electrode.

According to some embodiments of the disclosure, the forming a planar transistor on the vertical ring channel transistor includes: patterning the first drain layer, leaving the first drain layer in the gate peripheral region; forming a second gate oxide layer, a second channel layer and an unpatterned conductive layer, wherein the second gate oxide layer covers the exposed top surface of the oxide semiconductor material layer, the side surface of the first drain layer and the top surface of the first drain layer, the second channel layer covers the second gate oxide layer, and the conductive layer covers the second channel layer; and removing a part of the conductive layer corresponding to the first drain electrode layer, wherein the conductive layer positioned at one side of the first drain electrode layer forms the second source electrode layer, and the conductive layer positioned at the other side of the first drain electrode layer forms the second drain electrode layer.

A third aspect of the embodiments of the present disclosure provides an electronic device including the above-described semiconductor device.

According to some embodiments of the disclosure, the electronic device comprises a smart phone, a computer, a tablet, an artificial intelligence wearable device, or an intelligent mobile terminal.

The technical scheme provided by the embodiment of the disclosure can comprise the following beneficial effects: the 2T0C structure of the zero capacitance of the two transistors is formed by combining the semiconductor device with the channel full-surrounding structure and the planar metal oxide semiconductor device, the grid electrode, the first source electrode layer, the second source electrode layer and the second drain electrode layer in the 2T0C structure respectively correspond to four metal layers, the internal stress of the semiconductor device is reduced by reducing the number of the metal layers, the possibility of failure of the semiconductor device is reduced, and meanwhile, the yield of the semiconductor device is improved; in addition, because the second source electrode layer, the second drain electrode layer and the second channel layer form a capacitor structure, the purpose of changing the area of the storage area can be achieved by adjusting the distance between the second source electrode layer and the second drain electrode layer, namely the length of the second channel layer, to change the capacitance.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic structural view of a semiconductor device according to an exemplary embodiment.

FIG. 2 is a schematic diagram illustrating a first word line location according to an example embodiment.

Fig. 3 is a flowchart illustrating a method of fabricating a semiconductor device according to an exemplary embodiment.

Fig. 4 is a flowchart illustrating a method of fabricating a semiconductor device according to an exemplary embodiment.

Fig. 5 is a flowchart illustrating a method of fabricating a semiconductor device according to an exemplary embodiment.

Fig. 6 is a schematic diagram illustrating a third dielectric layer position in a method for fabricating a semiconductor device according to an exemplary embodiment.

Fig. 7 is a schematic diagram showing a position of a channel hole in a method of manufacturing a semiconductor device according to an exemplary embodiment.

Fig. 8 is a schematic diagram showing a gate position in a method of manufacturing a semiconductor device according to an exemplary embodiment.

Fig. 9 is a schematic view of a first gate oxide layer structure in a method for fabricating a semiconductor device according to an exemplary embodiment.

Fig. 10 is a schematic view of a first drain layer structure in a method of fabricating a semiconductor device according to an exemplary embodiment.

Fig. 11 is a schematic view showing a structure of a conductive layer in a method of manufacturing a semiconductor device according to an exemplary embodiment.

Reference numerals

1. A substrate; 2. an oxide semiconductor material layer; 21. a first dielectric layer; 22. a second dielectric layer; 23. a third dielectric layer; 3. a first source layer; 31. a first bit line; 4. a first drain layer; 5. a channel hole; 6. a gate; 61. a first word line; 62. a first through silicon via; 7. a first channel layer; 71. a first gate oxide layer; 8. a conductive layer; 81. a second drain layer; 811. a second word line; 812. a second through silicon via; 82. a second source layer; 821. a second bit line; 83. a second channel layer; 84. and a second gate oxide layer.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be arbitrarily combined with each other.

As to the background art, currently, the dynamic random access memory structure formed by adopting a Channel-All-Around structure or a planar semiconductor structure has a large number of metal layers, generally five layers, and is influenced by the number of metal layers, so that the internal stress of the existing DRAM structure is large and easy to fail.

Based on the semiconductor device and the manufacturing method of the semiconductor device, a 2T0C structure with zero capacitance of two transistors is formed by combining a channel fully-surrounding structure semiconductor and a planar metal oxide semiconductor device, and a grid electrode, a first source electrode layer, a second source electrode layer and a second drain electrode layer in the 2T0C structure correspond to four metal layers respectively; in addition, because the second source electrode layer, the second drain electrode layer and the second channel layer form a capacitor structure, the purpose of changing the area of the storage area can be achieved by adjusting the distance between the second source electrode layer and the second drain electrode layer, namely the length of the second channel layer, to change the capacitance.

Exemplary embodiments of the present disclosure provide a method for manufacturing a semiconductor device, and an electronic apparatus, as shown in fig. 1, fig. 1 is a schematic structural diagram of a semiconductor device according to an exemplary embodiment; FIG. 2 is a schematic diagram illustrating a first word line location; fig. 3 to 5 are flowcharts illustrating a method of fabricating a semiconductor device according to an exemplary embodiment; fig. 6 is a schematic diagram showing a third dielectric layer position in a method for manufacturing a semiconductor device according to an exemplary embodiment; fig. 7 is a schematic diagram showing the position of a channel hole in a method of manufacturing a semiconductor device according to an exemplary embodiment; fig. 8 is a schematic diagram showing a gate position in a method of manufacturing a semiconductor device according to an exemplary embodiment; fig. 9 is a schematic view showing a first gate oxide layer structure in a method of manufacturing a semiconductor device according to an exemplary embodiment; fig. 10 is a schematic view of a first drain layer structure in a method of fabricating a semiconductor device according to an exemplary embodiment; fig. 11 is a schematic view showing a structure of a conductive layer in a method of manufacturing a semiconductor device according to an exemplary embodiment. The following is explained in connection with fig. 1 to 11.

The following description is given for the purpose of facilitating understanding of the present embodiment by those skilled in the art, and is not intended to limit the scope of the present invention to the particular embodiments described below.

Referring to fig. 1 and 2, a semiconductor device according to an exemplary embodiment of the present disclosure includes: a substrate 1; a vertical ring channel type transistor disposed on the substrate 1, the vertical ring channel type transistor including a gate electrode 6, a first gate oxide layer 71 surrounding the gate electrode 6, a first channel layer 7 surrounding the first gate oxide layer 71, a first source layer 3 in contact with a bottom end of the first channel layer 7, and a first drain layer 4 in contact with a top end of the first channel layer 7; a planar transistor disposed on the vertical ring channel transistor, the planar transistor including a second gate oxide layer 84 covering the first drain layer 4, a second channel layer 83 covering the second gate oxide layer 84, a second source layer 82 contacting one side of the second channel layer 83, and a second drain layer 81 contacting the other side of the second channel layer 83, wherein the first drain layer 4 constitutes the gate 6 of the planar transistor.

For example, referring to fig. 1 and 2, a substrate 1 serves as a supporting member of a semiconductor device for supporting other members provided thereon. The substrate 1 material may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide. The first source layer 3 and the first drain layer 4 are stacked above the substrate 1, the top surfaces of the first channel layer 7, the first gate oxide layer 71 and the gate electrode 6 are all flush with the first drain layer 4, and the first channel layer 7, the first gate oxide layer 71 and the gate electrode 6 all extend into the first source layer 3, wherein the first gate oxide layer 71 covers the side wall and the bottom surface of the gate electrode 6, the first channel layer 7 covers the side wall and the bottom surface of the first gate oxide layer 71, and the bottom surface of the first channel layer 7 is located between the top surface of the first source layer 3 and the bottom surface of the first source layer 3.

The second gate oxide layer 84 and the second channel layer 83 are stacked over the first drain layer 4, the second gate oxide layer 84 covers the first drain layer 4 in a vertical direction, and the second channel layer 83 covers the second gate oxide layer 84 in a vertical direction. The second source layer 82 and the second drain layer 81 are respectively disposed on two sides of the top surface of the second channel layer 83, a space for exposing a part of the second channel layer 83 is left between the second source layer 82 and the second drain layer 81, the top surface of the gate 6 is exposed from the area between the second source layer 82 and the second drain layer 81, and the second source layer 82 and the second drain layer 81 both cover a part of the second channel layer 83 corresponding to the second source layer 82 and the second drain layer 81 in the vertical direction.

In this embodiment, a 2T0C structure with zero capacitance of two transistors is formed by combining a semiconductor device with a channel full-surrounding structure and a planar metal oxide semiconductor device, and the gate electrode 6, the first source electrode layer 3, the second source electrode layer 82 and the second drain electrode layer 81 in the 2T0C structure respectively correspond to four metal layers, so that the internal stress of the semiconductor device is reduced by reducing the number of metal layers, the possibility of failure of the semiconductor device is reduced, and the yield of the semiconductor device is improved; in addition, since the second source layer 82, the second drain layer 81 and the second channel layer 83 form a capacitor structure, the size of the storage area can be changed by adjusting the distance between the second source layer 82 and the second drain layer 81, i.e. the length of the second channel layer 83.

In an exemplary embodiment of the present disclosure, referring to fig. 1, the second source layer 82 covers a portion of the top surface of one side of the second channel layer 83, the second drain layer 81 covers a portion of the top surface of the other side of the second channel layer 83, and a predetermined distance is provided between the second source layer 82 and the second drain layer 81.

Illustratively, the second source layer 82 extends towards the gate electrode 6 and such that a portion of the second source layer 82 covers a portion of the second channel layer 83 that overlies the first drain layer 4; the second drain layer 81 extends towards the gate electrode 6 and has a portion of the second drain layer 81 covering a portion of the second channel layer 83 overlying the first drain layer 4. The second source layer 82 and the second drain layer 81 are disposed on both sides of the gate electrode 6, and the top surface of the gate electrode 6 and a portion of the top surface of the second channel layer 83 are exposed from an area defined by a predetermined distance D between the second source layer 82 and the second drain layer 81.

In this embodiment, the second source layer 82, the second drain layer 81 and the second channel layer 83 may form a capacitor structure, so that the size of the storage area can be changed by adjusting the preset distance D between the second source layer 82 and the second drain layer 81, i.e. the length of the second channel layer 83. For example, when the semiconductor device is required to have a longer information storage time, the area of the second channel layer 83 exposed from between the second source layer 82 and the second drain layer 81 may be increased by increasing the predetermined distance D between the second source layer 82 and the second drain layer 81, and the longer information storage time may be obtained by increasing the capacitance.

In an exemplary embodiment of the present disclosure, referring to fig. 1, the semiconductor device further includes an oxide semiconductor material layer 2 disposed between the first source layer 3 and the first drain layer 4, the second gate oxide layer 84 further covers the exposed top surface of the oxide semiconductor material layer 2, and the second source layer 82 and the second drain layer 81 are both located at regions corresponding to the exposed top surface of the oxide semiconductor material layer 2.

The oxide semiconductor material layer 2 is a material dielectric layer, and the oxide semiconductor material layer 2 has two layers, one oxide semiconductor material layer 2 covers the top surface of the substrate 1, and the first source electrode layer 3 covers the top surface of the oxide semiconductor material layer 2. Another oxide semiconductor material layer 2 covers the top surface of the first source layer 3, and a first drain layer 4 covers the top surface of this oxide semiconductor material layer 2. The oxide semiconductor material layer 2 separates the first source layer 3 from the substrate 1 and the first source layer 3 from the first drain layer 4.

In this embodiment, the first drain layer 4 covers a part of the top surface of the oxide semiconductor material layer 2, and the second gate oxide layer 84 covers the top surface of the oxide semiconductor material layer 2, which is not covered by the first drain layer 4, i.e. the second gate oxide layer 84 is stepped at the boundary between the second drain layer 81 and the oxide semiconductor material layer 2.

In an exemplary embodiment of the present disclosure, referring to fig. 1, the area of the first drain layer 4 is smaller than the area of the first source layer 3, and the projection of the first drain layer 4 onto the first source layer 3 is located within the outer contour of the first source layer 3.

Illustratively, the first source layer 3 entirely covers the top surface of the oxide semiconductor material layer 2 covering the top surface of the substrate 1 in the vertical direction, the first drain layer 4 is located at a middle position of the top surface of the oxide semiconductor material layer 2 covering the top surface of the first source layer 3, and the first drain layer 4 covers the top surface of the middle region of the oxide semiconductor material layer 2, and the top surface of the edge region of the oxide semiconductor material layer 2 is exposed from the edge of the first drain layer 4. The second gate oxide layer 84 covering the top surface of the first drain layer 4 extends down to the top surface of the oxide semiconductor material layer 2 at the edge of the first drain layer 4 and covers the top surface of the edge portion of the oxide semiconductor material layer 2; similarly, the second channel layer 83 covering the top surface of the second gate oxide layer 84 also extends downward at the edge of the second drain layer 81 to completely cover the second gate oxide layer 84.

In an exemplary embodiment of the present disclosure, referring to fig. 1, the top surface of the oxide semiconductor material layer 2, which is covered by the second gate oxide layer 84, is lower than the top surface of the region covered by the first drain layer 4.

Illustratively, the edge physical thickness of the oxide semiconductor material layer 2 covering the top surface of the first source layer 3 and covering the first drain layer 4 is smaller than the physical thickness of the intermediate position. I.e. the top surface of the oxide semiconductor material layer 2 is stepped at the edge of the first drain layer 4.

In an exemplary embodiment of the present disclosure, referring to fig. 1, the semiconductor device further includes a channel hole 5, the channel hole 5 penetrates the first drain layer 4 and a bottom surface of the channel hole 5 is located between the top surface and the bottom surface of the first source layer 3, and the first channel layer 7 covers the side surfaces and the bottom surface of the channel hole 5.

Illustratively, the channel hole 5 extends from the top surface of the first drain layer 4 toward the first source layer 3, and the bottom end of the channel hole 5 extends into the first source layer 3. The channel hole 5 is used for accommodating the grid electrode 6, the first channel layer 7 and the first grid oxide layer 71 are of hollow solid-bottom cylindrical structures, wherein the first channel layer 7 covers the inner wall of the channel hole 5, the first grid oxide layer 71 covers the inner wall of the first channel layer 7, the grid electrode 6 is located in the area surrounded by the first grid oxide layer 71 and fills the space surrounded by the first grid oxide layer 71, and the top surfaces of the first grid oxide layer 71, the first channel layer 7, the grid electrode 6 and the first drain electrode layer 4 are level in the horizontal direction.

In an exemplary embodiment of the present disclosure, referring to fig. 1 and 2, the semiconductor device further includes a first bit line 31, a first word line 61, a second bit line 821, and a second word line 811, wherein the first bit line 31 is disposed in the same layer as the first source layer 3 and is in contact with the first source layer 3; the first word line 61 is connected to the gate electrode 6 through a first through silicon via 62; the second bit line 821 is arranged in the same layer as the second source layer 82 and is in contact with the second source layer 82, and the second word line 811 is connected to the second drain layer 81 through the second through silicon via 812; alternatively, the second bit line 821 is connected to the second source layer 82 through a third through-silicon via, and the second word line 811 is arranged in the same layer as the second drain layer 81 and is in contact with the second drain layer 81.

Illustratively, the first bit line 31 penetrates the first source layer 3 in the horizontal direction, the first through silicon via 62 penetrating the second channel layer 83 and the second gate oxide layer 84 in the vertical direction is formed on the second channel layer 83 at a position corresponding to the gate electrode 6, the first through silicon via 62 is coaxially disposed with the channel hole 5, and the inner wall of the first through silicon via 62 is flush with the inner wall of the first gate oxide layer 71 in the vertical direction, and the first word line 61 is connected to the first gate electrode 6 through the first through silicon via 62. The second bit line 821 penetrates the second source layer 82 in the horizontal direction, the second drain layer 81 is provided with a second through silicon via 812, and the second word line 811 is connected to the second drain layer 81 through the second through silicon via 812.

It should be understood that the second bit line 821 described above penetrates the second source layer 82 in the horizontal direction, the second through silicon via 812 is disposed on the second drain layer 81, the second word line 811 is connected to the second drain layer 81 through the second through silicon via 812, and in other embodiments, the second source layer 82 may also be used as a drain, while the second drain layer 81 may be used as a source, and similarly, the second bit line 821 connected to the second source layer 82 may be used as a word line, while the second word line 811 connected to the second drain layer 81 may be used as a bit line.

In this embodiment, the first bit line 31, the first word line 61, the second bit line 821 and the second word line 811 are four metal layers of the semiconductor device, and the semiconductor device is formed into a 2T0C structure with zero capacitance of two transistors by combining the semiconductor device with a channel full-surrounding structure and the planar metal oxide semiconductor device, and the gate electrode 6, the first source electrode layer 3, the second source electrode layer 82 and the second drain electrode layer 81 in the 2T0C structure correspond to the four metal layers respectively, so that the internal stress of the semiconductor device is reduced by reducing the number of metal layers, the possibility of failure of the semiconductor device is reduced, and the yield of the semiconductor device is improved.

In an exemplary embodiment of the present disclosure, referring to fig. 2, the first bit line 31 is parallel to the first word line 61 and disposed at an angle to the second bit line 821, and the second word line 811 is parallel to the second bit line 821 and disposed at an angle to the first word line 61; the first word line 61 is located between the second bit line 821 and the second word line 811.

Illustratively, the first bit line 31, the first word line 61, the second bit line 821, and the second word line 811 are distributed in four layers of different heights, wherein the projection of the first bit line 31 in the vertical direction is perpendicular to the projection of the first word line 61 in the vertical direction, and the projection of the second word line 811 in the vertical direction is perpendicular to the projection of the second bit line 821 in the vertical direction.

In a second aspect of the embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, and referring to fig. 3, the method for manufacturing a semiconductor device includes:

s100, providing a substrate.

For example, referring to fig. 1 and 2, a substrate 1 serves as a supporting member of a semiconductor device for supporting other members provided thereon. The substrate 1 material may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide.

S200, forming a vertical ring channel transistor on a substrate, the vertical ring channel transistor including a gate electrode, a first gate oxide layer surrounding the gate electrode, a first channel layer surrounding the first gate oxide layer, a first source layer in contact with a bottom end of the first channel layer, and a first drain layer in contact with a top end of the first channel layer.

Illustratively, referring to fig. 1 and 2, the first source layer 3 and the first drain layer 4 are stacked over the substrate 1, the first channel layer 7, the first gate oxide layer 71, and the top surface of the gate electrode 6 are all flush with the first drain layer 4, and the first channel layer 7, the first gate oxide layer 71, and the gate electrode 6 all extend into the first source layer 3, wherein the first gate oxide layer 71 covers the sidewall and bottom surface of the gate electrode 6, the first channel layer 7 covers the sidewall and bottom surface of the first gate oxide layer 71, and the bottom surface of the first channel layer 7 is located between the top surface of the first source layer 3 and the bottom surface of the first source layer 3.

And S300, forming a planar transistor on the vertical annular channel type transistor, wherein the planar transistor comprises a second gate oxide layer covering the first drain electrode layer, a second channel layer covering the second gate oxide layer, a second source electrode layer contacted with one side of the second channel layer and a second drain electrode layer contacted with the other side of the second channel layer, and the first drain electrode layer forms a grid electrode of the planar transistor.

Illustratively, a second gate oxide layer 84 and a second channel layer 83 are stacked over the first drain layer 4, the second gate oxide layer 84 vertically covering the first drain layer 4, and the second channel layer 83 vertically covering the second gate oxide layer 84. The second source layer 82 and the second drain layer 81 are respectively disposed on two sides of the top surface of the second channel layer 83, a space for exposing a part of the second channel layer 83 is left between the second source layer 82 and the second drain layer 81, the top surface of the gate 6 is exposed from the area between the second source layer 82 and the second drain layer 81, and the second source layer 82 and the second drain layer 81 both cover a part of the second channel layer 83 corresponding to the second source layer 82 and the second drain layer 81 in the vertical direction.

In this embodiment, a 2T0C structure with zero capacitance of two transistors is formed by combining a semiconductor device with a channel full-surrounding structure and a planar metal oxide semiconductor device, and the gate electrode 6, the first source electrode layer 3, the second source electrode layer 82 and the second drain electrode layer 81 in the 2T0C structure respectively correspond to four metal layers, so that the internal stress of the semiconductor device is reduced by reducing the number of metal layers, the possibility of failure of the semiconductor device is reduced, and the yield of the semiconductor device is improved; in addition, since the second source layer 82, the second drain layer 81 and the second channel layer 83 form a capacitor structure, the size of the storage area can be changed by adjusting the distance between the second source layer 82 and the second drain layer 81, i.e. the length of the second channel layer 83.

In an exemplary embodiment of the present disclosure, referring to fig. 4, step S200 of forming a vertical ring channel transistor on a substrate specifically includes:

s210, sequentially stacking a first dielectric layer, a first source electrode layer, a second dielectric layer, a first drain electrode layer and a third dielectric layer on a substrate.

For example, referring to fig. 6, the first dielectric layer 21, the second dielectric layer 22 and the third dielectric layer 23 are oxide semiconductor material layers, the first dielectric layer 21 is first deposited on the top surface of the substrate 1 by a vapor deposition process (or an atomic layer deposition process), and then the first source layer 3, the second dielectric layer 22, the first drain layer 4 and the third dielectric layer 23 are sequentially deposited by the same process (or different processes), so that the first source layer 3 formed by deposition in this step covers the top surface of the first dielectric layer 21, the second dielectric layer 22 covers the top surface of the first source layer 3, the first drain layer 4 covers the top surface of the second dielectric layer 22, and the third dielectric layer 23 covers the top surface of the first drain layer 4.

S220, forming a channel hole, wherein the channel hole penetrates through the third dielectric layer, the first drain electrode layer and the second dielectric layer and extends into the first source electrode layer.

For example, referring to fig. 7, a channel hole 5 is formed by sequentially penetrating the first drain layer 4 and the second dielectric layer 22 through the etching process on the top surface of the third dielectric layer 23 toward the first source layer 3, the opening of the channel hole 5 is located on the top surface of the third dielectric layer 23, the bottom end of the channel hole 5 extends into the first source layer 3, and the bottom end of the channel hole 5 is located at a position between the top surface of the first source layer 3 and the bottom surface of the first source layer 3.

And S230, forming an unpatterned first channel layer, a first gate oxide layer and a grid electrode, wherein the first channel layer covers the top surface of the third dielectric layer and the side surfaces and the bottom surface of the channel hole, the first gate oxide layer covers the first channel layer, and the grid electrode covers the first gate oxide layer and fills the space surrounded by the first gate oxide layer in the channel hole.

Illustratively, referring to fig. 8, a first channel material is deposited on the inner wall of the formed channel hole 5 and the top surface of the third dielectric layer 23 through an atomic layer deposition process (or a vapor deposition process), and the deposited first channel material covers the top surface of the third dielectric layer 23 and the inner wall of the channel layer and forms an unpatterned first channel layer 7; similarly, depositing a first gate oxide material on the unpatterned first channel layer 7 by an atomic layer deposition process (or a vapor deposition process) and forming an unpatterned first gate oxide layer 71, the first gate oxide layer 71 covering the top surface of the unpatterned first channel layer 7 above the third dielectric layer 23 and the inner wall of the first channel layer 7 within the channel hole 5; gate electrode 6 material is deposited on the unpatterned first gate oxide layer 71 by an atomic layer deposition process (or vapor deposition process) and unpatterned gate electrode 6 is formed, and gate electrode 6 covers the top surface of first gate oxide layer 71 over third dielectric layer 23 and fills the space of first gate oxide layer 71 around channel hole 5.

And S240, performing grinding treatment from the top surface of the grid electrode to remove the third dielectric layer, part of the grid electrode, part of the first grid oxide layer and part of the first channel layer until the top surface of the first drain electrode layer is exposed, so as to obtain the first channel layer, the first grid oxide layer and the grid electrode.

Illustratively, referring to fig. 9, the third dielectric layer 23, the gate electrode 6 above the third dielectric layer 23, the first gate oxide layer 71 above the third dielectric layer 23, and the first channel layer 7 above the third dielectric layer 23 are removed by a chemical mechanical polishing technique (or a mask etching technique), exposing the top surface of the first drain layer 4, and simultaneously exposing the top surfaces of the first channel layer 7, the first gate oxide layer 71, and the gate electrode 6, resulting in the first channel layer 7, the first gate oxide layer 71, and the gate electrode 6.

In an exemplary embodiment of the present disclosure, referring to fig. 5, step S300 of forming a planar transistor on a vertical ring channel transistor specifically includes:

s310, patterning the first drain electrode layer, and reserving the first drain electrode layer in the peripheral area of the grid electrode.

Illustratively, referring to fig. 10, the edge portion of the first drain layer 4 is patterned by an etching process to expose a portion of the top surface of the second dielectric layer 22 that is originally covered by the edge region of the first drain layer 4, and the remaining first drain layer 4 is located inside the region surrounded by the top surface of the second dielectric layer 22 and is disposed around the gate electrode 6.

In this embodiment, the etching process is used to pattern the first drain electrode layer 4 and remove part of the second dielectric layer 22 at the same time, so that the top surface of the second dielectric layer 22 is stepped at the edge of the first drain electrode layer 4.

S320, forming a second gate oxide layer, a second channel layer and an unpatterned conductive layer, wherein the second gate oxide layer covers the exposed top surface of the second dielectric layer, the side surface of the first drain electrode layer and the top surface of the first drain electrode layer, the second channel layer covers the second gate oxide layer, and the conductive layer covers the second channel layer.

Illustratively, referring to fig. 10 and 11, a second gate oxide material is deposited on the exposed portions of the top surface of the second dielectric layer 22, the exposed portions of the sidewalls of the first drain layer 4, and the top surface of the first drain layer 4 by an atomic layer deposition process (or a vapor deposition process) to form a second gate oxide layer 84 covering the exposed portions of the top surface of the second dielectric layer 22, the exposed portions of the sidewalls of the first drain layer 4, and the top surface of the first drain layer 4. Similarly, a second channel material is deposited on the top surface of the second gate oxide layer 84 by an atomic layer deposition process (or a vapor deposition process), forming a second channel layer 83 covering the top surface of the second gate oxide layer 84. Similarly, an unpatterned conductive layer 8 covering the top surface of the second channel layer 83 is formed by depositing a conductive material on the top surface of the second channel layer 83 by an atomic layer deposition process (or a vapor deposition process).

S330, removing a part of the conductive layer corresponding to the first drain electrode layer, wherein the conductive layer positioned at one side of the first drain electrode layer forms a second source electrode layer, and the conductive layer positioned at the other side of the first drain electrode layer forms a second drain electrode layer.

For example, referring to fig. 11 and 1, a portion of the conductive layer 8 over the first drain electrode is patterned by an etching process, such that the originally integrated conductive layer 8 forms the second source electrode layer 82 and the second drain electrode layer 81 that are separated at both sides of the gate electrode 6.

In this embodiment, when patterning the conductive layer 8, the edge of the first drain layer 4 is used as a boundary, and all the conductive layer 8 above the first drain layer 4 is selectively removed. In other embodiments, a portion of the conductive layer 8 above the edge of the first drain layer 4 may also be left, such that the second source layer 82 and the second drain layer 81 are formed to cover a portion of the second channel layer 83 above the edge of the first drain. When the conductive layer 8 is formed on the top surface of the second channel layer 83 by a deposition process and a portion of the conductive layer 8 above the first drain layer 4 is removed by taking the edge of the first drain layer 4 as a boundary, the edge of the formed conductive layer 8 is close to the step surface of the second channel layer 83 due to the low thickness of the second channel layer 83 and the second gate oxide layer 84, a vertical gap exists between the conductive layer 8 and the second channel layer 83, conductive material powder or other impurities easily fall into the gap at the step bending surface of the second channel layer 83 due to the action of gravity, so that the bonding degree between the conductive layer 8 and the second channel layer 83 is reduced, and the performance of the formed semiconductor device is weakened. After the part of the conductive layer 8 above the edge of the first drain layer 4 is reserved, the edge of the finally formed conductive layer 8 is far away from the step surface of the second channel layer 83, the gap at the edge of the conductive layer 8 is in the horizontal direction, and the gap has a longer length along with the reserved degree of the conductive layer 8 above the edge of the first drain layer 4, so that the gap at the juncture of the first source layer 3 and the first drain layer 4 and the second channel layer 83 can be ensured to be clean, impurities are reduced to enter the gap, and the possibility of influencing the performance of the finally formed semiconductor device is further reduced.

In an exemplary embodiment of the disclosure, referring to fig. 1, after removing a portion of a region of the conductive layer corresponding to the first drain layer, the second channel layer and the second gate oxide layer are patterned to expose the top surface of the gate electrode in step S330.

Illustratively, referring to fig. 11 and 1, after the first source layer 3 and the first drain layer 4 are formed, the second channel layer 83 and the second gate oxide layer 84 over the gate electrode 6 are patterned by an etching process, exposing the top surface of the gate electrode 6.

A third aspect of the embodiments of the present disclosure provides an electronic device including the above semiconductor device.

Illustratively, the electronic device is a smart phone. In other embodiments, the electronic device may also be a computer or tablet or artificial intelligence wearable device or intelligent mobile terminal.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (13)

1. A semiconductor device, the semiconductor device comprising:

a substrate;

a vertical ring channel type transistor disposed on the substrate, the vertical ring channel type transistor including a gate electrode, a first gate oxide layer surrounding the gate electrode, a first channel layer surrounding the first gate oxide layer, a first source layer in contact with a bottom end of the first channel layer, and a first drain layer in contact with a top end of the first channel layer;

the planar transistor is arranged on the vertical annular channel transistor and comprises a second gate oxide layer covering the first drain electrode layer, a second channel layer covering the second gate oxide layer, a second source electrode layer contacted with one side of the second channel layer and a second drain electrode layer contacted with the other side of the second channel layer, wherein the first drain electrode layer forms a grid electrode of the planar transistor.

2. The semiconductor device according to claim 1, wherein the second source layer covers a portion of a top surface of one side of the second channel layer, the second drain layer covers a portion of a top surface of the other side of the second channel layer, and a predetermined distance is provided between the second source layer and the second drain layer.

3. The semiconductor device of claim 1, further comprising an oxide semiconductor material layer disposed between the first source layer and the first drain layer, the second gate oxide layer further covering an exposed top surface of the oxide semiconductor material layer, the second source layer and the second drain layer both being located in regions corresponding to the exposed top surface of the oxide semiconductor material layer.

4. The semiconductor device of claim 3, wherein an area of the first drain layer is smaller than an area of the first source layer, and a projection of the first drain layer onto the first source layer is within an outer contour of the first source layer.

5. The semiconductor device of claim 3, wherein a top surface of the oxide semiconductor material layer where the second gate oxide layer covers is lower than a top surface of the oxide semiconductor material layer where the first drain layer covers.

6. The semiconductor device of claim 1, further comprising a channel hole extending through the first drain layer and having a bottom surface between the top and bottom surfaces of the first source layer, the first channel layer covering the sides and bottom surfaces of the channel hole.

7. The semiconductor device of claim 1, further comprising a first bit line, a first word line, a second bit line, and a second word line, wherein,

the first bit line is arranged on the same layer as the first source electrode layer and is contacted with the first source electrode layer;

the first word line is connected with the grid electrode through a first through silicon via;

the second bit line is arranged on the same layer as the second source electrode layer and is in contact with the second source electrode layer, and the second word line is connected with the second drain electrode layer through a second silicon through hole; or the second bit line is connected with the second source electrode layer through a third through silicon via, and the second word line is arranged in the same layer as the second drain electrode layer and is contacted with the second drain electrode layer.

8. The semiconductor device of claim 7, wherein the first bit line is parallel to the first word line and is disposed at an angle to the second bit line, and wherein the second word line is parallel to the second bit line and is disposed at an angle to the first word line;

the first word line is located between the second bit line and the second word line.

9. A method of fabricating a semiconductor device, the method comprising:

providing a substrate;

forming a vertical ring channel type transistor on the substrate, the vertical ring channel type transistor including a gate electrode, a first gate oxide layer surrounding the gate electrode, a first channel layer surrounding the first gate oxide layer, a first source layer in contact with a bottom end of the first channel layer, and a first drain layer in contact with a top end of the first channel layer;

and forming a planar transistor on the vertical ring channel transistor, wherein the planar transistor comprises a second gate oxide layer covering the first drain electrode layer, a second channel layer covering the second gate oxide layer, a second source electrode layer contacted with one side of the second channel layer and a second drain electrode layer contacted with the other side of the second channel layer, and the first drain electrode layer forms a grid electrode of the planar transistor.

10. The method of manufacturing a semiconductor device according to claim 9, wherein the forming a vertical ring channel transistor on the substrate comprises:

sequentially stacking a first dielectric layer, a first source electrode layer, a second dielectric layer, a first drain electrode layer and a third dielectric layer on the substrate;

forming a channel hole, wherein the channel hole penetrates through the third dielectric layer, the first drain electrode layer and the second dielectric layer and extends into the first source electrode layer;

forming an unpatterned first channel layer, a first gate oxide layer and a gate electrode, wherein the first channel layer covers the top surface of the third dielectric layer, the side surface and the bottom surface of the channel hole, the first gate oxide layer covers the first channel layer, and the gate electrode covers the first gate oxide layer and fills a space surrounded by the first gate oxide layer in the channel hole;

and performing grinding treatment on the top surface of the grid electrode to remove the third dielectric layer, part of the grid electrode, part of the first gate oxide layer and part of the first channel layer until the top surface of the first drain electrode layer is exposed, so as to obtain the first channel layer, the first gate oxide layer and the grid electrode.

11. The method of manufacturing a semiconductor device according to claim 10, wherein forming a planar transistor over the vertical ring channel transistor comprises:

patterning the first drain layer, leaving the first drain layer in the gate peripheral region;

forming a second gate oxide layer, a second channel layer and an unpatterned conductive layer, wherein the second gate oxide layer covers the exposed top surface of the oxide semiconductor material layer, the side surface of the first drain layer and the top surface of the first drain layer, the second channel layer covers the second gate oxide layer, and the conductive layer covers the second channel layer;

and removing a part of the conductive layer corresponding to the first drain electrode layer, wherein the conductive layer positioned at one side of the first drain electrode layer forms the second source electrode layer, and the conductive layer positioned at the other side of the first drain electrode layer forms the second drain electrode layer.

12. An electronic device, characterized in that the electronic device comprises the semiconductor device according to any one of claims 1 to 8.

13. The electronic device of claim 12, wherein the electronic device comprises a smart phone, a computer, a tablet computer, an artificial intelligence wearable device, or a smart mobile terminal.