CN117459052A - Output circuit of I2C interface circuit and I2C interface circuit - Google Patents

Output circuit of I2C interface circuit and I2C interface circuit Download PDF

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Publication number
CN117459052A
CN117459052A CN202311518340.9A CN202311518340A CN117459052A CN 117459052 A CN117459052 A CN 117459052A CN 202311518340 A CN202311518340 A CN 202311518340A CN 117459052 A CN117459052 A CN 117459052A
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voltage
module
nmos tube
output
intermediate node
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CN117459052B (en
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迟明
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Gl Microelectronics Inc
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Gl Microelectronics Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018557—Coupling arrangements; Impedance matching circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)

Abstract

The invention relates to the technical field of integrated circuits, and provides an output circuit of an I2C interface circuit and the I2C interface circuit, wherein the output circuit comprises: the grid electrode of the first NMOS tube is connected with the output end of an isolator in the I2C interface circuit, the drain electrode of the first NMOS tube is connected with the I2C data end, and the source electrode of the first NMOS tube, the regulating end of the voltage regulating module and the input end of the voltage sensing module are respectively connected to the intermediate node; the output end of the voltage sensing module is connected with the control end of the voltage regulating module and is used for sensing the voltage change of the intermediate node and controlling the opening and closing of the voltage regulating module according to the voltage change of the intermediate node; and when the first NMOS tube is conducted, the voltage of the intermediate node is a low-level threshold value, and when the voltage regulating module is started, the voltage value of the intermediate node is regulated to the low-level threshold value. The problem of inaccurate output signals caused by bus operation of other I2C bus devices can be avoided, and the reliability of the I2C interface circuit is improved.

Description

Output circuit of I2C interface circuit and I2C interface circuit
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to an output circuit of an I2C interface circuit and an I2C interface circuit.
Background
In the prior art, an I2C interface circuit with single-channel bidirectional transmission consists of two digital isolation channels with reverse transmission, each digital isolation channel has an input circuit, an isolator and an output circuit, and the digital isolation channels share an isolator.
As shown in fig. 1, when the signal transmission direction is from side1 to side2, the input module 1 on side1 operates, the voltage of the data terminal SDA1 is compared with the low level threshold VREF1, and the voltage of the data terminal SDA1 is identified as high when the amplitude is higher than the low level threshold VREF1 and as low when the amplitude is lower than the low level threshold VREF1. The signal output by the input module 1 is encoded and decoded by the isolator IB, specifically, the isolator IB includes an encoder, an isolation circuit and a decoder, and the encoder and the decoder are respectively disposed on the side1 side and the side2 side. When the input module 1 outputs a low level, the high level is output through the inverter in the output module 1, the NMOS tube M0 is conducted, and when the input module 1 outputs a high level, the low level is output through the inverter in the output module 1, and the NMOS tube M0 is turned off.
When the channel direction is from side2 to side1, the output module 2 on the side1 works, when the RX_OUT signal is low level, the NMOS tube M1 is turned off, and the data end SDA1 is pulled to high level by the pull-up resistor RUP 1; when the RX_OUT signal is high, the NMOS transistor M1 is turned on, and the voltage at the point A is equal to the low level threshold VREF2 (VREF 2> VREF 1) due to the voltage boosting effect of the diode D1, i.e., the voltage at the data terminal SDA1 is VREF2.
In the prior art, when the voltage of the data terminal SDA2 on the side2 is at a low level, the rx_out signal input by the NMOS transistor M1 is at a high level, and the output level amplitude of the output module 2 on the side1 is at VREF2.VREF2 is greater than the low level threshold VREF1 of the input module on side1, thereby avoiding the problem of level latch-up.
However, in practical applications, the I2C bus isolation circuit and other devices are connected to the I2C bus in a hanging manner, when the output module outputs a low level signal, the other devices pull the I2C bus low and then release the signal, which results in an overshoot of the voltage at the data terminal SDA1 in fig. 1, and the simulated waveform is shown in fig. 2, where the overshoot voltage is 1.36V, and far exceeds the high level threshold of the output module, so that the original low level output signal is erroneously identified as high level, thereby affecting the reliability of the I2C bus isolation circuit.
Disclosure of Invention
The invention is used for solving the problem that the I2C interface circuit has poor reliability because the I2C bus can generate overshoot phenomenon when other devices on the I2C bus are pulled down and released in the prior art and the low level output by the output circuit of the I2C interface circuit can be mistaken for the high level.
In order to solve the above technical problem, an aspect of the present invention provides an output circuit of an I2C interface circuit, the output circuit comprising: the device comprises a first NMOS tube, a voltage sensing module and a voltage regulating module;
the grid electrode of the first NMOS tube is connected with the output end of an isolator in the I2C interface circuit, the drain electrode of the first NMOS tube is connected with an I2C data end, and the source electrode of the first NMOS tube, the regulating end of the voltage regulating module and the input end of the voltage sensing module are respectively connected to intermediate nodes;
the output end of the voltage sensing module is connected with the control end of the voltage regulating module and is used for sensing the voltage change of the intermediate node and controlling the voltage regulating module to be turned on and off according to the voltage change of the intermediate node;
and when the first NMOS tube is conducted, the voltage of the intermediate node is a low-level threshold value, and when the voltage regulating module is started, the voltage regulating module is used for regulating the voltage value of the intermediate node to the low-level threshold value.
In a further embodiment of the present invention, the voltage sensing module includes: the positive input end of the comparator is connected with the intermediate node, the negative input end of the comparator is connected with a low-level threshold value, and the output end of the comparator is connected with the control end of the voltage regulating module;
when the voltage of the intermediate node is greater than a low level threshold, starting the voltage regulating module;
and when the voltage of the intermediate node is smaller than or equal to a low level threshold value, closing the voltage regulating module.
In a further embodiment of the present invention, the voltage adjustment module includes: the device comprises a feedback module, a pull-up module and an adjusting controller, wherein the adjusting controller is provided with a control end, a first adjusting end and a second adjusting end;
the output end of the pull-up module is connected with the control end of the adjusting controller and is used for starting or closing the adjusting controller according to the feedback voltage output by the feedback module, so as to adjust the voltage value of the intermediate node to a low level threshold value;
the input end of the feedback module is connected with the output end of the comparator and the first regulating end of the regulating controller, and the output end of the feedback module is connected with the input end of the pull-up module and is used for collecting the voltage between the output end of the comparator and the first regulating end;
the first adjusting point of the adjusting controller is connected with the grounding end, the second adjusting point of the adjusting controller is connected with the intermediate node, and the control end of the adjusting controller is connected with the output end of the comparator;
the comparator and the pull-up module can both open or close the regulating controller.
In a further embodiment of the present invention, the adjustment controller includes at least: the first adjusting end, the second adjusting end and the control end are respectively a source electrode, a drain electrode and a grid electrode of the second NMOS tube.
In a further embodiment of the present invention, the feedback module includes: a third NMOS tube and a bias unit;
the grid electrode of the third NMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the third NMOS tube is connected with the source electrode of the second NMOS tube, and the drain electrode of the third NMOS tube is connected with the input end of the pull-up module and the biasing unit;
the bias unit is used for providing bias current for the third NMOS tube.
In a further embodiment of the present invention, the bias unit includes at least: a first PMOS tube;
the grid electrode of the first PMOS tube is connected with bias voltage, the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is connected with the drain electrode of the third NMOS tube.
In a further embodiment of the present invention, the pull-up module includes: the second PMOS tube and the pull-up resistor;
the grid electrode of the second PMOS tube is connected with the drain electrode of the third NMOS tube, the drain electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, and the source electrode of the second PMOS tube is connected with one end of the pull-up resistor;
the other end of the pull-up resistor is connected with a power supply.
In a further embodiment of the present invention, the method further includes: and the voltage stabilizing capacitor is connected between the drain electrode of the third NMOS and the grounding end.
A second aspect of the present invention provides a unidirectional transport I2C interface circuit comprising: an input circuit, an output circuit as in any one of the preceding embodiments, and an isolator connected between the input circuit and the output circuit.
A third aspect of the present invention provides a bi-directional transmission I2C interface circuit comprising: two reverse-transmitted digital isolation channels, one of which comprises: the unidirectional transport I2C interface circuit of the preceding embodiment.
According to the output circuit of the I2C interface circuit, the voltage sensing module is arranged at the source electrode end of the first NMOS tube, so that voltage fluctuation generated when other devices on the I2C bus are pulled down and released can be automatically identified when the first NMOS tube is conducted. Through the voltage regulation module designed between the source terminal of the first NMOS tube and the voltage sensing module, the voltage at the source side of the first NMOS tube can be quickly regulated to be recovered to a low level threshold value, and the condition that the low level output of the first NMOS tube is mistakenly considered to be high level can not occur, so that the reliability of the I2C interface circuit can be improved.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 shows a prior art I2C interface circuit schematic;
FIG. 2 is a schematic diagram showing a simulation waveform related to the port voltage of the data port SDA1 in FIG. 1 when the I2C bus is released after being pulled down according to the embodiment of the present invention;
FIG. 3 is a first schematic diagram of an output circuit of an I2C interface circuit according to an embodiment of the present invention;
FIG. 4 is a second schematic diagram of the output circuit of the I2C interface circuit according to the embodiment of the present invention;
FIG. 5 is a third schematic diagram of an output circuit of an I2C interface circuit according to an embodiment of the invention;
FIG. 6 is a fourth schematic diagram of an output circuit of an embodiment I2C interface circuit of the present invention;
FIG. 7 is a fifth schematic diagram of an output circuit of an I2C interface circuit according to an embodiment of the invention;
fig. 8 is a schematic diagram showing a simulation waveform related to the port voltage of the data port SDA1 when the I2C bus is released after being pulled down according to an embodiment of the present invention.
Description of the drawings:
m0, M1, M2, M3, N1-N11 and NMOS tubes;
m4, M5, P1-P19, PMOS tube;
SDA1, SDA2, data end;
d1, a diode;
VS, intermediate node;
r1, R2, pull-up resistor;
CMP, comparator;
VG, output end;
C. a voltage stabilizing capacitor;
10. a voltage sensing module;
20. a voltage regulation module;
201. a feedback module;
202. a pull-up module;
203. and adjusting the controller.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or device that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or device.
In an embodiment of the present invention, an output circuit of an I2C interface circuit is provided, which is used to solve the problem in the prior art that when other devices on an I2C bus are pulled down and released, an I2C bus will generate an overshoot phenomenon, and a low level output by the output circuit of the I2C interface circuit will be mistaken for a high level, so that the I2C interface circuit has poor reliability.
Specifically, as shown in fig. 3, the output circuit of the I2C interface circuit includes: the device comprises a first NMOS tube M1, a voltage sensing module 10 and a voltage adjusting module 20.
The grid electrode of the first NMOS tube M1 is connected with an output signal RX_OUT of an isolator in the I2C interface circuit, the drain electrode of the first NMOS tube M1 is connected with an I2C data end SDA1, and the source electrode of the first NMOS tube M1, the regulating end of the voltage regulating module 20 and the input end of the voltage sensing module 10 are respectively connected to an intermediate node VS. The circuit for generating the output signal rx_out refers to the circuits side2 to side1 in fig. 1, the circuit for connecting the data terminal SDA1 refers to the circuit for connecting the data terminal SDA1 in fig. 1, and the circuit for generating the output signal rx_out and the circuit for connecting the data terminal SDA1 will not be described in detail. In specific implementation, as shown in fig. 6, the voltage of the data terminal SDA1 is connected to the power supply through the pull-up resistor R1.
The output end of the voltage sensing module 10 is connected to the control end of the voltage regulating module 20, and is used for sensing the voltage change of the intermediate node VS, and controlling the voltage regulating module 20 to be turned on and off according to the voltage change of the intermediate node.
The voltage of the intermediate node VS is a low level threshold VREF2 when the first NMOS transistor M1 is turned on, that is, vs=vref 2=vsda 1 (the voltage of the data terminal SDA 1), and the voltage adjusting module 20 is turned on to adjust the voltage value of the intermediate node to the low level threshold VREF2. In particular, the I2C interface circuit further includes a digital isolation channel circuit capable of outputting a low level threshold VREF1, such as the digital isolation channel circuits side1 to side2 in fig. 1, where the low level threshold VREF2 output by the output circuit of the I2C interface circuit when the first NMOS transistor M1 is turned on is greater than the low level threshold VREF1 output by the other isolation channel circuit.
In this embodiment, by setting the voltage sensing module at the source end of the first NMOS transistor, when the first NMOS transistor is turned on, voltage fluctuations (i.e., signal amplitude of the data end SDA 1) generated when other devices on the I2C bus are pulled down and released can be automatically identified. Through the voltage regulation module designed between the source terminal of the first NMOS tube and the voltage sensing module, the voltage at the source side of the first NMOS tube can be quickly regulated to be recovered to the low level threshold VREF2, the condition that the low level output of the first NMOS tube is mistakenly regarded as high level can not occur, and therefore the reliability of the I2C interface circuit can be improved.
In one embodiment of the present invention, as shown in fig. 4, the voltage sensing module 10 includes: and a comparator CMP. The positive input end of the comparator CMP is connected with the intermediate node VS, the negative input end of the comparator CMP is connected with the low level threshold VREF2, and the output end of the comparator CMP is connected with the control end of the voltage regulating module 20.
When the voltage of the intermediate node VS is greater than the low level threshold VREF2, the voltage regulation module 20 is turned on. When the voltage of the intermediate node VS is less than or equal to the low level threshold VREF2, the voltage regulation module 20 is turned off.
Referring back to fig. 4, the voltage adjustment module 20 includes: the device comprises a feedback module 201, a pull-up module 202 and an adjustment controller 203, wherein the adjustment controller 203 is provided with a control end, a first adjustment end and a second adjustment end.
The output end of the pull-up module 202 is connected to the control end of the adjustment controller 203, and is used for adjusting the voltage of the control end of the adjustment controller 203 according to the feedback voltage output by the feedback module 201, so as to open or close the adjustment controller 203, and further adjust the voltage value of the intermediate node to a low level threshold VREF2.
The input end of the feedback module 201 is connected to the output end VG of the comparator CMP and the first adjusting end, the output end of the feedback module 201 is connected to the input end of the pull-up module 202, and the feedback module 201 is configured to collect the voltage between the output end VG of the CMP and the first adjusting end of the adjusting controller 203.
The first adjusting point of the adjusting controller 203 is connected to the ground, the second adjusting point of the adjusting controller 203 is connected to the intermediate node VS, and the control end of the adjusting controller 203 is connected to the output end VG of the comparator CMP.
Either the comparator CMP or the pull-up module may turn the adjustment controller 203 on or off.
In one embodiment, as shown in fig. 5, the adjustment controller 203 includes at least: the first adjusting end, the second adjusting end and the control end of the second NMOS tube M2 are respectively a source electrode, a drain electrode and a grid electrode of the second NMOS tube.
Taking the adjustment controller 203 as the second NMOS transistor M2 as an example, when rx_out is at a high level, the first NMOS transistor M1 is turned on, and at this time, the voltages at the output end SDA1 and the intermediate node VS of the output module are both VREF2, i.e., vs=vref 2=vsda 1, the comparator CMP outputs a low level, and the second NMOS transistor M2 is not turned on. When rx_out is at a high level, if other devices connected to the I2C bus operate the I2C bus port, when the port is forcibly pulled down and released, the voltage of SDA1 will rise, thereby causing the voltage of the intermediate node VS to rise, the voltage of the positive input end of the comparator CMP is greater than VREF2, the output voltage increases, the feedback module 201 samples the voltage between the voltage of the output end VG of the comparator and the voltage of the source electrode of the second NMOS tube M2 in real time, the feedback module 201 controls the pull-up module 202 through the feedback voltage VFB, the gate voltage of the second NMOS tube M2 is quickly pulled up, and the second NMOS tube M2 is controlled to be turned on (i.e., the adjustment controller is turned on), so that the voltage of the intermediate node VS is quickly pulled up to VREF2, thereby forming a quick response channel.
In an embodiment of the present invention, as shown in fig. 6, the feedback module includes a third NMOS transistor M3 and a bias unit.
The grid electrode of the third NMOS tube M3 is connected with the grid electrode of the second NMOS tube M2, the source electrode of the third NMOS tube M3 is connected with the source electrode of the second NMOS tube M2, and the drain electrode of the third NMOS tube M3 is connected with the input end of the pull-up module and the bias unit; the bias unit is used for providing bias current for the third NMOS tube M3. The turn-on voltage of the third NMOS transistor M3 is lower than the turn-on voltage of the second NMOS transistor M2.
In one embodiment, the biasing unit at least includes: and a first PMOS tube M4. The grid electrode of the first PMOS tube M4 is connected with bias voltage, the source electrode of the first PMOS tube M4 is connected with a power supply, and the drain electrode of the first PMOS tube M4 is connected with the drain electrode of the third NMOS tube M3.
As shown in FIG. 6, the pull-up module includes a second PMOS tube M5 and a pull-up resistor R2. The grid electrode of the second PMOS tube M5 is connected with the drain electrode of the third NMOS tube M3, the drain electrode of the second PMOS tube M5 is connected with the control end of the second NMOS tube or the output end of the comparator CMP, and the source electrode of the second PMOS tube M5 is connected with one end of the pull-up resistor R2; the other end of the pull-up resistor R2 is connected with a power supply.
When rx_out is at a high level, the first NMOS transistor M1 is turned on, and at this time, the voltage at the data terminal SDA1 and the voltage at the intermediate node VS of the output module are both VREF2, i.e., vs=vref 2=vsda 1, and the comparator CMP outputs a low level, so that the second NMOS transistor M2 is not turned on. If other devices connected with the I2C bus operate the I2C bus port at this time, when the port is forced to be pulled down and released, the voltage of the SDA1 will rise, so as to cause the voltage of the intermediate node VS to rise, the voltage of the forward input end of the comparator CMP is greater than VREF2, the output voltage of the comparator CMP increases, the third NMOS tube M3 is turned on, the feedback module outputs the feedback voltage VFB, at this time, the feedback voltage is VFB at a low level, the second PMOS tube M5 is turned on, the pull-up module pulls up the VG voltage rapidly, the second NMOS tube M2 is turned on, so that the voltage of the intermediate node VS is pulled up to VREF2 rapidly, and a rapid response channel is formed.
The feedback module in this embodiment cooperates with the pull-up module, so that the intermediate node voltage VS can be quickly pulled back to VREF2 after being higher, so that the intermediate node voltage VS is kept stable, and further, the voltage of the data end SDA1 of the output circuit is kept stable.
In an embodiment of the present invention, the third NMOS transistor further includes a voltage stabilizing capacitor connected between a drain of the third NMOS transistor and a ground terminal. The embodiment can stabilize the output voltage of the feedback module.
In one embodiment of the present invention, as shown in FIG. 7, the output circuit of the I2C interface circuit includes NMOS transistors M1-M3, N1-N11, PMOS transistors M5, P1-P19, a pull-up resistor R2 and a stabilizing capacitor C.
M5 and R2 constitute pull-up module, M3 constitutes feedback module, N1-N7, P1-P9, P18-P19 constitute bias circuit, N8-N11, P10-P17 constitute comparator.
The drain electrode of N1 is connected with Iref, the grid electrode of N1, the drain electrode of N1, the grid electrode of N2 are connected with the grid electrode of N3, the drain electrode of N2, the drain electrode of P1, the grid electrode of P1 are connected with the grid electrode of P3, and the voltage is marked as BIA 1. The drain of P2 is connected to the source of P3, the drain of N3 is connected to the gate of P2, and the voltage is labeled BIA 2. The drain of P4 is connected to the source of P5, the drain of N4, the gate of N4 are connected to the gate of N5, and the voltage is labeled VBN. The drain electrode of P6 is connected with the source electrode of P7, and the drain electrode of P7 and the drain electrode of N5 are connected with the grid electrode of N6. The drain electrode of P8 is connected with the source electrode of P9, and the drain electrode of P9 and the drain electrode of N7 are connected with the grid electrode of N7.
The drain of P10 is connected to the source of P11, the drain of P11, the source of P12 is connected to the source of P13, and the gate of P12 is connected to VREF2. The gate of P13, the source of M1, and the drain of M2 are connected, and the voltage thereat is labeled VS. The drain electrode of P12 and the source electrode of N9 are connected with the drain electrode of N11, and the drain electrode of P13 and the source electrode of N8 are connected with the drain electrode of N10. The drain of P14 is connected with the source of P16, the drain of N8, the gate of N10 is connected with the gate of N11, the gate of N8, the gate of N9 is connected with the voltage VBN. The drain of P15 is connected to the source of P17, the drain of N9, the drain of M3, the gate of M2 is connected to the gate of M3, and is referred to herein as VG. The source of M5 is connected to VDD via a pull-up resistor R2, the gate of M5, the drain of P19 is connected to the drain of M3, and the voltage thereat is labeled VFB. The gate of M1 is connected to RX_OUT, and the drain of M1 is connected to SDA 1. The drain of P18 is connected to the source of P19. The gates of P4, P6, P8, P10, P14, P15, P18 are connected to BIA2, and the gates of P5, P7, P9, P11, P16, P17, P19 are connected to BIA 1. Sources of P1, P2, P4, P6, P8, P10, P14, P15, P18 are connected to VDD, and sources of N1, N2, N3, N4, N6, N7, N10, N11, M2, M3 are connected to GND. One end of the voltage stabilizing capacitor C is connected with the VFB, and the other end of the voltage stabilizing capacitor C is connected with the GND.
P10, P11, P12, P13, P14, P15, P16, P17 and N8, N9, N10, N11 constitute a comparator CMP. M2, pull-up modules M5 and R2, feedback module M3 and the comparator together function as zener diode D in FIG. 1, clamping VS voltage at VREF2. However, unlike the diode D in fig. 1, the negative feedback path in fig. 7 can quickly adjust the voltage of the output circuit, and the situation that the low level output from the output circuit is mistaken for the high level will not occur, so that the reliability of the I2C interface circuit can be improved.
Specifically, when the control signal rx_out is at a high level, M1 is turned on, and the data terminal SDA1 on the I2C bus is forced to be pulled to a low level (VREF 2), since M1 is turned on, VS also outputs a low level signal, at this time, if other devices connected to the I2C bus operate on the bus, and when the other devices are pulled down and suddenly released, the output voltage of VS will increase, and the output voltage of the comparator increases, so that M3 is turned on, the feedback voltages VFB, VFB are output at a low level, M5 is turned on, so that the potential of the VG point is pulled high, and M2 is turned on, so that the potential of VS is pulled to VREF2.
In this embodiment, when the bus is pulled down by other devices and suddenly released, M2 can be quickly turned on, so that VS electric potential can be quickly clamped to VRFE2, and further, the problem of overshoot of the data end SDA1 is avoided.
As shown in fig. 8, the simulation waveforms generated by the circuit of fig. 7 are shown in fig. 8, and it can be seen from fig. 8 that when other devices pull down the bus and then release the bus, the voltage of the data terminal SDA1 is only 670mV below the high level threshold of the output port, so that the problem of overshoot of the data terminal SDA1 can be avoided.
In an embodiment of the present invention, there is also provided an I2C interface circuit for unidirectional transmission, including: an input circuit, an output circuit as in any one of the preceding embodiments, and an isolator connected between the input circuit and the output circuit.
In an embodiment of the present invention, there is also provided a bi-directional transmission I2C interface circuit, including: two reverse-transmitted digital isolation channels, one of which comprises: the unidirectional transport I2C interface circuit of the previous embodiment. In one embodiment, the output circuit shown in fig. 3 to 6 is used to replace the output module 2 in fig. 1.
The principles and embodiments of the present invention have been described in detail with reference to specific examples, which are provided to facilitate understanding of the method and core ideas of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims (10)

1. An output circuit of an I2C interface circuit, the output circuit comprising: the device comprises a first NMOS tube, a voltage sensing module and a voltage regulating module;
the grid electrode of the first NMOS tube is connected with the output end of an isolator in the I2C interface circuit, the drain electrode of the first NMOS tube is connected with an I2C data end, and the source electrode of the first NMOS tube, the regulating end of the voltage regulating module and the input end of the voltage sensing module are respectively connected to intermediate nodes;
the output end of the voltage sensing module is connected with the control end of the voltage regulating module and is used for sensing the voltage change of the intermediate node and controlling the voltage regulating module to be turned on and off according to the voltage change of the intermediate node;
and when the first NMOS tube is conducted, the voltage of the intermediate node is a low-level threshold value, and when the voltage regulating module is started, the voltage regulating module is used for regulating the voltage value of the intermediate node to the low-level threshold value.
2. The output circuit of claim 1, wherein the voltage sense module comprises: the positive input end of the comparator is connected with the intermediate node, the negative input end of the comparator is connected with a low-level threshold value, and the output end of the comparator is connected with the control end of the voltage regulating module;
when the voltage of the intermediate node is greater than a low level threshold, starting the voltage regulating module;
and when the voltage of the intermediate node is smaller than or equal to a low level threshold value, closing the voltage regulating module.
3. The output circuit of claim 2, wherein the voltage regulation module comprises: the device comprises a feedback module, a pull-up module and an adjusting controller, wherein the adjusting controller is provided with a control end, a first adjusting end and a second adjusting end;
the output end of the pull-up module is connected with the control end of the adjusting controller and is used for starting or closing the adjusting controller according to the feedback voltage output by the feedback module so as to adjust the voltage value of the intermediate node to a low level threshold value;
the input end of the feedback module is connected with the output end of the comparator and the first regulating end of the regulating controller, and the output end of the feedback module is connected with the input end of the pull-up module and is used for collecting the voltage between the output end of the comparator and the first regulating end;
the first adjusting point of the adjusting controller is connected with the grounding end, the second adjusting point of the adjusting controller is connected with the intermediate node, and the control end of the adjusting controller is connected with the output end of the comparator;
the comparator and the pull-up module can both open or close the regulating controller.
4. The output circuit of claim 3 wherein said regulation controller comprises at least: the first adjusting end, the second adjusting end and the control end are respectively a source electrode, a drain electrode and a grid electrode of the second NMOS tube.
5. The output circuit of claim 4, wherein the feedback module comprises: a third NMOS tube and a bias unit;
the grid electrode of the third NMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the third NMOS tube is connected with the source electrode of the second NMOS tube, and the drain electrode of the third NMOS tube is connected with the input end of the pull-up module and the biasing unit;
the bias unit is used for providing bias current for the third NMOS tube.
6. The output circuit of claim 5, wherein the bias unit comprises at least: a first PMOS tube;
the grid electrode of the first PMOS tube is connected with bias voltage, the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is connected with the drain electrode of the third NMOS tube.
7. The output circuit of claim 5, wherein the pull-up module comprises: the second PMOS tube and the pull-up resistor;
the grid electrode of the second PMOS tube is connected with the drain electrode of the third NMOS tube, the drain electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, and the source electrode of the second PMOS tube is connected with one end of the pull-up resistor;
the other end of the pull-up resistor is connected with a power supply.
8. The output circuit of claim 5, further comprising: and the voltage stabilizing capacitor is connected between the drain electrode of the third NMOS tube and the grounding end.
9. An I2C interface circuit for unidirectional transmission, comprising: input circuit, output circuit according to any of claims 1 to 8, an isolator connected between the input circuit and the output circuit.
10. An I2C interface circuit for bi-directional transmission, comprising: two reverse-transmitted digital isolation channels, one of which comprises: the unidirectional transport I2C interface circuit of claim 9.
CN202311518340.9A 2023-11-15 2023-11-15 Output circuit of I2C interface circuit and I2C interface circuit Active CN117459052B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113760029A (en) * 2021-08-31 2021-12-07 西安电子科技大学 Novel low dropout linear regulator based on full MOS reference source
CN216718968U (en) * 2022-01-21 2022-06-10 苏州源特半导体科技有限公司 Programmable control chip and drive circuit thereof
CN114785335A (en) * 2022-04-25 2022-07-22 荣湃半导体（上海）有限公司 Pull-up resistor circuit, I2C isolation circuit and pull-up resistor setting method
CN218213921U (en) * 2022-07-15 2023-01-03 苏州纳芯微电子股份有限公司 Clamping circuit and input/output interface circuit
CN116774766A (en) * 2023-07-26 2023-09-19 北京中科格励微科技有限公司 High-voltage output linear voltage stabilizer circuit with current limiting protection function

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113760029A (en) * 2021-08-31 2021-12-07 西安电子科技大学 Novel low dropout linear regulator based on full MOS reference source
CN216718968U (en) * 2022-01-21 2022-06-10 苏州源特半导体科技有限公司 Programmable control chip and drive circuit thereof
CN114785335A (en) * 2022-04-25 2022-07-22 荣湃半导体（上海）有限公司 Pull-up resistor circuit, I2C isolation circuit and pull-up resistor setting method
CN218213921U (en) * 2022-07-15 2023-01-03 苏州纳芯微电子股份有限公司 Clamping circuit and input/output interface circuit
CN116774766A (en) * 2023-07-26 2023-09-19 北京中科格励微科技有限公司 High-voltage output linear voltage stabilizer circuit with current limiting protection function

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