CN117458829A - Reverse current detection method, circuit and direct current-direct current converter - Google Patents

Abstract

When a first signal input end is detected to receive a signal, a first MOS tube in the reverse current detection circuit is controlled to be conducted, a second MOS tube works in a source follower mode, a first capacitor at the source end of the second MOS tube is stored with energy, and the storage voltage of the first capacitor is determined; when the second signal input end receives a signal, the first MOS tube in the reverse current detection circuit is controlled to be conducted, the second MOS tube works in a comparator mode, and the grid voltage and the turnover voltage of the second MOS tube are obtained; and using the difference between the gate voltage of the second MOS tube and the overturning voltage of the second MOS tube to offset the threshold voltage of all the MOS tubes and the circuit supply voltage, and determining the load input voltage. Therefore, the built reverse current detection circuit is not influenced by the mismatch of the MOS tube, and the threshold precision of the reverse current detection circuit can be effectively improved.

Description

Reverse current detection method, circuit and direct current-direct current converter

Technical Field

The present disclosure relates to the field of electronic devices, and in particular, to a reverse current detection method, a circuit, and a dc-dc converter.

Background

In the prior art, the reverse current detection of the direct current-direct current converter is not accurate enough, and generally, the existing reverse current detection circuit has larger mismatch voltage (the traditional reverse current detection circuit is realized by adopting a comparator to compare the voltage drop of a low-side power tube with the voltage of 0 volt), the mismatch voltage difference of the comparator between chips is larger, and particularly, as the size of the power tube becomes larger (the direct current-direct current converter with larger output current is generally designed to have larger power tube size), the current detection threshold deviation caused by the mismatch voltage is larger. The offset current may be approximately calculated as Δi=vos/Rds, where Vos is the mismatch voltage of the reverse current detection circuit (typically, this mismatch voltage is affected by the MOS transistor threshold voltage mismatch, for example, the threshold voltage mismatch of the two input pair transistors of the differential input comparator), rds is the power transistor on-resistance, and the smaller the power transistor on-resistance, the larger the offset current Δi. Designing a reverse current detection circuit with smaller mismatch voltage can help to improve the current detection threshold accuracy between chips.

Disclosure of Invention

In view of the above, an object of the present application is to provide a reverse current detection method, a circuit and a dc-dc converter, by which the reverse current detection circuit can be constructed without being affected by the mismatch of the MOS transistor, so that the threshold accuracy of the reverse current detection circuit can be effectively improved.

The embodiment of the application provides a reverse current detection method, which is applied to a reverse current detection circuit, and comprises the following steps:

detecting the signal receiving state of each signal input end of the reverse current detection circuit in real time; the signal input end comprises a first signal input end and a second signal input end;

when the first signal input end receives a signal, controlling a first MOS tube in the reverse current detection circuit to be conducted, controlling a second MOS tube to work in a source follower mode, storing energy of a first capacitor at the source end of the second MOS tube, and determining the storage voltage of the first capacitor; the storage voltage is determined according to threshold voltages of all MOS transistors in the reverse current detection circuit and circuit supply voltage;

when the second signal input end receives a signal, controlling a first MOS tube in the reverse current detection circuit to be conducted and a second MOS tube to work in a comparator mode, and obtaining the grid voltage and the turnover voltage of the second MOS tube; the gate voltage is determined according to the threshold voltage of the first MOS tube, the load input voltage and the circuit supply voltage, and the overturning voltage is determined according to the storage voltage and the threshold voltage of the second MOS tube;

using the difference between the grid voltage of the second MOS tube and the overturning voltage of the second MOS tube to offset the threshold voltage of all MOS tubes and the circuit power supply voltage, and determining the load input voltage; wherein the load input voltage is used for determining a reverse current detection result.

Optionally, after determining the load input voltage, the reverse current detection method further includes:

determining a target level state output by the current reverse current detection circuit according to the polarity of the load input voltage and a preset polarity-level state corresponding relation;

and controlling the reverse current detection circuit to output the level of the target level state.

Optionally, a first resistor and a first current source are connected in series at the source of the first MOS transistor in the reverse current detection circuit; the product of the resistance value of the first resistor and the current value of the first current source is a circuit power supply voltage, and the sum voltage of the circuit power supply voltage and the absolute value of the threshold voltage of the first MOS tube is larger than the threshold voltage of the second MOS tube.

The embodiment of the application provides a reverse current detection circuit, which comprises a first switch, a second switch, a third switch, a first MOS tube, a second MOS tube, a first resistor, a first capacitor, a first current source, a second current source, a third current source, a first inverter and a second inverter;

the grid electrode of the first MOS tube, one end of the first switch and one end of the second switch are interconnected, the other end of the first switch is grounded, the source electrode of the first MOS tube is interconnected with one end of the first resistor, the drain electrode of the first MOS tube is grounded, and one end of the third switch is interconnected with one end of the first capacitor;

the grid electrode of the second MOS tube, the other end of the first resistor and one end of the first current source are interconnected, the drain electrode of the second MOS tube, the input end of the first inverter and one end of the second current source are interconnected, and the source electrode of the second MOS tube, one end of the third current source and the other end of the first capacitor are interconnected;

the other end of the third current source is connected with the other end of the third switch, so that the on-off of the third switch is controlled by the level type through the second inverter.

Optionally, the first MOS transistor is a PMOS.

Optionally, the second MOS transistor is an NMOS.

Optionally, the reverse current detection circuit further comprises a voltage source, and the voltage source is interconnected with the other end of the first current source and the other end of the second current source.

Optionally, the reverse current detection circuit further includes a first signal input terminal and a second signal input terminal:

the first signal input end is used for receiving a first control signal for controlling the first switch to be conducted;

the second signal input end is used for receiving a second control signal for controlling the second switch to be turned on and the third switch to be turned off.

The embodiment of the application provides a direct current-direct current converter, which comprises a negative feedback loop, a third inverter, a logic gate device and a reverse current detection circuit:

the first output end of the negative feedback loop, the second signal end of the reverse current detection circuit and the first input end of the logic gate device are interconnected;

a second output end of the negative feedback loop is interconnected with a first signal input end of the reverse current detection circuit;

a third output end of the negative feedback loop is interconnected with a third input end of the reverse current detection circuit, and an output end of the reverse current detection circuit is interconnected with an input end of the third inverter;

an output of the third inverter is interconnected with a second input of the logic gate device;

an output of the logic gate device is interconnected with an input of the negative feedback loop.

Optionally, the negative feedback loop includes a pulse width modulation module, a first driver, a second driver, a conversion circuit, and a voltage sampling circuit:

the first output end of the pulse width modulation module, the second signal input end of the reverse current detection circuit and the first input end of the logic gate device are interconnected, and the second output end of the pulse width modulation module is interconnected with the input end of the first driver;

the first input end of the conversion circuit, the first signal input end of the reverse current detection circuit and the output end of the first driver are interconnected, the second input end of the conversion circuit is interconnected with the output end of the second driver, the first output end of the conversion circuit is interconnected with the input end of the voltage sampling circuit, and the second output end of the conversion circuit is interconnected with the third input end of the reverse current detection circuit;

the output end of the voltage sampling circuit is interconnected with the input end of the pulse width modulation module;

an input of the second driver is interconnected with an output of the logic gate device.

Optionally, the conversion circuit includes a fourth switch, a fifth switch, an inductor, and a second capacitor:

one end of the fourth switch, one end of the fifth switch and one end of the inductor are interconnected, the other end of the inductor is interconnected with one end of the second capacitor, and the other end of the fourth switch and the other end of the second capacitor are grounded.

Optionally, the logic gate device is an and logic gate device.

Optionally, the conversion circuit is configured to convert the received duty cycle signal into the output voltage.

The embodiment of the application provides a reverse current detection method, a circuit and a direct current-direct current converter, wherein the reverse current detection method comprises the following steps: detecting the signal receiving state of each signal input end of the reverse current detection circuit in real time; the signal input end comprises a first signal input end and a second signal input end; when the first signal input end receives a signal, controlling a first MOS tube in the reverse current detection circuit to be conducted, controlling a second MOS tube to work in a source follower mode, storing energy of a first capacitor at the source end of the second MOS tube, and determining the storage voltage of the first capacitor; the storage voltage is determined according to threshold voltages of all MOS transistors in the reverse current detection circuit and circuit supply voltage; when the second signal input end receives a signal, controlling a first MOS tube in the reverse current detection circuit to be conducted and a second MOS tube to work in a comparator mode, and obtaining the grid voltage and the turnover voltage of the second MOS tube; the gate voltage is determined according to the threshold voltage of the first MOS tube, the load input voltage and the circuit supply voltage, and the overturning voltage is determined according to the storage voltage and the threshold voltage of the second MOS tube; using the difference between the grid voltage of the second MOS tube and the overturning voltage of the second MOS tube to offset the threshold voltage of all MOS tubes and the circuit power supply voltage, and determining the load input voltage; wherein the load input voltage is used to determine the reverse current detection result.

Therefore, the constructed reverse current detection circuit is not influenced by the mismatch of the MOS tube, so that the threshold precision of the reverse current detection circuit can be effectively improved.

In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flowchart of a reverse current detection method according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a reverse current detection circuit according to an embodiment of the present application;

fig. 3 is a schematic diagram of a dc-dc converter according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a DC-DC converter according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a conversion circuit according to an embodiment of the present application.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. Based on the embodiments of the present application, every other embodiment that a person skilled in the art would obtain without making any inventive effort is within the scope of protection of the present application.

In the prior art, the reverse current detection of the direct current-direct current converter is not accurate enough, and generally, the existing reverse current detection circuit has larger mismatch voltage (the traditional reverse current detection circuit is realized by adopting a comparator to compare the voltage drop of a low-side power tube with the voltage of 0 volt), the mismatch voltage difference of the comparator between chips is larger, and particularly, as the size of the power tube becomes larger (the direct current-direct current converter with larger output current is generally designed to have larger power tube size), the current detection threshold deviation caused by the mismatch voltage is larger. The offset current may be approximately calculated as Δi=vos/Rds, where Vos is the mismatch voltage of the reverse current detection circuit (typically, this mismatch voltage is affected by the MOS transistor threshold voltage mismatch, for example, the threshold voltage mismatch of the two input pair transistors of the differential input comparator), rds is the power transistor on-resistance, and the smaller the power transistor on-resistance, the larger the offset current Δi. Designing a reverse current detection circuit with smaller mismatch voltage can help to improve the current detection threshold accuracy between chips.

Based on this, the embodiment of the application provides a reverse current detection circuit, through the reverse current detection circuit that builds, can not receive the influence of MOS pipe mismatch to can effectually improve reverse current detection circuit's threshold value precision.

Referring to fig. 1, fig. 1 is a flowchart of a reverse current detection method according to an embodiment of the present application. The reverse current detection method is applied to the reverse current detection circuit, as shown in fig. 1, and the reverse current detection method provided in the embodiment of the application includes:

s101, detecting the signal receiving state of each signal input end of the reverse current detection circuit in real time.

Here, the signal input terminal includes a first signal input terminal and a second signal input terminal. The first signal input end and the second signal input end alternately receive signals; the signal input end receives PWM signals.

The signal receiving state of each signal input end of the reverse current detection circuit is detected in real time, and the conducting state of the first signal input end and the conducting state of the second signal input end are determined.

And S102, when the first signal input end is detected to receive a signal, controlling a first MOS tube in the reverse current detection circuit to be conducted, controlling a second MOS tube to work in a source follower mode, storing energy of a first capacitor at the source end of the second MOS tube, and determining the storage voltage of the first capacitor.

Here, the storage voltage is determined according to the threshold voltages of all MOS transistors in the reverse current detection circuit and the circuit supply voltage.

When the first signal input end receives a signal, namely the first signal input end receives a high-level signal.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a reverse current detection circuit provided in this embodiment of the present application, as shown in fig. 2, when it is detected that the first signal input end receives a high level signal, the switch first switch S1 is turned on, the ground voltage is connected to the gate of the first MOS transistor MOS1, the voltage at the point SP1 of the source of the first MOS transistor MOS1 becomes 0+|vthp|= |vthp|, the voltage at the node GN1 becomes |vthp|+i1.r1, where Vthp is the threshold voltage of the first MOS transistor MOS1 (since the PMOS threshold is usually negative, an absolute value sign is added here to take a positive number), I1 is the current value of the first current source, and R1 is the resistance value of the first resistor. After passing through the second MOS tube (working in a source follower mode), the first capacitor is stored with energy, and the voltage V is stored on the first capacitor _Cf Equal to |vthp|+i1×r1-Vthn, where Vthp is the threshold voltage of MP1, I1 is the current value of the first current source, R1 is the resistance value of the first resistor, vthn is the threshold voltage of the second MOS transistor, and I1×r1 is the circuit supply voltage. Therefore, through the circuit constructed by the method, when reverse detection is not performed, the threshold voltage of each MOS is recorded, so that when the reverse detection is performed subsequently, the recorded threshold voltages of the MOS can be counteracted, and the problem that the accuracy of the current detection threshold is reduced due to mismatching of the threshold voltages of the MOS tubes is avoided.

And S103, when the second signal input end receives a signal, controlling the first MOS tube in the reverse current detection circuit to be conducted, and controlling the second MOS tube to work in a comparator mode, so as to obtain the grid voltage and the turnover voltage of the second MOS tube.

Here, the gate voltage is determined according to the threshold voltage of the first MOS transistor, the load input voltage, and the circuit supply voltage, and the flip voltage is determined according to the storage voltage and the threshold voltage of the second MOS transistor.

When the second signal input end receives a signal, namely the first signal input end receives a high-level signal.

With continued reference to fig. 2, as shown in fig. 2, it is detected that the first signal input terminal receives a high level signal, the second switch S2 is controlled to be turned on, the GP1 node voltage is a load input voltage received by the third input terminal, and the SP1 node voltage is equal to V _SW +|Vthp|, where V _SW For the voltage value received at the third input (load input voltage), the GN1 node voltage is equal to V _SW +|vthp|+i1R 1. When the first signal input end receives a high-level signal, inv2 is output to be low level, and controls the third switch S3 to be opened, at this time, the second MOS transistor MOS2 works in a comparator mode, and the inversion voltage of the gate voltage is Vthn+V _C When the gate voltage of the second MOS transistor MOS2 is higher than vthn+v, the ratio of the gate voltage to vthp+i1×r1 _C When the output DN1 thereof goes low; when the gate voltage of the second MOS transistor MOS2 is lower than Vthn+V _C When this output DN1 goes high.

S104, using the difference between the gate voltage of the second MOS tube and the overturning voltage of the second MOS tube to offset the threshold voltage of all the MOS tubes and the circuit supply voltage, and determining the load input voltage.

Here, the load input voltage is used to determine a reverse current detection result. When the load input voltage is positive, the output DN1 becomes low level, the load input voltage is negative, and the output DN1 becomes high level.

With continued reference to FIG. 2, as shown in FIG. 2, the gate voltage (GN 1 node voltage) of the second MOS transistor is equal to V _SW The load input voltage V can be obtained by making a difference between the gate voltage of the second MOS tube and the flip voltage of the second MOS tube by using the++ Vthp|+I1R 1 _SW Therefore, the comparison circuit equivalently compares V _SW +|vthp|+i1R 1 and vthn+v _C Is also equivalent to comparison of V _SW +|vthp|+i1R 1 and |vthp|+i1R 1 are also equivalent to V _SW And a size of 0. As can be seen from the above description, the circuit is not affected by the mismatch of the MOS transistors, and the threshold precision of the reverse current detection circuit is improved.

In one embodiment provided in the present application, after determining the load input voltage, the reverse current detection method further includes: determining a target level state output by the current reverse current detection circuit according to the polarity of the load input voltage and a preset polarity-level state corresponding relation; and controlling the reverse current detection circuit to output the level of the target level state.

Here, the polarity of the load input voltage and the preset polarity-level state correspondence are specifically: the reverse current detection circuit outputs a high level when the load input voltage is positive, and outputs a low level when the load input voltage is negative.

In another embodiment provided in the present application, a first resistor and a first current source connected in series are disposed at a source of the first MOS transistor in the reverse current detection circuit; the product of the resistance value of the first resistor and the current value of the first current source is a circuit power supply voltage, and the sum voltage of the circuit power supply voltage and the absolute value of the threshold voltage of the first MOS tube is larger than the threshold voltage of the second MOS tube.

This is because there may be a difference between chips in mass production, and there may be a case where |vthp| -Vthn <0 occurs in a small number of chips, and a larger I1R 1 needs to be designed to satisfy |vthp|+i1R 1-Vthn >0, otherwise an error may occur, because |vthp|+i1.r1-Vthn <0, when the voltage is stored in the first capacitor, the second MOS transistor cannot be turned on, and the storage function fails.

With continued reference to fig. 2, as shown in fig. 2, the reverse current detection circuit 110 includes a first switch S1, a second switch S2, a third switch S3, a first MOS transistor MOS1, a second MOS transistor MOS2, a first resistor R1, a first capacitor C1, a first current source I1, a second current source I2, a third current source I3, a first inverter inv1, and a second inverter inv2;

the grid electrode of the first MOS tube MOS1, one end of the first switch S1 and one end of the second switch S2 are connected with each other, the other end of the first switch S1 is grounded, the source electrode of the first MOS tube MOS1 is connected with one end of the first resistor R1 in an interconnection mode, and the drain electrode of the first MOS tube MOS1 is grounded, one end of the third switch S3 and one end of the first capacitor C1 are connected with each other.

The grid electrode of the second MOS tube MOS2, the other end of the first resistor R1 and one end of the first current source I1 are interconnected, the drain electrode of the second MOS tube MOS2, the input end of the first inverter inv1 and one end of the second current source I2 are interconnected, and the source electrode of the second MOS tube MOS2, one end of the third current source I3 and the other end of the first capacitor C1 are interconnected.

The other end of the third current source I3 is connected to the other end of the third switch S3, so that the on-off of the third switch S3 is controlled by the type of level through the second inverter inv 2.

Here, the level type includes a low level and a high level, the third switch S3 is turned on when the level type through the second inverter inv2 is a high level, and the third switch S3 is turned off when the level type through the second inverter inv2 is a low level.

Here, the first MOS transistor is a PMOS, and the second MOS transistor is an NMOS.

The reverse current detection circuit further comprises a voltage source VIN, which is interconnected with the other end of the first current source I1 and the other end of the second current source I2.

The reverse current detection circuit 110 further includes a first signal input terminal 1 and a second signal input terminal 2, where the first signal input terminal 1 is configured to receive a first control signal for controlling the first switch S1 to be turned on; the second signal input terminal 2 is configured to receive a second control signal for controlling the second switch S2 to be turned on and the third switch S3 to be turned off.

With continued reference to fig. 2, the sw terminal is a third input terminal of the reverse current detection circuit, and the ZC terminal is an output terminal of the reverse current detection circuit.

When the signal received by the first signal input end is at a high level, the first switch S1 is turned on, the ground voltage is connected to the gate of the first MOS transistor MOS1, the source voltage of the MOS1 becomes 0+|vthp|= |vthp|, and the GN1 node voltage becomes |vthp|+i1×r1.

Wherein Vthp is the threshold voltage of the first MOS transistor MOS1 (since the PMOS threshold is usually a negative value, and the absolute value sign is added to take a positive number here), I1 is the current value of the current source I1, and R1 is the resistance value of the resistor R1.

The second MOS tube MOS2 works in a source follower mode, and after passing through the second MOS tube MOS2, the voltage V stored on the first capacitor C1 _C Equal to |vthp|+i1×r1-Vthn, where Vthp is the threshold voltage of the first MOS transistor, I1 is the current value of the current source I1, R1 is the resistance value of the resistor R1, and Vthn is the threshold voltage of the second MOS transistor.

When the signal received by the second signal input end is at a high level, the second switch S2 is controlled to be turned on, the GP1 node voltage is equal to the SW voltage, and the source voltage of the first MOS tube is equal to V _SW +|Vthp|, where V _SW For the voltage value of SW terminal, GN1 node voltage is equal to V _SW +|Vthp|+I1*R1。

When the signal received by the second signal input terminal is at high level, the second inverter inv2 outputs at low level to control the third switch S3 to be turned off, and the second MOS transistor MOS2 works in a comparator mode, and the inversion threshold of the gate voltage is Vthn+V _C When the gate voltage of the second MOS transistor MOS2 is higher than vthn+v, the ratio of the gate voltage to the gate voltage of the second MOS transistor MOS2 is = |vthp|+i1×r1 _C When the output DN1 thereof goes low; when the gate voltage of the second MOS transistor MOS2 is lower than Vthn+V _C When this output DN1 goes high. And the GN1 node voltage is equal to V _SW ++ vthp|+i1R 1, so the comparison circuit is equivalent to compare V _SW +|vthp|+i1R 1 and vthn+v _C Is also equivalent to comparison of V _SW +|vthp|+i1R 1 and |vthp|+i1R 1 are also equivalent to V _SW And a size of 0. In this way, the moment when the low side switching current changes from positive to 0 (i.e., the moment when the current is reversed) can be determined. From the above description, it can be seen that the circuit is not affected by the mismatch of the MOS transistor, so that the threshold accuracy of the reverse current detection circuit is improved.

The second MOS transistor MOS2 has a characteristic that when Vgs > Vthn, the drain current thereof increases rapidly, and when Vgs < Vthn, the drain current thereof is zero. Wherein Vgs is the gate-source voltage of the second MOS transistor MOS2 and Vthn is the threshold voltage thereof.

It should be noted that, the reason that the reverse current detection circuit designed by the scheme is not influenced by the mismatch of the MOS tube is as follows: the idea of the invention is to store Vthp and Vthn information when not compared (i.e. HON is high); these physical quantities are cancelled out when compared. Vthp and Vthn of the same device do not change during storage and comparison.

In addition, for better operation, a higher yield is achieved, in a preferred embodiment, when setting the device parameters in the reverse detection circuit, |vthp|+i1×r1—vthn >0 is set, because there may be a difference between chips in mass production, there may be a case where |vthp| -Vthn <0 occurs in a small number of chips, and a larger I1×r1 is required to satisfy |vthp|+i1×r1—vthn >0, otherwise an error may occur because |vthp|+i1×r1—vthn <0, when the voltage is stored in the first capacitor C1, the second MOS transistor MOS2 cannot be turned on, and the storage function fails.

Therefore, the mismatch voltage is smaller by the reverse current detection circuit constructed by the method, so that the accuracy of the current detection threshold value between chips can be effectively improved.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a dc-dc converter according to an embodiment of the present application. As shown in fig. 3, the dc-dc converter 100 includes a negative feedback loop 120, a third inverter inv3, a logic gate device and1, and a reverse current detection circuit 110:

a first output of the negative feedback loop 120, a second signal input of the reverse current detection circuit 110, and a first input of the logic gate device and1 are interconnected.

A second output of the negative feedback loop 120 is interconnected with a first signal input of the reverse current detection circuit 110; a third output of the negative feedback loop 120 is interconnected with a third input of the reverse current detection circuit 110, and an output of the reverse current detection circuit 110 is interconnected with an input of the third inverter inv 3.

An output of the third inverter inv3 is interconnected with a second input of the logic gate device and 1.

The output of the logic gate device and1 is interconnected with the input of the negative feedback loop 120.

Wherein the logic gate device is an AND logic gate device.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating a dc-dc converter according to an embodiment of the present disclosure. As shown in fig. 4, the negative feedback loop 120 includes a pulse width modulation module 1201, a first driver HDRV, a second driver LDRV, a conversion circuit 1202, and a voltage sampling circuit 1203:

a first output of the pulse width modulation module 1201, a second signal input of the reverse current detection circuit 110, and a first input of the logic gate device and1 are interconnected, and a second output of the pulse width modulation module 1201 is interconnected with an input of the first driver HDRV.

A first input terminal of the conversion circuit 1202, a first signal input terminal of the reverse current detection circuit 110 are interconnected with an output terminal of the first driver HDRV, a second input terminal of the conversion circuit 1202 is interconnected with an output terminal of the second driver LDRV, a first output terminal of the conversion circuit 1202 is interconnected with an input terminal of the voltage sampling circuit 1203, and a second output terminal of the conversion circuit 1202 is interconnected with a third input terminal of the reverse current detection circuit 110.

An output of the voltage sampling circuit 1203 is interconnected with an input of the pulse width modulation module 1201.

An input of the second driver LDRV is interconnected with an output of the logic gate device and 1.

Here, the first output terminal of the pulse width modulation module 1201 is a first output terminal of the negative feedback loop 120, the output terminal of the first driver HDRV is a second output terminal of the negative feedback loop 120, the second output terminal of the conversion circuit 1202 is a third output terminal of the negative feedback loop 120, and the input terminal of the second driver LDRV is an input terminal of the negative feedback loop 120.

As shown in fig. 4, the voltage sampling circuit 1203 is generally formed by voltage division of two resistors, the voltage sampling circuit 1203 samples the voltage VO to generate a feedback voltage Vfb, the feedback voltage Vfb is input to the pulse width modulation module 1201, the pulse width modulation module 1201 generates a high-side switch control signal HON and a low-side switch control signal LON, and when HON is high, the high-side switch control signal HON is also high after passing through the first driver HDRV, and the high-side switch in the conversion circuit 1202 is controlled to be turned on; when HON is low, it is also low after passing through the first driver HDRV, and the high-side switch in the switching circuit 1202 is controlled to be turned off; when the pulse width modulation module 1201 generates LON to be at high level, if the output of the reverse current detection circuit 110 is at low level, it is at high level after inv3, it is at high level after AND logic gate and1, it is also at high level after AND logic gate and1, and it controls the switch on of the low side in the switching circuit 1202; when the LON is low or the output of the reverse current detecting circuit 110 is high, the and1 output is low, and the low side switch in the switching circuit 1202 is controlled to be opened after the second driver LDRV is also low.

The conversion circuit 1202 is configured to convert a received duty cycle signal into an output voltage.

The first driver HDRV and the second driver LDRV are used to increase current output capability.

It should be noted that, the purpose of the reverse current detection circuit 110 is to turn off the low-side switch in time when detecting that the current direction of the low-side switch is reversed, so as to avoid occurrence of excessive reverse current (the reverse current causes a decrease in energy efficiency).

The pwm module 1201, the first driver, the second driver, the conversion circuit 1202, and the voltage sampling circuit 1203 constitute a negative feedback loop 120. When the voltage sampling circuit 1203 outputs a Vfb voltage lower than the reference voltage in the pulse width modulation module 1201, the pulse width modulation module 1201 controls the duty ratio of the output HON to increase (the duty ratio of LON to decrease), resulting in an increase in the output voltage of the conversion circuit 1202, resulting in an increase in the Vfb voltage; when the voltage sampling circuit 1203 outputs a Vfb voltage higher than the reference voltage in the pulse width modulation module 1201, the pulse width modulation module 1201 controls the duty cycle of the output HON to decrease (the duty cycle of LON to decrease), resulting in the output voltage of the conversion circuit 1202 to decrease, resulting in the Vfb voltage to decrease.

Where the negative feedback loop 120 is stable, it is possible to achieve that the Vfb voltage is equal to the reference voltage, thereby controlling the sampling voltage of the voltage sampling circuit to be a constant voltage.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a conversion circuit according to an embodiment of the present application. As shown in fig. 5, the conversion circuit 1202 includes a fourth switch S4, a fifth switch S5, an inductor L, and a second capacitor C2:

one end of the fourth switch S4, one end of the fifth switch S5 and one end of the inductor L are interconnected, the other end of the inductor L is interconnected with one end of the second capacitor C2, and the other end of the fourth switch S4 and the other end of the second capacitor C2 are grounded.

Wherein S5 is a high side switch and S4 is a low side switch. S5, when the inductor is conducted, energy is stored in the inductor, and the inductor current is supplied; and S4, when the switch is turned on, the inductor releases energy. The inductance operates on the principle of storing energy in the form of current. By alternating conduction of S4 and S5, efficient transfer of the energy of the external power supply to the output voltage with the inductor can be achieved.

The control signal of the fifth switch S5 is from the output of the first driver HDRV, the control signal of the fourth switch S4 is from the output of the second driver LDRV, a second output end of the conversion circuit is disposed between the fourth switch S4, the fifth switch S5 and the inductor L, and a first output end of the conversion circuit is disposed between the inductor L and the second capacitor C2.

Thus, the working performance of the DC-DC converter is improved by the constructed reverse current detection circuit with high current detection threshold precision.

It will be clear to those skilled in the art that, for convenience and brevity of description, the specific working procedures of the systems, apparatuses and units described above may refer to the corresponding procedures in the foregoing embodiments, and are not repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed circuits and devices may be implemented in other manners. The above-described circuit embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Finally, it should be noted that: the foregoing examples are merely specific embodiments of the present application, and are not intended to limit the scope of the present application, but the present application is not limited thereto, and those skilled in the art will appreciate that while the foregoing examples are described in detail, the present application is not limited thereto. Any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or make equivalent substitutions for some of the technical features within the technical scope of the disclosure of the present application; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (12)

1. A reverse current detection method, characterized by being applied to a reverse current detection circuit, comprising:

detecting the signal receiving state of each signal input end of the reverse current detection circuit in real time; the signal input end comprises a first signal input end and a second signal input end;

when the first signal input end receives a signal, controlling a first MOS tube in the reverse current detection circuit to be conducted, controlling a second MOS tube to work in a source follower mode, storing energy of a first capacitor at the source end of the second MOS tube, and determining the storage voltage of the first capacitor; the storage voltage is determined according to threshold voltages of all MOS transistors in the reverse current detection circuit and circuit supply voltage;

when the second signal input end receives a signal, controlling a first MOS tube in the reverse current detection circuit to be conducted and a second MOS tube to work in a comparator mode, and obtaining the grid voltage and the turnover voltage of the second MOS tube; the gate voltage is determined according to the threshold voltage of the first MOS tube, the load input voltage and the circuit supply voltage, and the overturning voltage is determined according to the storage voltage and the threshold voltage of the second MOS tube;

using the difference between the grid voltage of the second MOS tube and the overturning voltage of the second MOS tube to offset the threshold voltage of all MOS tubes and the circuit power supply voltage, and determining the load input voltage; wherein the load input voltage is used to determine the reverse current detection result.

2. The reverse current detection method according to claim 1, wherein after determining the load input voltage, the reverse current detection method further comprises:

determining a target level state output by the current reverse current detection circuit according to the polarity of the load input voltage and a preset polarity-level state corresponding relation;

and controlling the reverse current detection circuit to output the level of the target level state.

3. The reverse current detection method according to claim 1, wherein a first resistor and a first current source are connected in series at a source of the first MOS transistor in the reverse current detection circuit; the product of the resistance value of the first resistor and the current value of the first current source is a circuit power supply voltage, and the sum voltage of the circuit power supply voltage and the absolute value of the threshold voltage of the first MOS tube is larger than the threshold voltage of the second MOS tube.

4. The reverse current detection circuit is characterized by comprising a first switch, a second switch, a third switch, a first MOS tube, a second MOS tube, a first resistor, a first capacitor, a first current source, a second current source, a third current source, a first inverter and a second inverter;

the grid electrode of the first MOS tube, one end of the first switch and one end of the second switch are interconnected, the other end of the first switch is grounded, the source electrode of the first MOS tube is interconnected with one end of the first resistor, the drain electrode of the first MOS tube is grounded, and one end of the third switch is interconnected with one end of the first capacitor;

the grid electrode of the second MOS tube, the other end of the first resistor and one end of the first current source are interconnected, the drain electrode of the second MOS tube, the input end of the first inverter and one end of the second current source are interconnected, and the source electrode of the second MOS tube, one end of the third current source and the other end of the first capacitor are interconnected;

the other end of the third current source is connected with the other end of the third switch, so that the on-off of the third switch is controlled by the level type through the second inverter.

5. The reverse current detection circuit of claim 4, wherein the first MOS transistor is PMOS and the second MOS transistor is NMOS.

6. The reverse current detection circuit of claim 4 further comprising a voltage source interconnected with the other end of the first current source and the other end of the second current source.

7. The reverse current detection circuit of claim 4 further comprising a first signal input and a second signal input:

the first signal input end is used for receiving a first control signal for controlling the first switch to be conducted;

the second signal input end is used for receiving a second control signal for controlling the second switch to be turned on and the third switch to be turned off.

8. A dc-dc converter comprising a negative feedback loop, a third inverter, a logic gate device, and the reverse current detection circuit of any of claims 4 to 7:

a first output terminal of the negative feedback loop, a second signal input terminal of the reverse current detection circuit, and a first input terminal of the logic gate device are interconnected;

a second output end of the negative feedback loop is interconnected with a first signal input end of the reverse current detection circuit;

a third output end of the negative feedback loop is interconnected with a third input end of the reverse current detection circuit, and an output end of the reverse current detection circuit is interconnected with an input end of the third inverter;

an output of the third inverter is interconnected with a second input of the logic gate device;

an output of the logic gate device is interconnected with an input of the negative feedback loop.

9. The dc-dc converter of claim 8, wherein the negative feedback loop comprises a pulse width modulation module, a first driver, a second driver, a conversion circuit, and a voltage sampling circuit:

the first output end of the pulse width modulation module, the second signal input end of the reverse current detection circuit and the first input end of the logic gate device are interconnected, and the second output end of the pulse width modulation module is interconnected with the input end of the first driver;

the first input end of the conversion circuit, the first signal input end of the reverse current detection circuit and the output end of the first driver are interconnected, the second input end of the conversion circuit is interconnected with the output end of the second driver, the first output end of the conversion circuit is interconnected with the input end of the voltage sampling circuit, and the second output end of the conversion circuit is interconnected with the third input end of the reverse current detection circuit;

the output end of the voltage sampling circuit is interconnected with the input end of the pulse width modulation module;

an input of the second driver is interconnected with an output of the logic gate device.

10. The dc-dc converter of claim 9, wherein the conversion circuit includes a fourth switch, a fifth switch, an inductor, and a second capacitor:

one end of the fourth switch, one end of the fifth switch and one end of the inductor are interconnected, the other end of the inductor is interconnected with one end of the second capacitor, and the other end of the fourth switch and the other end of the second capacitor are grounded.

11. The dc-dc converter of claim 8, wherein the logic gate device is an and logic gate device.

12. The dc-dc converter of claim 9, wherein the conversion circuit is configured to convert the received duty cycle signal to an output voltage.