CN117457655A

CN117457655A - Semiconductor device, forming method thereof and memory circuit

Info

Publication number: CN117457655A
Application number: CN202311254663.1A
Authority: CN
Inventors: 廖翊博; 蔡劲
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-10-05
Filing date: 2023-09-26
Publication date: 2024-01-26

Abstract

The device comprises: a first stack of first semiconductor nanostructures; a second stack of second semiconductor nanostructures on the first stack of first semiconductor nanostructures; a third stack of first semiconductor nanostructures adjacent to the first stack; a first gate structure surrounding the first stack and the second stack; a second gate structure surrounding the third stack; a gate isolation structure between the first gate structure and the second gate structure; a dielectric layer on the second gate structure and laterally adjoining the gate isolation structure; and a through hole. The through hole includes: a first portion extending in a first direction, the first portion being located on the first gate structure, the gate isolation structure and the dielectric layer; and a second portion extending in a second direction transverse to the first direction. Embodiments of the present application also relate to semiconductor devices, methods of forming the same, and memory circuits.

Description

Semiconductor device, forming method thereof and memory circuit

Technical Field

Embodiments of the present application relate to semiconductor devices, methods of forming the same, and memory circuits.

Background

The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such scaled down processes generally provide benefits by improving production efficiency and reducing associated costs. This shrinking also increases the complexity of processing and manufacturing ICs.

Disclosure of Invention

Some embodiments of the present application provide a semiconductor device including: a first stack of first semiconductor nanostructures; a second stack of second semiconductor nanostructures on the first stack of first semiconductor nanostructures; a third stack of first semiconductor nanostructures adjacent to the first stack; a first gate structure surrounding the first stack and the second stack; a second gate structure surrounding the third stack; a gate isolation structure located between the first gate structure and the second gate structure; a dielectric layer on the second gate structure and laterally adjoining the gate isolation structure; and a through hole including: a first portion extending in a first direction, the first portion being located on the first gate structure, the gate isolation structure and the dielectric layer; and a second portion extending in a second direction transverse to the first direction.

Further embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a first vertical stack of nanostructure channels, a second vertical stack of nanostructure channels, a third vertical stack of nanostructure channels, and a fourth vertical stack of nanostructure channels over a substrate, the second vertical stack being located on the first vertical stack, the fourth vertical stack being located on the third vertical stack; forming a first source/drain region adjacent to the nanostructure channel of the first vertical stack and forming a second source/drain region adjacent to the nanostructure channel of the second vertical stack; forming a gate structure surrounding the nanostructure channels of the first vertical stack, the second vertical stack, the third vertical stack, and the fourth vertical stack; forming a first gate structure and a second gate structure by forming a gate isolation structure extending through the gate structure; forming an opening by removing a portion of the second gate structure; forming a dielectric layer in the opening; and forming a via hole on the first gate structure and the dielectric layer.

Still further embodiments of the present application provide a memory circuit comprising: a first pull-up transistor having a first stack of nanostructure channels; a first pull-down transistor comprising: a second stack of nanostructure channels on the first stack; and a drain electrode coupled to the drain electrode of the first pull-up transistor; a second pull-up transistor having a gate electrode; a first pass gate transistor comprising: a third stack of nanostructure channels laterally spaced apart from the first stack and the second stack; a gate electrode; and a drain electrode coupled to drain electrodes of the first pull-up transistor and the first pull-down transistor; and a through hole including: a first portion extending in a first direction, the first portion being located on the gate electrode; and a second portion extending in a second direction transverse to the first direction, the second portion being located on drains of the first pull-up transistor, the first pull-down transistor, and the first pass-gate transistor.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a circuit diagram of a memory circuit according to an embodiment of the invention.

Fig. 2A-15D are views of an IC device at various stages of manufacture in accordance with aspects of the present invention.

Fig. 16A-19D are views of different embodiments of an IC device at various stages of forming a via, according to various embodiments.

Fig. 20A and 20B are schematic cross-sectional side views of an IC device according to various embodiments.

Fig. 21A-21C are schematic plan views of intermediate vias according to various embodiments.

Fig. 22 is a schematic plan view of an IC device in accordance with various embodiments.

Fig. 23A-23C are schematic plan views of intermediate vias according to various embodiments.

Fig. 24 is a flowchart illustrating a method of fabricating a semiconductor device according to aspects of the present invention.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as "under …," "under …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The present invention relates generally to semiconductor devices and, more particularly, to Field Effect Transistors (FETs), such as planar FETs, three-dimensional fin line FETs (finfets), or nanostructured devices. Examples of nanostructure devices include fully wrap Gate (GAA) devices, nanoflake FETs (NSFETs), nanowire FETs (NWFETs), and the like. In prior art nodes, static Random Access Memory (SRAM) area reduction is increasingly difficult as Integrated Circuit (IC) devices are scaled down. Complementary (CFET) devices are promising candidates for advanced logic and memory technologies due to high transistor density, which may be achieved by stacking devices in the bottom and top layers. In CFET SRAM, the gate-to-drain connection uses a larger extension since the gate and drain are connected by a lateral via.

Embodiments disclosed herein include an L-shaped intermediate via for gate-to-drain connection, which reduces SRAM area. Removal of the sacrificial gate and nanostructure channel is followed by formation of a dielectric replacement layer, which facilitates the provision of an L-shaped intermediate via to reduce the SRAM area. The inclusion of an L-shaped intermediate via for gate-to-drain connection relaxes the gate isolation (CMG) overlay window and the source/drain isolation (CMD) overlay window, which is advantageous for reducing the SRAM area. The L-shaped intermediate via may be provided at the front side of the IC device or at the back side of the IC device, which increases design flexibility, and when the L-shaped intermediate via is provided at the back side, front-side wiring may be simplified.

Fig. 1 is a circuit schematic diagram illustrating a six transistor (6T) SRAM memory circuit or memory cell 180 in accordance with various embodiments. For simplicity of illustration, a 6T cell is described, but it should be understood that the L-shaped intermediate vias of the present invention may be included in other memory cells, such as 7T or 8T memory cells. The IC device may include a memory circuit 180, and the memory circuit 180 may be one of millions, billions, or trillion arrangements of similar memory circuits.

The memory circuit 180 includes two pull-up transistors 182L, 182R that are each operable to pull up the voltage at the nodes 190L, 190R to a first voltage level VDD, which may be a high voltage in some embodiments. The pull-up transistors 182L, 182R may be p-type field effect transistors (PFETs), as shown. In some embodiments, the pull-up transistors 182L, 182R are n-type field effect transistors (NFETs). Each of the pull-up transistors 182L, 182R has a source electrode coupled to a first supply node, a drain electrode coupled to a respective node 190L, 190R, and a gate electrode coupled to the other of the nodes 190L, 190R, as shown.

The memory circuit 180 includes two pull-down transistors 184L, 184R that are operable to pull down the voltage at nodes 190L, 190R to a second voltage level VSS, which may be a low voltage or ground in some embodiments. The pull-down transistors 184L, 184R may be NFETs, as shown, or PFETs. Each of the pull-down transistors 184L, 184R has a source electrode coupled to the second supply node, a drain electrode coupled to the respective node 190L, 190R, and a gate electrode coupled to the other of the nodes 190L, 190R, as shown.

The memory circuit 180 includes two pass gate transistors 186L, 186R that are operable to establish or break electrical communication between nodes 190L, 190R and respective bit lines 192L, 192R, respectively. Pass gate transistors 186L, 186R may be NFETs (as shown) or PFETs. Each of the pass gate transistors 186L, 186R has a first source/drain electrode coupled to a respective bit line 192L, 192R, a second source/drain electrode coupled to a respective node 190L, 190R, and a gate electrode coupled to a word line 194. Bit line 192L passes the first bit line signal B1, bit line 192R passes the second bit line signal BLB, and word line 194 passes the word line signal WL.

The memory circuit 180 includes two gate-to-drain vias 360, each of the two gate-to-drain vias 360 being connected to a respective pair of drain electrodes and a respective pair of gate electrodes of the transistors 182L, 184L or the transistors 182R, 184R. For example, one of the gate-to-drain vias 360 is connected to the gate electrode of the pull-up transistor 182L and the drain electrode of the pull-up transistor 182R. For example, the other of the gate-to-drain vias 360 is connected to the gate electrode of the pull-up transistor 182R and the drain electrode of the pull-up transistor 182L. The gate-to-drain via 360 is L-shaped and may be referred to as an "L-shaped intermediate via 360," which will be described in more detail with reference to fig. 15A-23C. The L-shaped intermediate vias 360 allow for relaxed gate and source/drain isolation overlap, which enables a layout area of the memory circuit 180 to be reduced.

Fig. 2A-15D illustrate the formation of an IC device including one or more CFETs in accordance with various embodiments. In some embodiments, the method 1000 for forming a semiconductor structure includes a number of operations (1100, 1200, 1300, 1400, 1500, 1600, and 1700). The method 1000 for forming a semiconductor structure will be further described in accordance with one or more embodiments. It should be noted that the operations of method 1000 may be rearranged or otherwise modified within the scope of the various aspects. It should also be noted that additional processes may be provided before, during, and after method 1000, and that some other processes may be described only briefly herein.

Fig. 2A illustrates a portion of IC device 100, which may be IC device 180, in accordance with various embodiments. IC device 100 may include one or more CFETs, which will be described in more detail with reference to fig. 2B-15D. IC device 100 includes a gate electrode 112, source/drain regions 116, and source/drain contacts 124. The cross-sectional lines A-A, B-B, C-C and D-D are shown in fig. 2A. Cross-sectional line A-A is an X-direction line through gate electrode 112, source/drain region 116, and source/drain contact 124. Section line B-B is a Y-direction line passing through one of the gate electrodes 112. Section line C-C, D-D is a Y-direction line passing through the respective source/drain regions 116 on either side of section line B-B.

Fig. 2B is a cross-sectional Y-view of IC device 100 at an intermediate stage of manufacture according to some embodiments. In fig. 2B, the multilayer lattice 149 includes a plurality of semiconductor layers 150 and a plurality of sacrificial semiconductor layers 152, 167 stacked on the substrate 101. The sacrificial semiconductor layers 152, 167 are located between the semiconductor layers 150. As will be described in more detail below, the semiconductor layer 150 will ultimately be patterned to form semiconductor nanostructures 106/107, the semiconductor nanostructures 106/107 corresponding to the channel regions of the complementary transistors 104/105 that together constitute the CFET 102. The multilayer lattice 149 may be referred to as a hybrid nanostructure, or may be patterned to form a hybrid nanostructure, as will be described in more detail below.

The sacrificial semiconductor layer 152 includes a semiconductor material different from that of the semiconductor layer 150. In particular, sacrificial semiconductor layer 152 comprises a material that is selectively etchable relative to the material of semiconductor layer 150. As will be described in further detail below, the sacrificial semiconductor layer 152 will ultimately be patterned to form sacrificial semiconductor nanostructures. The sacrificial semiconductor nanostructures will eventually be replaced by gate metal located between the semiconductor nanostructures 106. In one example, the sacrificial semiconductor layer 152 may comprise a single crystal semiconductor material, such as, but not limited to Si, ge, siGe, gaAs, inSb, gaP, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb and InP. In the exemplary process described herein, sacrificial semiconductor layer 152 comprises SiGe and semiconductor layer 150 comprises Si. Other materials and configurations may be used for sacrificial semiconductor layer 152 and semiconductor layer 150 without departing from the scope of the present invention.

In some embodiments, each semiconductor layer 150 comprises intrinsic silicon and each sacrificial semiconductor layer 152 comprises silicon germanium. The sacrificial semiconductor layer may have a relatively low germanium concentration of between 10% and 35%. The concentration in this range may provide sacrificial semiconductor layer 152 that is selectively etchable relative to semiconductor layer 150. In some embodiments, semiconductor layer 150 has a thickness between 2nm and 5 nm. In some embodiments, the sacrificial semiconductor layer 152 has a thickness between 4nm and 10 nm. Other materials, concentrations, and thicknesses may be used for semiconductor layer 150 and sacrificial semiconductor layer 152 without departing from the scope of the present invention.

In some embodiments, the multilayer lattice 149 is formed by performing a series of epitaxial growth processes. The first epitaxial growth process grows the lowermost sacrificial semiconductor layer 152 on the semiconductor substrate 133. The second epitaxial growth process grows the lowermost semiconductor layer 150 on the lowermost sacrificial semiconductor layer 152. An alternating epitaxial growth process is performed to form four lowermost sacrificial semiconductor layers 152 and three lowermost semiconductor layers 150. Depending on the number of semiconductor nanostructures desired for the lower transistor 105 of the CFET 102, more or fewer sacrificial semiconductor layers 152 and semiconductor layers 150 may be formed.

After the semiconductor layer 150 and the sacrificial semiconductor layer 152 related to the lower transistor 105 have been formed, the sacrificial semiconductor layer 167 will be formed. In particular, an epitaxial growth process is performed to form the sacrificial semiconductor layer 167. In one example, sacrificial semiconductor layer 167 is silicon germanium having a thickness between 1nm and 25nm and a length between 15nm and 30 nm. The thickness of the sacrificial semiconductor layer 167 is greater than the thickness of the sacrificial semiconductor layer 152. The thickness of the sacrificial semiconductor layer 152 is greater than the thickness of the semiconductor layer 150. Other compositions, materials, and thicknesses may be used for sacrificial semiconductor layer 167 without departing from the scope of the present invention.

After forming the sacrificial semiconductor layer 167, an upper sacrificial semiconductor layer 152 and a semiconductor layer 150 associated with the upper transistor 104 are formed. The upper sacrificial semiconductor layer 152 and the semiconductor layer 150 may be formed with an alternating epitaxial growth process as described with respect to the lower semiconductor layer 150 and the sacrificial semiconductor layer 152.

A mask layer 160 is formed and patterned over the multilayer lattice 149. In some embodiments, an optional layer 158 is formed between the multilayer lattice 149 and the mask layer 160, as shown. Optional layer 158 may be, for example, a dielectric layer comprising an oxide of the semiconductor material of top semiconductor layer 150. The view in fig. 2C omits optional layer 158.

In fig. 2C, a fin or "fin structure" 32 is formed in a substrate 101 and nanostructures 106, 107 are formed in a multilayer lattice 149, corresponding to operation 1100 of fig. 24. In some embodiments, the nanostructures 106, 107, 165, 167 and the fin 32 may be formed by etching trenches 164 in the multilayer lattice 149 and the substrate 101. The etching may be any acceptable etching process, such as Reactive Ion Etching (RIE), neutral Beam Etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. The first nanostructures 106, 107 (hereinafter also referred to as "channels") are formed by the semiconductor layer 150, and the second nanostructures 165, 167 are formed by the sacrificial semiconductor layer 152, 167. The distance between adjacent fins 32 and nanostructures 106, 107, 165, 167 may be from about 18nm to about 100nm in the Y-axis direction, although other distances less than 18nm or greater than 100nm are also embodiments contemplated herein.

The fins 32 and nanostructures 106, 107, 165, 167 may be patterned by any suitable method. For example, one or more photolithographic processes, including double patterning or multiple patterning processes, may be used to form the fins 32 and the nanostructures 106, 107, 165, 167. Typically, double patterning or multiple patterning processes combine photolithography and self-aligned processes, allowing for a pitch smaller than that obtainable using a single, direct photolithography process. As an example of a multiple patterning process, a sacrificial layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and then the remaining spacers may be used to pattern the fins 32.

Fig. 2C shows fin 32 with tapered sidewalls such that the width of each of fin 32 and/or nanostructures 106, 107, 165, 167 increases continuously in a direction toward substrate 101. In such embodiments, each of the nanostructures 106, 107, 165, 167 may have a different width and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered) such that the width of the fin 32 and the nanostructures 106, 107, 165, 167 are substantially similar, and each of the nanostructures 106, 107, 165, 167 is rectangular in shape.

In fig. 3, after forming the trench 164, an isolation region 174, which may be a Shallow Trench Isolation (STI) region, is formed adjacent to the fin 32. Isolation region 174 may be formed by depositing an insulating material over substrate 101, fin 32, and nanostructures 106, 107, 165, 167 and between adjacent fins 32 and nanostructures 106, 107, 165, 167. The insulating material may be an oxide such as silicon oxide, nitride, or the like, or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. In some embodiments, a liner (not separately shown) may first be formed along the surfaces of the substrate 101, fin 32, and nanostructures 106, 107, 165, 167. Thereafter, a filler or core material, such as those discussed above, may be formed over the liner.

The insulating material is subjected to a removal process, such as a Chemical Mechanical Polishing (CMP), an etchback process, a combination thereof, or the like, to remove excess insulating material over the nanostructures 106, 107, 165, 167. After the removal process is complete, the top surfaces of the nanostructures 106, 107, 165, 167 may be exposed and level with the insulating material.

The insulating material is then recessed to form isolation regions 174. After recessing, the nanostructures 106, 107, 165, 167 and the upper portion of the fin 32 may protrude from between adjacent isolation regions 174. Isolation region 174 may have a top surface that is flat, convex, concave (as shown), or a combination thereof. In some embodiments, isolation region 174 is recessed by an acceptable etching process, such as oxide removal using, for example, dilute hydrofluoric acid (dHF), which is selective to the insulating material and leaves fin 32 and nanostructures 106, 107, 165, 167 substantially unchanged.

Furthermore, in fig. 3, suitable wells (not separately shown) may be formed in fin 32, nanostructures 106, 107, 165, 167, and/or isolation region 174. Using the mask, n-type impurity implantation may be performed in the p-type region of the substrate 101, and p-type impurity implantation may be performed in the n-type region of the substrate 101. Exemplary n-type impurities may include phosphorus, arsenic, antimony, and the like. Exemplary p-type impurities may include boron, boron fluoride, indium, and the like. An anneal may be performed after implantation to repair the implant damage and activate the p-type and/or n-type impurities. In some embodiments, in-situ doping during epitaxial growth of the fin 32 and the nanostructures 106, 107, 165, 167 may avoid separate implants, but in-situ doping and implant doping may be used together.

In fig. 4A-4C, a dummy gate structure or sacrificial gate structure 40 is formed over fin 32 and/or nanostructures 106, 107, 165, 167. A dummy gate layer or sacrificial gate layer 45 is formed over fin 32 and/or nanostructures 106, 107, 165, 167. The dummy gate layer 45 may be made of a material having a high etching selectivity with respect to the isolation region 174. The dummy gate layer 45 may be a conductive, semiconductive, or nonconductive material, and may be or include one or more of amorphous silicon, polysilicon (poly-silicon), poly-silicon-germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. Dummy gate layer 45 may be deposited by Physical Vapor Deposition (PVD), CVD, sputter deposition, or other technique for depositing the selected material. A mask layer 47, which may include, for example, silicon nitride, silicon oxynitride, or the like, is formed over the dummy gate layer 45. In some embodiments, a gate dielectric layer (not shown for simplicity) is formed before dummy gate layer 45 and dummy gate layer 45 between fins 32 and/or nanostructures 106, 107, 165, 167.

In fig. 5A to 5C, a spacer layer 131 is formed over the mask layer 47 and the sidewalls of the dummy gate layer 45. According to some embodiments, the spacer layer 131 is made of an insulating material, such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. The spacer layer 131 may be formed by depositing a spacer material layer (not shown) over the mask layer 47 and the dummy gate layer 45. According to some embodiments, portions of the spacer material layer between the dummy gate structures 40 are removed using an anisotropic etching process.

In fig. 5A-5C, an etching process is performed to etch the protruding fin 32 and/or portions of the nanostructures 106, 107, 165, 167 not covered by the dummy gate structure 40, resulting in the illustrated structure. The recess may be anisotropic such that the portions of fin 32 directly underneath dummy gate structure 40 and spacer layer 41 are protected and not etched. According to some embodiments, the top surface of recessed fin 32 may be substantially coplanar with the top surface of isolation region 174, as shown. According to some other embodiments, the top surface of recessed fin 32 may be lower than the top surface of isolation region 174.

Fig. 6A-6C illustrate the formation of the inner spacers 114. A selective etching process is performed to recess end portions of the nanostructures 165, 167 exposed by the openings in the spacer layer 131 without substantially attacking the nanostructures 106, 107. After the selective etching process, grooves are formed in the nanostructures 165, 167 at locations where the removed end portions were located.

Next, an inner spacer layer is formed to fill the recesses in the nanostructures 165, 167 formed by the previous selective etching process. The internal spacer layer may be a suitable dielectric material such as silicon carbonitride (SiCN), silicon oxynitride (SiOCN), or the like, formed by a suitable deposition method such as PVD, CVD, ALD, or the like. An etching process, such as an anisotropic etching process, is performed to remove portions of the inner spacer layer that are outside the grooves provided in the nanostructures 165, 167. The remaining portions of the inner spacer layer (e.g., the portions disposed inside the grooves in the nanostructures 165, 167) form the inner spacers 114. The resulting structure is shown in fig. 6A.

Fig. 6A-6C illustrate the formation of lower source/drain regions 117, corresponding to operation 1200 of fig. 24. A bottom isolation layer may be formed on the bottom surface of the S/D trench before forming the lower source/drain region 117, and is omitted from the drawing for simplicity of illustration. The formation of the bottom isolation layer may include various processes. For example, an isolation layer may be deposited over the dummy gate structure 40, along the sidewalls of the gate spacer 131, and in the S/D trench. In some embodiments, the isolation layer includes a dielectric material having a different selectivity than the gate spacer 131. For example, the isolation layer comprises a material such as SiO, siN, alumina (Al ₂ O ₃ ) Isolation material, other isolation material, or a combination thereof. The isolation layer may be deposited by CVD, PVD, ALD, other suitable processes, or a combination thereof. The isolation layer has a thickness in the range of about 1nm to about 10nm above the bottom surface of the S/D trench (e.g., the exposed surface of fin structure 32 in the S/D trench), such that the isolation layerThin enough to leave sufficient space for future formed S/D features and thick enough to ensure isolation function over recessed fin portions in the S/D regions. Too thin an isolation layer may cause the bottom isolation layer to crack during a later etching process, such that the S/D component may epitaxially grow from fin structure 32 and cause a significant amount of leakage therebetween.

In the illustrated embodiment, the lower source/drain regions 117 are epitaxially grown from epitaxial material. When a bottom isolation layer is present, the lower source/drain regions 117 may be epitaxially grown outward from the sidewalls of the channels 107 and may merge in the lateral spacing between the channels 107 in the S/D trenches. When a bottom spacer is not present, such as shown in fig. 6A, lower source/drain regions 117 may be epitaxially grown outward from the sidewalls of fin 32 and channel 107. In some embodiments, the lower source/drain regions 117 exert stress in the respective channels 107, thereby improving performance. The lower source/drain regions 117 are formed such that each dummy gate structure 40 is disposed between a respective adjacent pair of the lower source/drain regions 117. In some embodiments, spacer layer 131 separates lower source/drain regions 117 from dummy gate layer 45 by an appropriate lateral distance to prevent electrical bridging to the subsequently formed gates of the resulting device.

The lower source/drain regions 117 may comprise any acceptable material, such as a material suitable for n-type or p-type devices. In some embodiments, for n-type devices, the lower source/drain regions 117 comprise a material that imparts a tensile strain in the channel region, such as silicon, siC, siCP, siP, siAs, and the like. According to some embodiments, when forming a p-type device, the lower source/drain region 117 comprises a material that imparts a compressive strain in the channel region, such as Si B, siGe: B, siGeB, ge, geSn, and the like. The lower source/drain regions 117 may have surfaces that protrude from the corresponding surfaces of the fins 32, and may have facets, as shown in fig. 6C. In some embodiments, adjacent lower source/drain regions 117 may merge to form a single source/drain region 117 adjacent to two adjacent fins 32.

The lower source/drain regions 117 may be implanted with dopants followed by annealing. Lower source/drainPolar region 117 may have a thickness of about 10 ¹⁹ cm ^-3 About 10 ²¹ cm ^-3 The impurity concentration between them. The n-type and/or p-type impurities for the lower source/drain regions 117 may be any of the impurities previously discussed. In some embodiments, the lower source/drain regions 117 are doped in-situ during growth.

In fig. 7A-7C, a lower Contact Etch Stop Layer (CESL) 130 and a lower interlayer dielectric (ILD) 128 (e.g., shown in fig. 7C) are then formed overlying the dummy gate structure 40 (not shown) and the lower source/drain regions 117. The lower CESL 130 may be or include a dielectric material, such as SiN, siCN, etc., which may be formed as a conformal layer, such as PVD, CVD, ALD, etc., by a first deposition operation. The lower ILD 128 may be or include an oxide layer, such as silicon oxide. In some embodiments, the lower ILD 128 may be or include carbon doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated Silicate Glass (FSG), porous dielectric material, or the like. The lower ILD 128 may be formed by a second deposition operation, which may be PVD, CVD, ALD, etc. After depositing the lower ILD 128, the excess portions of the lower ILD 128 that overlie the dummy gate structures 40 and the lower source/drain regions 117 may be removed by one or more suitable removal operations, such as CMP, etching, or other removal operations. The material of the lower ILD 128 may be recessed to a level between the uppermost channel 107 and the lowermost channel 106 by one or more removal operations, as shown in fig. 7A.

In fig. 7A-7C, the upper source/drain regions 116 are formed after the lower ILD 128 is formed. In the illustrated embodiment, the upper source/drain regions 116 are epitaxially grown from an epitaxial material. Upper source/drain regions 116 are epitaxially grown outward from the sidewalls of channel 106 due to the presence of lower ILD 128 and merge in the lateral spacing between channels 106 in the S/D trenches. In some embodiments, the upper source/drain regions 116 exert stress in the respective channels 106, thereby improving performance. The upper source/drain regions 116 are formed such that each dummy gate structure 40 is disposed between a respective adjacent pair of the upper source/drain regions 116. In some embodiments, spacer layer 131 separates upper source/drain regions 116 from dummy gate layer 45 by an appropriate lateral distance to prevent electrical bridging to the subsequently formed gates of the resulting device.

The upper source/drain regions 116 may comprise any acceptable material, such as a material suitable for n-type or p-type devices. In some embodiments, for n-type devices, the upper source/drain regions 116 comprise a material that imparts a tensile strain in the channel region, such as silicon, siC, siCP, siP, siAs, and the like. According to some embodiments, upper source/drain regions 116 comprise a material that imparts a compressive strain in the channel region when forming a p-type device, such as SiGe, siGeB, ge, geSn and the like. The upper source/drain regions 116 may be implanted with dopants followed by an anneal. The upper source/drain regions 116 may have a thickness of about 10 a ¹⁹ cm ^-3 About 10 ²¹ cm ^-3 The impurity concentration between them. The n-type and/or p-type impurities for the upper source/drain regions 116 may be any of the impurities previously discussed. In some embodiments, the upper source/drain regions 116 are doped in-situ during growth.

The upper source/drain regions 116 may have facets as shown in fig. 7C. In some embodiments, adjacent upper source/drain regions 116 may merge to form a single source/drain region 116 adjacent to two adjacent fins 32. In embodiments where a bottom spacer is not present, such that lower source/drain regions 117 are epitaxially grown from fin 32, upper source/drain regions 116 and lower source/drain regions 117 may have different profiles in the XZ plane and the YZ plane, as shown in fig. 7A and 7C. For example, upper source/drain regions 116 grow laterally outward from channel 106, and lower source/drain regions 117 grow laterally outward from channel 107 and upward from fin 32. Thus, the bottom surface of the respective upper source/drain regions 116 may be flat (e.g., inherit the profile of the lower ILD 128), and the bottom surface of the respective lower source/drain regions 117 may be convex (e.g., inherit the profile of the fin 32). The lower source/drain regions 117 may have protruding portions that extend downward below the lower CESL 130, as shown in fig. 7C. The upper source/drain regions 116 may not extend downward under the upper CESL 130A, and the upper CESL 130A may be formed in a later operation (for example, see fig. 8A to 8C). In some embodiments, the bottom surface of the upper source/drain regions 116 is substantially coplanar with the bottom surface of the upper CESL 130A and/or the upper surface of the lower ILD 128.

The source/drain regions 116 comprise a semiconductor material. The semiconductor material may comprise the same semiconductor material as the semiconductor nanostructures 106. Alternatively, the semiconductor material of the source/drain regions 116 may be different from the semiconductor material of the semiconductor nanostructures 106.

In fig. 8A-8C, an upper Contact Etch Stop Layer (CESL) 130A and an upper interlayer dielectric (ILD) 128A are then formed overlying the dummy gate structure 40 (not shown) and the upper source/drain regions 116 (e.g., shown in fig. 8C). The upper CESL 130A may be or include a dielectric material, such as SiN, siCN, etc., which may be formed as a conformal layer, such as PVD, CVD, ALD, etc., by a first deposition operation. The upper ILD 128A may be or include an oxide layer, such as silicon oxide. In some embodiments, upper ILD 128A may be or include carbon doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated Silicate Glass (FSG), porous dielectric material, or the like. The upper ILD 128A may be formed by a second deposition operation, which may be PVD, CVD, ALD, etc. After the deposition of the upper ILD 128A, the excess portions of the upper ILD 128A overlying the dummy gate structure 40 and the upper source/drain regions 116 may be removed by one or more suitable removal operations, such as CMP, etching, or other removal operations. The material of upper ILD 128A, sidewall spacers 131 and dummy gate structure 40 is recessed by one or more removal operations, thereby exposing sacrificial gate layer 45, as shown in fig. 8A. After one or more removal operations, upper surfaces of the sacrificial gate layer 45, the sidewall spacers 131, the upper CESL 130A, and the upper ILD 128A may be substantially coplanar.

Fig. 9A-9C illustrate releasing the channels 106, 107 by removing the nanostructures 165, 167 and the dummy gate layer 45, which corresponds to step 1300 of fig. 24. After a planarization process is performed to make the top surfaces of the sacrificial gate layer 45 and the sidewall spacers 131 flush, the top surface of the dummy gate layer 45 is exposed.

Next, the dummy gate layer 45 is removed in an etching process, thereby forming a groove. In some embodiments, the dummy gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reaction gas, which selectively etches the dummy gate layer 45 without etching the spacer layer 131. When the dummy gate layer 45 is etched, the dummy gate dielectric (when present) may serve as an etch stop layer. Then, after removing the dummy gate layer 45, the dummy gate dielectric may be removed.

The nanostructures 165, 167 are removed to release the nanostructures 106, 107. After removal of the nanostructures 165, 167, the nanostructures 106, 107 form a plurality of nanoplatelets that extend horizontally (e.g., parallel to the major upper surface of the substrate 110). The nanoplates may be collectively referred to as channels 106, 107 of the formed nanostructure device 10.

In some embodiments, the nanostructures 165, 167 are removed by a selective etching process using an etchant that is selective to the material of the nanostructures 165, 167, thereby removing the nanostructures 165, 167 without substantially attacking the nanostructures 106, 107. In some embodiments, the etching process is an isotropic etching process using an etching gas and optionally a carrier gas, wherein the etching gas comprises F ₂ And HF, and the carrier gas may be an inert gas such as Ar, he, N ₂ Combinations thereof, and the like.

In some embodiments, the nanoplatelets 106, 107 of the nanostructure device 10 are remodelled (e.g., thinned) by a further etching process to improve the gate fill window. Remodeling may be performed by an isotropic etching process selective to the nanoplatelets 106, 107. After remodeling, the nanoplatelets 106, 107 may take on a dog bone shape, wherein a middle portion of the nanoplatelets 106, 107 is thinner in the X-direction than a peripheral portion of the nanoplatelets 106, 107.

In fig. 10A-10C, after removal of the sacrificial semiconductor nanostructures 165, 167, after the sacrificial semiconductor nanostructures 165, 167 are sacrificialThe locations where the semiconductor nanostructures 165, 167 were once are left with gaps. The semiconductor nanostructures 106, 107 are exposed. An interfacial gate dielectric layer (or simply "interfacial layer") 108 and a high-K gate dielectric layer 110 are then deposited over the semiconductor nanostructures 106, 107, surrounding the semiconductor nanostructures 106, 107. Interfacial gate dielectric layer 108 may comprise silicon oxide, siON, siN, hfSiO, etc., and may be present inAnd->And a thickness therebetween. A high K dielectric layer 110 is deposited on the interfacial dielectric layer 108 and may comprise hafnium oxide, hfSiO, zrO, or another suitable high K dielectric material. The high-K dielectric layer 110 may have a dielectric constant of +. >And->And a thickness therebetween. The material of gate dielectric layers 108 and 110 may be deposited by ALD, CVD or PVD. Other structures, materials, thicknesses, and deposition processes may be used for the gate dielectric layer without departing from the scope of the invention.

After depositing the interfacial gate dielectric layer 108 and the high-K gate dielectric layer 110 around the semiconductor nanostructures 106, 107, a gate metal 112 is deposited. Gate metal 112 may be deposited by PVD, CVD, ALD or other suitable process. One or more materials of the gate metal 112 may be selected to provide a desired work function with respect to the semiconductor nanostructure 107 of the P-type transistor 105. In one example, the gate metal 112 comprises titanium aluminum. However, other conductive materials may be used for the gate metal 112 without departing from the scope of the present invention. For example, the gate metal 112 may be or include one or more of W, tiN, ti, taN, ta, al, ru, etc.

When the gate metal 112 is initially deposited, the gate metal 112 surrounds or encapsulates the semiconductor nanostructures 106 and the semiconductor nanostructures 107. In some embodiments, the gate metal 112 is of a material that provides a desired work function for the lower transistor 105, and the gate metal 112 may not provide a desired work function for the upper transistor 104. Thus, an etch back process may be performed that removes the gate metal 112 to a level well below the lowermost semiconductor nanostructure 106. In some embodiments, an etch back process removes gate metal 112 to a level approximately in the vertical middle of lower ILD 128 and a second gate metal (not shown) may be formed in place of previously removed gate metal 112.

After depositing the gate metal 112 or optionally after depositing the second gate metal, an etch back process is optionally performed to reduce the height of the gate metal 112 above the top semiconductor nanostructure 106. An optional gate cap metal may be deposited over the gate metal 112 after the etch back process of the gate metal 112. The gate cap metal may comprise tungsten, fluorine-free tungsten, or other suitable conductive material. The gate cap metal may be deposited by PVD, CVD, ALD or other suitable deposition process. The gate cap metal may have a vertical thickness between 1nm and 10 nm. Other dimensions may be utilized without departing from the scope of the present invention.

In fig. 11A-11C, after forming the gate metal 112, a gate isolation structure 99 is formed, corresponding to step 1400 of fig. 24. The gate isolation structure 99 may be or include one or more materials that electrically isolate portions of the gate metal 112 from other portions of the gate metal 112. The material of the gate isolation structure 99 may include SiO ₂ SiON, siN, etc. The gate isolation structure 99 may be a multilayer including one or more of the just mentioned materials. The formation of the gate isolation structure 99 may include one or more operations including photolithography, etching, and deposition. One or more mask layers may be formed over the gate metal 112, the upper ILD 128A, the upper CESL 130A, and the sidewall spacers 131. The mask layer may be patterned by photolithographic exposure, and then exposed or unexposed areas of the mask layer may be removed to form openings therein. After forming the openings, the openings may be etched through one or more of the openings in the mask layer The etching operation removes the exposed areas of the gate metal 112, the upper and lower ILD 128A and 128, and the upper and lower CESL 130A and 130 to form gate isolation openings. After the gate isolation openings are formed, the material of the gate isolation structure 99 is deposited in the gate isolation openings by a suitable deposition operation, which may be PVD, CVD, ALD or the like.

In some embodiments, the gate isolation structures 99 extend in a first direction (e.g., an X-axis direction) and are arranged along a second direction (e.g., a Y-axis direction). The width of the gate isolation structure 99 (e.g., in the Y-axis direction) may be in the range of about 5nm to about 40 nm.

In fig. 12A-12D, after forming the gate isolation structure 99, source/drain contacts 124A, 124B and optional suicides 120A, 120B are formed. In some embodiments, one or more mask layers are formed over gate metal 112, upper ILD 128A, upper CESL 130A, sidewall spacers 131, and gate isolation structure 99. The mask layer may be patterned by photolithographic exposure, and then exposed or unexposed areas of the mask layer may be removed to form openings therein. The exposed areas of the upper ILD 128A and the upper CESL 130A may be etched through openings in the mask layer to form contact openings. One or more of the contact openings (which may be referred to as first contact openings) may extend through one of the upper source/drain regions 116, the lower ILD 128, and the lower CESL 130 to expose the lower source/drain regions 117. For example, a first contact opening corresponding to the source/drain contact 124B may be etched in a first etching operation while masking a region corresponding to the source/drain contact 124A, and then a second etching operation may be performed, which forms a second contact opening corresponding to the source/drain contact 124A and extends the first contact opening.

After the contact openings are formed, the source/drain contacts 124A, 124B may be formed by one or more deposition operations. The source/drain contacts 124A, 124B may comprise a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. The source/drain contacts 124A, 124B may be laterally surrounded by a barrier layer (not shown), such as SiN or TiN, which helps prevent or reduce diffusion of material from the source/drain contacts 124A, 124B into the source/drain contacts 124A, 124B.

Silicide layers 120A, 120B, 120C may also be formed between the source/drain regions 116, 117 and the source/drain contacts 124A, 124B, which may be advantageous in reducing the source/drain contact resistance. The silicide layers 120A, 120B, 120C may comprise a metal silicide material, such as cobalt silicide in some embodiments, or TiSi in some other embodiments. The silicide layers 120A, 120B may be referred to as horizontal silicide layers and have major surfaces in the XY plane. Silicide layer 120C may be referred to as a vertical silicide layer and has a major surface in the XZ plane. Source/drain contacts 124B extending through upper source/drain regions 116 are adjacent to or laterally surrounded by vertical silicide layer 120C and adjacent to or directly on horizontal silicide layer 120B, as shown in fig. 12C. As shown in fig. 12D, the source/drain contacts 124A may extend laterally (e.g., in the Y-axis direction) to abut one of the gate isolation structures 99.

In fig. 13A-13D, one or more front side interconnect layers may be formed after the source/drain contacts 124A, 124B are formed. Each front-side interconnect layer may include one or more of ILD and CESL and may include metal regions, which may be wires, traces, vias, and the like. A single front side interconnect layer including CESL 142, ILD 320, and source/drain vias 360 is shown in fig. 13A-13D. CESL 142 may be deposited, and ILD 320 may then be deposited over CESL 142. ILD 320 and CESL 142 may be patterned to form one or more openings exposing source/drain contacts 124, such as source/drain contacts 124B shown in fig. 13A. Source/drain vias 360 are then formed in the openings by a suitable deposition process, such as PVD, CVD, ALD. The source/drain via 360 may comprise the same material as the source/drain contact 124B or a different material, and may comprise Ru, W, al, cu, mo, co, combinations thereof, or the like. Although not specifically shown, gate vias may be formed through ILD 320 and CESL 142 to contact gate metal 112. One or more of the source/drain vias 360 may contact the source/drain contacts 124 and the gate metal 112.

In fig. 14A-14D, an additional front side interconnect layer 400 is formed over ILD 320 and source/drain via 360. Each of the front-side interconnect layers 400 may include one or more of ILD and CESL and may include metal regions, which may be wires, traces, vias, etc. The front-side interconnect layer 400 facilitates the formation of electrical connections between the source/drain electrodes 116, 117 and the electrodes of other transistors, capacitors, resistors, etc. The front-side interconnect layer 400 may be referred to as a front-side back-end-of-line (BEOL) interconnect structure.

In fig. 15A to 15D, a backside interconnect structure 500 is formed on the bottom side of the substrate 101. Forming the backside interconnect structure 500 may include: attaching a carrier substrate to the front side of the intermediate structure, flipping the structure over; and performing a backside process on the backside of the intermediate structure. The backside processing may include removing the substrate 101, removing the fins 32, and optionally the isolation regions 174. Removing the substrate 101 and fin 32, and optional isolation region 174, may include one or more removal processes, such as a planarization process, an etching process, and the like. The planarization process may include CMP, grinding, and the like. In some embodiments, the substrate 101 is removed by a planarization process, exposing the fin 32 and isolation region 174. Fin 32 and optional isolation region 174 are then removed by one or more etching operations that stop on underlying structures, such as high-k gate dielectric layer 110, lower source/drain regions 117, inner spacers 114, and gate isolation structure 99. As shown in fig. 15C, the etching operation may stop on the lower source/drain region 117. After removing the substrate 101, fin 32, and optional isolation regions 174, the bottom of the lower source/drain regions 117 is exposed.

In fig. 15A to 15D, the isolation region 174 is not removed. In such an embodiment, after removing fin 32, a dielectric liner layer 471 and a dielectric core layer 470 may be formed in the opening where fin 32 was located between isolation regions 174, as shown. The liner layer 471 and the core layer 470 may then be patterned to form backside contact openings exposing one or more of the lower source/drain regions 117.

After exposing the lower source/drain regions 117, backside source/drain contacts 460 are formed in the backside contact openings, which may be implemented using the same or similar materials and processes used to form source/drain contacts 124 on the front side. In some embodiments, the backside source/drain contacts 460 are laterally surrounded by one or more barrier layers, which may be similar or identical to the barrier layers previously described with reference to the source/drain contacts 124.

After the backside source/drain contacts 460 are formed, the backside interconnect structure 500 is formed. The backside interconnect structure 500 may also be referred to as a backside back-end-of-line (BEOL) interconnect structure 500. The backside interconnect structure 500 is similar in many respects to the front side interconnect structure 400 and may include one or more interconnect layers. Each of the interconnect layers may include a CESL, an ILD, and one or more metal features in the CESL and ILD. The metal components may include vias, wires, traces, and the like. In some embodiments, the backside interconnect structure 500 may include electrical contacts, such as solder bumps, controlled collapse chip connection (C4) bumps, and the like. In some embodiments, the front side of the IC device 100 is free of electrical contacts.

Fig. 16A to 23C are a schematic plan view and a sectional side view showing the formation of an L-shaped intermediate through hole 360 according to various embodiments. Fig. 16A, 17A, 18A, and 19A are plan views. Fig. 16B, 17B, 18B, and 19B are cross-sectional side views along line B-B of fig. 16A, 17A, 18A, and 19A. Fig. 16C, 17C, 18C and 19C are cross-sectional side views along line C-C of fig. 16A, 17A, 18A and 19A. Fig. 16D, 17D, 18D and 19D are cross-sectional side views along line D-D of fig. 16A, 17A, 18A and 19A.

In fig. 16A to 16D, a gate isolation structure 99 is formed in a similar manner to that described with reference to fig. 11A to 11C. Gate isolation structure 99 extends from the top of gate metal 112 to the upper surface of isolation region 174. Fig. 16A shows the relative positions of the transistors 182L, 182R, 184L, 184R, 186L, 186R in dashed lines. As an example, as shown in fig. 16C, a pull-down transistor 184L is disposed over the pull-up transistor 182L, and a transfer gate transistor 186L is adjacent to the pull-up transistor 182L in the X-axis direction. The transistor 188 directly above the transfer gate transistor 186L is removed in a subsequent operation, and the transistor 188 may be referred to as a dummy transistor or a sacrificial transistor 188.

In fig. 17A-17D, a dielectric layer 99A is formed after forming the gate isolation structure 99, corresponding to steps 1500 and 1600 of fig. 24. The dielectric layer 99A may be formed by one or more photolithographic operations that form openings exposing the gate metal 112 of the dummy transistor 188. The gate metal 112 is etched through the opening or the gate metal 112 is recessed (step 1500). After the gate metal 112 is removed, the nanostructure channel 106 of the dummy transistor 188 is completely or partially removed.

After recessing the gate metal 112, a dielectric layer 99A is formed in the opening (step 1600). As shown in fig. 17C, dielectric layer 99A may abut channel 106, inner spacer 114, sidewall spacer 131, and the remaining portion of gate metal 112 that underlies dummy transistor 188. The dielectric layer 99A may be or include the same material as the gate isolation structure 99. In some embodiments, the dielectric layer 99A is a different material than the gate isolation structure 99. The dielectric layer 99A may be deposited by a suitable deposition process, such as PVD, CVD, ALD and the like.

In fig. 18A to 18D, an L-shaped intermediate through hole 360 is formed, corresponding to step 1700 of fig. 24. Prior to forming the L-shaped intermediate via 360, the source/drain contact 124 is formed as described with reference to fig. 12A-12D. As shown in fig. 18C, the source/drain contacts 124 may include a source contact 124A that contacts the source 116 of the pull-down transistor 184L. Source/drain contacts 124 may include drain contacts 124B that contact drains 116 of pull-up transistor 182L, pull-down transistor 184L, and pass-gate transistor 186L. Source/drain contacts 124 may include drain contacts 124C (see fig. 18D) that contact drains 116 of pull-up transistor 182R, pull-down transistor 184R, and pass-gate transistor 186R.

After the source/drain contacts 124 are formed, L-shaped intermediate vias 360 are formed. CESL 142 and ILD 320 may be formed as described with reference to fig. 13A-13D. ILD 320 and CESL 142 may then be patterned to form openings in which L-shaped intermediate vias 360 are formed in subsequent operations. An L-shaped intermediate through hole 360 is then formed in the opening. In some embodiments, the L-shaped intermediate vias 360 are formed in the same manner using the same materials and processes described with reference to fig. 13A-13D. The material of the L-shaped intermediate vias 360, such as W, co, mo, ru, cu, al, etc., may be deposited in the openings by a suitable deposition operation, such as PVD, CVD, or ALD. The excess material of the L-shaped intermediate vias 360 that is located over the ILD 320 may then be removed by a planarization operation, such as CMP.

As shown in fig. 18A, each of the intermediate through holes 360 may have a first portion extending in a first direction (such as a Y-axis direction). Each of the intermediate through holes 360 may have a second portion extending in a second direction (such as the X-axis direction). The second portion may be wider than the first portion in the X-axis direction. The first portion may overlap the gate metal 112, the gate isolation structure 99, and the dielectric layer 99A of the transistors 182L, 184L (or the transistors 182R, 184R). In some embodiments, the first portion extends beyond the second portion, as shown in phantom in fig. 18B, and is labeled 360A. The second portion extends to contact the drain contact 124C (or drain contact 124B), as shown in fig. 18A, 18C, and 18D. Providing the intermediate via 360 to overlap the dielectric layer 99A allows for a reduction in cell height by relaxing the gate isolation structure cover window and the drain isolation/spacer cover window.

In fig. 19A to 19D, front-side wirings and back-side wirings are formed, which are described with reference to fig. 14A to 14D and fig. 15A to 15D, respectively. As shown in fig. 19C, a first backside via 460 is provided to couple a lower source region 117 to a bit line 192L that conveys a signal BL, and a second backside via 460A is provided to couple another lower source region 117 to a power supply node that provides a first voltage level VDD. Source via 124A couples upper source region 116 to a power supply node that provides a second voltage level VSS.

In the devices shown in fig. 19A to 19D, the transistor including the lower source/drain region 117 is a P-type transistor, and the transistor including the upper source/drain region 116 is an N-type transistor. In some embodiments, the transistor including the lower source/drain region 117 is an N-type transistor and the transistor including the upper source/drain region 116 is a P-type transistor. In such an embodiment, the pass gate transistors 186L, 186R located under the dielectric layer 99A may be N-type transistors. The gate electrodes 112 of pass gate transistors 186L, 186R are coupled to the word line through backside gate via 470.

Fig. 20A, 20B illustrate an embodiment in which pass gate transistors 186L, 186R are located over dielectric layer 99A and connected to upper source/drain regions 116. For simplicity of illustration, some components (e.g., ILD 320) are omitted from the views in one or both of fig. 20A, 20B. In such an embodiment, an L-shaped intermediate via 360 is provided on the back side of the IC device 100, as shown by L-shaped intermediate via 360BS in fig. 20A. The gate electrodes 112 of pass gate transistors 186L, 186R are coupled to the word line through front side gate via 470 FS.

In the embodiment shown in fig. 20A, 20B, the dielectric layer 99A may be formed using a different process than previously described. That is, after the front side source/drain contacts 124 and the front side interconnect structure 400 are formed, the IC device may be flipped over and the substrate 101 may be removed, as previously described with reference to fig. 15A-15D. After removing the substrate 101, the isolation region 174 and the fin 32 corresponding to the gate metal 112 to be removed are removed, thereby exposing the gate metal 112. The gate metal 112 and the nanostructures 107 are completely or partially removed by a suitable etching process, leaving an opening for depositing the dielectric layer 99A. In such an embodiment, dielectric layer 99A may contact channel 107, inner spacer 114, and the bottom of gate metal 112 of pass gate transistor 186L (or 186R), as shown in fig. 20B. After forming the dielectric layer 99A, the L-shaped intermediate via 360BS may be formed in a backside process similar to the process described with reference to fig. 15A to 15D. That is, after forming the backside source/drain contacts 460 (or 460A) in the backside ILD 420, the backside L-shaped intermediate vias 360BS may be formed by patterning a second backside ILD on the backside ILD 420 to form openings, and depositing conductive material of the backside L-shaped intermediate vias 360BS in the openings.

In some embodiments, the pass gate transistors 186L, 186R shown in fig. 20A are N-type transistors or P-type transistors. In fig. 20A, pass gate transistors 186L, 186R are of the same type as pull-down transistors 184L, 184R. In fig. 19A, pass gate transistors 186L, 186R are of the same type as pull-up transistors 182L, 182R.

Fig. 21A-21C are plan views of L-shaped intermediate through holes 360 according to various embodiments. In some embodiments, the L-shaped intermediate through-hole 360 has a height H and a width W, as shown. The width W may be in the range of about 20nm to about 80 nm. The ratio of height H to width W may be about 2 (fig. 21A), about 1.5 (fig. 21B), or 1 (fig. 21C). Other ratios of height H to width W that fall between the ratios just mentioned are also embodiments contemplated herein. For example, the ratio may be 1.2, 1.7, or another suitable ratio.

Fig. 22 and 23A-23C illustrate L-shaped intermediate through holes 360 according to various other embodiments. In fig. 22, the L-shaped intermediate through hole 360 has a first portion that extends beyond a second portion, as described above with reference to fig. 18A-18D. As shown in fig. 23A to 23C, the extension portion of the intermediate through hole 360 may have a height H2 and a width W1. The height H1 may be the same size as the height H shown in fig. 21A to 21C. The width w1+w2 may be the same size as the width W shown in fig. 21A to 21C. In some embodiments, the height H2 of the extension portion may be in the range of about 10nm to about 40 nm. The shape of the intermediate through-hole 360 may also be referred to as a T-shape, and the intermediate through-hole 360 of fig. 23A to 23C may be referred to as a T-shaped intermediate through-hole 360A. Referring again to fig. 18b, the extension of the t-shaped intermediate through-hole 360A is shown in phantom. In such an embodiment, a first portion of the T-shaped intermediate via 360A extending in the Y-axis direction may extend beyond the nanostructure 107, as shown in fig. 18B.

Embodiments may provide advantages. The L-shaped intermediate via 360 or the T-shaped intermediate via 360A reduces the cell area by relaxing the gate isolation structure cover window and the source/drain region isolation cover window.

According to at least one embodiment, a device includes: a first stack of first semiconductor nanostructures; a second stack of second semiconductor nanostructures on the first stack of first semiconductor nanostructures; a third stack of first semiconductor nanostructures adjacent to the first stack; a first gate structure surrounding the first stack and the second stack; a second gate structure surrounding the third stack; a gate isolation structure between the first gate structure and the second gate structure; a dielectric layer on the second gate structure and laterally adjoining the gate isolation structure; and a through hole. The through hole includes: a first portion extending in a first direction, the first portion being located on the first gate structure, the gate isolation structure and the dielectric layer; and a second portion extending in a second direction transverse to the first direction.

According to at least one embodiment, a method comprises: forming a first vertical stack of nanostructure channels, a second vertical stack of nanostructure channels, a third vertical stack of nanostructure channels, and a fourth vertical stack of nanostructure channels over the substrate, the second vertical stack being on the first vertical stack, the fourth vertical stack being on the third vertical stack; forming a first source/drain region adjacent the nanostructure channel of the first vertical stack and forming a second source/drain region adjacent the nanostructure channel of the second vertical stack; forming a gate structure surrounding nanostructure channels of the first vertical stack, the second vertical stack, the third vertical stack, and the fourth vertical stack; forming a first gate structure and a second gate structure by forming a gate isolation structure extending through the gate structure; forming an opening by removing a portion of the second gate structure; forming a dielectric layer in the opening; and forming a via hole on the first gate structure and the dielectric layer.

According to at least one embodiment, a memory circuit includes: a first pull-up transistor having a first stack of nanostructure channels; a first pull-down transistor. The first pull-down transistor includes: a second stack of nanostructure channels on the first stack; and a drain electrode coupled to the drain electrode of the first pull-up transistor. The memory circuit further includes: a second pull-up transistor having a gate electrode; a first pass gate transistor comprising: a third stack of nanostructure channels laterally spaced apart from the first stack and the second stack; a gate electrode; and a drain electrode coupled to the drain electrodes of the first pull-up transistor and the first pull-down transistor; and a through hole. The through hole includes: a first portion extending in a first direction, the first portion being located on the gate electrode; and a second portion extending in a second direction transverse to the first direction, the second portion being on the drains of the first pull-up transistor, the first pull-down transistor, and the first pass-gate transistor.

Some embodiments of the present application provide a semiconductor device including: a first stack of first semiconductor nanostructures; a second stack of second semiconductor nanostructures on the first stack of first semiconductor nanostructures; a third stack of first semiconductor nanostructures adjacent to the first stack; a first gate structure surrounding the first stack and the second stack; a second gate structure surrounding the third stack; a gate isolation structure located between the first gate structure and the second gate structure; a dielectric layer on the second gate structure and laterally adjoining the gate isolation structure; and a through hole including: a first portion extending in a first direction, the first portion being located on the first gate structure, the gate isolation structure and the dielectric layer; and a second portion extending in a second direction transverse to the first direction. In some embodiments, the first portion partially overlaps the third stack in the first direction. In some embodiments, the first portion extends in the first direction across the third stack. In some embodiments, the via is electrically connected to a drain region of a first pull-up transistor and to a gate electrode of a second pull-up transistor, the gate electrode comprising the first gate structure. In some embodiments, the first portion overlaps the gate electrode and the second portion overlaps the drain region. In some embodiments, the through hole has a height in the first direction and a width in the second direction, and a ratio of the height to the width is in a range of 1 to 2. In some embodiments, the semiconductor device further comprises: a first source/drain region adjacent to the first stack of first semiconductor nanostructures; a second source/drain region adjacent to a second stack of the first semiconductor nanostructure; a third source/drain region adjacent to a third stack of the first semiconductor nanostructure; a first source/drain contact on the second source/drain region; and a second source/drain contact located under the first source/drain region. In some embodiments, the semiconductor device further comprises: a fourth source/drain region adjacent to the dielectric layer; and a third source/drain contact located on the third source/drain region, the third source/drain contact extending through the fourth source/drain region.

Further embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a first vertical stack of nanostructure channels, a second vertical stack of nanostructure channels, a third vertical stack of nanostructure channels, and a fourth vertical stack of nanostructure channels over a substrate, the second vertical stack being located on the first vertical stack, the fourth vertical stack being located on the third vertical stack; forming a first source/drain region adjacent to the nanostructure channel of the first vertical stack and forming a second source/drain region adjacent to the nanostructure channel of the second vertical stack; forming a gate structure surrounding the nanostructure channels of the first vertical stack, the second vertical stack, the third vertical stack, and the fourth vertical stack; forming a first gate structure and a second gate structure by forming a gate isolation structure extending through the gate structure; forming an opening by removing a portion of the second gate structure; forming a dielectric layer in the opening; and forming a via hole on the first gate structure and the dielectric layer. In some embodiments, the method further comprises: source/drain contacts are formed on the second source/drain regions. In some embodiments, the openings are formed after the source/drain contacts are formed. In some embodiments, the method further comprises: exposing an underside of the second gate structure by removing the substrate; and forming the opening by etching the underside of the second gate structure. In some embodiments, the through hole comprises: a first portion extending in a first direction, the first portion being located on the first gate structure, the gate isolation structure and the dielectric layer; and a second portion extending in a second direction transverse to the first direction.

Still further embodiments of the present application provide a memory circuit comprising: a first pull-up transistor having a first stack of nanostructure channels; a first pull-down transistor comprising: a second stack of nanostructure channels on the first stack; and a drain electrode coupled to the drain electrode of the first pull-up transistor; a second pull-up transistor having a gate electrode; a first pass gate transistor comprising: a third stack of nanostructure channels laterally spaced apart from the first stack and the second stack; a gate electrode; and a drain electrode coupled to drain electrodes of the first pull-up transistor and the first pull-down transistor; and a through hole including: a first portion extending in a first direction, the first portion being located on the gate electrode; and a second portion extending in a second direction transverse to the first direction, the second portion being located on drains of the first pull-up transistor, the first pull-down transistor, and the first pass-gate transistor. In some embodiments, the memory circuit further comprises: a second pull-down transistor having a gate electrode coupled to the gate electrode of the second pull-up transistor; and a second pass gate transistor having a drain electrode coupled to drain electrodes of the second pull-up transistor and the second pull-down transistor. In some embodiments, the memory circuit further includes a second via, the second via including: a third portion extending in the first direction, the third portion being located on gate electrodes of the first pull-up transistor and the first pull-down transistor; and a fourth portion extending in the second direction transverse to the first direction, the second portion being on the drains of the second pull-up transistor, the second pull-down transistor, and the second pass-gate transistor. In some embodiments, the via and the second via are disposed on a backside of the memory circuit. In some embodiments, the memory circuit further comprises: a dielectric layer on the third stack. In some embodiments, the dielectric layer extends vertically from the gate electrode of the first pass gate transistor to a bottom side of the via. In some embodiments, the memory circuit further comprises: a backside via electrically connected to the gate electrode of the first pass gate transistor and electrically connected to a word line.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising:

a first stack of first semiconductor nanostructures;

a second stack of second semiconductor nanostructures on the first stack of first semiconductor nanostructures;

a third stack of first semiconductor nanostructures adjacent to the first stack;

a first gate structure surrounding the first stack and the second stack;

a second gate structure surrounding the third stack;

a gate isolation structure located between the first gate structure and the second gate structure;

A dielectric layer on the second gate structure and laterally adjoining the gate isolation structure; and

a through-hole, the through-hole comprising:

a first portion extending in a first direction, the first portion being located on the first gate structure, the gate isolation structure and the dielectric layer; and

a second portion extending in a second direction transverse to the first direction.

2. The semiconductor device of claim 1, wherein the first portion partially overlaps the third stack in the first direction.

3. The semiconductor device of claim 1, wherein the first portion extends in the first direction across the third stack.

4. The semiconductor device of claim 1, wherein the via is electrically connected to a drain region of a first pull-up transistor and to a gate electrode of a second pull-up transistor, the gate electrode comprising the first gate structure.

5. The semiconductor device according to claim 4, wherein the first portion overlaps with the gate electrode and the second portion overlaps with the drain region.

6. The semiconductor device according to claim 1, wherein the via has a height in the first direction and a width in the second direction, and a ratio of the height to the width is in a range of 1 to 2.

7. The semiconductor device of claim 1, further comprising:

a first source/drain region adjacent to the first stack;

a second source/drain region adjacent to the second stack;

a third source/drain region adjacent to the third stack;

a first source/drain contact on the second source/drain region; and

a second source/drain contact is located under the first source/drain region.

8. The semiconductor device of claim 7, further comprising:

a fourth source/drain region adjacent to the dielectric layer; and

a third source/drain contact is located on the third source/drain region, the third source/drain contact extending through the fourth source/drain region.

9. A method of forming a semiconductor device, comprising:

forming a first vertical stack of nanostructure channels, a second vertical stack of nanostructure channels, a third vertical stack of nanostructure channels, and a fourth vertical stack of nanostructure channels over a substrate, the second vertical stack being located on the first vertical stack, the fourth vertical stack being located on the third vertical stack;

Forming a first source/drain region adjacent to the nanostructure channel of the first vertical stack and forming a second source/drain region adjacent to the nanostructure channel of the second vertical stack;

forming a gate structure surrounding the nanostructure channels of the first vertical stack, the second vertical stack, the third vertical stack, and the fourth vertical stack;

forming a first gate structure and a second gate structure by forming a gate isolation structure extending through the gate structure;

forming an opening by removing a portion of the second gate structure;

forming a dielectric layer in the opening; and

a via is formed over the first gate structure and the dielectric layer.

10. A memory circuit, comprising:

a first pull-up transistor having a first stack of nanostructure channels;

a first pull-down transistor comprising:

a second stack of nanostructure channels on the first stack; and

a drain electrode coupled to a drain electrode of the first pull-up transistor;

a second pull-up transistor having a gate electrode;

a first pass gate transistor comprising:

a third stack of nanostructure channels laterally spaced apart from the first stack and the second stack;

A gate electrode; and

a drain electrode coupled to drain electrodes of the first pull-up transistor and the first pull-down transistor; and

a through-hole, the through-hole comprising:

a first portion extending in a first direction, the first portion being located on the gate electrode; and

a second portion extending in a second direction transverse to the first direction, the second portion being on the drains of the first pull-up transistor, the first pull-down transistor, and the first pass-gate transistor.