CN117457522A

CN117457522A - Display processing method and device for wafer test result and electronic equipment

Info

Publication number: CN117457522A
Application number: CN202311466637.5A
Authority: CN
Inventors: 蒋宏业; 郑尊标; 欧阳震
Original assignee: Hangzhou Chipwing Technology Co ltd
Current assignee: Hangzhou Chipwing Technology Co ltd
Priority date: 2023-11-06
Filing date: 2023-11-06
Publication date: 2024-01-26

Abstract

The application provides a display processing method and device for wafer test results and electronic equipment, wherein the method comprises the following steps: acquiring test information of each crystal grain of a target wafer and position information in the target wafer, wherein the test information comprises a test wheel identifier, a test time identifier and a test result in each test time of the crystal grain; determining the number of test wheels and the number of test times of each grain according to the test wheel identification and the test time identification of each grain; and drawing and displaying the test information of each die in the wafer map of the target wafer according to the number of test rounds, the test times of each die, the test results in each test round and the position information. The test information of all rounds of each crystal grain in the wafer can be visually checked, so that the retested crystal grain and retested test result and the change condition of the test result of each round can be rapidly determined, and the efficiency of analyzing the test result by a user is improved.

Description

Display processing method and device for wafer test result and electronic equipment

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a display processing method and apparatus for a wafer test result, and an electronic device.

Background

In the field of semiconductor technology, wafer probe testing refers to testing voltage, current, frequency and the like on chip dies on a wafer before packaging, and is used for verifying whether each chip meets product specifications, when the wafer testing is performed, multiple tests are required to be performed on defective dies, multiple test results exist for the dies tested for multiple times, and a tester analyzes the dies according to the multiple test results tested.

In the prior art, a tester analyzes a wafer graph drawn by a first test result and a wafer graph drawn by a last test result of a wafer in a manual naked eye comparison mode.

However, this method cannot check all test results, and when the number of dies retested on one wafer map is large, it is difficult to quickly and accurately identify the retested dies by naked eye comparison, so that the wafer cannot be accurately analyzed.

Disclosure of Invention

The invention aims to provide a display processing method, a device and electronic equipment for wafer test results, aiming at the defects in the prior art, and the display processing method, the device and the electronic equipment can visually check all test results of each crystal grain in a wafer and improve the efficiency of analyzing the test results by a user.

In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

in a first aspect, an embodiment of the present application provides a method for displaying and processing a wafer test result, where the method includes:

acquiring test information of each crystal grain of a target wafer and position information in the target wafer, wherein the test information comprises a test wheel identifier, a test time identifier and test results in each test time of the crystal grain, and the test results are used for indicating whether the crystal grain is tested successfully or not;

determining the number of test wheels and the number of test times of each grain according to the test wheel identification and the test time identification of each grain;

and drawing and displaying the test information of each die in the wafer map of the target wafer according to the number of test rounds, the test times of each die, the test results in each test round and the position information.

Optionally, the drawing and displaying the test information of each die on the target wafer according to the number of test rounds, the test times, the test results in each test round and the position information of each die includes:

determining a die block of the die in the wafer map according to the position information;

Cutting the grain blocks according to the number of test rounds and the test times to obtain at least one sub-grain block, and establishing a corresponding relation between each sub-grain block and each test result according to the sequence among the test results;

and drawing and displaying corresponding display marks on each sub-grain block according to the corresponding relation between each sub-grain block and each test result and the display marks corresponding to each test result.

Optionally, the dicing the die block according to the number of test rounds and the number of test times to obtain at least one sub-die block, including:

the grain blocks are subjected to segmentation processing according to the number of the test wheels and the sequence of the test wheels, so that at least one middle grain block is obtained, and each middle grain block is used for corresponding one-round test;

and sequentially cutting each intermediate grain block according to the test times and the test time sequence corresponding to each round of test to obtain at least one sub-grain block.

Optionally, the drawing and displaying the corresponding display mark on each sub-die block according to the corresponding relation between each sub-die block and each test result and the display mark corresponding to each test result includes:

Obtaining a target display mode selected by a user, wherein the target display mode comprises the following steps: a success-failure mode or a multi-dimensional mode;

determining display marks corresponding to all test results according to the target display mode;

Optionally, the determining, according to the target display mode, a display mark corresponding to each test result includes:

and if the target display mode is the success/failure mode, traversing each test result, and aiming at the traversed current test result, if the current test result indicates that the test is successful, determining that the display mark of the current test result is a first mark, otherwise, determining that the display mark of the current test result is a second mark.

and if the target display mode is the multi-dimensional mode, traversing each test result, and aiming at the traversed current test result, if the current test result indicates that the test is successful, determining the display mark of the current test result as a third mark, otherwise, determining the display mark of the current test result according to failure grade information in the current test result.

Optionally, the method further comprises:

determining the grains with abnormal testing process according to the testing information of each grain;

drawing a preset abnormal mark at the edge of each grain block with abnormal testing process in the wafer map.

In a second aspect, an embodiment of the present application further provides a display processing device for a wafer test result, where the device includes:

the device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring test information of each crystal grain of a target wafer and position information in the target wafer, the test information comprises a test wheel identifier, a test time identifier and a test result in each test time of the crystal grain, and the test result is used for indicating whether the test of the crystal grain is successful or not;

the determining module is used for determining the number of test wheels and the number of test times of each grain according to the test wheel identifier and the test time identifier of each grain;

and the drawing module is used for drawing and displaying the test information of each crystal grain in the wafer diagram of the target wafer according to the test round number, the test times, the test results in each test round and the position information of each crystal grain.

Optionally, the drawing module is specifically configured to:

Optionally, the drawing module is further specifically configured to:

In a third aspect, an embodiment of the present application further provides an electronic device, including: the device comprises a processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor, when an application program runs, the processor and the storage medium are communicated through the bus, and the processor executes the program instructions to execute the steps of the wafer test result display processing method in the first aspect.

In a fourth aspect, embodiments of the present application further provide a computer readable storage medium, where a computer program is stored, where the computer program is read and executed to perform the steps of the method for displaying a wafer test result according to the first aspect.

The beneficial effects of this application are:

according to the display processing method, the display processing device and the electronic equipment for the wafer test result, the test wheel number and the test times of each crystal grain are determined through the obtained test wheel identification and the test time identification of each crystal grain, the test information of each crystal grain is drawn and displayed in the wafer diagram of the target wafer according to the test wheel number, the test times, the test result and the position information of each crystal grain, the test information of all the crystal grain in the wafer can be visually checked, the retested crystal grain and the retested test result can be quickly determined, and the change condition of the test result of each time can enable a user to quickly identify defects according to the displayed test information of each crystal grain, the retested proportion and effect can be intuitively analyzed, and the efficiency of the user in analyzing the test result is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flow chart of a processing method for displaying wafer test results according to an embodiment of the present application;

fig. 2 is a schematic view of a portion of a structure of a target wafer according to an embodiment of the present application;

FIG. 3 is a flow chart of another method for displaying wafer test results according to an embodiment of the present disclosure;

FIG. 4 is a flowchart of another method for displaying wafer test results according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a die block divided according to a round in accordance with an embodiment of the present application;

FIG. 6 is a flowchart illustrating a processing method for displaying a wafer test result according to another embodiment of the present disclosure;

FIG. 7 is a schematic diagram of an apparatus for displaying a wafer test result according to an embodiment of the present disclosure;

Fig. 8 is a block diagram of an electronic device according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it should be understood that the accompanying drawings in the present application are only for the purpose of illustration and description, and are not intended to limit the protection scope of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. A flowchart, as used in this application, illustrates operations implemented according to some embodiments of the present application. It should be understood that the operations of the flow diagrams may be implemented out of order and that steps without logical context may be performed in reverse order or concurrently. Moreover, one or more other operations may be added to the flow diagrams and one or more operations may be removed from the flow diagrams as directed by those skilled in the art.

In addition, the described embodiments are only some, but not all, of the embodiments of the present application. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.

It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the presence of the features stated hereinafter, but not to exclude the addition of other features.

Optionally, the method for displaying and processing the wafer test result provided in the embodiment of the present application is applied to an electronic device, where the electronic device may be, for example, a mobile phone, a tablet computer, a notebook computer, a palm computer, a desktop computer, or other terminal devices with computing processing capability and display function, or may also be a server. The method can be applied to application programs in terminal equipment, such as: APP (application) of a mobile phone, an application system on a computer, and the like.

The following specifically explains the implementation procedure of the display processing of the wafer test result provided in the embodiment of the present application.

Fig. 1 is a flow chart of a processing method for displaying wafer test results according to an embodiment of the present application, where a main execution body of the method is as described in the foregoing electronic device. As shown in fig. 1, the method includes:

s101, acquiring test information of each die of a target wafer and position information in the target wafer.

The test information may include a test round identifier, a test time identifier of the die, and a test result in each test round, where the test result may be used to indicate whether the die is tested successfully.

Alternatively, multiple tests may be included in each round of testing, e.g., 3 tests may be performed in a first round of testing and 2 tests may be performed in a second round of testing for a die. Wherein the test results in each test round refer to the test results in each test in each round, such as the first test result of a certain die in the first round, the second test result in the first round, and the third test result in the first round.

Optionally, the test information of each wafer may be stored in a test data file, and the test information of each die in the target wafer and the position information of the target wafer may be obtained from the test data file. After the test data file of the target wafer is obtained, the test data file is parsed to obtain the test information of each die in the target wafer and the position information of each die in the target wafer, wherein the position information can refer to a two-dimensional coordinate and can be expressed by using (x, y), for example, the test information of the die with the coordinate of (27,45) can be obtained. After the test data of each target wafer is obtained, the test information of each die may be ranked according to the test wheel identifier and the test sub-identifier of each die, so as to obtain the test information of each die in the ranked target wafer, which is shown in table 1 below. The test wheel identification of each grain is consistent with the test wheel identification of the target wafer containing the grain; the test time identification of each die may be identified, for example, using test times, each of which may indicate that the die has undergone a test.

TABLE 1

Alternatively, the target wafer may refer to any wafer, and for each wafer, an identifier may be used to indicate the wafer, for example, each wafer may be classified by number, data of different wafer numbers are stored in different classifications, data of the same wafer number is stored in a classification, for example, lot1_i may be used to indicate the classification of each wafer, where i=01, 02,03 … n, specifically, lot1_01 may refer to wafer classification 1; LOT1_02 may refer to wafer class No. 2; LOT1_03 may refer to wafer class No. 3.

Alternatively, multiple rounds of testing may be performed for each wafer, for example, the identity of each round of testing may be represented using lot1_i_ CPj, where j=1, 2,3 … n, j may refer to the jth round of testing in the wafer; for example, lot1_01_cp1 may refer to the first round of testing of wafer number 1; LOT1_01_CP2 may refer to the second round of testing of wafer number 1; the lot1_01_cp3 may refer to a third round of testing in wafer No. 1, and so on, to obtain a test round identifier for each wafer.

Alternatively, the file name of the data file stored in the test information of each die in each wafer may be represented by, for example, lot1_i_ CPj _k.tdas.csv, where k=1, 2,3 … n, k may be used to indicate the number of tests of each wafer, for example, lot1_i_ CPj _k.tdas.csv may refer to the test data file of the kth test of the i-th wafer in the jth round of test, and it is worth noting that, in the test data of the kth test of the target wafer, not all dies in the target wafer are tested k times, and the test identifier of a die refers to the test time of each die in the foregoing.

S102, determining the number of test rounds and the number of test times of each crystal grain according to the test round identifier and the test time identifier of each crystal grain.

Optionally, as can be seen from the foregoing, the test wheel identifier of the die is consistent with the test wheel identifier of the target wafer on which the die is located, and the test time identifier of the die may refer to the test time of each die in each round, and each test time may indicate that the die has undergone one test.

Illustratively, as for the die with coordinates (27,45) in table 1, there are 3 test times, i.e., 3 test marks, in the CP1 round of testing, which indicates that the die has undergone 3 tests in the CP1 round of testing; two test times, namely two test marks, exist in the CP2 round of test, and 2 times of test are carried out in the CP2 round of test; there are also two test times in the CP3 round of testing, namely two test identifications, which have been subjected to 2 tests.

The number of test rounds for each die and the number of tests in each round of testing may be determined based on the test round identification and the test time identification for each die.

S103, drawing and displaying the test information of each die in a wafer map of the target wafer according to the number of test rounds, the test times of each die, the test results in each test round and the position information.

Optionally, the wafer map of the target wafer may include die blocks of each die of the wafer, and the test information of each die is drawn in each die block in the wafer map according to the number of test rounds, the number of test times, the test results in each test round, and the position information of each die.

As shown in fig. 2, fig. 2 is a schematic diagram of a portion of a structure of a target wafer according to an embodiment of the present application, where it can be seen in fig. 2 that a plurality of die blocks are included in the target wafer, and test information of each die block can be plotted and displayed in each die block, specifically, as an enlarged display diagram of a die with a coordinate of (27,45) in fig. 2, the number of test rounds, the number of test times, and the test results in each round of the die can be seen in the enlarged display diagram.

In this embodiment, the number of test rounds and the number of test times of each die are determined by the obtained test round identifier and the test time identifier of each die, and according to the number of test rounds, the number of test times, the test result in each test round and the position information of each die, the test information of each die is drawn and displayed in the wafer map of the target wafer, so that the test information of all rounds of each die in the wafer can be visually checked, the retested die and retested test result and the change condition of each round test result can be quickly determined, the user can quickly identify defects according to the displayed test information of each die, the retested proportion and effect can be intuitively analyzed, and the efficiency of the user in analyzing the test result can be improved.

Fig. 3 is a flow chart of another method for displaying and processing a wafer test result according to the embodiment of the present application, as shown in fig. 3, in S103, according to the number of test rounds, the number of test times, the test result in each test round, and the position information of each die, the method may include:

s201, determining a die block of the die in the wafer map according to the position information.

Optionally, as can be seen from the foregoing, the position information refers to the coordinate position information of each die on the target wafer, and the die block of the die in the wafer map may be determined according to the coordinate position information of each die. Specifically, as shown in fig. 2, the die blocks in the wafer map of the target wafer are square blocks, and other shapes may be used to represent the die blocks, which is not limited in this embodiment of the present application.

S202, cutting the grain blocks according to the number of test rounds and the test times to obtain at least one sub-grain block, and establishing the corresponding relation between each sub-grain block and each test result according to the sequence among the test results.

Alternatively, if the number of test rounds of the die is one and the number of test times is one, it is indicated that the die is tested only once, and at the same time, the die has only one test result, and at this time, the dicing process is not required for the die, and the sub-die block of the die is also referred to as the whole die block of the die.

Optionally, after the test data file of the target wafer is obtained, the test information of each die in the target wafer is ordered, and the test results are ordered according to the sequence of the test round identifier and the test time identifier, where the sequence between the test results refers to the sequence of the round test of the die and the sequence of the test results of the secondary test in each round test. Exemplary as in table 1 above, for a grain with coordinates (27,45), the round order is CP1, CP2, and CP3 in order; the secondary test results in the CP1 are orderly sequenced according to the test identification; the secondary test results in the CP2 are orderly sequenced according to the test identification; the secondary test results in CP3 are sequentially ordered according to the test identifier, thereby obtaining the order between the test results of the die.

Optionally, for each sub-die block, a correspondence between each sub-die block and each test result may be established, that is, each test result corresponds to each sub-die block one-to-one.

S203, drawing and displaying corresponding display marks on each sub-grain block according to the corresponding relation between each sub-grain block and the test result and the display marks corresponding to each test result.

Alternatively, for each test result, a display mark may be corresponding, where the display mark may be, for example, a color mark, or may be another form of mark.

In this embodiment, by performing dicing processing on the die blocks according to the number of test rounds and the number of test times, and drawing and displaying corresponding display marks on each sub-die block according to the correspondence between each sub-die block and the test result and the display marks corresponding to each test result, all the test results of the die can be drawn and displayed in each die block.

Fig. 4 is a flow chart of another method for displaying and processing a wafer test result according to the embodiment of the present application, as shown in fig. 4, in S202, dicing a die block according to the number of test rounds and the number of test times to obtain at least one sub-die block, which may include:

s301, cutting the grain blocks according to the number of the test rounds and the sequence of the test rounds to obtain at least one middle grain block.

Wherein each middle grain block is used for corresponding one round of test.

Optionally, if the number of test rounds of a certain grain block is 1, the grain block does not need to be split, and the middle grain block of the grain refers to the whole grain block; if the number of test wheels of a certain grain block is greater than 2, the grain block of the grain is segmented according to the number of test wheels and the sequence of test wheels.

Specifically, the die blocks may be segmented according to the number of test rounds and the sequence of the test rounds, each intermediate die block corresponds to one round of test, and the sequence of each intermediate die block is consistent with the sequence of the test rounds.

For example, continuing with the example of the die set with coordinates (27,45) in table 1, 3 rounds of testing are performed, where the 3 rounds of testing are CP1, CP2 and CP3 in sequence, the die block of the die may be divided into 3 small groups of color blocks from top to bottom transversely, so as to obtain 3 intermediate die blocks, as shown in fig. 5, and fig. 5 is a schematic structural diagram of dividing the die block according to rounds provided in the embodiment of the present application. In fig. 5, the die blocks are segmented according to the number of test rounds and the sequence of test rounds, so CP1 corresponds to a first intermediate die block (corresponding to the uppermost intermediate die block in fig. 5) of the segments, CP2 corresponds to a second intermediate die block (corresponding to the intermediate die block in the intermediate layer in fig. 5), and CP3 corresponds to a third intermediate die block (corresponding to the lowermost intermediate die block in fig. 5) of the segments.

It should be noted that, the die blocks may be divided into a plurality of intermediate die blocks according to the number of test rounds from left to right, or may be divided in other sequences, which is not limited in this embodiment.

S302, cutting each middle grain block according to the corresponding test times and test time sequences of each round of test to obtain at least one sub grain block.

Optionally, each test round includes at least one test, if the test times in the test round are one, the dicing process is not performed on the middle grain block corresponding to the test round, and the sub grain block of the test round is the middle grain block of the test round; if the number of tests in the round of tests is greater than two, the middle grain block of the round of tests is sequentially segmented according to the test order corresponding to the round of tests to obtain sub grain blocks of the round of tests, each sub grain block corresponds to one test, the order of each sub grain block is consistent with the test order, specifically, for each round of tests, the first test corresponds to the segmented first sub grain block, the second test corresponds to the segmented second sub grain block, and the like, the corresponding relation between each test and each sub grain block in each round of tests can be obtained, and accordingly, the corresponding relation between each sub grain block and each test result can be established.

Alternatively, as can be seen from S301, the middle grain block may be split in the order from top to bottom, and on this basis, the middle grain block corresponding to each round may be split in the order from left to right; if the middle grain blocks are segmented according to the left-to-right sequence, the middle grain blocks corresponding to each round can be segmented according to the top-to-bottom sequence. For the specific method of segmentation, other sequences may be used for segmentation, which is not limited in the embodiment of the present application.

Illustratively, taking the crystal grain with the coordinate of (27,45) in the table 1 as an example, 3 tests are included in the CP1 round of tests, 2 tests are included in the CP2 round of tests, and 2 tests are included in the CP3 round of tests, then the middle crystal grain blocks of each round of tests are subjected to slicing treatment according to the test times and the test sequences of each round of tests, so as to obtain each sub crystal grain block. Specifically, as shown in fig. 5, for the uppermost middle die block of the CP1 test, the uppermost middle die block corresponding to CP1 is split into 3 sub-die blocks, the middle die block of the middle layer corresponding to CP2 is split into 2 sub-die blocks, and the lowermost middle die block corresponding to CP3 is split into 2 sub-die blocks. The order between each test in each round of testing is consistent with the order in which the dice are singulated.

For example, for the die with the coordinate of (27,45) in fig. 2, based on the dicing method of dicing the die block from top to bottom, and dicing the die block from left to right, the number of test rounds of the die may be 1, in which the die has undergone 3 tests, the leftmost sub-die block corresponds to the first test, the middle sub-die block corresponds to the second test, and the rightmost sub-die block corresponds to the third test.

It should be noted that, the number of test rounds and the number of tests are different between the die with the coordinate (27,45) in table 1 and the die with the coordinate (27,45) in fig. 1, and the die block in fig. 2 shows that the die has undergone 1 round of test, which may refer to the test of the CP1 round in table 1; two more tests are added to the die after the CP1 test, the CP2 test and the CP3 test can be performed, and the specific test information is shown in table 1.

Optionally, through the corresponding relation between each sub-grain block and each round of test, the corresponding relation between each sub-grain block and each round of test result can be established.

In this embodiment, the dicing process is performed on the die blocks according to the number of test rounds and the sequence of test rounds, and then the dicing process is performed on the die blocks again according to the number of tests corresponding to each round of test and the sequence of test rounds, so as to obtain at least one sub-die block, so that each sub-die block can be in one-to-one correspondence with each test in each round of test, and the test result of each round of test can be in one-to-one correspondence with each sub-die block.

Fig. 6 is a flowchart of another method for displaying and processing a wafer test result according to the embodiment of the present application, as shown in fig. 6, in S203, according to the correspondence between each sub-die block and the test result and the display mark corresponding to each test result, the drawing and displaying the corresponding display mark on each sub-die block may include:

s401, acquiring a target display mode selected by a user.

Optionally, the target display mode may include a success-failure mode or a multi-dimensional mode, where the target mode is selected based on different test results to be displayed, and the test results may be viewed according to a success failure dimension, or may be viewed from multiple dimensions, for example, may be viewed from a Bin dimension, where the Bin dimension may refer to the number of functions that fail when a die test is failed, and may be, for example, bin1 to Bin9; the drawing of each test item dimension can be similar to the two modes, or a wafer map can be drawn for each test item of each die, that is, all test results of one test item are shown in the wafer map.

S402, determining display marks corresponding to all test results according to the target display mode.

Optionally, the test results displayed by different target display modes are different, so when the target display mode is a success or failure mode, a display mark corresponding to the test result of the crystal grain in the success or failure mode needs to be determined; when the target display mode is a multi-dimensional mode, such as a Bin mode, the corresponding display mark can be determined according to the test result in the Bin mode.

S403, drawing and displaying corresponding display marks on each sub-grain block according to the corresponding relation between each sub-grain block and each test result and the display marks corresponding to each test result.

Optionally, after determining the display marks corresponding to the test results, the display marks corresponding to the test results may be drawn in each sub-die block according to the correspondence between each sub-die block and each test result.

For example, as shown in fig. 2, the left-most sub-die block of the die block corresponds to the first test, the middle-most sub-die block corresponds to the second test, the right-most sub-die block corresponds to the third test, and the user selects the Bin mode, so as to determine the display mark corresponding to each test result in the Bin mode, and if the three test results are Bin9, bin6, and Bin1 in sequence, respectively, the display mark corresponding to each test result is determined, and then the display mark corresponding to each test result is drawn in each sub-die block.

In this embodiment, display marks corresponding to the test results in different target display modes are determined according to the different target display modes, and the determined display marks are respectively drawn in the corresponding sub-grain blocks, so that different test results correspond to different display marks, and a user can intuitively view test information of each turn of the grain according to the sub-grain blocks and the display marks of each sub-grain block.

Optionally, determining the display mark corresponding to each test result according to the target display mode in S402 may include:

optionally, if the target display mode is a success or failure mode, traversing each test result, and aiming at the traversed current test result, if the current test result indicates that the test is successful, determining the display mark of the current test result as a first mark; otherwise, determining the display mark of the current test result as a second test result.

Optionally, the test result in the success/failure mode includes that the test result of the die is a test success (P) or a test failure (F), where the test result refers to a test result of each round, that is, a test result of each test corresponding to each round of test.

Alternatively, for the test result of a certain die in each round, the test results may be sequentially traversed according to the test time, and if the current test result indicates that the die is tested successfully, the display flag of the current test result may be determined to be a first flag, specifically, the first flag may be, for example, a white flag, a green flag, a flag of another color, or a flag of another form, which is not limited in this embodiment. If the current test result indicates that the die is a test failure, it may be determined that the display flag of the current test result is a second flag, which may be, for example, a black flag or other color flag or other form of flag, that is different from the display form of the first flag, for example, that is different from the color of the first flag, or that is different from the display form of the second flag.

optionally, if the target display mode is a multi-dimensional (Bin) mode, traversing each test result, and aiming at the traversed current test result, if the current test result indicates that the test is successful, determining that the display mark of the current test result is a third mark, wherein the third mark can be the same as or different from the first mark; otherwise, if the current test result indicates that the test fails, determining a display mark of the current test result according to failure grade information in the current test result, wherein the failure grade information specifically can refer to Bin grade information and can comprise all grades from Bin1 to Bin 9; the corresponding display mark can be determined according to the test result of each Bin.

As shown in fig. 2, the three test results of the die in a round of test are Bin9, bin6 and Bin1, respectively, and as shown in fig. 2, it may be determined that the display of Bin9 is dark gray, the display of Bin6 is medium gray and the display of Bin1 is light gray; it may also be determined that the display flag of Bin9 is purple, the display flag of Bin6 is medium blue, and the display flag of Bin1 is red. The display marks of the Bin levels are different.

It should be noted that, other display forms may be used for the display mark of each test result in the Bin mode, which is not limited in this embodiment.

In this embodiment, the drawing result of each sub-die block in each die block in the wafer map may be made different by determining different display marks according to the test results under different display models. The test condition of each crystal grain can be intuitively and rapidly checked by a user.

Optionally, the method may further include:

optionally, determining the grains with abnormal testing process according to the testing information of each grain. The abnormal testing process refers to that a plurality of tested grains exist, specifically, if the last testing result of each test of a certain grain is used as the final testing result of the test of the round, if the final testing result of the previous round is failure and the subsequent test of the round exists, the grain is used as the abnormal grain of the testing process. This is because if a die fails in the final test result of a certain round of test, the die does not need to be tested in the next round, and if there is a subsequent round of test, it is indicated that the die is a die with abnormal test process, and the reason for the abnormal test process may be due to input error of the position information of the die or test error in the test process.

Optionally, the presence of retested dies is determined based on the test information for each die. Specifically, if the die has multiple tests or multiple tests, that is, the die contains multiple test results, the die is determined to be a retested die. If there are two or more sub-die pieces in a die in the wafer map, that is, if the die pieces are diced, it is also possible to indicate that the die is a retested die.

Optionally, drawing a preset abnormal mark on the edge of each die block with abnormal testing process in the wafer map. The abnormal mark can be, for example, a red frame, a thickened and blackened frame or other forms of abnormal marks, so that the grain block can be highlighted compared with other grain blocks with normal testing processes, and a user can quickly identify testing abnormality and timely find out abnormal problems.

Optionally, the method may further include: the wafer map can be scaled, and particularly the wafer map can be scaled through a keyboard or a mouse, so that a user can conveniently check the whole condition and the local detail condition of the wafer.

Optionally, when the user views a certain die, display information of the die block may be displayed to the user based on a view trigger operation of the user, and specifically, the die block may be displayed in an enlarged manner in a popup window, where the popup window may include position information, test results, and other attribute information of the die in the wafer, where the test results are sequentially arranged according to a sequence of the test. Specifically as shown by the pop-up window of the die at the coordinates (27,45) in fig. 2.

Fig. 7 is a schematic device diagram of a method for displaying and processing a wafer test result according to an embodiment of the present application, where, as shown in fig. 7, the device includes:

an obtaining module 501, configured to obtain test information of each die of a target wafer and position information in the target wafer, where the test information includes a test wheel identifier of the die, a test time identifier, and a test result in each test time, where the test result is used to indicate whether the die is tested successfully;

a determining module 502, configured to determine the number of test rounds and the number of test times of each die according to the test round identifier and the test time identifier of each die;

and a drawing module 503, configured to draw and display the test information of each die in the wafer map of the target wafer according to the number of test rounds, the number of test times, the test result in each test round, and the position information of each die.

Optionally, the drawing module 503 is specifically configured to:

Optionally, the drawing module 503 is further specifically configured to:

Fig. 8 is a block diagram of an electronic device 600 according to an embodiment of the present application. As shown in fig. 8, the electronic device may include: processor 601, memory 602.

Optionally, a bus 603 may be further included, where the memory 602 is configured to store machine readable instructions executable by the processor 601 (e.g. executing instructions corresponding to the acquiring module, the determining module, the drawing module in the apparatus in fig. 7, etc.), where when the electronic device 600 is running, the processor 601 communicates with the memory 602 by storing the machine readable instructions through the bus 603, where the machine readable instructions are executed by the processor 601 to perform the method steps in the foregoing method embodiments.

The embodiment of the application also provides a computer readable storage medium, and a computer program is stored on the computer readable storage medium, and when the computer program is executed by a processor, the method steps in the embodiment of the wafer test result display processing method are executed.

It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system and apparatus may refer to corresponding procedures in the method embodiments, which are not described in detail in this application. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, and the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, and for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, indirect coupling or communication connection of devices or modules, electrical, mechanical, or other form.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions are covered in the protection scope of the present application.

Claims

1. A method for displaying and processing a wafer test result, the method comprising:

2. The method according to claim 1, wherein the drawing and displaying the test information of each die on the target wafer according to the number of test rounds, the number of test times, the test results in each test round, and the positional information, comprises:

3. The method for displaying wafer test results according to claim 2, wherein the dicing the die block according to the number of test rounds and the number of tests to obtain at least one sub-die block comprises:

4. The method according to claim 2, wherein the drawing and displaying the corresponding display mark on each sub-die block according to the correspondence between each sub-die block and each test result and the display mark corresponding to each test result comprises:

5. The method for displaying and processing wafer test results according to claim 4, wherein determining display marks corresponding to the test results according to the target display mode comprises:

6. The method for displaying and processing wafer test results according to claim 4, wherein determining display marks corresponding to the test results according to the target display mode comprises:

7. The method for displaying wafer test results according to any one of claims 1 to 6, further comprising:

8. A display processing apparatus for wafer test results, comprising:

9. An electronic device comprising a memory and a processor, the memory storing a computer program executable by the processor, the processor implementing the steps of the method for displaying wafer test results according to any one of claims 1-7 when the computer program is executed.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, performs the steps of the method for displaying wafer test results according to any one of claims 1 to 7.