CN117456868A

CN117456868A - Display panel and display device

Info

Publication number: CN117456868A
Application number: CN202311309774.8A
Authority: CN
Inventors: 李文齐; 杨程
Original assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2023-10-10
Filing date: 2023-10-10
Publication date: 2024-01-26

Abstract

The application discloses display panel and display device, this display panel includes the pixel circuit, the pixel circuit includes light emitting device and drive transistor, through adopting the bias control voltage signal that the offset direction of the threshold voltage of drive transistor and/or offset range generated under the condition of data signal transmission to drive transistor's second grid to control drive transistor's first grid potential, can reverse compensation drive transistor's electrical property change, not only improved drive transistor's hysteresis effect, but also can control drive transistor's threshold voltage drift, and then reduced the luminance difference between the different pixel circuits, and improved the display of afterimage. In addition, aiming at the screen flashing phenomenon under low frequency, the grid leakage current of the driving transistor is restrained through corresponding improvement, and the screen flashing or screen flashing phenomenon under low frequency is effectively improved.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display device.

Background

With the popularization of mobile phones, flat panels and even televisions, display back panels are widely applied to display panels required for consumer products such as mobile phones, flat panels and notebook computers. However, various problems such as non-uniformity of device process and device hysteresis result in non-ideal display effects, such as uneven display brightness (Mura), screen display, or non-ideal display lifetime.

In order to exhibit a desired specific luminance in a pixel, it is necessary to be able to rapidly control a driving current flowing through a driving transistor. However, due to the hysteresis characteristics of the driving transistor, the driving current may vary along various paths, and a difference in the driving current may occur between pixels representing the same gray scale luminance. The difference of different driving currents generated by gray level change can be visually recognized as an afterimage by a user.

Disclosure of Invention

The application provides a display panel and a display device, which are used for relieving the technical problems of larger hysteresis effect and threshold voltage drift of a driving transistor.

In a first aspect, the present application provides a display panel, the display panel including a pixel circuit, the pixel circuit including a light emitting device and a driving transistor, the light emitting device being connected in series between a first power line and a second power line; the driving transistor is connected in series with the light emitting device, a first grid electrode of the driving transistor is connected with a bias control voltage signal, the bias control voltage signal is generated according to the stress condition of the driving transistor, and the stress condition is the offset direction and/or the offset amplitude of the threshold voltage of the driving transistor under the condition that a data signal is transmitted to a second grid electrode of the driving transistor.

In some embodiments, the display panel further includes a timing controller and a column bias voltage control driving module, where the timing controller generates a corresponding bias voltage control signal according to the gray scale data and the acting time thereof; the column bias voltage control driving module is connected with the time sequence controller and the pixel circuit and generates bias control voltage signals according to the bias voltage control signals.

In some embodiments, the timing controller includes a stress calculating unit and a voltage calculating unit, wherein the stress calculating unit calculates stress conditions of the driving transistor according to the gray scale data and the acting time thereof; the voltage calculation unit is connected with the stress calculation unit and the column bias voltage control driving module, and generates bias control voltage signals with the first lookup table according to stress conditions.

In some embodiments, the display panel further includes one or more bias control voltage lines transmitting bias control voltage signals, each bias control voltage line being connected to at least one column of pixel circuits, the voltage calculation unit.

In some embodiments, the pixel circuit further includes a first light emitting control transistor, a second light emitting control transistor, a write transistor, a first compensation transistor, a second compensation transistor, and a first control transistor, a first electrode of the first light emitting control transistor is connected to the first power line, a second electrode of the first light emitting control transistor is connected to the first electrode of the drive transistor, and a gate of the first light emitting control transistor is connected to the light emitting control line; the first electrode of the second light-emitting control transistor is connected with the second electrode of the driving transistor, the second electrode of the second light-emitting control transistor is connected with the anode of the light-emitting device, and the grid electrode of the second light-emitting control transistor is connected with the light-emitting control line; a first pole of the writing transistor is connected with a data line for transmitting data signals, a second pole of the writing transistor is connected with a source electrode or a drain electrode of the driving transistor, and a grid electrode of the writing transistor is connected with a first grid electrode driving line; a first electrode of the first compensation transistor is connected with a second gate of the driving transistor, and a gate of the first compensation transistor is connected with a first gate driving line; the first pole of the second compensation transistor is connected with the second pole of the first compensation transistor, the second pole of the second compensation transistor is connected with the source electrode or the drain electrode of the driving transistor, and the grid electrode of the second compensation transistor is connected with the first grid electrode driving line; the first pole of the first control transistor is connected with the second pole of the first compensation transistor, the grid electrode of the first control transistor is connected with the light-emitting control line, the second pole of the first control transistor is connected with a first reference potential signal, and the first reference potential signal is generated according to the time sequence control signal and gray scale data.

In some of these embodiments, the timing controller further comprises a frequency analyzer, a gray scale transcoder, a control voltage data generator, a variable impedance circuit, and a compensation voltage generator, the frequency analyzer outputting a frame refresh frequency according to the timing control signal; the gray scale code converter outputs corresponding gray scale horizontal codes according to the gray scale data; the control voltage data generator is connected with the frequency analyzer and the gray level code converter and generates corresponding reference voltage data according to the frame refreshing frequency, the gray level code and the second lookup table; the variable impedance circuit is connected with the control voltage data generator and generates corresponding output power supply voltage according to the reference voltage data and the input power supply voltage; the compensation voltage generator is connected with the variable impedance circuit and generates a first reference potential signal according to the output power supply voltage.

In some embodiments, the control voltage data generator comprises a comparator and a data judgment generator, wherein the comparator is connected with the frequency analyzer, and the comparator outputs a comparison result of the frame refresh frequency and the reference frame rate; the data judging generator is connected with the comparator and the variable impedance circuit and generates reference voltage data according to the comparison result, the frame refreshing frequency and the gray level code.

In some of these embodiments, the timing controller further includes a register storing a threshold voltage of the at least one driving transistor, the register being coupled to the variable impedance circuit.

In some of these embodiments, the pixel circuit further includes a first initialization transistor, a second initialization transistor, and a second control transistor, a first electrode of the first initialization transistor being connected to a second gate of the driving transistor, a gate of the first initialization transistor being connected to a second gate driving line; the first pole of the second initialization transistor is connected with the second pole of the first initialization transistor, the second pole of the second initialization transistor is connected with the initialization line, and the grid electrode of the second initialization transistor is connected with the second grid electrode driving line; the first pole of the second control transistor is connected with the second pole of the first initialization transistor, the grid electrode of the second control transistor is connected with the light emitting control line, the second pole of the second control transistor is connected with a second reference potential signal or a first reference potential signal, the second reference potential signal is generated according to a time sequence control signal and gray scale data, and the second reference potential signal is different from the first reference potential signal.

In a second aspect, the present application provides a display device, which includes a display panel in at least one embodiment described above.

According to the display panel and the display device, the first grid potential of the driving transistor is controlled by adopting the bias control voltage signal generated in the offset direction and/or the offset amplitude of the threshold voltage of the driving transistor under the condition that the data signal is transmitted to the second grid electrode of the driving transistor, so that the electrical change of the driving transistor can be reversely compensated, the hysteresis effect of the driving transistor is improved, threshold voltage drift of the driving transistor can be controlled, and further the brightness difference among different pixel circuits is reduced, and the display of afterimages is improved.

Drawings

Technical solutions and other advantageous effects of the present application will be made apparent from the following detailed description of specific embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic circuit diagram of a pixel circuit in the related art.

Fig. 2 is a schematic structural diagram of a display panel in the related art.

Fig. 3 is a schematic circuit diagram of a first embodiment of a pixel circuit.

Fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present application.

Fig. 5 is a first driving frame diagram of a display panel according to an embodiment of the present application.

Fig. 6 is a schematic diagram of a relationship between bias control voltage signals and threshold voltages of driving transistors according to an embodiment of the present disclosure.

Fig. 7 is a schematic diagram of a relationship between gray scale and threshold voltage of a driving transistor according to an embodiment of the present disclosure.

Fig. 8 is a schematic diagram illustrating a first effect of hysteresis characteristics on luminance or light-emitting current according to an embodiment of the present application.

Fig. 9 is a schematic diagram showing a second effect of hysteresis characteristics on luminance or light-emitting current according to an embodiment of the present application.

FIG. 10 is a schematic diagram of external compensation for single gray scale aging of FIG. 9.

Fig. 11 is a schematic diagram of external compensation for multi-gray scale aging according to an embodiment of the present application.

Fig. 12 is a schematic diagram of a first structure of a timing controller according to an embodiment of the present application.

Fig. 13 is a second circuit schematic of the pixel circuit according to the embodiment of the present application.

Fig. 14 is a third circuit schematic of the pixel circuit according to the embodiment of the present application.

Fig. 15 is a second driving frame diagram of a display panel according to an embodiment of the present application.

Fig. 16 is a fourth circuit schematic of the pixel circuit according to the embodiment of the present application.

Fig. 17 is a fifth circuit schematic of the pixel circuit according to the embodiment of the present application.

Fig. 18 is a third driving frame diagram of a display panel according to an embodiment of the present application.

Fig. 19 is a sixth circuit schematic of the pixel circuit according to the embodiment of the present application.

Fig. 20 is a timing diagram of the pixel circuit shown in fig. 19.

Fig. 21 is a seventh circuit schematic of the pixel circuit according to the embodiment of the present application.

Fig. 22 is a timing diagram of the pixel circuit shown in fig. 21.

Fig. 23 is a third driving frame diagram of a display panel according to an embodiment of the present application.

Fig. 24 is a schematic diagram of a second structure of the timing controller according to the embodiment of the present application.

Fig. 25 is a schematic structural diagram of a control voltage data generator according to an embodiment of the present application.

Fig. 26 is a schematic diagram of a third structure of the timing controller according to the embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated, whereby a feature defining "first," "second," or the like, may explicitly or implicitly include one or more of such features, and in the description of the present invention, "a plurality" means two or more, unless otherwise specifically limited.

As shown in fig. 1, the pixel circuit having the dual gate driving transistor T1 includes at least one of a first light emitting control transistor T5, a second light emitting control transistor T6, a driving transistor T1, a writing transistor T2, a first compensation transistor T31, a second compensation transistor T32, a first initialization transistor T41, a second initialization transistor T42, a third initialization transistor T7, a storage capacitor Cst, and a light emitting device EL.

In the case where the first and second compensation transistors T31 and T32 are turned off, a leakage current (Ioff) may flow between the nodes B and C.

The specific structure of the driving transistor T1 is shown in fig. 2, and the display panel includes at least one of a first polyimide layer PI1, a Barrier layer Barrier1, a second polyimide layer PI2, a first gate electrode GE2, a multiple Barrier layer MB, a Buffer layer Buffer, an active layer Poly, a first gate electrode GE2 insulating layer GI1, a second gate electrode GE1 insulating layer GI2, a first metal layer, a first spacer layer ILD1, a third gate insulating layer GI3, a second spacer layer ILD2, a second metal layer, a first flat layer PLN1, a third metal layer, a second flat layer PLN2, a pixel defining layer PDL covering an anode ANO, and a spacer structure PS, which are sequentially stacked.

The first gate electrode GE2 has a first gate electrode GE2 of the driving transistor T1 in the first gate electrode GE2 layer, and the first gate electrode GE2 is electrically connected to one electrode (SD 1 on the left side) of the second metal layer through a via hole to receive the power positive signal ELVDD.

The first gate electrode GE2 of the driving transistor T1 is also connected to the first power line as a barrier shield metal electrode (BSM, blocking Shielding Metal) to maintain a constant voltage at the potential of the power positive signal ELVDD.

The blocking shielding metal electrode is added mainly to prevent light from irradiating the channel of the driving transistor T1, and simultaneously, the blocking shielding metal electrode and other parts of the driving transistor T1 form a stable electromagnetic field by switching on the potential of the power positive signal ELVDD, so that the electrical property of the driving transistor T1 is kept stable together.

The electrode CE in the first metal layer and the second gate electrode GE1 of the driving transistor T1 in the second gate electrode GE1 layer form a storage capacitor Cst.

One electrode of the second metal layer connected to the active layer Poly is electrically connected to the anode ANO through the electrode SD2 of the third metal layer.

In order to exhibit a desired specific luminance in a pixel, it is necessary to be able to rapidly control the driving current flowing through the driving transistor T1, as Id in fig. 1. However, due to the hysteresis characteristics of the driving transistor T1, the driving current may vary along various paths, and a difference in the driving current may occur between pixels representing the same gray scale luminance.

In view of the above-mentioned problems of the driving transistor T1 with large hysteresis effect and threshold voltage drift, the present embodiment provides a display panel, referring to fig. 1 to 26, the display panel includes a pixel circuit, the pixel circuit includes a light emitting device EL and the driving transistor T1, and the light emitting device EL is connected in series between a first power line and a second power line; the driving transistor T1 is connected in series with the light emitting device EL, and the first gate electrode GE2 of the driving transistor T1 is connected to a bias control voltage signal, which is generated according to a stress condition of the driving transistor T1, the stress condition being a shift direction and/or a shift magnitude of a threshold voltage of the driving transistor T1 in a case where a data signal is transmitted to the second gate electrode GE1 of the driving transistor T1.

It can be appreciated that in the display panel provided in this embodiment, by controlling the potential of the first gate GE2 of the driving transistor T1 by using the bias control voltage signal generated by the offset direction and/or the offset amplitude of the threshold voltage of the driving transistor T1 when the data signal is transmitted to the second gate GE1 of the driving transistor T1, the electrical variation of the driving transistor T1 can be reversely compensated, so that not only the hysteresis effect of the driving transistor T1 is improved, but also the threshold voltage drift of the driving transistor T1 can be controlled, thereby reducing the brightness difference between different pixel circuits and improving the display of the afterimage.

The shift direction and/or the shift amplitude of the threshold voltage of the driving transistor T1 are the contrast variation before and after the data signal is transmitted to the second gate GE1 of the driving transistor T1.

Wherein the first power line is used for transmitting a power positive signal ELVDD. The second power line is for transmitting a power negative signal ELVSS. The potential of the power positive signal ELVDD is higher than the potential of the power negative signal ELVSS.

The light emitting device EL may be an organic light emitting diode, a mini light emitting diode, a micro light emitting diode, or a quantum dot light emitting diode.

Fig. 3 is a schematic circuit diagram of a first embodiment of a pixel circuit. Unlike fig. 1, the first gate electrode GE2 of the driving transistor T1 in the pixel circuit is connected to the bias control voltage signal instead of the constant voltage signal, so that the electrical variation of the driving transistor T1 can be reversely compensated to keep the electrical property of the driving transistor T1 stable.

Fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present application. Unlike fig. 2, the first gate electrode GE2 of the driving transistor T1 in the display panel is electrically connected to one electrode (SD 1 on the left) in the second metal layer through a via hole to receive a bias control voltage signal of which potential is adaptively changed.

It will be appreciated that since the first gate electrode GE2 of the driving transistor T1 in the pixel circuit shown in fig. 3 introduces a new signal, i.e., a bias control voltage signal, it is required for a driving architecture of the display panel that generates and transmits the bias control voltage signal, as shown in fig. 5. The display panel includes at least one of Pixel circuits (pixels), a timing controller, a light emission control driver, a gate driver, a data driver, a column bias voltage control driving module, and a power management circuit chip in a display area.

The column bias voltage control driving module is connected with the time sequence controller and the pixel circuit. The pixel circuits may be distributed in an array, for example, m rows and n columns.

The column bias voltage control driving module may provide a corresponding bias control voltage signal to each pixel circuit according to a Bias Voltage Control Signal (BVCS) generated by the timing controller. And different bias control voltage signals (VB 1, vb2..vbj..vbn-1, VBn) need to be transferred corresponding to different bias control voltage lines, therefore, in order to reduce the number of bias control voltage lines in the display area to increase the pixel density or the aperture ratio, a bias control voltage line may be provided to be connected to at least one column of pixel circuits.

The data driver can control signals according to RGB signals and data sent by the time schedule controller DCS) for supplying the required data signals (D1) D2. Dj. Dn-1, dn). The data lines may be disposed side by side or in parallel with the bias control voltage lines.

The emission control driver may provide the respective pixel circuits with the corresponding emission control signals (EM 1, EM2 to EMk) through the corresponding emission control lines according to the emission start signal (ESP) and the clock signal (CLK) transmitted from the timing controller.

The gate driver may include one or more gate driving circuits, for example, a first gate GE2 driving circuit. Wherein each gate driving circuit may have access to a different or the same gate start signal (gsp 1.

The power management circuit chip may supply the power positive signal ELVDD and the power negative signal ELVSS required for each pixel circuit.

Wherein the drive current (Id) flowing through the pixel circuit may be cooperatively controlled by the data signal and the bias control voltage signal (VB 1, vb2..vbj..vbn-1, VBn).

The timing controller or timing control chip (T/Con, timing Controller) is used as the core of the whole driving architecture for controlling the light-emitting control driver, the gate driver, the data driver and the column bias voltage control driving module to perform orderly operation. The column bias voltage control driving module can be completely integrated with the data driver; or, the driving circuit can be partially integrated in the time schedule controller and partially integrated in the data driver, so that the integration level of the driving framework is improved and the occupied space of the frame is reduced.

Considering the wiring difficulty, the chip (IC) cost and the actual compensation requirement, the ratio (η) of the number of bias control voltage lines to the number of data lines may be considered to be not 1:1, but 1:2, 1:3 or 1:4 as shown in fig. 5, so that the number of bias control voltage lines and bias control voltage signals can be reduced to 1/2/1/3 or 1/4 of the original number. The potential of the bias control voltage signal supplied to the pixel circuits in the plurality of columns may be an average value of the potentials of the bias voltage signals of the pixel circuits in the original columns, or may be selected as the potential of the bias control voltage signal to which the pixel circuit in one column is originally connected.

The Bias Voltage Control Signal (BVCS) is used to control the column bias voltage control driving module to output a bias control voltage signal having a predetermined voltage for each column in a second, subsequent period, according to the stress (or stress value) to which the pixel circuit is subjected in the first period. Here, stress means stress (stress) applied to the driving transistor T1 in the pixel circuit (sub-pixel). For example, the stress of a pixel indicates: the data signal is applied to the second gate electrode GE1 of the driving transistor T1, causing an offset direction and/or an offset magnitude of the threshold voltage (Vth) of the driving transistor T1.

Specifically, the timing controller generates a corresponding Bias Voltage Control Signal (BVCS) according to the stress applied to the sub-pixels during the reference period (e.g., the first period). For example, the timing controller may accumulate gray scale values (or integrate data signals) of the Pixel (1, 1), such as about several tens of seconds, to calculate this stage stress of the Pixel (1, 1), and determine the bias control voltage signal VB1 to be applied to the first column bias control voltage line based on this stage stress of the Pixel (1, 1). For example: the stress to which this stage of Pixel (1, 1) is subjected is greater than the reference stress, the timing controller may determine that the bias control voltage signal VB1 to be applied to the first column of bias control voltage lines is at a potential less than the reference control voltage, and when the threshold voltage (Vth) of the driving transistor T1 in Pixel (1, 1) is shifted negatively due to the stress in this stage, its Vth may be shifted positively due to the relatively low bias control voltage signal VB 1; conversely, the timing controller may determine that Vth will shift positively due to stress at this stage and will shift negatively due to the relatively high bias control voltage signal VB1 when the potential of the bias control voltage signal VB1 is greater than the baseline reference control voltage. Other pixels are also externally compensated in the same manner, so that the entire display area is relatively more likely to normally emit light at the originally desired set brightness without afterimage.

That is, as shown in fig. 6, the bias control voltage signal VBj affects the threshold voltage thereof by acting on the first gate electrode GE2 of the driving transistor T1. If the driving transistor T1 is a P-channel thin film transistor, when the voltage of the first gate GE2 decreases, vth of the driving transistor T1 increases; conversely, vth of the driving transistor T1 decreases. If the driving transistor T1 is an N-channel type thin film transistor, the situation is the opposite to that of a P-channel type thin film transistor. Therefore, the control bias control voltage signal VBj can adjust the electrical property of the driving transistor T1.

As shown in fig. 4, the distance from the second gate electrode GE1 to the active layer is smaller than the distance from the first gate electrode GE2 to the active layer. The driving current (Id) of the driving transistor T1 is mainly determined by the voltage of the second gate GE1, and the voltage of the first gate GE2 can determine the Vth.

On the other hand, as shown in fig. 7, when the display state is in a high gray level (e.g. white screen L255) for a long time, the display state is switched to a lower gray level (e.g. L128), the driving current (Id) or brightness thereof will jump to a driving current (Id) or brightness corresponding to the lower gray level (L128), for example, be located on P0-L, and then after a long time, the display state may return to the current or brightness (point corresponding to the same Vgs on the standard curve, such as point P0) of the originally desired gray level, as gradually approaching to point P0 on the standard curve; conversely, when the display state is in the low gray level display state for a long time, the display state is switched to the higher gray level, the driving current (Id) or brightness jumps to be lower than the driving current (Id) or brightness corresponding to the higher gray level, for example, the display state is positioned on P0-R, and the display state slowly returns to the current or brightness of the gray level which is expected to be set after a long time. Where Vgs is the difference between the gate potential and the source potential of the driving transistor T1. Ids is the drive current (Id).

Therefore, the hysteresis of the driving transistor T1 causes the Δvth and Δi to occur, so that the adjacent pixels may have brightness differences, and the afterimage may affect the picture quality. Where Δvth represents the amount of change in threshold voltage. Δi is the amount of change in drive current (Id).

In other words, a left shift curve is formed by long-time high gray scale stress; conversely, a right shift curve is formed. In this way, according to fig. 7, by reversely adjusting the potential of the first gate GE2 of the driving transistor T1, the control curve can be returned to the original position as soon as possible, and Δvth and Δi can be reduced or eliminated as soon as possible.

As shown in fig. 8 and 9, t1 to t2 are aging/stress time periods, the time period is 255 gray scale (or 0 gray scale) display states, the corresponding data voltage VDS1 (VDS 2) corresponds to the maximum 255 gray scale (minimum 0 gray scale), the pixel is switched to 128 gray scale at the time point of t2, the time period t2 to t3 is a stress recovery time period, the larger deviation at the time point of t2 gradually returns to be close to the original set value, and when the ratio of the magnitude of the driving current (Id 1/Id 2) or the luminance (Lv 1/Lv 2) at a certain time point to the magnitude of the driving current or the luminance at the time point of t2 is smaller than a certain set ratio line, it is considered that the human eye hardly perceives the afterimage at the moment (t 3).

Fig. 9 illustrates waveform changes of driving current or luminance after switching pixels to display gray scale after aging due to hysteresis characteristics of the driving transistor T1. The bias control voltage signal VBj is reverse bias compensation voltage, which can inhibit the driving current and the brightness offset amplitude, so that the driving current and the brightness quickly return to the original sizes. If the control bias control voltage signal VBj is not separately applied to the first gate electrode GE2 of the driving transistor T1, the stress recovery time may be significantly longer, and the human eye can easily recognize the afterimage. In actual operation, the compensation stage is performed in the case of black screen or in the best mode, and the method is also feasible in the case of bright screen.

As shown in fig. 9, 10 and 11, the stress recovery rate of the Pixel is significantly increased after the external compensation is adopted, and the aging/stress period is not only single gray scale display, but also multi-gray scale change display (at this time or with its average gray scale). Several voltage relationships among which bias control voltage signals VBj1/VBj 2: v1 is less than V0 and less than V2.

As shown in fig. 12, the timing controller includes a similar functional module as a stress calculating unit, and calculates the cumulative stress (e.g., the aging degree is calculated by integrating) of the Pixel according to the gray scale (RGB VDS) of each display data and the duration (τ) of the effect thereof, wherein the cumulative stress (the degradation degree of the image) is proportional to the gray scale value and the light emitting time. Then comparing with the original set value, determining the direction and the magnitude of the reverse compensation, and then transmitting to a voltage calculating unit, wherein the voltage calculating unit determines a bias voltage control signal (BCVS) according to a first lookup table (LUT 1 is a voltage value related to gray scale and recovery time length) stored in a register of a time sequence controller in advance, and finally communicating with a column bias voltage control driving module to enable the column bias voltage control driving module to output a bias control voltage signal VBj corresponding to each column. The fluctuation range of the bias control voltage signal VBj control voltage may be only about ±0.5v (the fluctuation range and the stepping data of the bias control voltage signal VBj may be obtained according to specific design and process conditions and a large amount of statistical data after experiments).

The voltage calculation unit is connected with the stress calculation unit and the column bias voltage control driving module.

It can be understood that the stress calculating unit calculates the stress condition of the driving transistor T1 according to the gray scale data and the duration of action thereof; the voltage calculation unit generates a bias control voltage signal according to the stress condition and the first lookup table.

For larger size display panels, such as flat panel and notebook size OLED displays, uniformity and reliability are more difficult to maintain. Since the current-driven type light emitting device EL is extremely sensitive to current variation, compensation for increasing the driving current is also necessary on the basis of compensation for devices in an Array (Array) substrate.

As shown in fig. 13 and 14, the design of the pixel circuit is similar to that of the pixel circuit shown in fig. 3, the distance between the second gate electrode GE1 of the driving transistor T1 and the active layer is smaller than the distance between the first gate electrode GE2 of the driving transistor T1 and the active layer, and the first gate electrode GE2 of each column is also used as a barrier shielding metal electrode and is respectively connected to the bias control voltage signal VBj corresponding to each column. The write transistor T2, the drive transistor T1, and the sense transistor M1 may be N-type oxide transistors by controlling the magnitude of the drive current flowing through the drive transistor T1 by the potential at the point C. As described above, as the potential of the first gate GE2 increases, the threshold voltage of the driving transistor T1 is biased positively and negatively. Therefore, the electrical property of the driving transistor T1 can also be adjusted by controlling the voltage of the bias control voltage signal VBj.

The write transistor T2 is used to control the input of the Data signal (Data [ j ]). The sense transistor M1 may perform an initializing function, i.e., reset the anode potential of the light emitting device EL before the Data signal (Data [ j ]) is input at the beginning of each cycle, and at the same time, the sense transistor M1 may perform a reading function, i.e., introduce the driving current into the chip (IC) during the light emitting phase, so that the chip can determine how to perform external compensation on the driving current by adjusting the potential of the Data signal.

As shown in the circuit of fig. 14, considering that the potential of the power positive signal ELVDD may fluctuate and be non-uniform, thereby affecting the potential of the point a, thereby affecting the stability of the driving current (Id), the first light emitting control transistor T5 is added between the first power line and the driving transistor T1 to block the abrupt voltage change of the point a.

Compared with the pixel circuit shown in fig. 3, since the pixel circuits shown in fig. 13 and 14 reduce the number of transistors, the situation of in-plane wiring space shortage is eased, and more sufficient wiring space is provided for the bias control voltage lines in-plane and the transmission lines that transmit the current sensing signals (Read 1, read2. In turn, since the corresponding external compensation function is added, the internal compensation (Vth compensation) function removed by reducing the number of transistors can also be compensated.

The system architecture shown in fig. 15 can be applied to the pixel circuits shown in fig. 13 and 14, and compared with fig. 5, the system architecture is added with a read module and transmission lines corresponding to each column for transmitting current sensing signals, and can transmit the current sensing signals to the read module for analysis and comparison, so that the timing controller can provide data of reverse compensation driving current by adjusting the potential of the data signals. The read module may also be contained within the timing controller or the data driver.

Because the manufacturing process of the low-temperature polysilicon thin film transistor and the metal oxide thin film transistor is complex, the difficulty is high, the electrical property of the pixel circuit is difficult to keep stable, the BSM is often required to be added as a shading layer, and the steps of the manufacturing process are increased, so that the high manufacturing cost is brought. If the difficulty of the process is relatively low, the BSM light shielding layer can be omitted, and the cost of the panel process is relatively low.

If the key process of the array substrate has defects, the display screen of the low-temperature polysilicon thin film transistor can also increase the electrical property of the BSM protection driving transistor T1.

On the other hand, the first compensation transistor T31 and the second compensation transistor T32 in the factor pixel circuit adopt 2 oxide thin film transistors (mobility/switching characteristics are better than those of the low-temperature polysilicon thin film transistor), and the image quality of the display screen mixed by the low-temperature polysilicon thin film transistor and the metal oxide thin film transistor is better than that of the display screen of the low-temperature polysilicon thin film transistor during low-frequency display. The display screen of the low-temperature polysilicon thin film transistor has obvious low-frequency flash and is easy to be perceived by human eyes.

Therefore, if a display screen of a low-temperature polysilicon thin film transistor with low cost is to be used instead of a display screen in which the low-temperature polysilicon thin film transistor and the metal oxide thin film transistor are mixed, the problem of flicker during low-frequency display needs to be solved.

As the refresh frequency decreases, the time of one frame becomes longer. In this way, the amount of leakage of each of the compensation transistor, the first initialization transistor T41, and the second initialization transistor T42 in the pixel circuit becomes a root cause of low-frequency flicker (mainly, the leakage current Ioff of the compensation transistor) during the off period.

As shown in fig. 16 and 17, the pixel circuit has a high probability that parasitic capacitance exists between the point D and Scan1 i due to the stacked structure of the transistors, causing potential difference to be formed between the two ends of the first compensation transistor T31, causing unexpected leakage current and causing low flicker; this is also true between point E and Scan2[ i ].

Therefore, the first control transistor T8 can be directly used to control the first reference potential signal applied to the point D to balance the potential difference between the point C and the point D, even if the voltage (Vds) across the source and the drain of the first compensation transistor T31 is low enough to avoid the formation of leakage current, it can be presumed that the ideal potential of the point D should be close to or equal to the potential of the data signal.

The pixel circuits shown in fig. 16 and 17 further include a first light emitting control transistor T5, a second light emitting control transistor T6, a writing transistor T2, a first compensation transistor T31, a second compensation transistor T32, and a first control transistor T8, wherein a first pole of the first light emitting control transistor T5 is connected to a first power line, a second pole of the first light emitting control transistor T5 is connected to a first pole of the driving transistor T1, and a gate of the first light emitting control transistor T5 is connected to a light emitting control line; the first pole of the second light-emitting control transistor T6 is connected with the second pole of the driving transistor T1, the second pole of the second light-emitting control transistor T6 is connected with the anode of the light-emitting device EL, and the grid electrode of the second light-emitting control transistor T6 is connected with the light-emitting control line; a first pole of the writing transistor T2 is connected with a data line for transmitting data signals, a second pole of the writing transistor T2 is connected with a source electrode or a drain electrode of the driving transistor T1, and a grid electrode of the writing transistor T2 is connected with a first grid electrode GE2 driving line; the first pole of the first compensation transistor T31 is connected with the second grid electrode GE1 of the driving transistor T1, and the grid electrode of the first compensation transistor T31 is connected with a first grid electrode GE2 driving line; a first pole of the second compensation transistor T32 is connected with a second pole of the first compensation transistor T31, the second pole of the second compensation transistor T32 is connected with a source electrode or a drain electrode of the driving transistor T1, and a grid electrode of the second compensation transistor T32 is connected with a first grid electrode GE2 driving line; the first pole of the first control transistor T8 is connected with the second pole of the first compensation transistor T31, the grid electrode of the first control transistor T8 is connected with the light-emitting control line, the second pole of the first control transistor T8 is connected with a first reference potential signal, and the first reference potential signal is generated according to a time sequence control signal and gray scale data.

The first pole may be one of the source and the drain, and the second pole may be the other of the source and the drain. For example, in the case of a first pole being the source, the second pole may be the drain; alternatively, in the case of the first pole being the drain, the second pole may be the source.

Also, as shown in fig. 17, the E point potential can be controlled by the second control transistor T9 taking the first reference potential signal (Vref 1 j) or the second reference potential signal (Vref 2 j). Preferably, the second control transistor T9 controls the potential of the point E by using a second reference potential signal different from the first reference potential signal (the potentials of the point D and the point E are different when different gray scales are displayed), so that leakage current between the point C and the point E is avoided.

The pixel circuit shown in fig. 17 further includes a first initializing transistor T41, a second initializing transistor T42, and a second controlling transistor T9, the first electrode of the first initializing transistor T41 is connected to the second gate GE1 of the driving transistor T1, and the gate of the first initializing transistor T41 is connected to the second gate GE1 driving line; a first pole of the second initializing transistor T42 is connected with a second pole of the first initializing transistor T41, a second pole of the second initializing transistor T42 is connected with an initializing line, and a grid electrode of the second initializing transistor T42 is connected with a second grid electrode GE1 driving line; the first pole of the second control transistor T9 is connected with the second pole of the first initialization transistor T41, the grid electrode of the second control transistor T9 is connected with the light emitting control line, the second pole of the second control transistor T9 is connected with a second reference potential signal or a first reference potential signal, the second reference potential signal is generated according to a time sequence control signal and gray scale data, and the second reference potential signal is different from the first reference potential signal.

The system architecture for the pixel circuit shown in fig. 16 and 17 is shown in fig. 18, and the system architecture has both the capability of maintaining the electrical property of the driving transistor T1 and the capability of suppressing low-frequency flicker. Compared with fig. 5, the column bias voltage control driving module adds two output signals, namely, a first reference potential signal and a second reference potential signal, correspondingly, the display area also needs to be added with reference voltage wiring for transmitting the first reference potential signal and the second reference potential signal.

According to the pixel circuit shown in fig. 17, the potentials at the D point and the E point are controlled by using different reference potential signals, respectively, depending on the potentials at the D point and the E point at the time of displaying different gray scales. If the specific design and process optimization are adopted, the potentials of the D point and the E point are identical in the same gray scale display under ideal conditions, one path of reference potential signal can be omitted, namely the system architecture integrally omits n columns of reference voltage wiring. As shown in fig. 19.

In addition, considering the wiring difficulty, the IC cost and the actual compensation requirement comprehensively, it can be considered that each reference voltage wiring corresponds to a plurality of columns of data lines, the number ratio η=1:2, 1:3 or 1:4, and the potential of the reference potential signal (Vrefj) can be averaged, so that the number of the reference voltage wirings and the reference potential signals thereof is reduced to 1/2, 1/3 or 1/4 of the original number.

As shown in the timing sequence of fig. 20, one frame period is divided into two phases, namely a first phase and a second phase:

in a first non-light-emitting stage in the first stage, sequentially undergoing gate reset, data writing +Vth compensation and anode reset; in the first light-emitting stage in the first stage, EM [ i ] is pulled down to emit light, meanwhile, the first control transistor T8 and the second control transistor T9 are turned on, and a control reference potential signal (Vrefj) acts on the point D and the point E, so that leakage current is reduced in the light-emitting stage.

The column data signals are most likely non-uniform, resulting in a difference in the desired equilibrium potential at point D. Meanwhile, the active time period of the reference potential signal (Vrefj) is in the light emitting stage, and the light emitting time periods of adjacent lines and even different lines in one frame picture can be overlapped, so that theoretically required reference potential signals (Vrefj) in each column are different in the next frame picture with specific frequency, and flicker can be avoided during light emission. Thus, the trace for each column of the transmitted reference potential signal (Vrefj) should be parallel to each column of the data line.

However, even in the case of the same data signal, a change in frame frequency (FRR, frame Refresh Rate) causes a change in leakage current. The external compensation circuit module should consider the influence of both the frame rate and the potential (gray scale) of the data signal.

In a second non-light-emitting stage in the second stage, only performing second anode reset to avoid residual charges on the anode in the operation process of the previous stage; in the second light-emitting stage in the first stage, EM [ i ] is pulled down to emit light, meanwhile, the first control transistor T8 and the second control transistor T9 are turned on, and a control reference potential signal (Vrefj) acts on the point D and the point E, so that leakage current is reduced in the light-emitting stage.

The frequency conversion operation mainly consists in pulling down the refresh rate of the image, i.e. reducing the frequency of Scan1 i and Scan2 i. The refresh rate (IRR, image refresh rate) of the image is less than or equal to the frame frequency, so that the power consumption of the gate driver and the data driver is saved. Frr=n×irr often occurs, such as irr=60 Hz, frr=120 Hz. At this time, the iteration number of the second stage per frame is 1, and as the IRR decreases, the iteration number of the second stage increases. Each frame period may thus comprise 1 first phase and a plurality of second phases.

As shown in fig. 21, the pixel circuit reduces the first initializing transistor T41, the second initializing transistor T42 and the second controlling transistor T9, and can control the leakage current in the light emitting period without considering the problem of leakage caused by unbalanced potential at the point E; while saving in-plane routing resources and complexity.

After the first initializing transistor T41 and the second initializing transistor T42 are removed, when the gate of the driving transistor T1 needs to be reset, only the second light-emitting control transistor T6, the first compensating transistor T31 and the second compensating transistor T32 need to be turned on at the same time, so that the initializing voltage (Vinitial) is communicated with the gate of the driving transistor T1. As shown in the signal waveform timing diagram of fig. 22, one frame period is also divided into two phases:

in a first non-light-emitting stage of the first stage, scan3[ i ] turns on the third initialization transistor T7, EM2[ i ] turns on the second light-emission control transistor T6 in the first initial stage to initialize the B-point potential and the anode potential of the light-emitting device EL; the third initializing transistor T7, the second light emission controlling transistor T6, the first compensating transistor T31, the second compensating transistor T32 are turned on synchronously in the second initial stage to initialize the gate potential of the driving transistor T1; turning on a third initializing transistor T7 in the first B point resetting stage, and initializing the anode potential of the light-emitting device EL again until the anode charge is thoroughly cleared, so that the black picture is prevented from being transparent; in the data writing stage, the writing transistor T2, the driving transistor T1, the first compensation transistor T31, and the second compensation transistor T32 are turned on, and the Data Signal (DS) is written to the gate of the driving transistor T1.

When EM1[ i ] and EM2[ i ] are simultaneously low, the first light-emitting stage is entered, the light-emitting device EL starts to emit light, and simultaneously EM1[ i ] turns on the first control transistor T8 to make the external complement control reference potential signal (Vrefj) so as to reduce leakage current.

In the third initial stage of the second non-light-emitting stage of the second stage, the same operation as in the first initial stage is performed, but the gate potential of the driving transistor T1 is not initialized any more. The data signal is not refreshed. Therefore, scan2 i is no longer set low, and the first compensation transistor T31 and the second compensation transistor T32 remain off.

At this time, scan1[ i ] may not be turned on to turn on the write transistor T2 any more, but if considering the hysteresis characteristic of the drive transistor T1, it may be turned on to be turned off low, and the data driving chip outputs a bias voltage (e.g., a potential around the power positive signal ELVDD) through the transmission channel of the data signal to act on the point a in this period, so that the drive transistor T1 is in a bias state, and the hysteresis characteristic thereof may be relieved as much as possible, so that the change of the light emission luminance caused by the low frequency driving operation is improved as much as possible.

Similar to the foregoing processing scheme of the bias control voltage signal VBj, the driving transistor T1 herein may also be configured as a dual gate to mitigate the hysteresis of the driving transistor T1 under the trimmed bias control voltage signal VBj.

Since the reference potential signal (Vrefj) acts on the pixel circuit only in the light emitting stage, the timing of outputting the data signal with the data driver is staggered from each other, so that the reference potential signal (Vrefj) and the data signal (Dj) can be provided considering multiplexing the same output port of the data driving chip for saving the cost of the data driving chip. The reference potential signal (Vrefj) may be, for example, a first reference potential signal (Vref 1 j) or a second reference potential signal (Vref 2 j).

Specifically, as shown in fig. 23, a multiplexing circuit is added, and the multiplexing circuit includes a plurality of sets of two switches (e.g., transistors) connected in parallel, and each output port of the data driving chip is connected in series with two switches connected in parallel, one of which outputs a data signal by control of the clock signal CLK1, and the other of which outputs a reference potential signal (Vrefj) by control of the clock signal CLK 2.

Wherein, each data driving chip can integrate all generation modules of control reference potential signals (Vrefj).

As shown in fig. 24, the timing controller further includes a frequency analyzer, a gray scale transcoder, a control voltage data generator, a variable impedance circuit, and a compensation voltage generator, the frequency analyzer outputting a frame refresh frequency according to the timing control signal; the gray scale code converter outputs corresponding gray scale horizontal codes according to the gray scale data; the control voltage data generator is connected with the frequency analyzer and the gray level code converter and generates corresponding reference voltage data according to the frame refreshing frequency, the gray level code and the second lookup table; the variable impedance circuit is connected with the control voltage data generator and generates corresponding output power supply voltage according to the reference voltage data and the input power supply voltage; the compensation voltage generator is connected with the variable impedance circuit and generates a reference potential signal (Vrefj) according to the output power supply voltage.

The reference potential signal (Vrefj) may be the first reference potential signal or the second reference potential signal. In the case that the first reference potential signal is different from the second reference potential signal, the amplitude of the first reference potential signal and the second reference potential signal can be adjusted by the variable impedance circuit so as to adapt to the requirement of the pixel circuit.

The timing control signal may be an output signal GSP/CLK/ESP of the timing controller, and an enable signal DE, a vertical synchronization signal Vsync, and a control signal (not shown) for switching frequencies, so that the frequency analyzer may determine a frame rate (FRR) of the display.

The gray scale transcoder receives gray scale data (RGB image signal and gray scale voltage information thereof), and the output gray scale level Code (GLC, gray scale Code) may be used to represent the gray scale (VDS or Vdata) size of the current Pixel, or the ratio of the gray scale size to the maximum gray scale size.

When the display frame rate (FRR) and the Gray Level Code (GLC) are generated, they are transferred to the control voltage data generator, and the reference voltage data is calculated. Which generates reference voltage data with reference to a reference voltage value (Vref) preset in a second lookup table based on a frame rate (FRR) and a Gray Level Code (GLC).

The second lookup table may be stored in advance as a plurality of tables set for respective different frequencies, respectively, and may be set and stored according to characteristics of the display.

If the driving transistor T1 is a P-channel transistor, the reference voltage value stored in the second lookup table is reduced along with the rise of the gray scale value corresponding to the gray scale level code at the same frame frequency; otherwise, the reference voltage value rises. The relationship between the frame rate, the gray scale value and the reference voltage value stored in the second lookup table may be set according to the characteristics of the display device or may be required to be obtained through a lot of experiments by a specific process condition.

The reference voltage data is then transferred to analog device blocks, such as variable resistance circuits and offset voltage generators, which ultimately produce the desired reference potential signal (Vrefj) for each column.

The variable resistance circuit, like a sliding rheostat, adjusts the amplitude of the reference potential signal (Vrefj) by adjusting the magnitude of the power supply Vpower' input to the compensation voltage generator.

As shown in fig. 25, the control voltage data generator includes a comparator and a data judgment generator, the comparator is connected with the frequency analyzer, and the comparator outputs a comparison result of the frame refresh frequency and the reference frame rate; the data judging generator is connected with the comparator and the variable impedance circuit and generates reference voltage data according to the comparison result, the frame refreshing frequency and the gray level code.

The comparator compares the magnitude relation (either greater than or equal to or less than) between the actual frame rate and the reference frame rate (frequency_ref), and notifies the data judgment generator. And finally outputting the reference voltage data under the common reference judgment of the frame frequency or the frame refresh Frequency (FRR), the default value of the gray level code and the comparison result.

If FRR is greater than or equal to frequency_ref=60 Hz, no flicker will generally occur, and the final output is a default value of the gray level code.

If FRR < frequency_ref is low Frequency driving display, the reference potential signal (Vrefj) to be finally output needs to refer to the second lookup table to determine the gray level code value.

As shown in fig. 26, the timing controller further includes a register storing a threshold voltage of at least one driving transistor T1, and the register is connected to the variable impedance circuit.

In this embodiment, compared with fig. 24, a register is added, and the register is used for storing distribution information of threshold voltages (Vth) of the driving transistors T1, for example, an average value of threshold voltages of the driving transistors T1 in one or more pixel circuits in the display surface, and a function of calling a data signal is added, which is used as an external compensation function: i.e., the drift of the threshold voltage of the reverse control drive transistor T1, is used to reverse compensate for the fluctuation of the drive current (Id), and likewise, the Vth distribution can be reflected in the finally output reference potential signal (Vrefj).

In summary, the above scheme can control the reference potential signal (Vrefj) of each column based on the frame Frequency (FRR) and the gray level of the corresponding frame. Therefore, it can alleviate the image flicker by alleviating the leakage current in the pixel circuit as much as possible by controlling the reference potential signal (Vrefj) in response to the change of the frame Frequency (FRR). In addition, the scheme can display static images at very low frequency, reduce power consumption and realize reliable low-power-consumption driving operation.

Meanwhile, the above embodiments can be organically and flexibly combined, not only can the electrical property of the driving transistor T1 be maintained, but also the quality of the low-frequency driving display can be protected and the power consumption can be saved.

Any of the transistors in the pixel circuits may be a P-channel type thin film transistor or an N-channel type thin film transistor. Preferably, the drawings show that the grid electrode is represented as a P-channel type thin film transistor with open circles, and the grid electrode is not represented as an N-channel type thin film transistor with open circles.

In one embodiment, the present embodiment provides a display device including the display panel in at least one embodiment.

It can be appreciated that, since the display device provided in this embodiment includes the display panel in at least one embodiment, the first gate GE2 potential of the driving transistor T1 can be controlled by using the bias control voltage signal generated by the offset direction and/or the offset amplitude of the threshold voltage of the driving transistor T1 when the data signal is transmitted to the second gate of the driving transistor T1, so that the electrical variation of the driving transistor T1 can be reversely compensated, not only the hysteresis effect of the driving transistor T1 is improved, but also the threshold voltage drift of the driving transistor T1 can be controlled, thereby reducing the brightness difference between different pixel circuits and improving the display of the afterimage.

In addition, aiming at the low-frequency flicker phenomenon, the grid leakage current of the driving transistor T1 is restrained through corresponding improvement, and the low-frequency flicker or flicker phenomenon is effectively improved.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

The display panel and the display device provided by the embodiments of the present application are described in detail, and specific examples are applied to illustrate the principles and embodiments of the present application, and the description of the above embodiments is only used to help understand the technical solution and core ideas of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, the display panel comprising a pixel circuit, the pixel circuit comprising:

the light-emitting device is connected in series between the first power line and the second power line;

And the first grid electrode of the driving transistor is connected with a bias control voltage signal, the bias control voltage signal is generated according to the stress condition of the driving transistor, and the stress condition is the offset direction and/or the offset amplitude of the threshold voltage of the driving transistor under the condition that a data signal is transmitted to the second grid electrode of the driving transistor.

2. The display panel of claim 1, further comprising:

the time sequence controller generates a corresponding bias voltage control signal according to the gray scale data and the acting time length thereof;

the column bias voltage control driving module is connected with the time sequence controller and the pixel circuit and generates the bias control voltage signal according to the bias voltage control signal.

3. The display panel of claim 2, wherein the timing controller comprises:

the stress calculation unit calculates the stress condition of the driving transistor according to the gray scale data and the acting time thereof;

The voltage calculating unit is connected with the stress calculating unit and the column bias voltage control driving module, and generates the bias control voltage signal according to the stress condition and the first lookup table.

4. A display panel according to claim 3, further comprising one or more bias control voltage lines transmitting the bias control voltage signals, each of the bias control voltage lines being connected to at least one column of the pixel circuits, the voltage calculation unit.

5. The display panel of claim 2, wherein the pixel circuit further comprises:

a first light emitting control transistor, a first pole of which is connected with the first power line, a second pole of which is connected with the first pole of the driving transistor, and a gate of which is connected with the light emitting control line;

a second light emission control transistor, a first electrode of which is connected to a second electrode of the driving transistor, a second electrode of which is connected to an anode of the light emitting device, and a gate of which is connected to the light emission control line;

A write transistor having a first electrode connected to a data line transmitting the data signal, a second electrode connected to a source or drain of the driving transistor, and a gate connected to a first gate driving line;

a first compensation transistor having a first electrode connected to the second gate of the driving transistor, and a gate connected to the first gate driving line;

a second compensation transistor, a first pole of which is connected with a second pole of the first compensation transistor, a second pole of which is connected with a source electrode or a drain electrode of the driving transistor, and a gate electrode of which is connected with the first gate driving line;

the first electrode of the first control transistor is connected with the second electrode of the first compensation transistor, the grid electrode of the first control transistor is connected with the light-emitting control line, the second electrode of the first control transistor is connected with a first reference potential signal, and the first reference potential signal is generated according to a time sequence control signal and gray scale data.

6. The display panel of claim 5, wherein the timing controller further comprises:

a frequency analyzer outputting a frame refresh frequency according to the timing control signal;

a gray scale transcoder, which outputs a corresponding gray scale horizontal code according to the gray scale data;

the control voltage data generator is connected with the frequency analyzer and the gray scale code converter and generates corresponding reference voltage data according to the frame refreshing frequency, the gray scale level code and a second lookup table;

the variable impedance circuit is connected with the control voltage data generator and generates corresponding output power supply voltage according to the reference voltage data and the input power supply voltage;

and the compensation voltage generator is connected with the variable impedance circuit and generates the first reference potential signal according to the output power supply voltage.

7. The display panel of claim 6, wherein the control voltage data generator comprises:

The comparator is connected with the frequency analyzer and outputs a comparison result of the frame refreshing frequency and a reference frame rate;

the data judging generator is connected with the comparator and the variable impedance circuit, and generates the reference voltage data according to the comparison result, the frame refreshing frequency and the gray level code.

8. The display panel according to claim 6, wherein the timing controller further comprises a register storing a threshold voltage of at least one of the driving transistors, the register being connected to the variable impedance circuit.

9. The display panel of claim 5, wherein the pixel circuit further comprises:

a first initializing transistor having a first electrode connected to the second gate of the driving transistor, the gate of the first initializing transistor being connected to the second gate driving line;

a second initializing transistor, a first pole of which is connected with a second pole of the first initializing transistor, a second pole of which is connected with an initializing line, and a gate of which is connected with the second gate driving line;

The first electrode of the second control transistor is connected with the second electrode of the first initialization transistor, the grid electrode of the second control transistor is connected with the light emitting control line, the second electrode of the second control transistor is connected with a second reference potential signal or the first reference potential signal, the second reference potential signal is generated according to the time sequence control signal and the gray scale data, and the second reference potential signal is different from the first reference potential signal.

10. A display device comprising the display panel according to any one of claims 1-9.