CN117453289A - Microprocessor, integrated circuit and electronic equipment without pipeline cavitation - Google Patents

Abstract

The invention provides a microprocessor without pipeline cavitation, an integrated circuit and electronic equipment, and relates to the technical field of microprocessors, wherein a fetching module is used for acquiring a jump instruction and a general instruction according to pipeline period, sending the jump instruction to a jump control module and sending the general instruction to a decoding module; the jump control module is used for calculating a jump target address according to the jump instruction and sending a jump execution signal and the target address to the instruction fetching module; the instruction fetching module is further used for obtaining a new jump instruction and a new general instruction from the target address according to the jump execution signal and the target address, sending the new jump instruction to the jump control module and sending the new general instruction to the decoding module. The invention realizes that the instruction flow is continuous when jumping, and does not need to empty the pipeline, so that the execution module in the pipeline can execute continuous instructions without interruption, thereby well solving the problem of pipeline cavitation caused by the jump instruction and having extremely high practicability.

Description

Microprocessor, integrated circuit and electronic equipment without pipeline cavitation

Technical Field

The invention relates to the technical field of processors, in particular to a microprocessor without pipeline cavitation, an integrated circuit and electronic equipment.

Background

At present, a microprocessor generally adopts a pipeline structure, and a classical processor pipeline can be divided into three pipeline stages of fetching, decoding and executing. The instruction fetch stage, the instruction fetch module, is responsible for fetching instructions from the instruction memory. The fetched instruction enters a decoding stage, and a decoding module decodes the instruction, analyzes the function of the instruction, the operand of the instruction and the like. Wherein the functions of the instruction comprise addition, multiplication, shift, comparison and the like; the operands include source operands and destination operands of the instructions, i.e., operands of operations such as add/multiply/shift. The decoded instruction enters an execution stage, and the execution module carries out corresponding operation on a source operand according to the function of the instruction, calculates a result and uses the result as a destination operand. Finally, the execution result is written into the destination register.

Typically in a pipelined processor, instructions are sequentially entered into the processor's pipeline in the form of a queue. Thus, each cycle, the execution module of the execution stage has an instruction executing; similarly, each cycle has an execution result output. If the programs executed by the processor are all instructions which are executed sequentially, the whole pipeline of the processor can be always in a filling state, and the execution stage of the processor always outputs an execution result.

However, in practical applications, the processor is not always a sequential instruction in the process of executing the program, and often jumps to another address to execute another program after executing the program, and jumps to execute the program … … in other places after executing the program, and the jump is implemented by a jump instruction, so that the pipeline cavitation problem is caused by such a processing procedure.

In processors, the main cause of pipeline cavitation is jump instructions, which require re-fetching instructions from the jump target address after execution by the execution stage, where the instructions that have entered the pipeline need to be flushed. The instruction with the new address needs to be reinitialized to the pipeline, and in the process of reinitializing the pipeline, the execution stage does not execute the instruction, namely does not output the instruction, so that pipeline cavitation is caused.

Therefore, how to solve pipeline cavitation is a problem that needs to be solved without emptying the pipeline when jumping.

Disclosure of Invention

In view of the above, the present invention provides a microprocessor, an integrated circuit and an electronic device without pipeline cavitation.

The embodiment of the invention provides a microprocessor without pipeline cavitation, which comprises: the device comprises an instruction fetching module, a jump control module and a decoding module;

the instruction fetching module is used for acquiring a jump instruction and a general instruction according to a pipeline period, sending the jump instruction to the jump control module and sending the general instruction to the decoding module;

the jump control module is used for calculating a jump target address according to the jump instruction and sending a jump execution signal and the target address to the instruction fetching module;

the decoding module is used for carrying out corresponding operation on the general instruction according to a conventional pipeline flow;

the instruction fetching module is further configured to obtain a new jump instruction and a new general instruction from the target address according to the jump execution signal and the target address, send the new jump instruction to the jump control module, and send the new general instruction to the decoding module;

wherein the jump instruction and the general instruction are two parallel instructions;

the jump instruction includes: jump address calculation instructions and jump execution instructions.

Optionally, the instruction fetching module acquires a jump instruction and a general instruction according to a pipeline period, and sends the jump instruction to the jump control module, and the specific process of sending the general instruction to the decoding module includes:

The instruction fetching module initiates an instruction fetching request in a first period, and acquires a first jump address calculation instruction and a first general instruction from a first address;

the instruction fetching module sends the acquired first jump address calculation instruction to the jump control module in a second period, sends the acquired first general instruction to the decoding module, and initiates an instruction fetching request to acquire a first jump execution instruction and a second general instruction from a second address;

the instruction fetching module sends the acquired first jump execution instruction to the jump control module in a third period, sends the acquired second general instruction to the decoding module, receives the first jump execution signal from the jump control module and the target address at the same time, initiates an instruction fetching request, and acquires a second jump address calculation instruction and a third general instruction from the target address;

the instruction fetching module sends the acquired second jump address calculation instruction to the jump control module in a fourth period, sends the acquired third general instruction to the decoding module, and simultaneously executes the flow: and initiating an instruction fetching request, and acquiring a second jump execution instruction and a fourth general instruction from an address after the target address.

Optionally, the jump control module calculates a jump target address according to the jump instruction, and the specific flow of sending a jump execution signal and the target address to the instruction fetching module includes:

the jump control module analyzes the first jump address calculation instruction in the second period, calculates the target address and stores the target address into a temporary register of the jump control module;

the jump control module receives the first jump execution instruction in the third period and sends the target address and the jump execution signal to the instruction fetching module;

the jump control module analyzes the second jump address calculation instruction in the fourth period, and executes the following steps: and calculating a new target address and storing the new target address into the temporary register.

Optionally, the specific process of the decoding module performing corresponding operation on the general instruction according to the conventional pipeline flow includes:

the decoding module decodes the first general instruction in the second period to obtain a function and an operand corresponding to the first general instruction, and sends the function and the operand to the execution module;

The decoding module decodes the second general instruction in the third period to obtain a function and an operand corresponding to the second general instruction, and sends the function and the operand to the execution module;

and the decoding module decodes the third general instruction in the fourth period to obtain the function and the operand corresponding to the third general instruction, and sends the function and the operand to the execution module.

Optionally, in the absence of a jump operation, the jump instruction is a null instruction, and the jump address calculation instruction and the jump execution instruction are both stuffed with nop instructions.

Optionally, when the jump instruction is the null instruction, the specific flow of calculating, by the jump control module, a target address of the jump according to the jump instruction, and sending, to the instruction fetching module, a jump execution signal and the target address includes:

the jump control module analyzes the first jump address calculation instruction in the second period to obtain that the first jump address calculation instruction is the nop instruction, does not perform any operation and waits for the next instruction;

and the jump control module receives the first jump execution instruction in the third period to analyze, obtains the first jump execution instruction as the nop instruction, does not perform any operation, and waits for the next instruction.

Optionally, in the third period, the execution module executes an operation according to a function and an operand corresponding to the first general instruction, and writes an execution result into a register;

the execution module executes operation according to the function and the operand corresponding to the second general instruction in the fourth period, and writes the execution result into the register;

and in a fifth period, the execution module executes operation according to the function and the operand corresponding to the third general instruction and writes the execution result into the register.

Optionally, when the jump instruction is the null instruction, the instruction fetching module acquires the jump instruction and the general instruction according to a pipeline period, and sends the jump instruction to the jump control module, and the specific process of sending the general instruction to the decoding module includes:

the instruction fetching module initiates an instruction fetching request in the first period, and acquires the first jump address calculation instruction and the first general instruction from the first address;

the instruction fetching module sends the acquired first jump address calculation instruction to the jump control module in the second period, sends the acquired first general instruction to the decoding module, and initiates an instruction fetching request to acquire the first jump execution instruction and the second general instruction from the second address;

The instruction fetching module sends the acquired first jump execution instruction to the jump control module in the third period, sends the acquired second general instruction to the decoding module, and initiates an instruction fetching request to acquire the second jump address calculation instruction and the fifth general instruction from a third address;

the instruction fetching module sends the acquired second jump address calculation instruction to the jump control module in the fourth period, sends the acquired fifth general instruction to the decoding module, and simultaneously executes the flow: and initiating an instruction fetching request, and acquiring the second jump execution instruction and the sixth general instruction from a fourth address.

The embodiment of the invention also provides an integrated circuit, which comprises: as described in any of the above.

The embodiment of the invention also provides electronic equipment, which comprises: as described in any of the above.

The microprocessor without pipeline cavitation provided by the invention comprises: the device comprises an instruction fetching module, a jump control module and a decoding module. The instruction fetching module is used for simultaneously acquiring two instructions, namely a jump instruction and a general instruction according to the pipeline period, wherein the jump instruction and the general instruction are two parallel instructions. The instruction fetching module sends the jump instruction to the jump control module at the same time, and sends the general instruction to the decoding module.

The jump control module is used for calculating a jump target address according to the jump instruction and sending a jump execution signal and the target address to the instruction fetching module; the decoding module is used for carrying out corresponding operation on the general instruction according to the conventional pipeline flow; the instruction fetching module is further used for obtaining a new jump instruction and a new general instruction from the target address according to the jump execution signal and the target address, sending the new jump instruction to the jump control module and sending the new general instruction to the decoding module.

The microprocessor provided by the invention creatively adds the independent jump control module into the microprocessor, and decodes and executes the jump instruction specially, so that the jump operation can be decoded and executed more quickly. The microprocessor also creatively adopts a double instruction stream structure, one of the double instruction streams is specially used for the jump instruction, so that the decoding and the execution of the jump instruction can be simplified, and the jump instruction can be decoded and executed more quickly. And the other instruction stream enters a normal pipeline, so that the execution module in the pipeline can execute continuous instructions without interruption.

Because the invention creatively adds a jump control simulation in the decoding stage, the jump instruction can directly enter the jump control module to be executed, but if the jump instruction is directly executed, the critical path of the jump control module is easy to be overlong, and the normal flow of the pipeline is influenced.

Thus, the jump instruction is creatively split into two instructions, namely: a jump address calculation instruction and a jump execution instruction, wherein the jump address calculation instruction is used for calculating a jump target address; the jump execution instruction is to execute a jump operation. After such splitting, the decode and execution logic of the jump instruction becomes simple and can be completed in one cycle. After the jump control module executes the jump instruction, the instruction fetching module may read the instruction in the target address. When the jump is realized, the instruction flow is continuous, and the pipeline is not required to be emptied, so that the execution module in the pipeline can execute continuous instructions without interruption, thereby well solving the problem of pipeline cavitation caused by the jump instruction and having extremely high practicability.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

FIG. 1 is a schematic diagram of a conventional pipelined microprocessor;

FIG. 2 is a schematic flow diagram of a pipeline of a conventional microprocessor without a jump instruction;

FIG. 3 is a schematic flow diagram of a pipeline of a conventional microprocessor when encountering a jump instruction;

FIG. 4 is a schematic diagram of a microprocessor without pipeline cavitation according to an embodiment of the present invention;

FIG. 5 is an example of dual instruction flow in a microprocessor in accordance with an embodiment of the present invention;

FIG. 6 is a schematic flow diagram of a pipeline upon encountering a jump instruction execution in an embodiment of the invention.

Detailed Description

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

The inventors have found that in a processor of pipeline architecture, instructions are typically in the form of queues that are sequentially entered into the pipeline of the processor. Thus, each cycle, the execution module of the execution stage has an instruction executing; similarly, each cycle has an execution result output. If the programs executed by the processor are all instructions which are executed sequentially, the whole pipeline of the processor can be always in a filling state, and the execution stage of the processor always outputs an execution result.

Referring to the architecture diagram of the conventional pipeline microprocessor shown in fig. 1, a Fetch module of a Fetch pipeline stage (indicated by Fetch in fig. 1 and the rest of the figures) fetches instructions from a Program Memory, the fetched instructions enter a Decode module of a Decode pipeline stage (indicated by Decode in fig. 1 and the rest of the figures), and the Decode module decodes the instructions, and resolves functions corresponding to the instructions and operands of the instructions. Wherein the functions of the instruction comprise addition, multiplication, shift, comparison and the like; the operands include source operands and destination operands of the instructions, i.e., operands of operations such as add/multiply/shift. The decoded instruction enters an execution stage, and an execution module (shown as Exe1 in the rest figures) performs corresponding operation on a source operand according to the function of the instruction to calculate a result as a destination operand. Finally, the execution result is written into the destination register (denoted Regs in fig. 1 and the rest of the figures), where "(output)" indicates that it can be output from the register to other modules.

Typically in a pipelined processor, instructions are sequentially entered into the processor's pipeline in the form of a queue. Such a flow may be more clearly understood with reference to the pipeline flow diagram of the conventional microprocessor shown in FIG. 2 without a jump instruction. Each cycle, the execution module of the execution stage has an instruction executing; similarly, each cycle has an execution result output. Taking the addresses addr10, addr11, addr12 as an example in fig. 2, at a certain period, for example, the 10 th period, fetch fetches one instruction ins1 from addr10, and during this period, decode, exe1, regs do not have any operation.

In cycle 11, fetch fetches an instruction ins2 from addr11, while decode decodes instruction ins1 during this cycle, and exe1, regs do not have any operation.

In cycle 12, fetch fetches an instruction ins3 from addr12, while decode decodes instruction ins2 during this cycle, exe1 performs operations on the functions and operands corresponding to instruction ins1, regs does not have any operation.

By analogy, cycle 13, fetch obtains an instruction ins4 (not shown in FIG. 1) from addr13 (not shown in FIG. 1), while decode decodes instruction ins3, exe1 performs operations on the functions and operands corresponding to instruction ins2, and the execution result of instruction ins1 is written into regs during this cycle.

Execution result output is provided for each cycle of 14 th cycle … …. Thus, if the program executed by the microprocessor is an instruction which is executed sequentially, the whole pipeline of the microprocessor can be always in a filling state, and the execution stage of the microprocessor can always output an execution result.

However, the inventors have found that in practical applications, the microprocessor will not always sequence instructions during the execution of the program, and will often jump to another address and then execute another program after executing one program, and will jump to execute the program … … elsewhere after executing another program. The jump is generally implemented by a jump instruction, and when the jump instruction enters the execution stage and is executed, the jump occurs, and the Fetch needs to read the instruction from the new address according to the jump target of the jump instruction. At this time, in the pipeline of the processor, the instruction already in the decoding stage needs to be emptied, waits for a new instruction read by the instruction acquisition module to enter the decoding stage and the execution stage in sequence, and outputs a result after the execution stage executes.

For a clearer understanding of the above process, reference is made to the pipeline flow diagram of a conventional microprocessor shown in FIG. 3 when a jump instruction is encountered. In this process, because the jump instruction needs to be fetched from a new address, the instruction of the decode stage needs to be flushed, which results in the generation of pipeline cavitation. The processor pipeline is flushed before a new instruction comes in, and the execution stage has no instructions executing nor execution results output.

Taking the addresses addr10, addr11, addr12, addr13, and addr14 as examples in fig. 3, at the 10 th cycle, fetch fetches one instruction ins1 from addr10, and during this cycle, decode, exe1, regs do not operate at all.

In cycle 11, fetch fetches an instruction ins2 from addr11, while decode decodes instruction ins1 during this cycle, and exe1, regs do not have any operation.

In cycle 12, fetch fetches an instruction ins3 from addr12, while decode decodes instruction ins2 during this cycle, exe1 performs operations on the functions and operands corresponding to instruction ins1, regs does not have any operation.

In cycle 13, fetch obtains instruction ins4 from addr13 following addr12, decode decodes instruction ins3 in the cycle, exe1 performs an operation on the function and operand corresponding to instruction ins2, and the result of execution of instruction ins1 is written into regs.

In cycle 14, fetch obtains instruction ins5 from addr14, during which decode should decode instruction ins4, exe1 performs the operation on the function and operand corresponding to instruction ins3, and the result of instruction ins2 is written into regs. However, since instruction ins3 is a jump instruction (indicated by branch in fig. 3), and assuming that its target address is addr100 (not shown in fig. 3), the instruction of the decode needs to be cleared due to the execution of the jump instruction, and 14 th cycle ins4 is flushed in the decode. Then at cycle 15 exe1 should perform the operation on the function and operand corresponding to instruction ins4, but ins4 is flushed, so at cycle 15 exe1 is not executed and the result of the execution of instruction ins3 is written into regs. In cycle 16, the result of execution of instruction ins4 is not written into regs. This results in the creation of pipeline cavitation. Before a new instruction, addr101, comes in, the microprocessor pipeline is flushed, the execution stage has no instructions executing nor results of execution output, and none of the decodes, exe1, regs is executing, but is waiting, as indicated by the diagonal lines in FIG. 3.

In addition, in some implementations, the developer may wish to have the microprocessor execute a program and output a pattern of data (typically referred to as generating a regular waveform or sequence, such as an ascending sequence or a descending sequence), where the output pattern needs to be continuous and not intermittent. For example, a developer wants a microprocessor to output an increasing data segment, and immediately after outputting a decreasing data segment, the middle needs to be continuous and not intermittent, which is very common in test equipment. In order for the microprocessor to generate the above two patterns, a general implementation manner is to write two sections of programs, wherein the first section of program uses an addition instruction to perform addition operation continuously, outputs a result and generates an incremental waveform; the second program is to use subtracting instruction to do subtracting operation continuously, and output the result to generate decreasing waveform.

After the execution of the first segment pattern is completed, the jump instruction is used to jump to the second segment program, and the execution of the second segment pattern is started. There is a problem that when the first program is executed and jumps to the second program, pipeline cavitation is caused by jump, no effective instruction is being executed by the execution stage of the microprocessor, and no incremental or decremental pattern output is generated by the microprocessor, so that pattern data between the incremental sequence and the decremental sequence is discontinuous, and the test requirement is not met. In some test devices, in order to test completeness, a professional desires that the test device be able to output waveforms of various stimuli, and the requirements on the output patterns are high, and the patterns need to be continuous and cannot have cavitation.

Obviously, in the conventional microprocessor, pipeline cavitation is inevitably generated due to jump operation, and the output excitation is discontinuous, so that the requirement of test equipment cannot be met.

In order to solve the above-mentioned problems, the inventors creatively propose a microprocessor, an integrated circuit and an electronic device without pipeline cavitation of the present invention, and the microprocessor, the integrated circuit and the electronic device without pipeline cavitation of the present invention are explained and described in detail below.

The microprocessor without pipeline cavitation provided by the invention comprises: the device comprises an instruction fetching module, a jump control module and a decoding module. The instruction fetching module is used for simultaneously acquiring two instructions, namely a jump instruction and a general instruction according to a pipeline period, wherein the jump instruction and the general instruction are two parallel instructions, and the jump instruction is split into two instructions at the same time, and the instruction fetching module comprises: jump address calculation instructions and jump execution instructions. The instruction fetching module sends the jump instruction to the jump control module at the same time, and sends the general instruction to the decoding module.

The jump control module is used for calculating a jump target address according to the jump instruction and sending a jump execution signal and the target address to the instruction fetching module; the decoding module is used for carrying out corresponding operation on the general instruction according to the conventional pipeline flow; the instruction fetching module is further used for obtaining a new jump instruction and a new general instruction from the target address according to the jump execution signal and the target address, sending the new jump instruction to the jump control module and sending the new general instruction to the decoding module.

The microprocessor without pipeline cavitation provided by the invention can be shown by referring to the architecture diagram shown in fig. 4, and other modules are the same as the traditional microprocessor, except that a jump control module is arranged at the same level as the decoding stage, and in fig. 4, the jump control module is denoted by BR ctrl.

In one possible embodiment, the instruction fetching module obtains the jump instruction and the general instruction according to the pipeline period, and sends the jump instruction to the jump control module, and the specific flow of sending the general instruction to the decoding module includes:

the instruction fetching module initiates an instruction fetching request in a first period, and acquires a first jump address calculation instruction and a first general instruction from a first address, namely the value fetching module acquires two instructions, namely a jump instruction and a general instruction, simultaneously, and the jump instruction is split into two instructions: the jump address calculation instruction and the jump execution instruction, so that the instruction acquired by the value module each time is definitely the jump address calculation instruction and the general instruction or the jump execution instruction and the general instruction.

And then, the instruction fetching module sends the acquired first jump address calculation instruction to the jump control module in a second period (the second period is assumed to be the later period of the first period), sends the acquired first general instruction to the decoding module, and simultaneously initiates an instruction fetching request to acquire a first jump execution instruction and a second general instruction from a second address (the second address is assumed to be the later address of the first address) according to the sequence. It should be noted that, from the initiation of the instruction fetch request by the value-taking module to the instruction fetch, there is a delay of the pipeline stage. This is because the instruction is stored in the instruction register, and the behavior attribute of the register itself determines that the fetch module must have a one cycle delay to fetch the instruction from the instruction register.

And then, the instruction fetching module sends the acquired first jump execution instruction to the jump control module in a third period (the third period is assumed to be the later period of the second period), sends the acquired second general instruction to the decoding module, receives the first jump execution signal and the target address from the jump control module, initiates an instruction fetching request, and acquires a second jump address calculation instruction and a third general instruction from the target address. I.e., the cycle, the value module obtains the jump instruction and the general instruction from the target address, rather than sequentially from the third address (assuming that the third address is the next address to the second address).

Then, the instruction fetching module sends the second jump address calculation instruction obtained from the target address to the jump control module in the fourth period (assuming that the fourth period is the period after the third period), and sends the third jump address calculation instruction obtained from the target address to the decoding module, and meanwhile, the flow is executed: an instruction fetch request is initiated and a second jump execution instruction and a fourth general instruction are fetched from an address subsequent to the target address, e.g., the target address addr300, and from this address addr 301.

The instruction fetching module continues according to the pipeline flow until all instructions are acquired.

The specific flow of the jump control module to calculate the jump target address according to the jump instruction and send the jump execution signal and the target address to the instruction fetching module comprises:

the jump control module receives the first jump address calculation instruction in the second period, analyzes the first jump address calculation instruction, calculates a target address if the jump instruction is not a null instruction (explained below), and stores the target address in a temporary register of the jump control module.

And then, the jump control module receives the first jump execution instruction in the third period, analyzes the first jump execution instruction, and sends a target address and a jump execution signal to the instruction fetching module if the jump instruction is not a null instruction.

Then, the jump control module receives the second jump address calculation instruction in the fourth period, analyzes the second jump address calculation instruction, and if the jump instruction is not a null instruction, executes the flow: and calculating to obtain a new target address and storing the new target address into a temporary register. The jump control module continues according to the pipeline flow until no jump instruction is sent in by the instruction fetching module.

Because the decoding module and the jump control module are both positioned at the decoding stage, and the general instructions acquired by the instruction fetching module are all sent in, therefore, the specific flow of the decoding module to perform corresponding operation on the general instruction according to the conventional flow of the pipeline corresponds to the flow of the instruction fetching module, and the specific flow includes:

and the decoding module decodes the first general instruction in the second period to obtain the function and the operand corresponding to the first general instruction, and sends the function and the operand to the execution module.

And then, the decoding module decodes the second general instruction in a third period to obtain the function and the operand corresponding to the second general instruction, and sends the function and the operand to the execution module.

And then, the decoding module decodes the third general instruction in a fourth period to obtain the function and the operand corresponding to the third general instruction, and sends the function and the operand to the execution module. The first general instruction and the second general instruction are both acquired by the aforementioned first address and the second address (assuming that the second address is a subsequent address to the first address), and the third instruction is acquired by the target address (which is not adjacent to the second address) and is not acquired by an address adjacent to the second address. And more importantly, the jump instruction is successfully operated, the instruction before the jump is successfully caught by the instruction acquired by the target address, the jump instruction is continuous, and the instruction in the decoding module is not cleared.

Because the continuous instructions are decoded all the time in the decoding module, the execution module naturally executes operation according to the function and the operand corresponding to the first general instruction in the third period corresponding to the pipeline flow of the instruction fetching module, and writes the execution result into the register; the execution module naturally executes operation according to the function and the operand corresponding to the second general instruction in the fourth period, and writes the execution result into the register; in the fifth cycle, the execution module naturally executes an operation according to the function and the operand corresponding to the third general instruction, and writes the execution result into the register. Therefore, the continuous instructions can be executed in the execution module without interruption, so that the problem of pipeline cavitation caused by jump instructions is well solved.

From the foregoing, it is known that the present invention creatively employs a dual instruction stream architecture in a microprocessor, one of which is dedicated to jump instructions. It is contemplated that in practical applications, jump instructions are not always required, but that when no jump is required, no jump instructions are present. Based on this requirement, without a jump operation, the jump instruction can be designed as a null instruction, i.e. both the jump address calculation instruction and the jump execution instruction are stuffed with nop instructions, which have no function.

Referring to FIG. 5, an example of dual instruction flow in a microprocessor is illustrated. The left-most instruction stream is a jump instruction corresponding to the jump control module, and the right-most instruction stream is a general instruction. In the jump instruction stream, where execution of the jump instruction is not required, padding is performed using a null instruction nop, which instruction has no function. The instruction fetching module fetches two instructions at a time, namely a jump instruction and a general instruction. In the case that the jump instruction is not a null instruction, it is split into two pieces: jump address calculation instruction br_addr and jump execution instruction br_run. br aim represents the jump target, i.e., the value module fetches instructions from behind br aim.

Therefore, when the skip instruction is a null instruction, the skip control module calculates a skip target address according to the skip instruction, and the specific flow of sending the skip execution signal and the target address to the instruction fetching module includes:

the jump control module analyzes the first jump address calculation instruction in the second period to obtain that the first jump address calculation instruction is a nop instruction, does not perform any operation, and waits for the next instruction. The first jump address calculation instruction is a nop instruction, and the natural first jump execution instruction is also a nop instruction, so that the jump control module receives the first jump execution instruction in a third period to analyze, naturally obtains that the first jump execution instruction is a nop instruction, does not perform any operation, and continues to wait for the next jump instruction.

When the skip instruction is a null instruction, the instruction fetching module obtains the skip instruction and the general instruction according to the pipeline period, and sends the skip instruction to the skip control module, and sends the general instruction to the decoding module, which is substantially the same as the current normal pipeline flow (i.e. normal pipeline flow), and includes:

the instruction fetching module initiates an instruction fetching request in a first period, and acquires a first jump address calculation instruction and a first general instruction from a first address; the instruction fetching module sends the acquired first jump address calculation instruction to the jump control module in a second period, sends the acquired first general instruction to the decoding module, initiates an instruction fetching request, and acquires a first jump execution instruction and a second general instruction from a second address.

The instruction fetching module sends the acquired first jump execution instruction to the jump control module in a third period, sends the acquired second general instruction to the decoding module, and initiates an instruction fetching request, and because the jump instruction is a null instruction, the value fetching module acquires a second jump address calculation instruction and a fifth general instruction from a third address (assuming that the third address is a later address of the second address).

The instruction fetching module sends the acquired second jump address calculation instruction to the jump control module in a fourth period, sends the acquired fifth general instruction to the decoding module, and simultaneously executes the following steps: an instruction fetch request is initiated, and a second jump execution instruction and a sixth general instruction are fetched from a fourth address (assuming the fourth address is a subsequent address to the third address). And when the jump instruction is not the null instruction, carrying out according to the pipeline flow corresponding to the jump instruction which is not the null instruction.

For better explanation and explanation of the above structure and the way in which direct current is applied. Referring to FIG. 6, a pipeline flow diagram of a jump instruction execution is shown in an embodiment of the invention.

Taking the addresses addr10, addr11, addr12, addr13, addr100 as an example in fig. 6, at the 10 th cycle, fetch gets a jump instruction from addr10, but is an empty instruction Nop, and a general instruction ins1, while decode, exe1, regs have no operation in this cycle.

In cycle 11, fetch fetches a jump instruction from addr11, but is a null instruction Nop, and a general instruction ins2, while decode decodes general instruction ins1 during this cycle, there is no operation on exe1, regs.

In cycle 12, fetch obtains a jump instruction from addr12, calculates instruction br_addr for jump address, and a general instruction ins3, while in this cycle decode decodes instruction ins2, exe1 performs operation on the function and operand corresponding to general instruction ins1, regs has no operation. In the period, the jump control module analyzes the jump address calculation instruction Br_addr, calculates the target address addr100 and stores the target address addr100 into a temporary register of the jump control module.

In the 13 th cycle, fetch obtains a jump instruction from addr13 after addr12, executes instruction br_run for jump, and a general instruction ins4, in which decode decodes general instruction ins3, exe1 executes operation on function and operand corresponding to general instruction ins2, and execution result of general instruction ins1 is written in regs. In the period, the jump control module analyzes the jump execution instruction Br_run and sends a target address addr100 and a jump execution signal to the instruction fetching module. Fetch directly fetches a general instruction ins0a from the new address addr 100.

In cycle 14, fetch obtains a jump instruction from addr100, but is a null instruction Nop, and a general instruction ins0a, during which decode decodes instruction ins4, exe1 performs operations on the functions and operands corresponding to instruction ins3, and the execution result of instruction ins2 is written into regs.

At cycle 15, fetch obtains a jump instruction and a general instruction ins0b (not shown in FIG. 6) from addr101 (not shown in FIG. 6), decode decodes instruction ins0a, exe1 performs the operation on the function and operand corresponding to instruction ins4, and the result of execution of instruction ins3 is written into regs. In connection with the example of the dual instruction stream shown in fig. 5, during the pipeline flow, the instruction fetching module fetches the general instructions in the normal instruction stream read back, and executes the general instructions forward in the normal pipeline without interruption. Even if the jump ins (i) instruction is executed, and then the jump ins (j) instruction continues to execute, the pipeline is not interrupted, pipeline cavitation is not generated, and thus the requirement of no bubble in the pipeline of the microprocessor can be met. And further, the output pattern is continuous without interruption in the middle, and the testing requirements of the testing equipment are met.

In the pipeline flow process, the jump control module executes the instruction with single function, the decoding logic is simple, and the calculation logic is also simple, so that the decoding and execution of the instruction can be completed in one period. That is, the decoding and execution of the br_addr instruction may be completed in one cycle; the decoding and execution of the br_run instruction can be completed in one period, so that the problem that the normal flow of the pipeline is affected due to overlong critical path of the jump control module when the jump control module directly executes the jump instruction is avoided.

Based on the microprocessor without pipeline cavitation, the embodiment of the invention also provides an integrated circuit, which comprises: a microprocessor without pipeline cavitation as claimed in any preceding claim.

Based on the microprocessor without pipeline cavitation, the embodiment of the invention also provides electronic equipment, which comprises: a microprocessor without pipeline cavitation as claimed in any preceding claim.

In summary, the microprocessor without pipeline cavitation of the present invention includes: the device comprises an instruction fetching module, a jump control module and a decoding module. The instruction fetching module is used for simultaneously acquiring two instructions, namely a jump instruction and a general instruction according to the pipeline period, wherein the jump instruction and the general instruction are two parallel instructions. The instruction fetching module sends the jump instruction to the jump control module at the same time, and sends the general instruction to the decoding module.

The jump control module is used for calculating a jump target address according to the jump instruction and sending a jump execution signal and the target address to the instruction fetching module; the decoding module is used for carrying out corresponding operation on the general instruction according to the conventional pipeline flow; the instruction fetching module is further used for obtaining a new jump instruction and a new general instruction from the target address according to the jump execution signal and the target address, sending the new jump instruction to the jump control module and sending the new general instruction to the decoding module.

The microprocessor provided by the invention creatively adds the independent jump control module into the microprocessor, and decodes and executes the jump instruction specially, so that the jump operation can be decoded and executed more quickly. The microprocessor also creatively adopts a double instruction stream structure, one of the double instruction streams is specially used for the jump instruction, so that the decoding and the execution of the jump instruction can be simplified, and the jump instruction can be decoded and executed more quickly. And the other instruction stream enters a normal pipeline, so that the execution module in the pipeline can execute continuous instructions without interruption.

Because the invention creatively adds a jump control simulation in the decoding stage, the jump instruction can directly enter the jump control module to be executed, but if the jump instruction is directly executed, the critical path of the jump control module is easy to be overlong, and the normal flow of the pipeline is influenced.

Thus, the jump instruction is creatively split into two instructions, namely: a jump address calculation instruction and a jump execution instruction, wherein the jump address calculation instruction is used for calculating a jump target address; the jump execution instruction is to execute a jump operation. After such splitting, the decode and execution logic of the jump instruction becomes simple and can be completed in one cycle. After the jump control module executes the jump instruction, the instruction fetching module may read the instruction in the target address. When the jump is realized, the instruction flow is continuous, and the pipeline is not required to be emptied, so that the execution module in the pipeline can execute continuous instructions without interruption, thereby well solving the problem of pipeline cavitation caused by the jump instruction and having extremely high practicability.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.

Claims (10)

1. A microprocessor without pipeline cavitation, the microprocessor comprising: the device comprises an instruction fetching module, a jump control module and a decoding module;

the instruction fetching module is used for acquiring a jump instruction and a general instruction according to a pipeline period, sending the jump instruction to the jump control module and sending the general instruction to the decoding module;

the jump control module is used for calculating a jump target address according to the jump instruction and sending a jump execution signal and the target address to the instruction fetching module;

the decoding module is used for carrying out corresponding operation on the general instruction according to a conventional pipeline flow;

the instruction fetching module is further configured to obtain a new jump instruction and a new general instruction from the target address according to the jump execution signal and the target address, send the new jump instruction to the jump control module, and send the new general instruction to the decoding module;

Wherein the jump instruction and the general instruction are two parallel instructions;

the jump instruction includes: jump address calculation instructions and jump execution instructions.

2. The microprocessor of claim 1, wherein the instruction fetching module obtains a jump instruction and a general instruction according to a pipeline cycle, and sends the jump instruction to the jump control module, and the specific flow of sending the general instruction to the decoding module comprises:

the instruction fetching module initiates an instruction fetching request in a first period, and acquires a first jump address calculation instruction and a first general instruction from a first address;

the instruction fetching module sends the acquired first jump address calculation instruction to the jump control module in a second period, sends the acquired first general instruction to the decoding module, and initiates an instruction fetching request to acquire a first jump execution instruction and a second general instruction from a second address;

the instruction fetching module sends the acquired first jump execution instruction to the jump control module in a third period, sends the acquired second general instruction to the decoding module, receives the first jump execution signal from the jump control module and the target address at the same time, initiates an instruction fetching request, and acquires a second jump address calculation instruction and a third general instruction from the target address;

The instruction fetching module sends the acquired second jump address calculation instruction to the jump control module in a fourth period, sends the acquired third general instruction to the decoding module, and simultaneously executes the flow: and initiating an instruction fetching request, and acquiring a second jump execution instruction and a fourth general instruction from an address after the target address.

3. The microprocessor of claim 2, wherein the jump control module calculates a jump target address based on the jump instruction, and wherein the specific process of sending a jump execution signal and the target address to the instruction fetch module comprises:

the jump control module analyzes the first jump address calculation instruction in the second period, calculates the target address and stores the target address into a temporary register of the jump control module;

the jump control module receives the first jump execution instruction in the third period and sends the target address and the jump execution signal to the instruction fetching module;

the jump control module analyzes the second jump address calculation instruction in the fourth period, and executes the following steps: and calculating a new target address and storing the new target address into the temporary register.

4. The microprocessor of claim 2, wherein the specific flow of the decoding module to perform the corresponding operation on the general-purpose instruction according to a conventional pipeline flow comprises:

the decoding module decodes the first general instruction in the second period to obtain a function and an operand corresponding to the first general instruction, and sends the function and the operand to the execution module;

the decoding module decodes the second general instruction in the third period to obtain a function and an operand corresponding to the second general instruction, and sends the function and the operand to the execution module;

and the decoding module decodes the third general instruction in the fourth period to obtain the function and the operand corresponding to the third general instruction, and sends the function and the operand to the execution module.

5. The microprocessor of claim 3, wherein in the absence of a jump operation, the jump instruction is a null instruction, and wherein the jump address calculation instruction and the jump execution instruction are both stuffed with nop instructions.

6. The microprocessor of claim 5, wherein the specific flow of the jump control module calculating a target address of a jump according to the jump instruction and sending a jump execution signal and the target address to the instruction fetch module if the jump instruction is the null instruction comprises:

The jump control module analyzes the first jump address calculation instruction in the second period to obtain that the first jump address calculation instruction is the nop instruction, does not perform any operation and waits for the next instruction;

and the jump control module receives the first jump execution instruction in the third period to analyze, obtains the first jump execution instruction as the nop instruction, does not perform any operation, and waits for the next instruction.

7. The microprocessor of claim 4, wherein the execution module performs an operation according to a function and an operand corresponding to the first general instruction and writes an execution result to a register in the third cycle;

the execution module executes operation according to the function and the operand corresponding to the second general instruction in the fourth period, and writes the execution result into the register;

and in a fifth period, the execution module executes operation according to the function and the operand corresponding to the third general instruction and writes the execution result into the register.

8. The microprocessor according to claim 5, wherein, in the case that the jump instruction is the null instruction, the instruction fetching module obtains the jump instruction and the general instruction according to a pipeline cycle, and sends the jump instruction to the jump control module, and the specific process of sending the general instruction to the decoding module includes:

The instruction fetching module initiates an instruction fetching request in the first period, and acquires the first jump address calculation instruction and the first general instruction from the first address;

the instruction fetching module sends the acquired first jump address calculation instruction to the jump control module in the second period, sends the acquired first general instruction to the decoding module, and initiates an instruction fetching request to acquire the first jump execution instruction and the second general instruction from the second address;

the instruction fetching module sends the acquired first jump execution instruction to the jump control module in the third period, sends the acquired second general instruction to the decoding module, and initiates an instruction fetching request to acquire the second jump address calculation instruction and the fifth general instruction from a third address;

the instruction fetching module sends the acquired second jump address calculation instruction to the jump control module in the fourth period, sends the acquired fifth general instruction to the decoding module, and simultaneously executes the flow: and initiating an instruction fetching request, and acquiring the second jump execution instruction and the sixth general instruction from a fourth address.

9. An integrated circuit, the integrated circuit comprising: a microprocessor as claimed in any one of claims 1 to 8, which is free of pipeline cavitation.

10. An electronic device, the electronic device comprising: a microprocessor as claimed in any one of claims 1 to 8, which is free of pipeline cavitation.