CN117439386A - Controller of power supply conversion circuit and operation method thereof - Google Patents

Abstract

A controller for a power conversion circuit generates a plurality of Pulse Width Modulation (PWM) signals to control a plurality of output stage circuits to provide an output voltage and a load current to an output terminal. The controller comprises a sensing circuit, a comparison circuit, a PWM generating circuit and a control loop. The sensing circuit is coupled to the plurality of output stage circuits and generates a current sensing signal related to the load current. The comparison circuit compares the current sensing signal with a preset value representing a current threshold value to generate a comparison result. The control loop is coupled to the output end, the PWM generating circuit and the comparing circuit, and generates a trigger signal according to the reference voltage and the output voltage so as to control the PWM generating circuit to generate a plurality of PWM signals. When the comparison result indicates that the load current exceeds the current threshold, the comparison result enables the control loop to temporarily stop providing the trigger signal to the PWM generating circuit so as to delay generating a plurality of PWM signals. The controller of the power supply conversion circuit and the operation method thereof can achieve the effect of simultaneously taking the total output current clamping and the balance of the output currents of all phases into consideration.

Description

Controller of power supply conversion circuit and operation method thereof

Technical Field

The present invention relates to power conversion circuits, and more particularly to a controller for a power conversion circuit and a method for operating the same.

Background

Generally, when the current demanded by the load exceeds a specified level, the controller of the power conversion circuit is required to limit the output current of the power stage to achieve the current clamp (current limit) effect.

One current clamping method is a PWM Skip mode (PWM Skip mode), which is to mask the next PWM signal to reduce the output current when the output current exceeds a predetermined level. If the PWM skip mode is implemented directly in the multiphase power conversion circuitry (total current limit), current balancing is difficult to control. That is, if the total current exceeds the preset level, the next pwm signal is masked to stop the output of the corresponding phase current, which is likely to cause that the pwm signal of the specific phase is more frequently masked to cause the output current of each phase to be uneven. If a single phase is often limited such that the phase output current is zero, it may even cause the current balancing mechanism to fail.

Another conventional method is phase shielding (phase shielding), i.e. when the total current exceeds a predetermined level, part of the phase is disabled to limit the total current. However, this method has a disadvantage in that the output is unstable when the phase is re-enabled, and the technology is still to be improved.

Disclosure of Invention

In view of the above, the present invention provides a controller of a power conversion circuit and an operating method thereof, so as to effectively solve the problems encountered in the prior art.

One embodiment according to the present invention is a controller for a power conversion circuit. In this embodiment, the controller is coupled to the plurality of output stage circuits and generates a plurality of pwm signals to control the plurality of output stage circuits respectively, so that the power conversion circuit provides the output voltage and the load current to the output terminal. The controller comprises a sensing circuit, a first comparison circuit, a pulse width modulation generating circuit and a control loop. The sensing circuit is coupled to the plurality of output stage circuits and generates a current sensing signal related to the load current. The first comparing circuit is coupled to the sensing circuit and compares the current sensing signal with a preset value to generate a first comparing result. The preset value is used for representing the current threshold value. The pulse width modulation generating circuit is coupled to the plurality of output stage circuits. The control loop is coupled between the output end and the pulse width modulation generating circuit, and is also coupled with the first comparison circuit. The control loop generates a trigger signal according to the reference voltage and the output voltage to control the pulse width modulation generating circuit to generate a plurality of pulse width modulation signals. When the first comparison result indicates that the load current exceeds the current threshold, the first comparison result enables the control loop to temporarily stop providing the trigger signal to the pulse width modulation generating circuit for delaying the generation of a plurality of pulse width modulation signals.

In one embodiment, the control loop includes a ramp signal generating circuit, an error amplifier, a compensation circuit and a second comparison circuit. The ramp signal generating circuit generates a ramp signal and also receives a trigger signal for resetting the ramp signal. The error amplifier is coupled to the output terminal and receives the reference voltage and a feedback voltage related to the output voltage to generate an error signal. The compensation circuit is coupled to the error amplifier and the second comparison circuit for providing a compensation signal. The second comparing circuit is coupled to the ramp signal generating circuit, the compensating circuit and the pulse width modulation generating circuit, respectively, and compares the ramp signal with the compensating signal to generate a second comparison result for generating a trigger signal.

In an embodiment, the ramp signal generating circuit is further coupled to the first comparing circuit, and when the current sensing signal is higher than the preset value, the first comparing result indicates that the load current exceeds the current threshold, and the first comparing result makes the waveform slope of the ramp signal zero.

In an embodiment, the control loop further includes a logic gate coupled to the first comparison circuit and the second comparison circuit, respectively, and generating a trigger signal according to the first comparison result and the second comparison result, and delaying the reset of the ramp signal.

In one embodiment, the control loop includes a second comparison circuit and a logic gate. The second comparing circuit is coupled to the output terminal, and receives and compares the reference voltage and a feedback voltage related to the output voltage to generate a second comparison result. The logic gate is coupled to the first comparison circuit and the second comparison circuit respectively, and generates a trigger signal according to the first comparison result and the second comparison result.

Another embodiment of the invention is a method for operating a controller of a power conversion circuit. In this embodiment, the controller is coupled to the plurality of output stage circuits and generates a plurality of pwm signals to control the plurality of output stage circuits respectively, so that the power conversion circuit provides the output voltage and the load current to the output terminal. The operation method comprises the following steps: (a) generating a current sense signal related to the load current; (b) Comparing the current sensing signal with a preset value to generate a first comparison result, wherein the preset value represents a current threshold; (c) Judging whether the first comparison result indicates that the load current exceeds a current threshold value; (d) If the judgment result of the step (c) is negative, providing a trigger signal according to the reference voltage and the output voltage to generate a plurality of pulse width modulation signals; and (e) if the judgment result in the step (c) is yes, temporarily stopping providing the trigger signal for delaying the generation of a plurality of pulse width modulation signals.

In one embodiment, step (d) of the operation method further comprises: generating a ramp signal and resetting the ramp signal according to the trigger signal; generating an error signal according to the reference voltage and a feedback voltage related to the output voltage; generating a compensation signal according to the error signal; and comparing the ramp signal with the compensation signal to generate a second comparison result for generating a trigger signal.

In one embodiment, the step (e) of the operation method further comprises: when the current sensing signal is higher than a preset value, the first comparison result indicates that the load current exceeds a current threshold value, and the first comparison result enables the waveform slope of the ramp signal to be zero.

In one embodiment, the step (e) of the operation method further comprises: the trigger signal is generated according to the first comparison result and the second comparison result, and is used for delaying the reset of the ramp signal.

In one embodiment, step (d) of the operation method further comprises: comparing the reference voltage with a feedback voltage related to the output voltage to generate a second comparison result; and generating a trigger signal according to the first comparison result and the second comparison result.

Compared with the prior art, the controller of the power conversion circuit and the operation method thereof of the invention carry out current clamping on the load current (total output current) on the premise of not changing the working phase number (full-phase full-time operation) and balancing the output current of each phase so as to achieve the effects that the total output current does not exceed the preset level and the output currents of each phase are in a balanced state, thereby achieving the effect of simultaneously balancing the total output current clamping and the output current of each phase.

The advantages and spirit of the present invention will be further understood from the following detailed description and drawings.

Drawings

The drawings of the invention are described as follows:

fig. 1 is a schematic diagram of a controller of a power conversion circuit according to an embodiment of the invention.

Fig. 2 is a waveform timing chart of each signal in fig. 1.

FIG. 3A is a schematic diagram of an embodiment of the ramp signal generating circuit in FIG. 1.

Fig. 3B is a waveform timing diagram of each signal in fig. 3A.

Fig. 4A is a schematic diagram of another embodiment of the ramp signal generating circuit in fig. 1.

Fig. 4B is a waveform timing diagram of each signal in fig. 4A.

Fig. 5 is a schematic diagram of a controller of a power conversion circuit according to another embodiment of the invention.

Fig. 6 is a waveform timing chart of each signal in fig. 5.

Fig. 7 is a schematic diagram of a controller of a power conversion circuit according to another embodiment of the invention.

Fig. 8 is a waveform timing chart of each signal in fig. 7.

FIG. 9 is a waveform timing diagram showing an imbalance between output currents of phases when a prior art multi-phase system total output current clamp is performed using a skip mode.

FIG. 10 is a waveform timing diagram showing the balance between the output currents of the phases when the total output current clamp is performed according to the present invention.

FIG. 11 is a flowchart illustrating a method for operating a controller of a power conversion circuit according to another embodiment of the present invention.

Description of main reference numerals:

1. 3, 5 … power conversion circuit

10. 30, 50, … controller

100. 300, 500, … sensing circuit

1001. 3001, 5001 … summing circuit

101. 301, 501 and … preset value generating circuit

102. 302, 502 … first comparison circuit

104. 304, 504, … control loop

1040. 5040 … error amplifier

1042. 5042 … compensation circuit

1044. 3040, 5044 and … second comparator circuit

1046. 5046 … ramp signal generating circuit

3042. 5048 … logic gate

105. 305, 505 … sequence control circuit

1061-106N, 3061-306N, 5061-506N … Pulse Width Modulation (PWM) generating circuit

K1-KN … phase current sensing circuit

I1-IN … phase sense current

DV … preset value

IS … current sense signal

+ … positive input terminal

- … negative input

OCLB … first comparison result

CMP … second comparison result

Comp … Compensation Signal

Error signal ERR …

RAMP … RAMP signal

DTR … trigger signal

TR1 to TRN … control signals

PWM 1-PWMN … Pulse Width Modulation (PWM) signals

OS 1-OSN … output stage circuit

d1-D2 … driver

M1-M2 … switch

L … output inductor

OUT … output terminal

VIN … input Voltage

VOUT … output voltage

COUT … output capacitor

ROUT … output resistor

RLD … load resistor

GND … grounding terminal

t0 to t7 … time

10460 … logic gate

10462 … current source

SW 1-SW 2 … switch

C … capacitor

S10-S18 … steps

Detailed Description

Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The same or similar reference numbers are used in the drawings and the embodiments to refer to the same or similar parts.

One embodiment according to the present invention is a controller for a power conversion circuit. In this embodiment, the power conversion circuit is a Multi-phase constant on-time (COT) power conversion circuit, but not limited thereto.

Referring to fig. 1, fig. 1 is a schematic diagram of a controller 10 of a power conversion circuit 1 in this embodiment. As shown in fig. 1, in the power conversion circuit 1, the controller 10 is coupled to the N output stage circuits OS1 to OSN and generates N PWM signals PWM1 to PWMN to control the N output stage circuits OS1 to OSN respectively, so that the power conversion circuit 1 provides the output voltage VOUT and the load current IL to the output terminal OUT. N is a positive integer greater than 1.

Each of the output stage circuits OS1 to OSN includes a driver D1 to D2, a switch M1 to M2, and an output inductance L. The driver D1 is coupled between the controller 10 and the control terminal of the switch M1. The driver D2 is coupled between the controller 10 and the control terminal of the switch M2. The switches M1 and M2 are connected in series between the input voltage VIN and the ground GND. One end of the output inductor L is coupled between the switch M1 and the switch M2, and the other end of the output inductor L is coupled to the output terminal OUT. The output capacitor COUT and the output resistor ROUT are connected in series between the output terminal OUT and the ground terminal GND. The load RLD is coupled between the output terminal OUT and the ground terminal GND.

The controller 10 includes a sensing circuit 100, a preset value generating circuit 101, a first comparing circuit 102, a control loop 104, a sequence control circuit 105, and N pwm generating circuits 1061-106N. The sensing circuit 100 includes N phase current sensing circuits K1 to KN and a summing circuit 1001. The N phase current sensing circuits K1 to KN are respectively coupled to the N output stage circuits OS1 to OSN to respectively sense the N phase currents I1 to IN of the N output stage circuits OS1 to OSN to obtain N sensing signals, and the N sensing signals are added by the adding circuit 1001 to generate a current sensing signal IS related to the load current IL. The preset value generating circuit 101 is configured to generate a preset value DV as a current threshold value for limiting the load current IL. The positive input terminal of the first comparing circuit 102 is +coupled to the preset value generating circuit 101 to receive the preset value DV. The negative input of the first comparison circuit 102 IS coupled to the sensing circuit 100 to receive the current sensing signal IS. The first comparing circuit 102 compares the current sensing signal IS with a preset value DV to generate a first comparison result OCLB.

The control circuit 104 is coupled to the output terminal of the first comparing circuit 102, the output terminal OUT and the sequence control circuit 105, and is configured to receive the output voltage VOUT, the reference voltage VREF and the first comparing result OCLB, respectively, to generate the trigger signal DTR to the sequence control circuit 105.

The sequence control circuit 105 is coupled between the control circuit 104 and the N PWM generation circuits 1061 to 106N, and is configured to sequentially generate N control signals TR1 to TRN to the corresponding N PWM generation circuits 1061 to 106N according to the trigger signal DTR, so as to control the N PWM generation circuits 1061 to 106N to generate N PWM signals PWM1 to PWMN to the N output stage circuits OS1 to OSN, respectively, to control the operations of the N output stage circuits OS1 to OSN, respectively.

In this embodiment, the control loop 104 includes an error amplifier 1040, a compensation circuit 1042, a second comparison circuit 1044, and a ramp signal generating circuit 1046. The error amplifier 1040 is coupled between the output terminal OUT and the compensation circuit 1042, and is configured to receive the reference voltage VREF and the output voltage VOUT (or a feedback voltage related to the output voltage VOUT) to generate an error signal ERR. The compensation circuit 1042 is coupled between the error amplifier 1040 and a negative input terminal of the second comparing circuit 1044 for converting the error signal ERR into a compensation signal COMP and inputting the compensation signal COMP to the negative input terminal of the second comparing circuit 1044.

The RAMP signal generating circuit 1046 is coupled to the output terminal of the first comparing circuit 102 and the positive input terminal+ and the output terminal of the second comparing circuit 1044, and is configured to receive the first comparing result OCLB from the first comparing circuit 102 to generate a RAMP signal RAMP to the positive input terminal+ of the second comparing circuit 1044 and to receive the trigger signal DTR from the output terminal of the second comparing circuit 1044 to reset the RAMP signal RAMP. The positive input terminal of the second comparing circuit 1044 is +coupled to the ramp signal generating circuit 1046, and the negative input terminal of the second comparing circuit 1044 is-coupled to the compensating circuit 1042. The output end of the second comparing circuit 1044 is coupled to the ramp signal generating circuit 1046 and the sequence control circuit 105, respectively. The second comparing circuit 1044 compares the RAMP signal RAMP with the compensation signal COMP to generate a second comparison result as the trigger signal DTR to be outputted to the sequence control circuit 105.

It should be noted that, when the current sensing signal IS not higher than the preset value DV, the first comparison result OCLB generated by the first comparison circuit 102 indicates that the load current does not exceed the current threshold, and the control circuit 104 normally provides the trigger signal DTR to the sequence control circuit 105, so that the PWM generation circuit 106 normally and sequentially generates the N PWM signals PWM 1-PWMN to the N output stage circuits OS 1-OSN. When the current sensing signal IS higher than the preset value DV, the first comparison result OCLB generated by the first comparison circuit 102 indicates that the load current exceeds the current threshold, and the first comparison result OCLB causes the control loop 104 to temporarily stop providing the trigger signal DTR to the sequence control circuit 105, thereby delaying the time of generating the next pwm signal by the pwm generation circuit 106.

In detail, in this embodiment, when the current sensing signal IS greater than the preset value DV, the current source in the RAMP signal generating circuit 1046 stops charging the capacitor to stop accumulation of the RAMP signal RAMP, so that the slope of the RAMP signal RAMP IS zero and the waveform stops to continue climbing, so as to delay the RAMP signal RAMP rising to the time crossing the compensation signal COMP.

Please refer to fig. 2. Fig. 2 is a waveform timing chart of each signal in fig. 1. Taking n=4 as an example, the PWM generation circuit 106 generates PWM signals PWM4, PWM3, PWM2, PWM1 to the output stage circuits OS4, OS3, OS2, OS1 according to the control signals TR1 to TR4, respectively.

Before time t1, the current sensing signal IS smaller than the preset value DV, and the pwm generation circuit 106 generates pwm signals of each phase according to the intersection condition of the RAMP signal RAMP and the compensation signal COMP. For example, at time t0, the RAMP signal RAMP and the compensation signal COMP intersect to enable the control circuit 104 to generate the trigger signal DTR, the sequence control circuit 105 controls the PWM generation circuit 106 to generate the PWM signal PWM1 according to the trigger signal DTR and the RAMP signal generation circuit 1046 simultaneously resets the waveform of the RAMP signal RAMP according to the trigger signal DTR.

At time t1, the current sensing signal IS initially greater than the preset value DV, the first comparison result OCLB output by the first comparison circuit 102 changes from the original High level (High) to the Low level (Low), so that the slope of the RAMP signal RAMP generated by the RAMP signal generating circuit 1046 IS zero, and the waveform IS maintained at the current level.

The waveform of the RAMP signal RAMP stops changing between time t1 and time t2, so that the RAMP signal RAMP and the compensation signal COMP do not cross over (i.e. the trigger signal DTR is not generated), so that the PWM generation circuit 106 does not generate the next PWM signal (PWM 4) during this period. During this period, the PWM signal PWM1 is generated according to the original generation mechanism until the on-time period is completed, and the next period waits for the trigger signal DTR to be generated.

At time t2, the current sensing signal IS smaller than the preset value DV, and the first comparison result OCLB output by the first comparison circuit 102 changes from the Low level (Low) to the High level (High), so that the waveform of the RAMP signal RAMP generated by the RAMP signal generating circuit 1046 starts to climb continuously.

At time t3, the RAMP signal RAMP and the compensation signal COMP intersect to make the control circuit 104 generate the trigger signal DTR, the sequence control circuit 105 generates the control signal TR1 according to the trigger signal DTR to control the PWM generation circuit 106 to generate the PWM signal PWM4 of the next phase, and the RAMP signal generation circuit 1046 resets the waveform of the RAMP signal RAMP according to the trigger signal DTR.

Please refer to fig. 3A. FIG. 3A is a schematic diagram of an embodiment of the ramp signal generating circuit in FIG. 1. As shown in fig. 3A, the ramp signal generating circuit 1046, which belongs to the rising type, includes a logic gate 10460, a current source 10462, switches SW1 to SW2, and a capacitor C. The current source 10462, the switch SW1 and the capacitor C are connected in series between the working voltage VDD and the ground GND. The logic gate 10460 receives the first comparison result OCLB output by the first comparison circuit 102 and the trigger signal DTR output by the control circuit 104, and controls whether the switch SW1 is turned on or not according to the first comparison result OCLB and the trigger signal DTR. The switch SW2 is coupled to two ends of the capacitor C, and whether the switch SW2 is turned on or not is controlled by the trigger signal DTR. The positive input terminal+ of the second comparing circuit 1044 is coupled between the switch SW1 and the capacitor C for receiving the RAMP signal RAMP. The second comparing circuit 1044 compares the RAMP signal RAMP with the compensation signal COMP and outputs a second comparison result as the trigger signal DTR.

Please refer to fig. 3B. Fig. 3B is a waveform timing diagram of each signal in fig. 3A. As shown in fig. 3B, at time t1, the current sensing signal IS starts to be greater than the preset value DV, and the first comparison result OCLB IS changed from the original High level (High) to the Low level (Low), so that the logic gate 10460 controls the switch SW1 to be non-conductive and turns off the charging path of the current source 10462 to the capacitor C, so that the waveform of the RAMP signal RAMP stops rising and IS maintained at the current level. Between time t1 and time t2, the waveform of the RAMP signal RAMP stops changing. At time t2, the current sensing signal IS smaller than the preset value DV, and the first comparison result OCLB IS changed from the Low level (Low) to the High level (High), so that the waveform of the RAMP signal RAMP starts to climb continuously. At time t3, when the RAMP signal RAMP and the compensation signal COMP intersect, the second comparing circuit 1044 generates the trigger signal DTR and the switch SW2 is controlled by the trigger signal DTR to be turned on at the same time so as to reset the waveform of the RAMP signal RAMP.

Please refer to fig. 4A. Fig. 4A is a schematic diagram of another embodiment of the ramp signal generating circuit in fig. 1. As shown in fig. 4A, the ramp signal generating circuit 1046 belonging to the falling type includes a logic gate 10460, a current source 10462, switches SW1 to SW2, and a capacitor C. The switch SW1 and the capacitor C are connected in series between the working voltage VDD and the ground GND. Whether the switch SW1 is turned on or not is controlled by the trigger signal DTR. The switch SW2 and the current source 10462 are connected in series to two ends of the capacitor C. The logic gate 10460 receives the first comparison result OCLB output by the first comparison circuit 102 and the trigger signal DTR output by the control circuit 104, and controls whether the switch SW2 is turned on or not according to the first comparison result OCLB and the trigger signal DTR. The negative input of the second comparator 1044 is coupled between the switch SW1 and the capacitor C for receiving the RAMP signal RAMP. The second comparing circuit 1044 compares the RAMP signal RAMP with the compensation signal COMP and outputs a second comparison result as the trigger signal DTR.

Please refer to fig. 4B. Fig. 4B is a waveform timing diagram of each signal in fig. 4A. As shown in fig. 4B, at time t1, the current sensing signal IS starts to be greater than the preset value DV, and the first comparison result OCLB IS changed from the original High level (High) to the Low level (Low), so that the logic gate 10460 controls the switch SW2 to be non-conductive and disconnect the discharging path, so that the waveform of the RAMP signal RAMP stops to decrease and IS maintained at the current level. Between time t1 and time t2, the waveform of the RAMP signal RAMP stops changing. At time t2, the current sensing signal IS smaller than the preset value DV, and the first comparison result OCLB IS changed from the Low level (Low) to the High level (High), so that the waveform of the RAMP signal RAMP starts to continuously decrease. At time t3, when the RAMP signal RAMP and the compensation signal COMP intersect, the second comparing circuit 1044 generates the trigger signal DTR and the switch SW1 is controlled by the trigger signal DTR to be turned on at the same time so as to reset the waveform of the RAMP signal RAMP.

Please refer to fig. 5. Fig. 5 is a schematic diagram of a controller of a power conversion circuit according to another embodiment of the invention. As shown in fig. 5, the controller 30 of the power conversion circuit 3 includes a sensing circuit 300, a preset value generating circuit 301, a first comparing circuit 302, a control loop 304, a sequence control circuit 305, and N pulse width modulation generating circuits 3061 to 306N.

It should be noted that, since the operations of the sensing circuit 300, the preset value generating circuit 301, the first comparing circuit 302, the sequence control circuit 305 and the N pwm generating circuits 3061-306N in fig. 5 are the same as the operations of the sensing circuit 100, the preset value generating circuit 101, the first comparing circuit 102, the sequence control circuit 105 and the N pwm generating circuits 1061-106N in fig. 1, the description thereof is omitted herein.

Next, the control loop 304 in fig. 5 will be described in detail.

The control loop 304 includes a second comparison circuit 3040 and a logic gate 3042. The positive input terminal of the second comparison circuit 3040+receives the reference voltage VREF and the negative input terminal of the second comparison circuit 3040-is coupled to the output terminal OUT and receives the output voltage VOUT (or a feedback voltage related to the output voltage VOUT). The second comparing circuit 3040 compares the output voltage VOUT with the reference voltage VREF to generate a second comparison result CMP. The logic gate 3042 is coupled to the output terminals of the first and second comparing circuits 302 and 3040, respectively, for receiving the first and second comparing results OCLB and CMP, respectively, and generating the trigger signal DTR to the sequence control circuit 305 according to the first and second comparing results OCLB and CMP.

When the current sensing signal IS greater than the preset value DV, the first comparison result OCLB IS changed from the High level (High) to the Low level (Low), such that the logic gate 3042 pauses the generation of the trigger signal DTR to the sequence control circuit 305 to control the pwm generation circuit 306 to pause the generation of the next pwm signal, so that the next pwm signal IS not generated when the second comparison result CMP IS at the High level (High).

Please refer to fig. 6. Fig. 6 is a waveform timing chart of each signal in fig. 5. Taking n=4 as an example, the PWM generation circuit 306 generates PWM signals PWM4, PWM3, PWM2, PWM1 to the output stage circuits OS4, OS3, OS2, OS1 according to the control signals TR1 to TR4, respectively.

At time t1, the current sensing signal IS less than the preset value DV, the first comparison result OCLB generated by the first comparison circuit 302 IS at a High level (High), the output voltage VOUT IS less than the reference voltage VREF, and the second comparison result CMP generated by the second comparison circuit 3040 IS at a High level (High), such that the logic gate 3042 IS allowed to generate the trigger signal DTR to the sequence control circuit 305 to control the PWM generation circuit 306 to generate the PWM signal PWM2.

Between time t2 and t3, the current sensing signal IS greater than the preset value DV, the first comparison result OCLB generated by the first comparison circuit 302 IS at a Low level (Low), and the output voltage VOUT IS greater than the reference voltage VREF at this time, the second comparison result CMP generated by the second comparison circuit 3040 IS at a Low level (Low), and the logic gate 3042 will not generate the trigger signal DTR to the sequence control circuit 305.

In the period from time t3 to time t5, the same as time t1 to time t3 is used, and thus, the description thereof will be omitted.

At time t5, the current sensing signal IS greater than the preset value DV, the first comparison result OCLB generated by the first comparison circuit 302 IS at a Low level (Low), the output voltage VOUT IS smaller than the reference voltage VREF, the second comparison result CMP generated by the second comparison circuit 3040 IS at a High level (High), and the logic gate 3042 temporarily stops generating the trigger signal DTR to the sequence control circuit 305 due to the second comparison result CMP of the first comparison result OCLB of the Low level (Low) shielding the High level (High), so as to control the pwm generation circuit 306 to temporarily stop generating the next pwm signal.

At time t6, the current sensing signal IS less than the preset value DV, the first comparison result OCLB generated by the first comparison circuit 302 IS at a High level (High), the output voltage VOUT IS less than the reference voltage VREF, and the second comparison result CMP generated by the second comparison circuit 3040 IS at a High level (High), such that the logic gate 3042 IS allowed to generate the trigger signal DTR to the sequence control circuit 305 to control the PWM generation circuit 306 to generate the PWM signal PWM4.

After time t7, since the output voltage VOUT is less than the reference voltage VREF, the second comparison result CMP generated by the second comparison circuit 3040 is at a High level (High), and the logic gate 3042 generates the trigger signal DTR to the sequence control circuit 305 when the first comparison result OCLB generated by the first comparison circuit 302 is at a High level (High), so as to control the pwm generation circuit 306 to sequentially generate a plurality of pwm signals.

Please refer to fig. 7. Fig. 7 is a schematic diagram of a controller of a power conversion circuit according to another embodiment of the invention. As shown in fig. 7, the controller 50 of the power conversion circuit 5 includes a sensing circuit 500, a preset value generating circuit 501, a first comparing circuit 502, a control loop 504, a sequence control circuit 505 and N pulse width modulation generating circuits 5061 to 506N.

It should be noted that, since the operations of the sensing circuit 500, the preset value generating circuit 501, the first comparing circuit 502, the sequence control circuit 505 and the pwm generating circuits 5061 to 506N in fig. 7 are the same as the operations of the sensing circuit 100, the preset value generating circuit 101, the first comparing circuit 102, the sequence control circuit 105 and the pwm generating circuits 1061 to 106N in fig. 1, the description thereof is omitted herein.

Next, a detailed description will be given of the control loop 504 in fig. 7.

The control loop 504 includes an error amplifier 5040, a compensation circuit 5042, a second comparison circuit 5044, a ramp signal generation circuit 5046, and a logic gate 5048. The error amplifier 5040 is coupled between the output terminal OUT and the compensation circuit 5042, and is configured to receive the reference voltage VREF and the output voltage VOUT (or a feedback voltage related to the output voltage VOUT) to generate an error signal ERR. The compensation circuit 5042 is coupled between the error amplifier 5040 and the negative input terminal of the second comparing circuit 5044, and is used for converting the error signal ERR into a compensation signal COMP and inputting the compensation signal COMP to the negative input terminal of the second comparing circuit 5044.

The RAMP signal generating circuit 5046 is coupled to the positive input terminal+ of the second comparing circuit 5044 and the output terminal of the logic gate 5048, respectively, for generating a RAMP signal RAMP to the positive input terminal+ of the second comparing circuit 5044 and receiving a trigger signal DTR from the output terminal of the logic gate 5048 to reset the RAMP signal RAMP.

The positive input terminal of the second comparing circuit 5044 is +coupled to the ramp signal generating circuit 5046 and the negative input terminal of the second comparing circuit 1044 is-coupled to the compensating circuit 5042. The output of the second comparator 5044 is coupled to the input of the logic gate 5048. The second comparing circuit 5044 compares the RAMP signal RAMP with the compensation signal COMP to generate a second comparison result CMP to the logic gate 5048. The logic gate 5048 is coupled to the output terminal of the first comparing circuit 502, the output terminal of the second comparing circuit 5044, and the sequence control circuit 505, and is configured to receive the first comparing result OCLB generated by the first comparing circuit 502 and the second comparing result CMP generated by the second comparing circuit 5044, and generate the trigger signal DTR accordingly to output to the sequence control circuit 505.

It should be noted that, when the first comparison result OCLB generated by the first comparison circuit 502 indicates that the current sensing signal IS not higher than the preset value DV, the control circuit 504 normally provides the trigger signal DTR to the sequence control circuit 505, so that the PWM generation circuit 506 normally sequentially generates the N PWM signals PWM 1-PWMN to the N output stage circuits OS 1-OSN. When the first comparison result OCLB generated by the first comparison circuit 502 indicates that the current sensing signal IS higher than the preset value DV, the first comparison result OCLB causes the control circuit 504 to temporarily stop providing the trigger signal DTR to the sequence control circuit 505, thereby delaying the time of generating the next pwm signal by the pwm generation circuit 506.

Please refer to fig. 8. Fig. 8 is a waveform timing chart of each signal in fig. 7. Fig. 8 differs from fig. 2 in that: in fig. 2, at time t0, when the RAMP signal RAMP crosses the compensation signal COMP, the control loop 104 immediately sends out the trigger signal DTR to start the pwm generation circuit 106 to generate the next pwm signal. In fig. 8, at time t1, when the RAMP signal RAMP crosses the compensation signal COMP, the control circuit 504 does not immediately output the trigger signal DTR, but waits until time t2, and the current sensing signal IS lower than the preset value DV, the control circuit 504 IS allowed to output the trigger signal DTR to start the pwm generation circuit 506 to generate the next pwm signal.

Please refer to fig. 9 and fig. 10 simultaneously. In fig. 9, since the prior art adopts the skip mode to clamp the total current, when the total current exceeds the preset level, a shielding signal is sent to shield the next pwm signal, so that the pwm signal of a specific phase is more often shielded, and the output currents I1 to I4 of each phase become quite unbalanced. In fig. 10, since the present invention performs current clamping on the total output current (i.e., the current sense signal IS) without changing the number of working phases (full-phase full-time operation) and the average of the output currents I1 to I4 of each phase, the total output current IS does not exceed the preset level and the output currents I1 to I4 of each phase are in an equilibrium state. Thus, as can be seen by comparing fig. 9 and 10: the invention delays the whole pulse width modulation signal, thus achieving the effect of current limitation without affecting the output of each phase current. The problem that the output currents of all phases are unbalanced when the total output current is clamped in the prior art can be effectively solved, and the effect of simultaneously clamping the total output current and balancing the output currents of all phases is achieved.

Another embodiment of the invention is a method for operating a controller of a power conversion circuit. In this embodiment, the power conversion circuit is a multiphase constant on-time power conversion circuit. The controller is coupled to the plurality of output stage circuits and generates a plurality of pulse width modulation signals to control the plurality of output stage circuits respectively, so that the power conversion circuit provides output voltage and load current to the output end.

Referring to fig. 11, fig. 11 is a flowchart illustrating an operation method of the controller of the power conversion circuit in this embodiment. As shown in fig. 11, the operation method of the controller of the power conversion circuit includes the following steps:

step S10: generating a current sense signal related to the load current;

step S12: comparing the current sensing signal with a preset value to generate a first comparison result;

step S14: judging whether the first comparison result indicates that the current sensing signal is higher than a preset value;

step S16: if the judgment result in the step S14 is yes, temporarily stopping providing the trigger signal for delaying the generation of the pulse width modulation signal; and

step S18: if the judgment result in the step S14 is no, providing a trigger signal according to the reference voltage and the output voltage to sequentially generate a plurality of pulse width modulation signals.

In practical applications, the operation method can generate a ramp signal according to the first comparison result and generate an error signal according to the reference voltage and a feedback voltage related to the output voltage, and then compare the ramp signal with the error signal to generate a second comparison result, but not limited thereto.

In an embodiment, the operation method generates the trigger signal according to the first comparison result. For example, the second comparison result can be generated according to the first comparison result and directly provided as the trigger signal. Or the first comparison result and the second comparison result are logically judged to generate a trigger signal. Then, the operation method resets the ramp signal according to the trigger signal delayed by the temporary stop, but not limited to this.

In another embodiment, since the power conversion circuit is a multiphase constant on-time power conversion circuit, the operation method further comprises: respectively sensing a plurality of output currents of a plurality of output stage circuits to obtain a plurality of phase sensing signals; and adding the plurality of phase sensing signals to obtain a current sensing signal, but not limited thereto.

Compared with the prior art, the controller of the power conversion circuit and the operation method thereof do not adopt the prior shielding or skipping mode, but delay the whole pulse width modulation signal by temporarily stopping generating the trigger signal, and can clamp the total output current on the premise of not influencing the number of working phases and balancing the output currents of all phases, thereby achieving the effects of clamping the total output current, not influencing the output voltage and maintaining the balance of the output currents of all phases.

Claims (10)

1. A controller of a power conversion circuit, wherein the controller is coupled to a plurality of output stage circuits and generates a plurality of pwm signals to control the plurality of output stage circuits respectively, so that the power conversion circuit provides an output voltage and a load current to an output terminal, the controller comprising:

a sensing circuit coupled to the plurality of output stage circuits and generating a current sensing signal related to the load current;

a first comparing circuit coupled to the sensing circuit and comparing the current sensing signal with a predetermined value to generate a first comparison result, wherein the predetermined value is used for representing a current threshold;

a pulse width modulation generating circuit coupled to the plurality of output stage circuits; and

a control loop coupled between the output end and the PWM generation circuit and further coupled to the first comparison circuit, wherein the control loop generates a trigger signal according to a reference voltage and the output voltage to control the PWM generation circuit to generate the PWM signals,

when the first comparison result indicates that the load current exceeds the current threshold, the first comparison result causes the control loop to temporarily stop providing the trigger signal to the pwm generation circuit for delaying generation of the pwm signals.

2. The controller of the power conversion circuit according to claim 1, wherein the control loop includes:

a ramp signal generating circuit for generating a ramp signal and receiving the trigger signal for resetting the ramp signal;

an error amplifier coupled to the output terminal for receiving the reference voltage and a feedback voltage related to the output voltage to generate an error signal;

a compensation circuit coupled to the error amplifier for receiving the error signal to generate a compensation signal; and

and a second comparing circuit coupled to the ramp signal generating circuit, the compensating circuit and the pwm generating circuit, respectively, for comparing the ramp signal with the compensating signal to generate a second comparison result for generating the trigger signal.

3. The controller of claim 2, wherein the ramp signal generating circuit is further coupled to the first comparing circuit, and the first comparing result indicates that the load current exceeds the current threshold when the current sensing signal is higher than the predetermined value, and the first comparing result makes the waveform slope of the ramp signal zero.

4. The controller of the power conversion circuit according to claim 2, wherein said control loop further comprises:

and a logic gate coupled to the first comparison circuit and the second comparison circuit respectively, for generating the trigger signal according to the first comparison result and the second comparison result and delaying the reset of the ramp signal.

5. The controller of the power conversion circuit according to claim 1, wherein the control loop includes:

a second comparing circuit coupled to the output end for receiving and comparing the reference voltage and a feedback voltage related to the output voltage to generate a second comparison result; and

and a logic gate coupled to the first comparison circuit and the second comparison circuit respectively, and generating the trigger signal according to the first comparison result and the second comparison result.

6. The operation method of the controller of the power conversion circuit is characterized in that the controller is coupled with a plurality of output stage circuits and generates a plurality of pulse width modulation signals to respectively control the plurality of output stage circuits so that the power conversion circuit provides an output voltage and a load current to an output end, and the operation method comprises the following steps of:

(a) Generating a current sense signal associated with the load current;

(b) Comparing the current sensing signal with a preset value to generate a first comparison result, wherein the preset value represents a current threshold;

(c) Judging whether the first comparison result indicates that the load current exceeds the current threshold value;

(d) If the judgment result in the step (c) is negative, providing a trigger signal according to a reference voltage and the output voltage so as to generate the pulse width modulation signals; and

(e) If the result of the determination in step (c) is yes, temporarily stopping providing the trigger signal for delaying the generation of the plurality of pulse width modulation signals.

7. The method of claim 6, wherein step (d) further comprises:

generating a ramp signal and resetting the ramp signal according to the trigger signal;

generating an error signal according to the reference voltage and a feedback voltage related to the output voltage;

generating a compensation signal according to the error signal; and

comparing the ramp signal with the compensation signal to generate a second comparison result for generating the trigger signal.

8. The method of claim 7, wherein step (e) further comprises: when the current sensing signal is higher than the preset value, the first comparison result indicates that the load current exceeds the current threshold, and the first comparison result enables the waveform slope of the ramp signal to be zero.

9. The method of claim 7, wherein the step (e) further comprises generating the trigger signal according to the first comparison result and the second comparison result, and delaying the reset of the ramp signal.

10. The method of claim 6, wherein step (d) further comprises:

comparing a reference voltage with a feedback voltage related to the output voltage to generate a second comparison result; and

generating the trigger signal according to the first comparison result and the second comparison result.