CN117438299B

CN117438299B - Etching method of III-V compound semiconductor material

Info

Publication number: CN117438299B
Application number: CN202311766582.XA
Authority: CN
Inventors: 马飞; 邹鹏辉; 王文博; 邱士起; 周康; 程永健
Original assignee: Zhejiang Jimaike Microelectronics Co Ltd
Current assignee: Zhejiang Jimaike Microelectronics Co Ltd
Priority date: 2023-12-21
Filing date: 2023-12-21
Publication date: 2024-03-29
Anticipated expiration: 2043-12-21
Also published as: CN117438299A

Abstract

The invention provides an etching method of a III-V compound semiconductor material, which comprises the following steps: removing epitaxial material of a predetermined thickness from the exposed portion of the epitaxial layer by a plurality of cyclical atomic layer etching processes, each atomic layer etching process being performed by alternately performing a passivation step and an etching step, based on the patterned hard mask layer, comprising: under the condition of applying bias to the substrate, carrying out surface modification on the exposed part of the epitaxial layer by using a first gas mixture containing oxygen ions to form a surface passivation layer; the surface passivation layer is exposed to a second gas mixture containing chloride ions and removed. According to the invention, the epitaxial layer is exposed to the reactant system containing oxygen ions and chloride ions sequentially to form atomic layer etching circulation, so that the accurate control of etching depth and uniformity is realized, the control precision of an etching process is improved, the ALE process is repeatedly executed, and the process steps can be greatly shortened.

Description

Etching method of III-V compound semiconductor material

Technical Field

The invention belongs to the technical field of semiconductors, and relates to an etching method of a III-V compound semiconductor material.

Background

With the development and popularization of radio frequency devices and high power devices, gallium nitride-based High Electron Mobility Transistor (HEMT) devices have gained increasing attention. Gallium nitride-based High Electron Mobility Transistor (HEMT) devices have performance superior to first generation silicon-based semiconductors and second generation gallium arsenide-based compound semiconductors due to their special two-dimensional electron gas transport mechanism and wider forbidden band width. The main challenges faced by gallium nitride devices are substrate, epitaxial growth and prior process instability compared to the first two generations of semiconductor processes.

The epitaxial material of the gallium nitride-based HEMT device generally comprises Al, ga and N compounds with different components, and the previous process comprises the following steps: ohmic contact, gate fabrication, metal interconnect, and the like. The gate pin region in the gallium nitride-based HEMT device can play a main role in controlling two-dimensional electron gas (2 DEG), and accordingly, the gate pin is an important step in the previous process. Typically, the manufacturing process of the gate pin includes protecting the gallium nitride-based epitaxial structure with a dielectric layer, etching the gate pin dielectric by photolithography and etching methods, and exposing the gallium nitride of the gate pin for subsequent schottky contact preparation. With the increase of the application frequency, the thickness of the barrier layer under the gate foot needs to be adjusted in order to reduce the short channel effect and ensure the two-dimensional electron gas concentration. In the existing process, for a 0.25um gate long device, the optimal thickness of the barrier layer is 17nm; for a 0.1um gate length device, the optimal height of the barrier layer is 11nm. However, conventional plasma etching equipment, after entering the technical generation below 14nm and other etching fields with low damage requirements, can face challenges such as etching damage, control accuracy and the like.

Accordingly, there is a need to provide a novel method for etching III-V compound semiconductor materials.

It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an etching method for a III-V compound semiconductor material, which is used to solve the problems of improving etching efficiency and simplifying the process while ensuring etching uniformity in the atomic layer etching process in the prior art.

To achieve the above and other related objects, the present invention provides a method for etching a III-V compound semiconductor material, comprising the steps of:

forming an epitaxial layer on a substrate, the epitaxial layer comprising a III-V compound semiconductor material;

forming a hard mask layer on the epitaxial layer, and patterning the hard mask layer to expose a part of the epitaxial layer;

removing epitaxial material with a preset thickness from the exposed part of the epitaxial layer through multiple times of circulating atomic layer etching processes based on the patterned hard mask layer, wherein each atomic layer etching process is executed in a mode of alternately executing a passivation step and an etching step;

the passivation step is performed by: surface modifying the exposed portion of the epitaxial layer with a first gas mixture containing oxygen ions under a bias voltage applied to the substrate to form a surface passivation layer;

the etching step is performed by: exposing the surface passivation layer to a second gas mixture containing chloride ions, and removing the surface passivation layer.

Optionally, the epitaxial layer comprises a binary compound semiconductor material or a multi-compound semiconductor material composed of at least two elements selected from Al, ga, in, N, P, as.

Optionally, the method further comprises: generating oxygen ions from an oxygen-containing gas by a plasma generator, and generating chlorine ions from a chlorine-containing gas, the oxygen-containing gas comprising N ₂ O、O ₂ 、O ₃ The chlorine-containing gas comprises one of boron trichloride and chlorine.

Optionally, etching the exposed portion of the epitaxial layer by a plasma etch process having anisotropy based on the patterned hard mask layer to form features extending longitudinally inward from the surface of the epitaxial layer.

Optionally, the step of performing the plasma etching process using an inductively coupled plasma generator, the step of etching the exposed portion of the epitaxial layer includes: and etching to form a recess extending inwards from the exposed surface of the epitaxial layer by taking the patterned hard mask layer as a mask, wherein each time the etching step is performed, the surface passivation layer positioned on the bottom surface of the recess is removed, and the surface passivation layer positioned on the side wall of the recess is reserved.

Optionally, after performing a plurality of cycles of atomic layer etching process to remove the epitaxial layer with a predetermined thickness, removing the surface passivation layer and ALE etching byproducts through a wet etching process; and annealing the substrate in a nitrogen-containing protective atmosphere to repair the etched surface of the epitaxial layer.

Optionally, the method further comprises: and after patterning the hard mask layer, removing etching byproducts of the hard mask layer through a wet etching process to expose a part of the epitaxial layer.

Optionally, the passivating step includes bombarding the exposed surface of the epitaxial layer with oxygen ions having sufficient energy to maintain formation of the surface passivation layer at a self-limiting level by adjusting a power level of a bias voltage applied to the substrate.

Optionally, after the passivation step, the etching step is performed sequentially, each etching step having a thickness of between 0.2nm and 1.5nm of the exposed portion of the epitaxial layer removed.

The invention also provides a semiconductor device, which comprises a substrate, a semiconductor epitaxial structure and a plurality of electrodes, and is characterized in that the semiconductor epitaxial structure comprises a GaN layer and a barrier layer, wherein the GaN layer and the barrier layer form a heterojunction on the substrate, the GaN layer and the barrier layer are sequentially stacked, and an opening extending inwards from the surface of the barrier layer is formed in the semiconductor epitaxial structure by the etching method of the III-V compound semiconductor material; the electrode includes a gate electrode disposed in the opening.

As described above, the etching method of the III-V compound semiconductor material provided by the invention has the following beneficial effects:

according to the etching method of the III-V compound semiconductor material, the epitaxial layer is exposed to a reactant system containing oxygen ions and chloride ions successively, after the surface passivation layer is formed on the epitaxial layer containing the III-V compound semiconductor material, the chloride ions are utilized to remove the surface passivation layer, so that the accurate control of etching depth and uniformity is realized, and the control precision of an etching process is improved; specifically, the depth of single etching is controlled between 0.2nm/cycle and 1.5nm/cycle, and a switching machine is not needed in the process of repeatedly executing the atomic layer etching, so that the working procedure steps can be greatly shortened. In addition, after a plurality of cycles of the atomic layer etching process, the flatness of the etched surface can be further improved and the surface damage defect can be reduced through post-treatment and annealing processes on the etched surface.

Drawings

FIG. 1 is a flow chart showing a method for etching III-V compound semiconductor material according to an embodiment of the present invention.

Fig. 2 is a schematic flow chart of performing an atomic layer etching process in multiple cycles according to an embodiment of the invention.

Fig. 3 is a schematic flow chart of a single atomic layer etching process according to an embodiment of the invention.

Fig. 4A to 4I are schematic structural diagrams showing the respective stages in the method for etching III-V compound semiconductor material according to the embodiment of the present invention.

Fig. 5 is a graph showing a time-dependent etch depth of a single atomic layer etching process performed using various passivation conditions according to an etching method of a III-V compound semiconductor material according to an embodiment of the present invention.

Fig. 6 is a graph showing a time-dependent etch depth of a single atomic layer etching process performed using a plurality of etching conditions according to an etching method of a III-V compound semiconductor material according to an embodiment of the present invention.

Fig. 7 is a graph showing a variation of an etching depth with Al composition in an epitaxial layer formed by performing a single atomic layer etching process according to an etching method of a III-V compound semiconductor material according to an embodiment of the present invention.

Fig. 8 to 9 are views showing Atomic Force (AFM) microscopic images and analysis results of epitaxial layer surfaces before and after an atomic layer etching process for performing an etching method of a III-V compound semiconductor material according to an embodiment of the present invention; wherein (a) in fig. 8 represents an unetched surface of the epitaxial layer before performing an atomic layer etching process; fig. 8 (b) shows an etched surface of the epitaxial layer after performing the atomic layer etching process; fig. 9 shows the results of characterization of line roughness by AFM.

Fig. 10 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.

Description of element numbers:

100-a substrate; 200-an epitaxial layer; 300-a hard mask layer; 310-photoresist pattern; 210—a surface passivation layer; 220-ALE etch byproducts; 230-etching the damaged layer; 240-feature; 302-etching residues of the hard mask medium; a 510-GaN layer; 520-barrier layer; 530-opening.

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.

In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

By "feature" herein is meant a recess in the surface of the substrate, and the feature may have many different shapes, including but not limited to cylindrical, elliptical, rectangular, square, other polygonal recesses, and trenches.

It should be noted that the embodiments of the present invention provided in connection with the accompanying drawings are merely to illustrate the basic idea of the present invention, and the drawings only show the components related to the present invention, not the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complex.

In the drawings for describing embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced for clarity, i.e., the drawings are not drawn to actual scale. The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at new embodiments without conflict.

Generally, an Inductively Coupled Plasma (ICP) etching device cannot control etching uniformity and etching depth to be within 1nm, and the surface obtained by etching is rough and has certain etching damage. In the field of etching into technology generations below 14nm and other low damage requirements, etching equipment of atomic layer etching technology is considered as the best solution. However, in the existing Atomic Layer Etching (ALE) process, an atomic layer etching cycle consisting of surface passivation and wet etching steps is adopted, and as the etching depth of each cycle is very small, the surface passivation and wet etching steps need to be performed repeatedly to remove the material layer with the required thickness; in other words, the etching depth is precisely controlled by controlling the number of cycles, so that good uniformity is ensured, but the surface passivation and wet etching steps are repeated for a plurality of times, and a switching machine is required, so that the process steps are greatly increased particularly in the case of large etching depth.

In order to accurately control etching thickness, improve etching efficiency and simplify process steps, the invention provides an etching method of a III-V compound semiconductor material, which comprises the following steps:

removing epitaxial material of a predetermined thickness from the exposed portion of the epitaxial layer by performing an atomic layer etching process through a plurality of cycles based on the patterned hard mask layer, each atomic layer etching process being performed by alternately performing a passivation step and an etching step;

Example 1

The method of etching the III-V compound semiconductor material of the present invention will be described in detail below with reference to the accompanying drawings.

Fig. 1 is a schematic flow chart of a method for etching a III-V compound semiconductor material according to an embodiment of the present invention, wherein the etching method starts at block 101 to form an epitaxial layer 200.

At block 101, an epitaxial layer 200 is formed on a substrate, the epitaxial layer 200 comprising a III-V compound semiconductor material. Specifically, materials of the substrate (not shown) include, but are not limited to: a silicon carbide substrate, a sapphire substrate, a silicon substrate, a gallium nitride substrate, an aluminum nitride substrate, or a graphene substrate. The kind of the substrate is not particularly limited here, and may be selected as needed.

As shown in fig. 4A, the material of the epitaxial layer 200 includes a binary compound semiconductor material or a multi-compound semiconductor material composed of at least two elements selected from Al, ga, in, N, P, as.

In this embodiment, an epitaxial layer is used as a barrier layer in a semiconductor device, and the barrier layer includes one or more of an AlGaN barrier layer and an InAlN barrier layer.

Then, the operation of block 102 is performed to form a hard mask layer 300 over the epitaxial layer 200.

After forming the epitaxial layer 200, a hard mask layer 300 is formed at block 102, as shown in fig. 4B.

In this embodiment, when forming features in the epitaxial layer as the barrier layer, a dielectric passivation layer (not shown) is preferably formed in advance before forming a hard mask layer for performing a patterning process on the epitaxial layer, for reducing drain current collapse, for example, the hard mask layer 300 may be selected to be a silicon nitride hard mask layer.

In other embodiments, the dielectric passivation layer itself may be used as a hard mask, and the material may be a combination of silicon oxide and silicon nitride; preferably, silicon oxide and silicon nitride may be grown sequentially on the epitaxial layer 200 by low pressure vapor deposition (LPCVD), plasma vapor deposition (PECVD), or the like.

Further, operations of blocks 103 through 104 are performed to pattern the hard mask layer.

Fig. 4C is a schematic diagram of the structure obtained after patterning the hard mask layer in this embodiment, and in some embodiments, the step of patterning the hard mask layer 300 includes: spin-coating a photoresist layer, and forming a photoresist pattern 310 on the hard mask layer 300 through a photolithography process; the hard mask layer 300 is etched using the photoresist pattern 310 as a mask to expose a portion of the epitaxial layer. The lithography process at block 103 may be performed by one selected from the group consisting of stepper lithography, contact lithography, electron beam lithography.

In a specific embodiment, the operation of block 104 performs an etch of the hard mask layer using an Inductively Coupled Plasma (ICP) device, transferring a photoresist pattern 310 onto the hard mask layer 300, as shown in FIG. 4D, while forming patterned regions through the hard mask layer, the etched surface is also covered with an etch residue 302 of the hard mask medium. The specific formulation of the etching process for the hard mask layer may be selected as desired, and is not excessively limited herein.

Then, operations from block 105 to block 106 are performed to surface treat the exposed portions of the epitaxial layer.

The operation of block 105 is performed before block 106, and fig. 4E shows a schematic diagram of the structure obtained after removing the residual photoresist in this embodiment. In some embodiments, the photoresist pattern 310 is removed by wet etching to prevent the photoresist residue from introducing contamination and other effects to subsequent atomic layer etching processes.

In a specific embodiment, as shown in FIG. 4E, the surface of the epitaxial layer is also covered with an etch residue 302 of a hard mask medium, using BOE (HF: NH ₄ F) The solution removes the etch residue 302 of the hard mask dielectric to reveal a portion of the epitaxial layer, resulting in a window defined in the self-patterned hard mask layer as shown in fig. 4F to reveal a portion of the epitaxial layer.

Then, at block 107, a predetermined thickness of epitaxial material is removed from the exposed portion of the epitaxial layer by a plurality of cycles of the atomic layer etching process based on the patterned hard mask layer.

Fig. 4G is a schematic structural diagram of the embodiment after performing the atomic layer etching process for a plurality of cycles, and preferably performing the atomic layer etching process for a plurality of cycles according to the process flow chart shown in fig. 2 until the epitaxial material of a predetermined thickness is removed.

In some embodiments, a recipe for performing an atomic layer etch process may be configured according to target process parameters, wherein the recipe for the atomic layer etch process includes a number of cycles, and ion dose during surface passivation and etch steps, and a power level applied to a semiconductor substrate. As shown in fig. 2, the single ALE etching process currently performed is a recipe n, and the number of recipes to be performed is determined to be m according to the target process parameters.

Specifically, referring to fig. 3, each atomic layer etching process is performed by alternately performing a passivation step and an etching step, including:

the passivation step is performed by: under the condition of applying bias to the substrate, carrying out surface modification on the exposed part of the epitaxial layer by using a first gas mixture containing oxygen ions to form a surface passivation layer;

In each atomic layer etching process, updating the cycle count of the atomic layer etching process after the etching step; and determining whether to continue the atomic layer etching process according to the comparison result of the cycle count and the cycle count required to be executed for acquiring the target process parameter. As shown in fig. 3, the currently executed Cycle count is Run, and after the Cycle is completed, when the currently executed Cycle count reaches the Cycle number to be executed, it is determined to stop the whole atomic layer etching process; otherwise, the next cycle is entered, namely the cycle number is run+1. In a specific embodiment, the target process parameter may be an etching process parameter, such as a material of the epitaxial layer, an etching depth, a surface roughness, and the like.

In the embodiment of the present application, when the multiple cycles of the atomic layer etching process are performed, a recipe of each of the multiple atomic layer etching processes may be configured, for example, the thickness of the surface passivation layer formed by each surface passivation step is the same; or the thickness of the surface passivation layer formed by each surface passivation step is different, so that the etched surface formed when the atomic layer etching process is stopped has lower surface roughness, and the removal efficiency of the material to be etched is improved.

In some embodiments, the passivation step may be performed by means well known to those skilled in the art, such as inductively coupled plasma generators, capacitively coupled plasma generators, generating oxygen ions from an oxygen-containing gas comprising N ₂ O、O ₂ 、O ₃ Because the III-V compound is surface-modified by oxygen ions, a passivation layer with higher density is formed, so that the etching depth reached by each execution of ALE cycle can be controlled at a single atomic layer level, compared with common Cl ₂ /BCl ₃ The reaction for forming the passivation layer in the above technical scheme has self-limiting property, and allows the formulation of ALE etching to be adjusted gradually, so that the etching depth of ALE can be controlled accurately.

Similarly, in the etching step, chloride ions may be generated from a chlorine-containing gas including one of boron trichloride, chlorine gas, and the second gas mixture further includes an inert gas such as argon (Ar). Preferably, BCl is used ₃ The good etching selectivity to the above surface passivation layer and the III-V compound ensures that each etch only removes the surface modified portion, i.e., the surface passivation layer, without over-etching the underlying III-V compound, e.g., alGaN, gaN, alN.

Referring back to fig. 4G, at block 107, the step of etching the epitaxial layer may be performed by an atomic layer etching process having anisotropy.

Specifically, the exposed portion of the epitaxial layer is etched by a plasma etch process having anisotropy, forming features 240 extending longitudinally inward from the surface of the epitaxial layer: the step of performing the plasma etching process using an Inductively Coupled Plasma (ICP) generator to etch the exposed portion of the epitaxial layer includes: and etching to form a recess extending inwards from the exposed surface of the epitaxial layer by taking the patterned hard mask layer as a mask, wherein each time the etching step is performed, the surface passivation layer positioned on the bottom surface of the recess is removed, and the surface passivation layer positioned on the side wall of the recess is remained. The bias voltage applied to the substrate during the plasma etching process is large enough to enable ions bombarded to the exposed portion of the epitaxial layer to push the longitudinal etching, the passivation layer on the surface of the side wall of the feature is thickened after a plurality of cycles, and the lateral etching is effectively inhibited, so that the feature 240 with the side wall extending longitudinally is formed. In some cases, an Inductively Coupled Plasma (ICP) generator is used to provide a first gas mixture containing oxygen ions and a second gas mixture containing chloride ions, and by adjusting the output power of the ICP in combination with a surface passivation layer at the sidewalls, lateral etching of the features is prevented or slowed down such that the features are formed in a highly directionally selective manner, ensuring the accuracy of the pattern formed by the etching, avoiding leakage paths introduced at the sidewalls.

In this embodiment, the feature 240 may be a trench formed to extend inward from the surface of the epitaxial layer, with the bottom of the trench exposing a layer of material that acts as a barrier layer.

In a specific embodiment, each time the atomic layer etching process is performed, the passivating step includes bombarding the exposed surface of the epitaxial layer with oxygen ions having sufficient energy to maintain the formation of the surface passivation layer at a self-limiting level after each performing the passivating step by adjusting a power level of a bias voltage applied to the substrate. Since the surface modification of the epitaxial material is performed in a self-limiting manner in each passivation step of the atomic layer etching process, the formed surface passivation layer is removed in the etching step, for example, the removed thickness is between 0.2nm and 1.5nm, thereby realizing accurate control of the etching depth.

In order to show the influence of the formulation of the atomic layer etching process on the etching effect, the etching method of the III-V compound semiconductor material in the embodiment of the invention is executed by adopting ICP etching equipment, and the variation trend of the etching depth obtained by the atomic layer etching process with the duration is compared by respectively adjusting the passivation condition, the etching condition and the material type of the etched surface in the atomic layer etching process.

Example 1

Adopting an AlGaN compound with an epitaxial material being 25% of an aluminum component, and circularly executing an atomic layer etching process for a plurality of times, wherein in order to reduce measurement errors, the cycle number is 10, and the condition of a passivation step in each atomic layer etching process is as follows; o (O) ₂ 15sccm, ICP output power 700w, bias voltage power 5w; the etching step conditions are as follows: BCl (binary coded decimal) ₃ 15sccm, ICP output power 700w, bias voltage power 5w, duration 50s.

Example 2

The etching method of this example is substantially the same as that of example 1, except for the passivation step, which is provided with: o (O) ₂ 15sccm, ICP output power 700w, bias voltage power 10w.

Example 3

The etching method of this example is substantially the same as that of example 1, except for the passivation step, which is provided with: o (O) ₂ The ICP outputs 700w of power and the bias voltage outputs 5w of power.

Fig. 5 is a graph showing the variation of etching depth with single passivation time under different passivation conditions according to the method for etching III-V compound semiconductor material according to an embodiment of the present invention.

As can be seen from fig. 5, as the duration of the passivation step increases, the degree of surface passivation increases and the etch depth correspondingly increases; the etch depth remains substantially unchanged after the surface is completely passivated. As the output power of ICP increases, the time required to fully passivate the epitaxial layer increases, and the etch depth increases with increasing oxygen ion energy.

Example 4

The present example is substantially the same as the etching method of example 1, except for the etching step, which is the condition; BCl (binary coded decimal) ₃ 15sccm, ICP output power 700w, bias voltage power 5w; and the duration of the passivation step is 50s.

Example 5

The etching method of this example is substantially the same as that of example 1, except that the etching step is performed under the condition that；BCl ₃ 15sccm, ICP output power 700w, bias voltage power 10w; and the duration of the passivation step is 50s.

Example 6

The present example is substantially the same as the etching method of example 1, except for the etching step, which is the condition; BCl (binary coded decimal) ₃ The flow rate of (2) sccm, ICP output power 700w, bias voltage power 5w; and the duration of the passivation step is 50s.

Fig. 6 is a graph showing the variation of etching depth with single passivation time under different etching conditions according to the method for etching III-V compound semiconductor material according to the embodiment of the present invention.

As can be seen from fig. 6, as the duration of the passivation step increases, the removal degree of the surface passivation layer increases, the etching depth correspondingly increases, and the removal rate of the surface passivation layer increases with the increase of the chloride ion dose. The etch depth remains substantially unchanged after the complete removal of the surface passivation layer. As the ICP output power increases, the removal rate of the surface passivation layer increases, but overetching of the surface of the exterior material is caused after the removal of the surface passivation layer.

Example 7

In this example, an atomic layer etching process is performed on AlGaN compounds with different Al and Ga compositions in the same manner as the etching method of example 1, and in order to reduce measurement errors, in performing the atomic layer etching process for 10 cycles, the condition of the passivation step in each atomic layer etching process is: o (O) ₂ 15sccm, ICP output power 700w, bias power 5w, duration 50s; the etching step conditions are as follows: BCl (binary coded decimal) ₃ The resulting etch depth profile for 15sccm, ICP output power 700w, bias power 5w, and duration 50s is shown in FIG. 7.

As shown in fig. 7, with the increase of aluminum component in AlGaN compound, the passivation layer formed by oxygen ion modification is more compact, resulting in a significant reduction of the etching depth obtained by the atomic layer etching process with the cycle number of 10 times; that is, the etch rate of the ALE process slows down.

Fig. 8 shows Atomic Force (AFM) microscopic images of the surface of the epitaxial layer before and after the atomic layer etching process, which are shown in fig. 8 (a) as a comparative example, showing AFM microscopic images of the surface of the epitaxial layer before the atomic layer etching process is performed and after the surface treatment, fig. 8 (b) shows AFM microscopic images of the etched surface of the epitaxial layer after the atomic layer etching process is performed, and fig. 8 (a) and (b) show AFM microscopic images and line roughness change curves based on surface peak-valley data fitting of the AFM microscopic images, respectively, in order from top to bottom.

As can be seen from fig. 8 (a) and (b), the etched surface shown in fig. 8 (b) has a reduced peak-to-valley height difference and a reduced rate of change compared to the surface shown in fig. 8 (a), indicating that the etched surface is smooth, free of significant defects, and good in uniformity. In order to facilitate comparison of the degree of change in surface roughness of epitaxial layers before and after etching, the line roughness measurement by AFM is shown in FIG. 9, where R _a For measuring the average height variation of the surface, R _q For characterizing the root mean square roughness of the surface.

As can be seen from fig. 9, after the atomic layer etching process is performed on the surface of the epitaxial layer, R _a And R is _q Obviously reduces, shows that the control precision of the etching process is higher, and the uniformity of the processed surface is improved.

As shown in fig. 3, after the cycle count of the atomic layer etching process has reached the number of cycles to be performed, the operation at block 107 is completed, and the resulting etched surface structure is shown in fig. 4G, where the initially formed etched surface is sequentially formed with an etch damage layer 230 and an ALE etch byproduct 220.

The operations of block 108 are then performed to post-treat the etched surface of the epitaxial layer.

Fig. 4H shows a schematic structure of the epitaxial layer after post-treatment of the etched surface by a wet etching process, which is performed with HCl solution in some embodiments, to remove ALE etch byproducts 220 formed during the atomic layer etching process, and the passivation layer on the surface of the feature sidewalls.

Further, after the wet etching step, the method may continue by annealing the substrate at block 109 to repair the etched surface of the epitaxial layer, and in particular repair the etch damage layer 230.

In some embodiments, the etched surface of the epitaxial layer is subjected to a Rapid Thermal Anneal (RTA) in an annealing atmosphere including, but not limited to, nitrogen or argon at a temperature of 400-600℃, such as 550℃, for a time of 5-20 minutes, such as 15 minutes. As shown in fig. 4I, the annealing process is performed in a nitrogen-containing protective atmosphere, and the etching damage layer 230 on the etching surface is repaired.

Example two

Referring to fig. 10, there is further provided a semiconductor device according to an embodiment of the present invention, wherein the semiconductor device includes a substrate, a semiconductor epitaxial structure including a GaN layer 510 and a barrier layer 520 forming a heterojunction with the GaN layer, and a plurality of electrodes, and wherein the semiconductor epitaxial structure is provided with a feature extending inward from a surface thereof, the feature being preferably formed by the method of etching the III-V compound semiconductor material described in the previous embodiment.

The barrier layer 520 is provided with features formed by the above-described etching method of the III-V compound semiconductor material. As shown in fig. 10, the semiconductor epitaxial structure is an epitaxial structure for manufacturing an enhanced gallium nitride power transistor, and includes, from bottom to top, a substrate 100, a GaN buffer layer, a GaN channel layer, and a barrier layer 520, the barrier layer 520 being provided with an opening 530 extending from the surface thereof to the inside.

In some embodiments, a P-type GaN layer, cap layer, passivation dielectric layer, or other functional layer is further disposed on the barrier layer 520.

In this embodiment, the electrode includes a gate electrode (not shown) disposed in the opening 530. The etched surface obtained by the atomic layer etching process is smooth, has no obvious defects and good uniformity, can exert the advantages of the enhanced HEMT device in terms of power gain and stability, and reduces the current collapse effect and the reliability of the device by reducing the surface damage defects.

By applying the etching method of the III-V compound semiconductor material, the enhanced HEMT device with the thinned barrier layer can be prepared at the gate pin, the advantages of the enhanced HEMT device in terms of power gain and stability can be exerted, and the reliability of the device is affected by reducing the surface damage defect and the current collapse effect.

In summary, according to the etching method of the III-V compound semiconductor material, the epitaxial layer is sequentially exposed to the reactant system containing oxygen ions and chloride ions, and after the surface passivation layer is formed on the epitaxial layer containing the III-V compound semiconductor material, the chloride ions are utilized to remove the surface passivation layer, so that the accurate control of the etching depth and uniformity is realized, and the control precision of the etching process is improved; the atomic layer etching process is circularly carried out for a plurality of times without switching a machine, so that the working procedure steps can be greatly shortened. In addition, after a plurality of cycles of the atomic layer etching process, the flatness of the etched surface can be further improved and the surface damage defect can be reduced through post-treatment and annealing processes on the etched surface.

Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. An etching method of a III-V compound semiconductor material, comprising the steps of:

etching the exposed part of the epitaxial layer through an anisotropic plasma etching process based on the patterned hard mask layer to form a feature extending longitudinally inwards from the exposed surface of the epitaxial layer, removing epitaxial material with a predetermined thickness from the exposed part of the epitaxial layer through a plurality of times of circulating atomic layer etching processes, each atomic layer etching process being performed by alternately performing a passivation step and an etching step;

the etching step is performed by: exposing the surface passivation layer to a second gas mixture containing chloride ions to form a recess inwardly from the exposed surface of the epitaxial layer, wherein each time the etching step is performed to remove the surface passivation layer at the bottom of the recess while retaining the surface passivation layer at the sidewalls of the recess;

and after the step of forming the characteristic through the multiple-cycle atomic layer etching process, carrying out post-treatment on the etched surface of the epitaxial layer through a wet etching process to remove the surface passivation layer and etching byproducts.

2. The etching method according to claim 1, characterized in that: the epitaxial layer comprises a binary compound semiconductor material or a multi-compound semiconductor material composed of at least two elements selected from Al, ga, in, N, P, as.

3. The etching method according to claim 1, further comprising: generating oxygen ions from an oxygen-containing gas by a plasma generator, and generating chlorine ions from a chlorine-containing gas, the oxygen-containing gas comprising N ₂ O、O ₂ 、O ₃ The chlorine-containing gas comprises one of boron trichloride and chlorine.

4. The method of claim 1, wherein the plasma etching process is performed using an inductively coupled plasma generator to etch the exposed portion of the epitaxial layer.

5. The etching method according to claim 4, further comprising: and annealing the substrate in a nitrogen-containing protective atmosphere to repair the etched surface of the epitaxial layer.

6. The etching method according to claim 5, further comprising: after patterning the hard mask layer, etching residues of the hard mask layer are removed through a wet etching process to expose a portion of the epitaxial layer.

7. The etching method according to claim 1, characterized in that: the passivating step includes bombarding the exposed surface of the epitaxial layer with oxygen ions having sufficient energy to maintain formation of the surface passivation layer at a self-limiting level by adjusting a power level of a bias voltage applied to the substrate.

8. The etching method according to claim 7, wherein: after the passivation step, the etching step is performed successively, each time the etching step causes the exposed portion of the epitaxial layer to be removed to a thickness between 0.2nm and 1.5 nm.

9. A semiconductor device comprising a substrate, a semiconductor epitaxial structure and a plurality of electrodes, wherein the semiconductor epitaxial structure comprises a GaN layer and a barrier layer forming a heterojunction with the GaN layer, which are sequentially stacked on the substrate, the semiconductor epitaxial structure being provided with an opening extending inward from the surface of the barrier layer by an etching method of the III-V compound semiconductor material according to any one of claims 1 to 8; the electrode includes a gate electrode disposed in the opening.