CN117436402B - Cross-voltage-domain time sequence path analysis method, device, medium and terminal - Google Patents

Abstract

The present application provides a method, device, medium and terminal for analyzing timing paths across voltage domains, including: forming several voltage domain groups by grouping each physical functional module into different voltage domains; obtaining each timing path between different voltage domain groups based on timing analysis and classifying them to form several timing path categories; obtaining the constraint conditions of each timing path of different categories after voltage changes based on simulation analysis; and optimizing the timing paths between the corresponding different voltage domain groups in the integrated circuit according to the obtained constraint conditions; and judging whether there are violations in the optimized timing paths. The present application can obtain the worst timing path situation in the early stage of physical design implementation, reduce the difficulty of timing convergence in the later stage, and can perform timing analysis more accurately without relying on a complete process library. The convergence results obtained can achieve a smaller area, lower power consumption and higher performance speed for the integrated circuit.

Description

Cross-voltage domain timing path analysis method, device, medium and terminal

Technical Field

The present application relates to the technical field of integrated circuit design, and in particular to a method, device, medium and terminal for analyzing a timing path across voltage domains.

Background Art

According to the design requirements of the integrated circuit chip project, different physical function modules in the integrated circuit may operate in different voltage domains, thereby saving power and achieving better performance. The interaction path of physical function modules in two different voltage domains is the cross-voltage domain path. The voltage fluctuations in different voltage domains are independent of each other. The timing devices of the cross-voltage domain path must not only meet the timing requirements of the same voltage domain, but also meet the timing requirements of the cross-voltage domain. Usually, different voltages will have corresponding process library information. When the process library is complete, timing analysis can be performed through tool configuration. However, at certain voltages, there may be no corresponding information in the process library, resulting in the inability to accurately perform timing analysis. In addition, in the prior art, timing analysis is usually performed based on experience or estimates. The timing may not meet the requirements due to inaccurate experience values, resulting in a large area, high power consumption, and poor performance and speed of the optimized integrated circuit.

Therefore, it is necessary to perform timing analysis through indirect calculation so that timing convergence can be achieved in different environments.

Summary of the invention

In view of the shortcomings of the prior art described above, the purpose of the present application is to provide a timing path analysis method, device, medium and terminal across voltage domains, which are used to solve the problem that the timing analysis in the prior art is inaccurate due to the lack of process library, or the timing analysis is performed after physical implementation based on experience, and timing convergence cannot be achieved, resulting in the optimized integrated circuit having a large area, high power consumption, and poor performance and speed.

To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a timing path analysis method across voltage domains, which is applicable to an integrated circuit, including:

Obtaining the operating voltage of each physical functional module according to the power profile of the integrated circuit;

According to the obtained working voltages of the physical function modules, the physical function modules are grouped into different voltage domains to form a plurality of voltage domain groups;

Acquire each timing path between different voltage domain groups based on timing analysis, and classify each timing path to form a plurality of timing path categories;

Based on simulation analysis, the constraint conditions of each timing path of different categories after voltage changes occur are obtained;

According to the acquired constraint conditions of each timing path of different categories after voltage change occurs, the timing paths between the corresponding different voltage domain groups in the integrated circuit are optimized;

Based on the timing analysis, it is determined whether there is a violation in the optimized timing path; if there is a violation, an engineering change order is executed; if there is no violation, it is determined that the timing path is converged.

In some embodiments of the first aspect of the present application, the method of acquiring each timing path between different voltage domain groups based on timing analysis and classifying each timing path to form a plurality of timing path categories includes a combination of any one or more of the following methods:

Based on the timing analysis, each data timing path between different voltage domain groups is obtained, and each data timing path is classified, wherein the classification result includes a data timing path from a low voltage domain group to a high voltage domain group, and a data timing path from a high voltage domain group to a low voltage domain group;

Based on the timing analysis, each clock timing path between different voltage domain groups is obtained, and each clock timing path is classified, wherein the classification result includes a clock timing path from a low voltage domain group to a high voltage domain group, and a clock timing path from a high voltage domain group to a low voltage domain group;

Based on the timing analysis, each clock source timing path between different voltage domain groups is obtained, and each clock source timing path is classified, and the classification result includes an external clock source timing path and an internal clock source timing path.

In some embodiments of the first aspect of the present application, the method of obtaining the constraint conditions of each timing path of different categories after the voltage change occurs based on the simulation analysis includes:

Calculating the timing paths of different categories using a calculation script to obtain a timing path with the worst voltage change among the timing paths;

The timing margin of the timing path with the worst voltage change is determined, and the constraint conditions of each timing path between different voltage domain groups after the voltage change are obtained based on simulation analysis.

In some embodiments of the first aspect of the present application, the method of optimizing the timing paths between the corresponding different voltage domain groups in the integrated circuit according to the constraints of the timing paths of different categories after the voltage change occurs includes any one or more of the following methods:

According to the acquired constraint conditions of each timing path of different categories after voltage change occurs, adjusting the combinational logic elements on the timing paths between the corresponding different voltage domain groups in the integrated circuit to optimize the timing paths;

According to the acquired constraint conditions of each timing path of different categories after voltage change occurs, the clock tree delay time between the corresponding different voltage domain groups in the integrated circuit is adjusted to optimize the timing paths.

In some embodiments of the first aspect of the present application, after determining whether there is a violation in the optimized timing path based on the timing analysis, the method is further used to perform the following steps:

Simulate each timing path between different voltage domain groups under different voltages to determine whether there is an unconverged timing path under different voltage conditions; if so, execute an engineering change command; if not, determine that the timing path is converged.

In some embodiments of the first aspect of the present application, the power configuration file includes power supply information for supplying power to the voltage domain where each physical functional module is located.

To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a timing path analysis device across voltage domains, including:

A voltage acquisition module, used to obtain the operating voltage of each physical functional module according to the power configuration file of the integrated circuit;

A voltage domain grouping module, used to group each physical function module into different voltage domains to form a plurality of voltage domain groups according to the acquired working voltages of each physical function module;

A timing path classification module, used for acquiring each timing path between different voltage domain groups through timing analysis, and classifying each timing path to form a plurality of timing path categories;

A constraint condition generation module is used to obtain the constraint conditions of each timing path of different categories after voltage changes occur through simulation analysis;

An optimization module, configured to optimize the timing paths between the corresponding different voltage domain groups in the integrated circuit according to the acquired constraint conditions of the timing paths of different categories after the voltage changes;

The judgment module is used to judge whether there is a violation in the optimized timing path through timing analysis; if there is a violation, the engineering change command is executed; if there is no violation, the timing path is determined to be converged.

In some embodiments of the second aspect of the present application, the optimization module is further configured to perform the following steps:

According to the acquired constraint conditions of each timing path of different categories after voltage change occurs, adjusting the combinational logic elements on the timing paths between the corresponding different voltage domain groups in the integrated circuit to optimize the timing paths;

According to the acquired constraint conditions of each timing path of different categories after voltage change occurs, the clock tree delay time between the corresponding different voltage domain groups in the integrated circuit is adjusted to optimize the timing paths.

To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the timing path analysis method across voltage domains as described above is implemented.

To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides an electronic terminal, including: a processor and a memory; the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory, so that the terminal executes the timing path analysis method across voltage domains as described above.

As described above, the timing path analysis method, device, medium and terminal across voltage domains of the present application have the following beneficial effects: by classifying different timing paths in the early stage of integrated circuit physical design implementation, analyzing specific situations, using different constraints for different timing path types, one-to-one correspondence, and using simulation tools for physical implementation, the setup time and hold time can be considered at the same time, and the timing path with the worst voltage change can be obtained, thereby reducing the difficulty of later timing convergence and making the convergence efficiency the highest. The processing of the simulation tool can also take into account area and power consumption, which is easier to improve the performance, power consumption and area of the integrated circuit than the prior art that uses estimated values to execute engineering change commands for optimization. In addition, the present invention does not rely on a complete process library. In the absence of a process library, timing analysis can be performed more accurately, and the convergence results obtained can achieve a smaller area, lower power consumption, and higher performance speed for the integrated circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic flow chart of a method for analyzing a timing path across voltage domains according to an embodiment of the present application.

FIG. 1B is a schematic diagram showing a process of obtaining constraint conditions in an embodiment of the present application.

FIG. 2 is a schematic diagram showing a design of an integrated circuit according to an embodiment of the present application.

FIG. 3 is a schematic diagram showing the structure of a timing path analysis device across voltage domains according to an embodiment of the present application.

FIG. 4 is a schematic diagram showing the structure of an electronic terminal in an embodiment of the present application.

DETAILED DESCRIPTION

The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

It should be noted that in the following description, with reference to the accompanying drawings, several embodiments of the present application are described in the accompanying drawings. It should be understood that other embodiments may also be used, and mechanical composition, structure, electrical and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present application is limited only by the claims of the published patents. The terms used here are only for describing specific embodiments and are not intended to limit the present application. Spatially related terms, such as "upper", "lower", "left", "right", "below", "below", "lower", "above", "upper", etc., may be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.

Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and/or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and/or groups. The terms "or" and "and/or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and/or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.

With the continuous improvement of the process of integrated circuit chip projects, the existing process libraries in integrated circuit chip projects using advanced processes may not be able to meet the requirements. There will often be situations where the process libraries are missing, incomplete, or have errors, and timing analysis cannot be performed accurately, which will lead to inaccurate analysis results, large area of optimized integrated circuits, high power consumption, poor performance and speed, etc. In the existing technology, timing analysis is usually performed based on experience or estimates, and margins are added in the timing analysis stage after physical implementation to meet the timing requirements. In this case, the timing may be too pessimistic, and too many delay units may be used, resulting in increased power consumption and area; it is also possible that the experience value is inaccurate, resulting in the timing not meeting the requirements, and at this time the clock tree has been completed, and adjusting the clock path is likely to cause timing problems in other places, which brings certain challenges to timing convergence.

In order to solve the problems in the prior art of inaccurate timing analysis caused by the lack of process library, or the inability to achieve timing convergence when performing timing analysis after physical implementation based on experience, resulting in large area, high power consumption, and poor performance and speed of the optimized integrated circuit, the present invention provides a timing path analysis method, device, medium and terminal across voltage domains, which are intended to classify different timing paths in the early stage of integrated circuit physical design implementation, analyze specific situations specifically, use different constraints for different timing path types, and correspond one to one, thereby reducing the difficulty of later timing convergence; in addition, it is possible to perform timing analysis more accurately without relying on a complete process library in the absence of a process library, and the convergence results obtained can achieve a smaller area, lower power consumption, and higher performance and speed of the integrated circuit.

Before further describing the present invention in detail, the nouns and terms involved in the embodiments of the present invention are explained. The nouns and terms involved in the embodiments of the present invention are applicable to the following interpretations:

<1> Timing closure: It is the process of adjusting and modifying the design during the design of integrated circuits such as field programmable gate arrays and application-specific integrated circuits so that the designed circuit meets the timing requirements.

<2>Hold time: refers to the time during which the data remains stable after the rising edge of the trigger's clock signal arrives.

At the same time, in order to make the purpose, technical solution and advantages of the present invention more clear, the technical solution in the embodiment of the present invention is further described in detail through the following embodiments and in combination with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention and are not used to limit the invention.

As shown in FIG1A , a schematic diagram of a flow chart of a method for analyzing a timing path across voltage domains in an embodiment of the present invention is shown. The method is applicable to integrated circuits and mainly includes the following steps:

S101: Obtaining the operating voltage of each physical functional module according to a power configuration file of the integrated circuit.

In this embodiment, the power profile includes power supply information for the voltage domain where each physical function module is located. Multi-voltage design technology is usually used in integrated circuits. Multi-voltage design technology is an effective low-power technology. Multi-voltage design technology uses power supplies with different voltage values for different physical function modules according to needs to achieve the purpose of balancing power consumption and performance, and realize the best performance-power consumption ratio of integrated circuits.

S102: According to the acquired operating voltages of the physical function modules, the physical function modules are grouped into different voltage domains to form a plurality of voltage domain groups.

In this embodiment, based on the obtained working voltage of each physical function module, each physical function module is grouped into different voltage domains to form a plurality of voltage domain groups. The working voltages of each physical function module in the same voltage domain group are the same, and the working voltages of each physical function module in different voltage domain groups are different.

In this embodiment, the commonly used operating voltages of the physical functional modules in the integrated circuit include, but are not limited to: one or a combination of 1.8V, 2.5V, 3.3V, and 5V.

In this embodiment, each physical function module on the integrated circuit performs different functions, including but not limited to: a storage physical function module, a data acquisition physical function module, a communication physical function module, and a digital signal processing physical function module, one or more combinations thereof.

S103: Acquire each timing path between different voltage domain groups based on timing analysis, and classify each timing path to form a plurality of timing path categories.

In this embodiment, the method of acquiring each timing path between each physical function module in different voltage domain groups based on timing analysis and classifying each timing path to form a plurality of timing path categories includes a combination of any one or more of the following methods:

(1) Based on the timing analysis, each data timing path between different voltage domain groups is obtained, and each data timing path is classified, wherein the classification results include a data timing path from a low voltage domain group to a high voltage domain group, and a data timing path from a high voltage domain group to a low voltage domain group.

(2) Based on the timing analysis, each clock timing path between different voltage domain groups is obtained, and each clock timing path is classified, wherein the classification results include a clock timing path from a low voltage domain group to a high voltage domain group, and a clock timing path from a high voltage domain group to a low voltage domain group.

(3) Based on the timing analysis, each clock source timing path between different voltage domain groups is obtained, and each clock source timing path is classified, wherein the classification results include an external clock source timing path and an internal clock source timing path.

S104: Obtain constraint conditions of timing paths of different categories after voltage changes occur based on simulation analysis.

In this embodiment, the working voltages of physical function modules in different voltage domain groups are different. Some physical function modules need to dynamically adjust their voltages according to the workload. After the voltage changes, the length of the corresponding timing path will change accordingly, which may result in a violation, causing the corresponding timing path to not converge. Based on this, simulation analysis is used to obtain the corresponding changes in the delay time of the input port and output port of each timing path of different categories after the voltage changes, and this change is converted into a corresponding constraint condition to achieve the purpose of timing convergence.

In this embodiment, as shown in FIG1B , a flow chart of obtaining constraint conditions in an embodiment of the present invention is shown. The method of obtaining constraint conditions of different categories of timing paths after voltage changes based on simulation analysis includes:

S1041: Calculate the timing paths of different categories using a calculation script to obtain a timing path with the worst voltage change among the timing paths.

S1042: Determine the timing margin of the timing path with the worst voltage change, and obtain the constraint conditions of each timing path between different voltage domain groups after the voltage changes based on simulation analysis.

In this embodiment, the constraint condition includes: after a voltage change occurs in a corresponding physical function module of each timing path between different voltage domain groups, a delay time of a corresponding input port and an output port changes accordingly.

Furthermore, in this embodiment, according to the corresponding changes in the delay time of the corresponding input port and output port, the integrated circuit is physically designed to converge the corresponding timing paths.

It is worth noting that in the prior art, timing convergence is performed based on experience or estimation after physical implementation. In order to achieve the convergence goal, the estimated value will add some extra margins, causing the timing to be too pessimistic and using too many delay units, which increases the power consumption and area of the integrated circuit. It is also possible that the timing cannot meet the requirements due to inaccurate experience values. Moreover, the clock tree has been completed at this time, and adjusting the clock path is likely to cause timing problems in other places, which brings certain challenges to timing convergence. However, the present invention can obtain the constraints of various timing paths of different categories after voltage changes in the early stage of integrated circuit physical design implementation, and use different constraints for different timing path types, which reduces the difficulty of later timing convergence and makes the convergence efficiency higher.

S105: Optimizing the timing paths between the corresponding different voltage domain groups in the integrated circuit according to the acquired constraint conditions of the timing paths of different categories after the voltage change occurs.

In this embodiment, after the voltage of each timing path of different categories changes, the length of the corresponding timing path will also change. Based on the simulation analysis, the constraint conditions after the voltage change are obtained to optimize the timing paths between the corresponding different voltage domain groups in the integrated circuit. The optimization method includes any one or more of the following methods:

(1) According to the acquired constraint conditions of each timing path of different categories after voltage change occurs, the combinational logic elements on the timing paths between the corresponding different voltage domain groups in the integrated circuit are adjusted to optimize the timing paths.

(2) According to the constraints of the timing paths of different categories obtained after the voltage change occurs, the clock tree delay time between the corresponding different voltage domain groups in the integrated circuit is adjusted to optimize the timing paths.

In this embodiment, as shown in FIG2 , a design schematic diagram of an integrated circuit in an embodiment of the present invention is shown. Physical function module A, physical function module B, physical function module C, physical function module D, physical function module E, and physical function module F are designed in the integrated circuit, and the physical function modules A, B, C, D, E, and F are respectively located in different voltage domain groups X, Y, Z, W, U, and T. The design schematic diagram shown in FIG2 is only one embodiment of the present invention, which is mainly used for explanation and description, rather than for limiting the scope of protection of the present invention. In actual application, the design schematic diagrams of different integrated circuits vary in form. Below, the principle of optimizing the timing paths between different voltage domain groups is exemplarily explained in conjunction with FIG2 .

In this embodiment, as shown in FIG. 2 , there is a data timing path between physical function module A and physical function module B, and the data timing path between physical function module A and physical function module B needs to meet the retention time requirement. For the receiving point, the new data cannot come too early to ensure that the data to be transmitted is maintained for a period of time. The data timing path is from physical function module A to B, and physical function module A has two working voltages V1 and V2 (V2>V1), and physical function module B has one working voltage V3. The delay of the same data timing path under different voltages is different. The higher the voltage, the smaller the delay of the timing device and the routing, the faster the working rate, and the shorter the timing path. Since this data timing path is transmitted from physical function module A to physical function module B, if the working voltage of physical function module A changes from V1 to V2, assuming that the holding time just does not violate the working voltage of physical function module A at V1, and after the voltage of physical function module A is increased to V2, the timing path in physical function module A will become shorter, and a violation may occur. At this time, it is necessary to adjust the constraints of the data timing path from physical function module A to physical function module B, and set the delay unit in physical function module B as much as possible. For example, by adjusting the combinational logic elements on the data timing path from physical function module A to physical function module B, or adjusting the clock tree delay time on the data timing path from physical function module A to physical function module B, the negative impact of voltage changes in physical function module A can be reduced.

In this embodiment, as shown in FIG2 , physical function module C and physical function module D also have data timing paths that need to meet the hold time requirement. The data timing path is from physical function module C to D, physical function module C has a working voltage V4, and physical function module D has two working voltages V5 and V6 (V6>V5). When the voltage in physical function module D increases from V5 to V6, the timing path delay in physical function module D becomes shorter. At this time, it is necessary to adjust the constraint conditions of the data timing path from physical function module C to physical function module D, and try to set the delay unit in physical function module C. For example, by adjusting the combinational logic elements on the data timing path from physical function module C to physical function module D, or adjusting the clock tree delay time on the data timing path from physical function module C to physical function module D, the negative impact of the voltage change in physical function module D can be reduced.

In this embodiment, as shown in FIG2 , physical function module E and physical function module F both have data timing paths and clock timing paths that need to meet the hold time. The data timing path is from physical function module E to F, physical function module E has two working voltages V7 and V8 (V8>V7), physical function module F has one working voltage V9, and the clock timing path is sent to physical function module F through physical function module E. When the voltage in physical function module E increases from V7 to V8, the data timing path and clock timing path in physical function module E will become shorter, so for physical function module F, its clock timing path will also be affected. At this time, it is necessary to compare the length of the clock timing path sent from physical function module E to the physical function module and the length of the clock timing path in physical function module E to determine whether the change in the clock timing path will have a negative impact on the hold time, so as to control the data timing path and clock timing path from physical function module E to physical function module F across the voltage domain to be respectively lengthened or shortened in the corresponding physical function module, so as to optimize the timing path from physical function module E to F.

S106: Determine whether there is any violation in the optimized timing path based on timing analysis.

S107: If there is a violation, execute the engineering change order.

S108: If there is no violation, determine that the timing path is converged.

In this embodiment, it is determined based on timing analysis whether there are violations in the optimized timing path. If there are violations, an electronic design automation tool is used to make an engineering change command for the violating part so that there are no violations at the convergence target. If there are no violations, it is determined that the optimized timing path is converged and can meet the hold time requirement.

In this embodiment, the engineering change command includes but is not limited to: increasing or decreasing the number of combinational logic elements on the corresponding timing path, changing the type of combinational logic elements on the corresponding timing path, and adjusting the delay time of the clock tree on the timing path, one or more combinations thereof.

It is worth noting that the present invention classifies different timing paths in the early stage of integrated circuit physical design implementation, analyzes specific situations, uses different constraints for different timing path types, and corresponds one to one. When using simulation tools for physical implementation, it can obtain the timing path with the worst voltage change, thereby reducing the difficulty of later timing convergence and making the convergence efficiency the highest. The processing of the simulation tool can also take area and power consumption into consideration, which is easier to improve the performance, power consumption and area of the integrated circuit than the prior art that uses estimated values to execute engineering change commands for optimization. In addition, the present invention does not rely on a complete process library. In the absence of a process library, the timing analysis can be performed more accurately, and the convergence results obtained can achieve a smaller area, lower power consumption, and higher performance speed for the integrated circuit.

In this embodiment, after determining whether there is a violation in the optimized timing path based on the timing analysis, the method can also be used to perform the following steps:

Simulate each timing path between different voltage domain groups under different voltages to determine whether there is an unconverged timing path under different voltage conditions; if so, execute an engineering change command; if not, determine that the timing path is converged.

In this embodiment, a simulation tool is used on the basis of the present invention to simulate the timing path across voltage domains, which simulates the voltage change situation, and uses the simulation results to determine whether there will be violations after the voltage change. If there are still violations, these violations can be processed by executing engineering change commands. If there are no violations, it is determined that the optimized timing path is converged, and this simulation step is equivalent to an additional convergence verification. Furthermore, each timing path between different voltage domain groups is simulated under different voltages to determine whether the timing paths are finally converged under different voltage conditions. If there are still timing paths that have not converged, they can be processed by executing engineering change commands to make the corresponding timing paths converge.

As shown in FIG3 , a schematic diagram of the structure of a timing path analysis device across voltage domains according to an embodiment of the present invention is shown. The device 300 includes:

The voltage acquisition module 301 is used to acquire the operating voltage of each physical functional module according to the power configuration file of the integrated circuit.

The voltage domain grouping module 302 is used to group the physical function modules into different voltage domains to form a plurality of voltage domain groups according to the acquired operating voltages of the physical function modules.

The timing path classification module 303 is used to obtain each timing path between different voltage domain groups through timing analysis, and classify each timing path to form a plurality of timing path categories.

The constraint condition generating module 304 is used to obtain the constraint conditions of each timing path of different categories after the voltage changes through simulation analysis.

The optimization module 305 is used to optimize the timing paths between the corresponding different voltage domain groups in the integrated circuit according to the acquired constraint conditions of the timing paths of different categories after the voltage change occurs.

The judgment module 306 is used to judge whether there is a violation in the optimized timing path through timing analysis; if there is a violation, execute the engineering change order; if there is no violation, determine that the timing path is converged.

In this embodiment, the timing path classification module 303 is further configured to perform any of the following steps:

(1) acquiring data timing paths between different voltage domain groups based on timing analysis, and classifying the data timing paths, wherein the classification results include data timing paths from a low voltage domain group to a high voltage domain group, and data timing paths from a high voltage domain group to a low voltage domain group;

(2) acquiring clock timing paths between different voltage domain groups based on timing analysis, and classifying the clock timing paths, wherein the classification results include clock timing paths from the low voltage domain group to the high voltage domain group, and clock timing paths from the high voltage domain group to the low voltage domain group;

(3) Based on the timing analysis, each clock source timing path between different voltage domain groups is obtained, and each clock source timing path is classified, wherein the classification results include an external clock source timing path and an internal clock source timing path.

In this embodiment, the constraint condition generating module 304 is further configured to perform the following steps:

Calculating the timing paths of different categories using a calculation script to obtain a timing path with the worst voltage change among the timing paths;

The timing margin of the timing path with the worst voltage change is determined, and the constraint conditions of each timing path between different voltage domain groups after the voltage change are obtained based on simulation analysis.

In this embodiment, the optimization module 305 is further configured to perform the following steps:

According to the acquired constraint conditions of each timing path of different categories after voltage change occurs, adjusting the combinational logic elements on the timing paths between the corresponding different voltage domain groups in the integrated circuit to optimize the timing paths;

According to the acquired constraint conditions of each timing path of different categories after voltage change occurs, the clock tree delay time between the corresponding different voltage domain groups in the integrated circuit is adjusted to optimize the timing paths.

In one embodiment of the present application, the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the above-mentioned timing path analysis method across voltage domains when executed by a processor.

Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to the computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk, etc., various media that can store program codes.

In the embodiments provided in the present application, the computer readable and writable storage medium may include a read-only memory, a random access memory, an EEPROM, a CD-ROM or other optical disk storage device, a disk storage device or other magnetic storage device, a flash memory, a USB flash drive, a mobile hard disk, or any other medium that can be used to store a desired program code in the form of an instruction or data structure and can be accessed by a computer. In addition, any connection can be appropriately referred to as a computer-readable medium. For example, if the instruction is sent from a website, a server or other remote source using a coaxial cable, an optical fiber cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, the coaxial cable, optical fiber cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. However, it should be understood that computer readable and writable storage media and data storage media do not include connections, carriers, signals, or other temporary media, but are intended to be non-temporary, tangible storage media. Disk and disc, as used in this application, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

As shown in Figure 4, it is a schematic diagram of the structure of an electronic terminal in one embodiment of the present application. The electronic terminal 400 provided in this example includes: a processor 401 and a memory 402; the memory 402 is connected to the processor 401 through a system bus and completes communication with each other, the memory 402 is used to store computer programs, and the processor 401 is used to run the computer programs stored in the memory 402, so that the electronic terminal 400 executes the timing path analysis method across voltage domains as described above.

The timing path analysis method across voltage domains provided in the embodiment of the present invention can be implemented on the terminal side or the server side. As for the hardware structure of the electronic terminal, please refer to FIG. 4, which is an optional hardware structure diagram of the electronic terminal 400 provided in the embodiment of the present invention. The terminal 400 can be a mobile phone, a computer device, a tablet device, a personal digital processing device, a factory background processing device, etc. The electronic terminal 400 includes: at least one processor 401, a memory 402, at least one network interface 404 and a user interface 406. The various components in the device are coupled together through a bus system 405. It can be understood that the bus system 405 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 405 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, various buses are marked as bus systems in FIG. 4.

The user interface 406 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

It is understood that the memory 402 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable categories of memory.

The memory 402 in the embodiment of the present invention is used to store various categories of data to support the operation of the electronic terminal 400. Examples of these data include: any executable program for operating on the electronic terminal 400, such as an operating system 4021 and an application 4022; the operating system 4021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 4022 may include various applications, such as a media player (MediaPlayer), a browser (Browser), etc., for implementing various application services. The timing path analysis method across voltage domains provided in the embodiment of the present invention may be included in the application 4022.

The method disclosed in the above embodiment of the present invention can be applied to the processor 401, or implemented by the processor 401. The processor 401 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 401 or the instruction in the form of software. The above processor 401 may be a general processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 401 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The general processor 401 can be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

In an exemplary embodiment, the electronic terminal 400 may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD) to execute the aforementioned method.

In summary, the timing path analysis method, device, medium and terminal across voltage domains provided by the present application form several voltage domain groups by grouping each physical function module into different voltage domains; based on timing analysis, each timing path between different voltage domain groups is obtained and classified to form several timing path categories; based on simulation analysis, the constraints of each timing path of different categories after voltage changes occur are obtained; and the timing paths between the corresponding different voltage domain groups in the integrated circuit are optimized according to the obtained constraints; and whether there are violations in the optimized timing paths. The present application can obtain the timing path with the worst voltage change in the early stage of physical design implementation, thereby reducing the difficulty of timing convergence in the later stage and making the convergence efficiency the highest; in addition, the present application can be independent of a complete process library. In the absence of a process library, the timing analysis can be performed more accurately, and the convergence results obtained can achieve a smaller area, lower power consumption, and higher performance speed of the integrated circuit. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims (8)

1. A timing path analysis method across voltage domains, applicable to integrated circuits, comprising: Obtaining the operating voltage of each physical functional module according to the power profile of the integrated circuit; According to the obtained working voltages of the physical function modules, the physical function modules are grouped into different voltage domains to form a plurality of voltage domain groups; Based on the timing analysis, each timing path between different voltage domain groups is obtained, and each timing path is classified to form a plurality of timing path categories; including the following methods: Based on the timing analysis, each clock timing path between different voltage domain groups is obtained, and each clock timing path is classified, wherein the classification result includes a clock timing path from a low voltage domain group to a high voltage domain group, and a clock timing path from a high voltage domain group to a low voltage domain group; Based on simulation analysis, the constraints of different types of timing paths after voltage changes occur are obtained, including the following: Calculating the timing paths of different categories using a calculation script to obtain a timing path with the worst voltage change among the timing paths; Determine the timing margin of the timing path with the worst voltage change, and obtain the constraint conditions of each timing path between different voltage domain groups after the voltage changes based on simulation analysis; According to the constraints of the obtained timing paths of different categories after the voltage change occurs, the timing paths between the corresponding different voltage domain groups in the integrated circuit are optimized; including the following methods: According to the acquired constraint conditions of each timing path of different categories after voltage change occurs, adjusting the combinational logic elements on the timing paths between the corresponding different voltage domain groups in the integrated circuit to optimize the timing paths; Based on the timing analysis, it is determined whether there is a violation in the optimized timing path; if there is a violation, an engineering change order is executed; if there is no violation, it is determined that the timing path is converged. 2. The method for analyzing timing paths across voltage domains according to claim 1, wherein the method of acquiring each timing path between different voltage domain groups based on timing analysis and classifying each timing path to form a plurality of timing path categories further comprises a combination of any one or more of the following methods: Based on the timing analysis, each data timing path between different voltage domain groups is obtained, and each data timing path is classified, wherein the classification result includes a data timing path from a low voltage domain group to a high voltage domain group, and a data timing path from a high voltage domain group to a low voltage domain group; Based on the timing analysis, each clock source timing path between different voltage domain groups is obtained, and each clock source timing path is classified, and the classification result includes an external clock source timing path and an internal clock source timing path. 3. The method for analyzing timing paths across voltage domains according to claim 1, wherein the method for optimizing the timing paths between the corresponding different voltage domain groups in the integrated circuit according to the constraints of the timing paths of different categories after the voltage change occurs further comprises the following method: According to the acquired constraint conditions of each timing path of different categories after voltage change occurs, the clock tree delay time between the corresponding different voltage domain groups in the integrated circuit is adjusted to optimize the timing paths. 4. The method for analyzing a timing path across voltage domains according to claim 1, wherein the power configuration file includes power supply information for supplying power to the voltage domain where each physical functional module is located. 5. A timing path analysis device across voltage domains, comprising: A voltage acquisition module, used to obtain the operating voltage of each physical functional module according to the power configuration file of the integrated circuit; A voltage domain grouping module, used to group each physical function module into different voltage domains to form a plurality of voltage domain groups according to the acquired working voltages of each physical function module; The timing path classification module is used to obtain each timing path between different voltage domain groups through timing analysis, and classify each timing path to form a plurality of timing path categories; including the following methods: Based on the timing analysis, each clock timing path between different voltage domain groups is obtained, and each clock timing path is classified, wherein the classification result includes a clock timing path from a low voltage domain group to a high voltage domain group, and a clock timing path from a high voltage domain group to a low voltage domain group; The constraint condition generation module is used to obtain the constraint conditions of each timing path of different categories after voltage changes through simulation analysis; including the following: Calculating the timing paths of different categories using a calculation script to obtain a timing path with the worst voltage change among the timing paths; Determine the timing margin of the timing path with the worst voltage change, and obtain the constraint conditions of each timing path between different voltage domain groups after the voltage changes based on simulation analysis; The optimization module is used to optimize the timing paths between the corresponding different voltage domain groups in the integrated circuit according to the constraints of the timing paths of different categories after the voltage change occurs; including the following methods: According to the acquired constraint conditions of each timing path of different categories after voltage change occurs, adjusting the combinational logic elements on the timing paths between the corresponding different voltage domain groups in the integrated circuit to optimize the timing paths; The judgment module is used to judge whether there is a violation in the optimized timing path through timing analysis; if there is a violation, the engineering change command is executed; if there is no violation, the timing path is determined to be converged. 6. The device for analyzing timing paths across voltage domains according to claim 5, wherein the optimization module is further configured to perform the following steps: According to the acquired constraint conditions of each timing path of different categories after voltage change occurs, the clock tree delay time between the corresponding different voltage domain groups in the integrated circuit is adjusted to optimize the timing paths. 7. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the method for analyzing a timing path across voltage domains according to any one of claims 1 to 4 is implemented. 8. An electronic terminal, comprising: a processor and a memory; The memory is used to store computer programs; The processor is used to execute the computer program stored in the memory, so that the terminal performs the cross-voltage domain timing path analysis method according to any one of claims 1 to 4.