CN117436402B - Cross-voltage-domain time sequence path analysis method, device, medium and terminal - Google Patents
Cross-voltage-domain time sequence path analysis method, device, medium and terminal Download PDFInfo
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Abstract
The application provides a method, a device, a medium and a terminal for analyzing a time sequence path crossing a voltage domain, which comprise the following steps: forming a plurality of voltage domain groups by grouping different voltage domains for each physical function module; acquiring each time sequence path between different voltage domain groups based on time sequence analysis and classifying to form a plurality of time sequence path categories; acquiring constraint conditions of each time sequence path of different categories after voltage change based on simulation analysis; optimizing time sequence paths among corresponding different voltage domain groups in the integrated circuit according to the obtained constraint conditions; and judging whether the optimized time sequence path has violations or not. The application can realize the worst time sequence path condition in the initial stage of physical design, reduce the difficulty of the later time sequence convergence, and can accurately perform the time sequence analysis without depending on a complete process library, and the obtained convergence result can realize smaller area, lower power consumption and higher performance speed of the integrated circuit.
Description
Technical Field
The present application relates to the field of integrated circuit design technologies, and in particular, to a method, an apparatus, a medium, and a terminal for analyzing a timing path across a voltage domain.
Background
According to the design requirement of the integrated circuit chip project, different physical function modules in the integrated circuit can work under different voltage domains, thereby achieving the purposes of saving power consumption and having better performance. The interaction path of the physical function modules under two different voltage domains is a cross-voltage domain path. The voltage fluctuation in different voltage domains is mutually independent, and the time sequence device of the cross-voltage domain path is required to meet the time sequence requirement of the same voltage domain and the time sequence requirement of the cross-voltage domain. Typically, different voltages will have corresponding process library information. In the case of a complete process library, the timing analysis may be performed by tool configuration. However, at some voltages, there may be no corresponding information in the process library, resulting in an inaccurate timing analysis. In addition, in the prior art, the time sequence analysis is usually performed according to experience or estimated conditions, and the time sequence can not meet the requirements possibly caused by inaccurate experience values, so that the optimized integrated circuit has large area, high power consumption and poor performance speed.
Therefore, timing analysis is needed by indirect calculation, so that timing convergence can be realized in different environments.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present application is directed to providing a method, an apparatus, a medium, and a terminal for analyzing a timing path across a voltage domain, so as to solve the problems of inaccurate timing analysis caused by a missing process library in the prior art, or failure to implement timing convergence due to performing timing analysis after physical implementation according to experience, resulting in large area, high power consumption, and poor performance of an optimized integrated circuit.
To achieve the above and other related objects, a first aspect of the present application provides a method for analyzing a timing path across a voltage domain, which is applicable to an integrated circuit, and includes:
acquiring the working voltage of each physical function module according to the power supply configuration file of the integrated circuit;
according to the obtained working voltage of each physical function module, different voltage domains are grouped for each physical function module to form a plurality of voltage domain groups;
acquiring each time sequence path between different voltage domain groups based on time sequence analysis, and classifying each time sequence path to form a plurality of time sequence path categories;
acquiring constraint conditions of each time sequence path of different categories after voltage change based on simulation analysis;
optimizing the time sequence paths among corresponding different voltage domain groups in the integrated circuit according to the constraint conditions of each time sequence path after the voltage change;
Judging whether the optimized time sequence path has violations or not based on time sequence analysis; if the violation exists, executing the engineering change command; and if no violation exists, determining that the timing sequence path converges.
In some embodiments of the first aspect of the present application, the manner of obtaining each timing path between different voltage domain groups based on the timing analysis and classifying each timing path to form a plurality of timing path categories includes any one or more of the following combinations:
Acquiring each data time sequence path between different voltage domain groups based on time sequence analysis, and classifying each data time sequence path, wherein the classification result comprises the data time sequence paths from the low voltage domain group to the high voltage domain group and the data time sequence paths from the high voltage domain group to the low voltage domain group;
acquiring each clock time sequence path between different voltage domain groups based on time sequence analysis, and classifying each clock time sequence path, wherein the classification result comprises the clock time sequence paths from the low voltage domain group to the high voltage domain group and the clock time sequence paths from the high voltage domain group to the low voltage domain group;
Each clock source time sequence path between different voltage domain groups is obtained based on time sequence analysis, and the clock source time sequence paths are classified, wherein the classification result comprises an external clock source time sequence path and an internal clock source time sequence path.
In some embodiments of the first aspect of the present application, the method for obtaining constraints of each timing path of different classes after the voltage change based on the simulation analysis includes:
Calculating each time sequence path of different categories by using a calculation script to obtain a time sequence path with worst voltage variation in each time sequence path;
and determining the time sequence margin of the time sequence path with the worst voltage change, and acquiring constraint conditions of each time sequence path among different voltage domain groups after the voltage change based on simulation analysis.
In some embodiments of the first aspect of the present application, the manner of optimizing the timing paths between the corresponding different voltage domain groups in the integrated circuit according to the constraint condition of each acquired timing path of the different classes after the voltage change includes any one or a combination of multiple manners as follows:
according to the constraint conditions of each acquired time sequence path with different types after voltage change, adjusting the combinational logic elements on the time sequence paths among the corresponding different voltage domain groups in the integrated circuit so as to optimize each time sequence path;
And adjusting clock tree delay time among corresponding different voltage domain groups in the integrated circuit according to the obtained constraint conditions of each time sequence path after the voltage change so as to optimize each time sequence path.
In some embodiments of the first aspect of the present application, after determining whether there is a violation of the optimized timing path based on the timing analysis, the method is further configured to perform the steps of:
Simulating each time sequence path among different voltage domain groups under different voltages to judge whether an unconverged time sequence path exists under different voltage conditions; if so, executing the engineering change command; and if not, determining that the timing sequence path converges.
In some embodiments of the first aspect of the present application, the power configuration file includes power information for powering a voltage domain in which each of the physical function modules is located.
To achieve the above and other related objects, a second aspect of the present application provides a timing path analysis device across voltage domains, comprising:
The voltage acquisition module is used for acquiring the working voltage of each physical function module according to the power supply configuration file of the integrated circuit;
The voltage domain grouping module is used for grouping different voltage domains of each physical function module according to the acquired working voltage of each physical function module to form a plurality of voltage domain groups;
the time sequence path classification module is used for acquiring each time sequence path between different voltage domain groups through time sequence analysis and classifying each time sequence path to form a plurality of time sequence path categories;
the constraint condition generation module is used for acquiring constraint conditions of various time sequence paths of different categories after voltage change occurs through simulation analysis;
The optimization module is used for optimizing the time sequence paths among the corresponding different voltage domain groups in the integrated circuit according to the constraint conditions of the acquired time sequence paths with different types after the voltage changes;
the judging module is used for judging whether the optimized time sequence path has violations or not through time sequence analysis; if the violation exists, executing the engineering change command; and if no violation exists, determining that the timing sequence path converges.
In some embodiments of the second aspect of the present application, the optimization module is further configured to perform the following steps:
according to the constraint conditions of each acquired time sequence path with different types after voltage change, adjusting the combinational logic elements on the time sequence paths among the corresponding different voltage domain groups in the integrated circuit so as to optimize each time sequence path;
And adjusting clock tree delay time among corresponding different voltage domain groups in the integrated circuit according to the obtained constraint conditions of each time sequence path after the voltage change so as to optimize each time sequence path.
To achieve the above and other related objects, a third aspect of the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method for analyzing a timing path across voltage domains as described above.
To achieve the above and other related objects, a fourth aspect of the present application provides an electronic terminal, comprising: a processor and a memory; the memory is used for storing a computer program; the processor is configured to execute the computer program stored in the memory, so that the terminal performs the method for analyzing a time sequence path crossing voltage domains as described above.
As described above, the method, the device, the medium and the terminal for analyzing the time sequence path crossing the voltage domain have the following beneficial effects: by classifying different timing paths in the initial stage of the physical design implementation of the integrated circuit, specifically analyzing the specific situation, using different constraints for different timing path types, and in one-to-one correspondence, when the physical implementation is carried out by means of the simulation tool, the situation of the timing path with the worst voltage variation can be obtained by considering the setup time and the hold time at the same time, so that the difficulty of later timing convergence is reduced, the convergence efficiency is highest, the area and the power consumption can be considered in the processing of the simulation tool, and compared with the prior art, the performance, the power consumption and the area of the integrated circuit are easier to be improved by executing engineering change commands by using the estimated values for optimization. In addition, the application can accurately perform time sequence analysis without depending on a complete process library, and the obtained convergence result can realize smaller area, lower power consumption and higher performance speed of the integrated circuit under the condition of lacking the process library.
Drawings
FIG. 1A is a flow chart illustrating a method of analyzing a timing path across a voltage domain according to an embodiment of the application.
FIG. 1B is a flow chart illustrating the acquisition of constraints according to an embodiment of the application.
Fig. 2 is a schematic diagram of an integrated circuit according to an embodiment of the application.
Fig. 3 is a schematic structural diagram of a timing path analysis device crossing voltage domains according to an embodiment of the application.
Fig. 4 is a schematic structural diagram of an electronic terminal according to an embodiment of the application.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
In the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the application. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "upper," and the like, may be used herein to facilitate a description of one element or feature as illustrated in the figures as being related to another element or feature.
Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, operations, elements, components, items, categories, and/or groups. The terms "or" and/or "as used herein are to be construed as inclusive, or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; A. b and C). An exception to this definition will occur only when a combination of elements, functions or operations are in some way inherently mutually exclusive.
Along with the continuous improvement of integrated circuit chip project technology, the existing process libraries in the integrated circuit chip project using advanced technology can not always be met, the conditions of missing, imperfect and error of the process libraries can often occur, time sequence analysis can not be carried out more accurately, and inaccurate analysis results, large area of the optimized integrated circuit, high power consumption, poor performance speed and the like can be caused. In the prior art, the time sequence analysis is usually carried out according to experience or estimated conditions, and margin is added in a time sequence analysis stage after physical realization, so that the time sequence analysis stage meets the time sequence requirement, the time sequence can be too pessimistic under the condition, and excessive delay units are used, so that the power consumption and the area are increased; the empirical value is inaccurate, so that the time sequence cannot meet the requirement, and the clock tree is completed at the moment, the clock paths are adjusted, the time sequence problem in other places is easy to bring, and a certain challenge is brought to the convergence of the time sequence.
In order to solve the problems that in the prior art, the timing analysis is inaccurate due to the lack of a process library, or the timing analysis is carried out after physical implementation according to experience, so that the timing convergence cannot be realized, and the optimized integrated circuit is large in area, high in power consumption and poor in performance speed, the invention provides a method, a device, a medium and a terminal for analyzing a timing path crossing a voltage domain, which aim to classify different timing paths in the early stage of the physical design of the integrated circuit, specifically analyze the specific situation, use different constraints according to different timing path types, and realize one-to-one correspondence, so that the difficulty of the timing convergence in the later stage is reduced; in addition, the time sequence analysis can be accurately carried out without depending on a complete process library under the condition of lacking the process library, and the obtained convergence result can realize smaller area, lower power consumption and higher performance speed of the integrated circuit.
Before explaining the present invention in further detail, terms and terminology involved in the embodiments of the present invention will be explained, and the terms and terminology involved in the embodiments of the present invention are applicable to the following explanation:
<1> Timing closure (Timing closure): the method is a process of adjusting and modifying design in the design process of integrated circuits such as field programmable gate arrays, application specific integrated circuits and the like, so that the designed circuit meets the time sequence requirement.
<2> Holding time: refers to the time that the data is stable after the rising edge of the clock signal of the flip-flop arrives.
Meanwhile, in order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be further described in detail by the following examples with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Fig. 1A shows a flow chart of a method for analyzing a time sequence path crossing a voltage domain in an embodiment of the invention. The method is suitable for an integrated circuit and mainly comprises the following steps:
s101: and acquiring the working voltage of each physical function module according to the power supply configuration file of the integrated circuit.
In this embodiment, the power configuration file includes power information for powering the voltage domain in which each of the physical function modules is located. In an integrated circuit, a multi-voltage design technology is generally adopted, and is an effective low-power consumption technology, and the multi-voltage design technology uses power supplies with different voltage values for different physical function modules according to requirements so as to achieve the purpose of balancing power consumption and performance and realize the optimal performance and power consumption ratio of the integrated circuit.
S102: and according to the acquired working voltage of each physical function module, grouping different voltage domains of each physical function module to form a plurality of voltage domain groups.
In this embodiment, according to the obtained working voltages of the physical function modules, different voltage domains are grouped for each physical function module to form a plurality of voltage domain groups, the working voltages of the physical function modules located in the same voltage domain group are the same, and the working voltages of the physical function modules located in different voltage domain groups are different.
In this embodiment, the operating voltages commonly used for each physical function module in the integrated circuit include, but are not limited to: 1.8V, 2.5V, 3.3V, 5V.
In this embodiment, each physical functional module on the integrated circuit performs a different function, including but not limited to: one or more of a storage physical function module, a data acquisition physical function module, a communication physical function module and a digital signal processing physical function module.
S103: each time sequence path between different voltage domain groups is acquired based on time sequence analysis, and the time sequence paths are classified to form a plurality of time sequence path categories.
In this embodiment, the manner of acquiring each timing path between each physical function module located in different voltage domain groups based on the timing analysis and classifying each timing path to form several timing path categories includes any one or a combination of several manners:
(1) And acquiring each data time sequence path between different voltage domain groups based on time sequence analysis, and classifying each data time sequence path, wherein the classification result comprises the data time sequence paths from the low voltage domain group to the high voltage domain group and the data time sequence paths from the high voltage domain group to the low voltage domain group.
(2) And acquiring each clock time sequence path between different voltage domain groups based on time sequence analysis, and classifying each clock time sequence path, wherein the classification result comprises the clock time sequence paths from the low voltage domain group to the high voltage domain group and the clock time sequence paths from the high voltage domain group to the low voltage domain group.
(3) Each clock source time sequence path between different voltage domain groups is obtained based on time sequence analysis, and the clock source time sequence paths are classified, wherein the classification result comprises an external clock source time sequence path and an internal clock source time sequence path.
S104: and obtaining constraint conditions of each time sequence path of different categories after voltage change based on simulation analysis.
In this embodiment, the working voltages of the physical function modules in different voltage domain groups are different, and some physical function modules need to dynamically adjust their voltages according to the workload, and after the voltages change, the corresponding time sequence path lengths will change accordingly, so that the situation of violation may occur, so that the corresponding time sequence paths do not converge. Based on the method, the conditions that delay time of the corresponding input port and output port changes correspondingly after voltage change of each time sequence path of different categories is obtained through simulation analysis, and the change conditions are converted into corresponding constraint conditions so as to achieve the purpose of time sequence convergence.
In this embodiment, as shown in fig. 1B, a flow chart of acquiring constraint conditions in the embodiment of the present invention is shown. The method for obtaining the constraint conditions of each time sequence path with different categories after the voltage change based on the simulation analysis comprises the following steps:
S1041: and calculating each time sequence path of different categories by using a calculation script to acquire the time sequence path with the worst voltage variation in each time sequence path.
S1042: and determining the time sequence margin of the time sequence path with the worst voltage change, and acquiring constraint conditions of each time sequence path among different voltage domain groups after the voltage change based on simulation analysis.
In this embodiment, the constraint condition includes: after the voltage of the corresponding physical functional module changes in each time sequence path among different voltage domain groups, the delay time of the corresponding input port and output port correspondingly changes.
Further, in this embodiment, the integrated circuit is physically designed to make the corresponding timing paths converge according to the corresponding delay time of the input port and the output port.
It should be noted that, in the prior art, timing sequence convergence is performed according to experience or estimated conditions after physical implementation, and some margin is additionally added to an estimated value in order to achieve the convergence goal, so that the timing sequence is too pessimistic, and excessive delay units are used to increase the power consumption and the area of the integrated circuit; the time sequence can not meet the requirement because of inaccurate experience values, and the clock tree is completed at the moment, the clock paths are adjusted, the time sequence problem in other places is easy to bring, and certain challenges are brought to the convergence of the time sequence. In the invention, constraint conditions of different types of time sequence paths after voltage change can be obtained at the initial stage of the physical design realization of the integrated circuit, and different constraints are used for different time sequence path types, so that the difficulty of later time sequence convergence is reduced, and the convergence efficiency is higher.
S105: and optimizing the time sequence paths among the corresponding different voltage domain groups in the integrated circuit according to the constraint conditions of the obtained time sequence paths after the voltage change.
In this embodiment, after the voltage change occurs in each timing path of different types, the corresponding timing path length also changes, and based on the constraint condition after the voltage change obtained by the simulation analysis, the timing paths between the corresponding different voltage domain groups in the integrated circuit are optimized, where the optimization mode includes any one or a combination of multiple modes as follows:
(1) And according to the obtained constraint conditions of each time sequence path of different types after the voltage change, adjusting the combinational logic elements on the time sequence paths among the corresponding different voltage domain groups in the integrated circuit so as to optimize each time sequence path.
(2) And adjusting clock tree delay time among corresponding different voltage domain groups in the integrated circuit according to the obtained constraint conditions of each time sequence path after the voltage change so as to optimize each time sequence path.
In this embodiment, as shown in fig. 2, a schematic design of an integrated circuit according to an embodiment of the invention is shown. The integrated circuit is designed with a physical function module A, a physical function module B, a physical function module C, a physical function module D, a physical function module E and a physical function module F, and the physical function modules A, B, C, D, E, F are respectively positioned in different voltage domain groups X, Y, Z, W, U, T. The design shown in fig. 2 is only one embodiment of the present invention, and is mainly used for illustration, not for limiting the scope of the present invention. In practical application, different integrated circuits are designed in different modes. The principle of optimizing the timing paths between the different voltage domain groups is described below by way of example in connection with fig. 2.
In this embodiment, as shown in fig. 2, the physical function module a and the physical function module B have data timing paths, and the data timing paths of the physical function module a and the physical function module B need to meet the holding time requirement. The hold time is not too early for the receiving point for new data to be transmitted to ensure that the data to be transmitted remains for a period of time. The data timing path is defined by physical function modules A through B, where physical function module A has two operating voltages V1, V2 (V2 > V1) and physical function module B has one operating voltage V3. The delays at different voltages are different for the same data timing path. The higher the voltage, the smaller the delay of the sequential device and trace, the faster the operating rate, and the shorter the sequential path. Since this data timing path is transmitted from physical function module a to physical function module B, if the operating voltage of physical function module a changes from V1 to V2, it is assumed that there is no violation in the holding time of the operating voltage of physical function module a at this time when V1, and after the voltage of physical function module a increases to V2, the timing path in physical function module a becomes shorter, and a violation may occur. At this time, it is necessary to adjust the constraint condition of the data timing paths from the physical function module a to the physical function module B, and set the delay unit in the physical function module B as much as possible, for example, by adjusting the combinational logic elements on the data timing paths from the physical function module a to the physical function module B, or adjusting the clock tree delay time on the data timing paths from the physical function module a to the physical function module B, so as to reduce the negative influence caused by the voltage variation in the physical function module a.
In this embodiment, as shown in fig. 2, there is also a data timing path between the physical function module C and the physical function module D, which needs to meet the hold time requirement. The data timing path is from physical function C to D, where physical function C has one operating voltage V4 and physical function D has two operating voltages V5 and V6 (V6 > V5). When the voltage in the physical function module D increases from V5 to V6, the delay of the timing path in the physical function module D becomes short, and at this time, the constraint condition of the data timing path from the physical function module C to the physical function module D needs to be adjusted, and the delay unit is set in the physical function module C as much as possible, for example, by adjusting the combinational logic element on the data timing path from the physical function module C to the physical function module D, or adjusting the delay time of the clock tree on the data timing path from the physical function module C to the physical function module D, so as to reduce the negative influence caused by the voltage change in the physical function module D.
In this embodiment, as shown in fig. 2, the physical function module E and the physical function module F have both the data timing path and the clock timing path to satisfy the hold time. The data timing path is from physical function block E to F, the physical function block E has two operating voltages V7 and V8 (V8 > V7), the physical function block F has one operating voltage V9, and the clock timing path is sent to the physical function block F through the physical function block E. When the voltage in the physical function module E increases from V7 to V8, both the data timing path and the clock timing path in the physical function module E become shorter, and thus the clock timing path of the physical function module F is also affected. At this time, the clock timing path length sent from the physical function module E to the physical function module and the clock timing path length in the physical function module E need to be compared to determine whether the change of the clock timing path has a negative effect on the retention time, so as to control the data timing path and the clock timing path from the physical function module E to the physical function module F across the voltage domain to be respectively long or short in the corresponding physical function module, so as to optimize the timing paths from the physical function module E to the physical function module F.
S106: and judging whether the optimized time sequence path has violations or not based on the time sequence analysis.
S107: and if the violation exists, executing the engineering change command.
S108: and if no violation exists, determining that the timing sequence path converges.
In this embodiment, whether the optimized timing path has a violation is determined based on the timing analysis, and if the violation exists, an electronic design automation tool is used to make a program change command for the violation part so that the convergence target does not have the violation; if no violation exists, the optimized timing path is determined to be convergent, and the requirement of the holding time can be met.
In this embodiment, the engineering change command includes, but is not limited to: increasing or decreasing the number of combinational logic elements on the corresponding timing path, changing the type of combinational logic elements on the corresponding timing path, adjusting the delay time of the clock tree on the timing path.
It is worth to say that, the invention classifies different timing paths in the initial stage of the physical design implementation of the integrated circuit, specifically analyzes the specific situation, uses different constraints for different timing path types, and can obtain the worst voltage variation timing path situation when the physical implementation is carried out by means of the simulation tool, thereby reducing the difficulty of the later timing convergence and maximizing the convergence efficiency, and the processing of the simulation tool can also consider the area and the power consumption, compared with the prior art that the project change command is executed by using the estimated value to optimize, the performance, the power consumption and the area of the integrated circuit are easier to improve. In addition, the invention can accurately perform time sequence analysis without depending on a complete process library, and the obtained convergence result can realize smaller area, lower power consumption and higher performance speed of the integrated circuit under the condition of lacking the process library.
In this embodiment, after determining whether the optimized timing path has a violation based on the timing analysis, the method may further be used to execute the following steps:
Simulating each time sequence path among different voltage domain groups under different voltages to judge whether an unconverged time sequence path exists under different voltage conditions; if so, executing the engineering change command; and if not, determining that the timing sequence path converges.
In this embodiment, a simulation tool is used to simulate a time sequence path crossing a voltage domain on the basis of the present invention, which is a simulation of a voltage change condition, and whether a violation exists after the voltage change is determined by a simulation result. If a violation still exists, the violation may be handled by executing the engineering change command. If no violations exist, the optimized timing path is determined to be convergent, and the simulation is equivalent to additional convergence verification. Further, each time sequence path among different voltage domain groups is simulated under different voltages to judge whether each time sequence path finally converges under the condition of different voltages, and if the time sequence paths which do not converge exist, the time sequence paths can be processed by executing engineering change commands so as to converge corresponding time sequence paths.
As shown in fig. 3, a schematic structural diagram of a device for analyzing a time sequence path crossing a voltage domain in an embodiment of the invention is shown, and the device 300 includes:
The voltage acquisition module 301 is configured to acquire an operating voltage of each physical function module according to a power configuration file of the integrated circuit.
The voltage domain grouping module 302 is configured to group different voltage domains of each physical function module according to the obtained working voltage of each physical function module to form a plurality of voltage domain groups.
The timing path classification module 303 is configured to obtain each timing path between different voltage domain groups through timing analysis, and classify each timing path to form a plurality of timing path classes.
The constraint condition generation module 304 is configured to obtain constraint conditions of each time sequence path of different types after the voltage change occurs through simulation analysis.
And the optimizing module 305 is configured to optimize the timing paths between the corresponding different voltage domain groups in the integrated circuit according to the constraint condition of each acquired timing path of the different types after the voltage change occurs.
A judging module 306, configured to judge whether the optimized timing path has a violation through timing analysis; if the violation exists, executing the engineering change command; and if no violation exists, determining that the timing sequence path converges.
In this embodiment, the timing path classification module 303 is further configured to perform any one of the following steps:
(1) Acquiring each data time sequence path between different voltage domain groups based on time sequence analysis, and classifying each data time sequence path, wherein the classification result comprises the data time sequence paths from the low voltage domain group to the high voltage domain group and the data time sequence paths from the high voltage domain group to the low voltage domain group;
(2) Acquiring each clock time sequence path between different voltage domain groups based on time sequence analysis, and classifying each clock time sequence path, wherein the classification result comprises the clock time sequence paths from the low voltage domain group to the high voltage domain group and the clock time sequence paths from the high voltage domain group to the low voltage domain group;
(3) Each clock source time sequence path between different voltage domain groups is obtained based on time sequence analysis, and the clock source time sequence paths are classified, wherein the classification result comprises an external clock source time sequence path and an internal clock source time sequence path.
In this embodiment, the constraint generating module 304 is further configured to perform the following steps:
Calculating each time sequence path of different categories by using a calculation script to obtain a time sequence path with worst voltage variation in each time sequence path;
and determining the time sequence margin of the time sequence path with the worst voltage change, and acquiring constraint conditions of each time sequence path among different voltage domain groups after the voltage change based on simulation analysis.
In this embodiment, the optimizing module 305 is further configured to perform the following steps:
according to the constraint conditions of each acquired time sequence path with different types after voltage change, adjusting the combinational logic elements on the time sequence paths among the corresponding different voltage domain groups in the integrated circuit so as to optimize each time sequence path;
And adjusting clock tree delay time among corresponding different voltage domain groups in the integrated circuit according to the obtained constraint conditions of each time sequence path after the voltage change so as to optimize each time sequence path.
In one embodiment of the present application, a computer readable storage medium is provided, on which a computer program is stored, which when executed by a processor implements a method of analyzing a timing path across voltage domains as described above.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the method embodiments described above may be performed by computer program related hardware. The aforementioned computer program may be stored in a computer readable storage medium. The program, when executed, performs steps including the method embodiments described above; and the aforementioned storage medium includes: various media that can store program code, such as ROM, RAM, magnetic or optical disks.
In the embodiments provided herein, the computer-readable storage medium may include read-only memory, random-access memory, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, U-disk, removable hard disk, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. In addition, any connection is properly termed a computer-readable medium. For example, if the instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable and data storage media do not include connections, carrier waves, signals, or other transitory media, but are intended to be directed to non-transitory, tangible storage media. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.
As shown in fig. 4, which is a schematic structural diagram of an electronic terminal according to an embodiment of the present application, an electronic terminal 400 provided in this example includes: a processor 401 and a memory 402; the memory 402 is connected to the processor 401 through a system bus and performs communication with each other, the memory 402 is used for storing a computer program, and the processor 401 is used for running the computer program stored in the memory 402, so that the electronic terminal 400 performs the above-mentioned cross-voltage-domain timing path analysis method.
Referring to fig. 4, an optional hardware structure schematic diagram of an electronic terminal 400 according to an embodiment of the present invention is shown, where the terminal 400 may be a mobile phone, a computer device, a tablet device, a personal digital processing device, a factory background processing device, etc. The electronic terminal 400 includes: at least one processor 401, a memory 402, at least one network interface 404, and a user interface 406. The various components in the device are coupled together by a bus system 405. It is understood that the bus system 405 is used to enable connected communications between these components. The bus system 405 includes a power bus, a control bus, and a status signal bus in addition to a data bus. But for clarity of illustration the various buses are labeled as bus systems in fig. 4.
The user interface 406 may include, among other things, a display, keyboard, mouse, trackball, click gun, keys, buttons, touch pad, or touch screen, etc.
It is to be appreciated that memory 402 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read Only Memory (ROM), a programmable Read Only Memory (PROM, programmable Read-Only Memory), which serves as an external cache, among others. By way of example, and not limitation, many forms of RAM are available, such as static random Access Memory (SRAM, staticRandom Access Memory), synchronous static random Access Memory (SSRAM, synchronous Static RandomAccess Memory). The memory described by embodiments of the present invention is intended to comprise, without being limited to, these and any other suitable types of memory.
The memory 402 in the embodiment of the present invention is used to store various kinds of data to support the operation of the electronic terminal 400. Examples of such data include: any executable programs for operating on electronic terminal 400, such as operating system 4021 and application programs 4022; the operating system 4021 contains various system programs, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks. The application programs 4022 may include various application programs such as a media player (MediaPlayer), a Browser (Browser), and the like for implementing various application services. The method for analyzing the time sequence path of the cross-voltage domain provided by the embodiment of the invention can be contained in the application 4022.
The method disclosed in the above embodiment of the present invention may be applied to the processor 401 or implemented by the processor 401. The processor 401 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 401 or by instructions in the form of software. The Processor 401 may be a general purpose Processor, a digital signal Processor (DSP, digital Signal Processor), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc. Processor 401 may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present invention. The general purpose processor 401 may be a microprocessor or any conventional processor or the like. The steps of the accessory optimization method provided by the embodiment of the invention can be directly embodied as the execution completion of the hardware decoding processor or the execution completion of the hardware and software module combination execution in the decoding processor. The software modules may be located in a storage medium having memory and a processor reading information from the memory and performing the steps of the method in combination with hardware.
In an exemplary embodiment, the electronic terminal 400 may be implemented by one or more Application Specific Integrated Circuits (ASICs), DSPs, programmable logic devices (PLDs, programmable Logic Device), complex programmable logic devices (CPLDs, complex Programmable LogicDevice) for performing the aforementioned methods.
In summary, the method, the device, the medium and the terminal for analyzing the time sequence path crossing the voltage domains provided by the application form a plurality of voltage domain groups by grouping different voltage domains of each physical function module; acquiring each time sequence path between different voltage domain groups based on time sequence analysis and classifying the time sequence paths to form a plurality of time sequence path categories; acquiring constraint conditions of each time sequence path of different categories after voltage change based on simulation analysis; optimizing time sequence paths among corresponding different voltage domain groups in the integrated circuit according to the obtained constraint conditions; and judging whether the optimized time sequence path has violations or not. The application can realize the situation of acquiring the timing sequence path with the worst voltage variation in the initial stage in the physical design, thereby reducing the difficulty of the later timing sequence convergence and maximizing the convergence efficiency; in addition, the application can accurately perform time sequence analysis without depending on a complete process library, and the obtained convergence result can realize smaller area, lower power consumption and higher performance speed of the integrated circuit under the condition of lacking the process library. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (8)
1. A method of analyzing a timing path across a voltage domain for an integrated circuit, comprising:
acquiring the working voltage of each physical function module according to the power supply configuration file of the integrated circuit;
according to the obtained working voltage of each physical function module, different voltage domains are grouped for each physical function module to form a plurality of voltage domain groups;
Acquiring each time sequence path between different voltage domain groups based on time sequence analysis, and classifying each time sequence path to form a plurality of time sequence path categories; the method comprises the following steps:
acquiring each clock time sequence path between different voltage domain groups based on time sequence analysis, and classifying each clock time sequence path, wherein the classification result comprises the clock time sequence paths from the low voltage domain group to the high voltage domain group and the clock time sequence paths from the high voltage domain group to the low voltage domain group;
Acquiring constraint conditions of each time sequence path of different categories after voltage change based on simulation analysis; the method comprises the following steps:
Calculating each time sequence path of different categories by using a calculation script to obtain a time sequence path with worst voltage variation in each time sequence path;
Determining the time sequence margin of the time sequence path with the worst voltage change, and acquiring constraint conditions of each time sequence path after the voltage change of different voltage domain groups based on simulation analysis;
Optimizing the time sequence paths among corresponding different voltage domain groups in the integrated circuit according to the constraint conditions of each time sequence path after the voltage change; the method comprises the following steps:
according to the constraint conditions of each acquired time sequence path with different types after voltage change, adjusting the combinational logic elements on the time sequence paths among the corresponding different voltage domain groups in the integrated circuit so as to optimize each time sequence path;
Judging whether the optimized time sequence path has violations or not based on time sequence analysis; if the violation exists, executing the engineering change command; and if no violation exists, determining that the timing sequence path converges.
2. The method of claim 1, wherein the step of obtaining each timing path between different voltage domain groups based on the timing analysis and classifying each timing path to form a plurality of timing path categories further comprises any one or more of the following combinations:
Acquiring each data time sequence path between different voltage domain groups based on time sequence analysis, and classifying each data time sequence path, wherein the classification result comprises the data time sequence paths from the low voltage domain group to the high voltage domain group and the data time sequence paths from the high voltage domain group to the low voltage domain group;
Each clock source time sequence path between different voltage domain groups is obtained based on time sequence analysis, and the clock source time sequence paths are classified, wherein the classification result comprises an external clock source time sequence path and an internal clock source time sequence path.
3. The method for analyzing the time sequence path across the voltage domain according to claim 1, wherein the method for optimizing the time sequence paths among the corresponding different voltage domain groups in the integrated circuit according to the constraint condition of each time sequence path of the obtained different types after the voltage change further comprises the following steps:
And adjusting clock tree delay time among corresponding different voltage domain groups in the integrated circuit according to the obtained constraint conditions of each time sequence path after the voltage change so as to optimize each time sequence path.
4. The method of claim 1, wherein the power profile includes power information for powering the voltage domain in which each of the physical function modules is located.
5. A voltage domain crossing timing path analysis apparatus, comprising:
The voltage acquisition module is used for acquiring the working voltage of each physical function module according to the power supply configuration file of the integrated circuit;
The voltage domain grouping module is used for grouping different voltage domains of each physical function module according to the acquired working voltage of each physical function module to form a plurality of voltage domain groups;
The time sequence path classification module is used for acquiring each time sequence path between different voltage domain groups through time sequence analysis and classifying each time sequence path to form a plurality of time sequence path categories; the method comprises the following steps:
acquiring each clock time sequence path between different voltage domain groups based on time sequence analysis, and classifying each clock time sequence path, wherein the classification result comprises the clock time sequence paths from the low voltage domain group to the high voltage domain group and the clock time sequence paths from the high voltage domain group to the low voltage domain group;
the constraint condition generation module is used for acquiring constraint conditions of various time sequence paths of different categories after voltage change occurs through simulation analysis; the method comprises the following steps:
Calculating each time sequence path of different categories by using a calculation script to obtain a time sequence path with worst voltage variation in each time sequence path;
Determining the time sequence margin of the time sequence path with the worst voltage change, and acquiring constraint conditions of each time sequence path after the voltage change of different voltage domain groups based on simulation analysis;
The optimization module is used for optimizing the time sequence paths among the corresponding different voltage domain groups in the integrated circuit according to the constraint conditions of the acquired time sequence paths with different types after the voltage changes; the method comprises the following steps:
according to the constraint conditions of each acquired time sequence path with different types after voltage change, adjusting the combinational logic elements on the time sequence paths among the corresponding different voltage domain groups in the integrated circuit so as to optimize each time sequence path;
the judging module is used for judging whether the optimized time sequence path has violations or not through time sequence analysis; if the violation exists, executing the engineering change command; and if no violation exists, determining that the timing sequence path converges.
6. The cross-voltage domain timing path analysis device of claim 5, wherein the optimization module is further configured to perform the steps of:
And adjusting clock tree delay time among corresponding different voltage domain groups in the integrated circuit according to the obtained constraint conditions of each time sequence path after the voltage change so as to optimize each time sequence path.
7. A computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the method of time-series path analysis across voltage domains of any one of claims 1 to 4.
8. An electronic terminal, comprising: a processor and a memory;
The memory is used for storing a computer program;
the processor is configured to execute the computer program stored in the memory, so that the terminal performs the method for analyzing a timing path across voltage domains according to any one of claims 1 to 4.
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