CN113705136A - Integrated circuit automation logic synthesis system, method, device and medium - Google Patents

Integrated circuit automation logic synthesis system, method, device and medium Download PDF

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CN113705136A
CN113705136A CN202110963117.XA CN202110963117A CN113705136A CN 113705136 A CN113705136 A CN 113705136A CN 202110963117 A CN202110963117 A CN 202110963117A CN 113705136 A CN113705136 A CN 113705136A
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comprehensive
utilization rate
optimized
path
standard unit
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李拓
王长红
刘凯
满宏涛
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Inspur Electronic Information Industry Co Ltd
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Inspur Electronic Information Industry Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/337—Design optimisation

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Abstract

The application discloses integrated circuit automation logic synthesis system, method, device and medium, the system includes: the environment configuration module is used for acquiring comprehensive parameters; the comprehensive optimization module is used for performing logic synthesis on the RTL code file to be synthesized according to the comprehensive parameters to obtain a preliminary synthesis result; the report generating module is used for generating a corresponding preliminary comprehensive report; the report automatic analysis module is used for analyzing the preliminary comprehensive report and determining an optimized control parameter; the iterative optimization command automatic generation module is used for optimizing the preliminary comprehensive result according to the optimization control parameters to obtain an optimized comprehensive result, calling the report generation module and the report automatic analysis module to update the optimization control parameters, and performing iterative optimization on the optimized comprehensive result according to the updated optimization control parameters until the optimized comprehensive result meets preset output conditions; and the result output module is used for outputting the target comprehensive result. Therefore, the design cost is saved, and the integrated circuit is favorable for being quickly marketed.

Description

Integrated circuit automation logic synthesis system, method, device and medium
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to an integrated circuit automation logic synthesis system, method, device, and medium.
Background
With the continuous development of information technology, people's life and working modes have changed greatly, and the core supporting these changes is just various integrated circuits with different functions. The structure of the current integrated circuit is more and more complex, an EDA (Electronic Design Automation) tool needs to be adopted to complete the Design of the integrated circuit, and the logic synthesis is a process of converting an RTL (Register Transfer Level) code into a gate-Level netlist, and is an extremely important step in the whole integrated circuit Design process, and the Design period of the integrated circuit directly relates to the Design cost.
After the initial synthesis result is obtained in the logic synthesis in the existing integrated circuit design, the report needs to be manually consulted and the timing violation part needs to be found out, and then the command is manually input for incremental iteration, so that the period of the logic synthesis is greatly prolonged, the design cost is increased, and the method is also very unfavorable for the rapid marketing of the integrated circuit.
Disclosure of Invention
In view of the above, an object of the present application is to provide an integrated circuit automated logic synthesis system, method, device and medium, which can automatically analyze a preliminary synthesis report after a first logic synthesis to determine an optimized control parameter, thereby automatically optimizing the preliminary synthesis result, without manually referring to the report and inputting a command, and instead, an automated method is adopted to implement a logic synthesis iteration process of an integrated circuit, thereby greatly shortening the design cycle, saving the design cost, and facilitating the rapid marketing of the integrated circuit. The specific scheme is as follows:
in a first aspect, the present application discloses an integrated circuit automation logic synthesis system, comprising:
the environment configuration module is used for acquiring comprehensive parameters;
the comprehensive optimization module is used for carrying out logic synthesis on the RTL code file to be synthesized according to the comprehensive parameters to obtain a preliminary synthesis result;
the report generating module is used for generating a preliminary comprehensive report according to the preliminary comprehensive result;
the report automatic analysis module is used for analyzing the preliminary comprehensive report and determining an optimized control parameter;
an iterative optimization command automatic generation module, configured to optimize a path in the preliminary comprehensive result according to the optimization control parameter to obtain an optimized comprehensive result, and invoke the report generation module and the report automatic analysis module to update the optimization control parameter according to the optimized comprehensive result, and perform iterative optimization on the optimized comprehensive result according to the updated optimization control parameter until a preset output condition is met, so as to obtain a target comprehensive result;
and the result output module is used for outputting the target comprehensive result.
Optionally, the environment configuration module includes:
the path information acquisition submodule is used for acquiring the path of the RTL code file to be synthesized, the path of the synthesis constraint file and the path of the library file;
the first comprehensive variable setting submodule is used for acquiring an optimized parameter threshold, wherein the optimized parameter threshold comprises preset longest iteration time, a preset establishing time sequence maximum violation threshold, a violation value ratio threshold, the maximum utilization rate of an LVT standard unit, the maximum increment of each iteration of the LVT standard unit, the maximum utilization rate of an ULVT standard unit and the maximum increment of each iteration of the ULVT standard unit;
and the second comprehensive variable setting submodule is used for acquiring comprehensive parameters except the optimized parameter threshold.
Optionally, the comprehensive optimization module includes:
a design read-in submodule, configured to read in the RTL code file to be integrated, the comprehensive constraint file, and the library file according to the path of the RTL code file to be integrated, the path of the comprehensive constraint file, and the path of the library file;
the path group setting submodule is used for acquiring the preset number of path groups;
and the comprehensive execution sub-module is used for performing logic synthesis on the RTL code file to be synthesized according to the comprehensive parameters, the comprehensive constraint file and the library file to obtain a preliminary synthesis result, wherein the preliminary synthesis result comprises a plurality of path groups of the preset path group.
Optionally, the report generating module is configured to:
and generating the preliminary comprehensive report by utilizing the establishing time sequence violation values of all paths in all path groups, the current utilization rate of the LVT standard unit, the current utilization rate of the ULVT standard unit and the comprehensive elapsed time in the preliminary comprehensive result.
Optionally, the report automatic analysis module includes:
the report information analysis submodule is used for determining the maximum value of the set-up time sequence violation and the average value of the set-up time sequence violation of each path group according to the set-up time sequence violation values of each path;
an analysis result output sub-module, configured to determine an optimized control variable tag of each path according to the violation value ratio of each path and the violation value ratio threshold, and output the optimized control variable tag, the maximum value of the violation of the setup time sequence, the current utilization rate of the LVT standard unit, the current utilization rate of the ULVT standard unit, and the comprehensive elapsed time as optimized control parameters;
the violation value ratio of any one path is the ratio of the establishment time sequence violation value of the path to the establishment time sequence violation average value of the path group to which the path belongs, the optimization control variable tag is 1, which indicates that the violation value ratio of the corresponding path is greater than the violation value ratio threshold, the optimization control variable tag is 0, which indicates that the violation value ratio of the corresponding path is not greater than the violation value ratio threshold.
Optionally, the module for automatically generating an iterative optimization command includes:
the optimization control submodule is used for judging whether the optimization control variables tag are all 0 or not when the maximum value of the violation of the set time sequence is not less than the maximum violation threshold of the preset set time sequence;
a path group generation submodule, configured to set, when the optimized control variable tag is not all 0, a path for which the optimized control variable is 1 as a new path group;
the optimization control submodule is used for judging whether the current utilization rate of the LVT standard unit is less than the maximum utilization rate of the LVT standard unit when the optimization control variables tag are all 0;
the LVT standard unit utilization rate setting sub-module is used for setting optimized LVT standard unit utilization rates according to the LVT standard unit maximum utilization rate, the maximum increment of each iteration of the LVT standard unit and the LVT standard unit current utilization rate when the LVT standard unit current utilization rate is smaller than the LVT standard unit maximum utilization rate;
the optimization control sub-module is used for judging whether the current utilization rate of the ULVT standard unit is less than the maximum utilization rate of the ULVT standard unit or not when the current utilization rate of the LVT standard unit is not less than the maximum utilization rate of the LVT standard unit;
an ULVT standard unit utilization rate setting submodule, configured to set, when the current utilization rate of the ULVT standard unit is less than the maximum utilization rate of the ULVT standard unit, an optimized ULVT standard unit utilization rate according to the maximum utilization rate of the ULVT standard unit, the maximum increment of each iteration of the ULVT standard unit, and the current utilization rate of the ULVT standard unit;
and the increment optimization comprehensive execution submodule is used for carrying out establishment time sequence violation optimization on the new path group when the comprehensive elapsed time is less than the preset longest iteration time, and optimizing the path in the preliminary comprehensive result according to the optimized LVT standard unit utilization rate and the optimized ULVT standard unit utilization rate to obtain the optimized comprehensive result.
Optionally, the LVT standard cell utilization rate setting submodule is configured to:
taking the sum of the maximum increment of each iteration of the LVT standard unit and the current utilization rate of the LVT standard unit as the utilization rate of a preselected LVT standard unit;
and setting the optimized LVT standard cell utilization rate according to the maximum value of the LVT standard cell maximum utilization rate and the preselected LVT standard cell utilization rate.
In a second aspect, the present application discloses a method for integrated circuit automated logic synthesis, comprising:
acquiring comprehensive parameters;
performing logic synthesis on the RTL code file to be synthesized according to the synthesis parameters to obtain a preliminary synthesis result;
generating a preliminary comprehensive report according to the preliminary comprehensive result;
analyzing the preliminary comprehensive report to determine an optimized control parameter;
optimizing paths in the preliminary comprehensive result according to the optimization control parameters to obtain an optimized comprehensive result, updating the optimization control parameters according to the optimized comprehensive result, and performing iterative optimization on the optimized comprehensive result according to the updated optimization control parameters until the optimized comprehensive result meets preset output conditions to obtain a target comprehensive result;
and outputting the target comprehensive result.
In a third aspect, the present application discloses an electronic device, comprising:
a memory and a processor;
wherein the memory is used for storing a computer program;
the processor is used for executing the computer program to realize the integrated circuit automation logic synthesis method disclosed in the foregoing.
In a fourth aspect, the present application discloses a computer readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the integrated circuit automation logic synthesis method disclosed above.
It can be seen that the present application discloses an integrated circuit automated logic synthesis system, comprising: the environment configuration module is used for acquiring comprehensive parameters; the comprehensive optimization module is used for carrying out logic synthesis on the RTL code file to be synthesized according to the comprehensive parameters to obtain a preliminary synthesis result; the report generating module is used for generating a preliminary comprehensive report according to the preliminary comprehensive result; the report automatic analysis module is used for analyzing the preliminary comprehensive report and determining an optimized control parameter; an iterative optimization command automatic generation module, configured to optimize a path in the preliminary comprehensive result according to the optimization control parameter to obtain an optimized comprehensive result, and invoke the report generation module and the report automatic analysis module to update the optimization control parameter according to the optimized comprehensive result, and perform iterative optimization on the optimized comprehensive result according to the updated optimization control parameter until a preset output condition is met, so as to obtain a target comprehensive result; and the result output module is used for outputting the target comprehensive result. Therefore, in the application, after the comprehensive optimization module performs preliminary logic synthesis on the RTL code file to be synthesized to obtain a preliminary comprehensive result, a preliminary comprehensive report can be generated according to the preliminary comprehensive result, then the report automatic analysis module analyzes the preliminary comprehensive report to determine the optimization control parameters, then the iterative optimization command automatic generation module optimizes the preliminary comprehensive result according to the optimization control parameters, and the report generation module and the report automatic analysis module are called back to update the optimization control parameters after each optimization, the optimized comprehensive result is iterated according to the updated optimization control parameters until the preset output conditions are met, the final target comprehensive result can be output by the result output module, so that the preliminary comprehensive report can be automatically analyzed after the preliminary logic synthesis to determine the optimization control parameters, therefore, the preliminary comprehensive result is automatically optimized, manual report lookup and command input are not needed, the logic comprehensive iterative process of the integrated circuit is realized in an automatic mode, the design period is greatly shortened, the design cost is saved, and the rapid marketing of the integrated circuit is facilitated.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of an integrated circuit automated logic synthesis system according to the present disclosure;
FIG. 2 is a schematic diagram of a portion of an integrated circuit automated logic synthesis system according to one embodiment of the present disclosure;
FIG. 3 is a flowchart illustrating operation of an exemplary integrated circuit automated logic synthesis system according to the present disclosure;
FIG. 4 is a flow chart of an exemplary integrated circuit automated logic synthesis method disclosed herein;
fig. 5 is a schematic structural diagram of an electronic device disclosed in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, an embodiment of the present application discloses an integrated circuit automation logic synthesis system, which includes:
the environment configuration module 11 is used for acquiring comprehensive parameters;
the comprehensive optimization module 12 is configured to perform logical synthesis on the RTL code file to be synthesized according to the comprehensive parameters to obtain a preliminary synthesis result;
a report generating module 13, configured to generate a preliminary comprehensive report according to the preliminary comprehensive result;
the report automatic analysis module 14 is used for analyzing the preliminary comprehensive report and determining an optimized control parameter;
an iterative optimization command automatic generation module 15, configured to optimize a path in the preliminary comprehensive result according to the optimization control parameter to obtain an optimized comprehensive result, and invoke the report generation module and the report automatic analysis module to update the optimization control parameter according to the optimized comprehensive result, and perform iterative optimization on the optimized comprehensive result according to the updated optimization control parameter until a preset output condition is met, so as to obtain a target comprehensive result;
and a result output module 16, configured to output the target integrated result.
It can be seen that the present application discloses an integrated circuit automated logic synthesis system, comprising: the environment configuration module is used for acquiring comprehensive parameters; the comprehensive optimization module is used for carrying out logic synthesis on the RTL code file to be synthesized according to the comprehensive parameters to obtain a preliminary synthesis result; the report generating module is used for generating a preliminary comprehensive report according to the preliminary comprehensive result; the report automatic analysis module is used for analyzing the preliminary comprehensive report and determining an optimized control parameter; an iterative optimization command automatic generation module, configured to optimize a path in the preliminary comprehensive result according to the optimization control parameter to obtain an optimized comprehensive result, and invoke the report generation module and the report automatic analysis module to update the optimization control parameter according to the optimized comprehensive result, and perform iterative optimization on the optimized comprehensive result according to the updated optimization control parameter until a preset output condition is met, so as to obtain a target comprehensive result; and the result output module is used for outputting the target comprehensive result. Therefore, in the application, after the comprehensive optimization module performs preliminary logic synthesis on the RTL code file to be synthesized to obtain a preliminary comprehensive result, a preliminary comprehensive report can be generated according to the preliminary comprehensive result, then the report automatic analysis module analyzes the preliminary comprehensive report to determine the optimization control parameters, then the iterative optimization command automatic generation module optimizes the preliminary comprehensive result according to the optimization control parameters, and the report generation module and the report automatic analysis module are called back to update the optimization control parameters after each optimization, the optimized comprehensive result is iterated according to the updated optimization control parameters until the preset output conditions are met, the final target comprehensive result can be output by the result output module, so that the preliminary comprehensive report can be automatically analyzed after the preliminary logic synthesis to determine the optimization control parameters, therefore, the preliminary comprehensive result is automatically optimized, manual report lookup and command input are not needed, the logic comprehensive iterative process of the integrated circuit is realized in an automatic mode, the design period is greatly shortened, the design cost is saved, and the rapid marketing of the integrated circuit is facilitated.
In practical applications, the integrated circuit automation logic synthesis system needs to include an environment configuration module for acquiring synthesis parameters required in a logic synthesis process input by a user. Specifically, the environment configuration module may include: the path information acquisition submodule is used for acquiring the path of the RTL code file to be synthesized, the path of the synthesis constraint file and the path of the library file; the first comprehensive variable setting submodule is used for acquiring an optimized parameter threshold, wherein the optimized parameter threshold comprises preset longest iteration time, a preset establishment time sequence maximum violation threshold, a violation value ratio threshold, the maximum utilization rate of an LVT (Low Voltage threshold) standard unit, the maximum increment of each iteration of the LVT standard unit, the maximum utilization rate of an ULVT (ultra Low Voltage threshold) standard unit and the maximum increment of each iteration of the ULVT standard unit; and the second comprehensive variable setting submodule is used for acquiring comprehensive parameters except the optimized parameter threshold.
That is, the environment configuration module needs to include a path information obtaining sub-module, which is used to obtain a path of the RTL code file to be synthesized, a path of the synthesis constraint file, and a path of the library file, and also can obtain a path of the generated log storage, a path of the report storage, and a path of the storage of the target synthesis result. The system also comprises a first comprehensive variable setting submodule for acquiring the preset longest iteration time TmaxPresetting a maximum violation threshold M of a time sequence, presetting a violation ratio threshold R, LVT, obtaining a maximum utilization ratio P% of standard units, and presetting a maximum increment P of each iteration of LVT standard unitsstepPercent, the maximum utilization rate Q% of the ULVT standard unit and the maximum increment Q% of the ULVT standard unit in each iterationstep% and the like. And a second comprehensive variable setting submodule for acquiring comprehensive parameters other than the optimized parameter threshold, for example, the number of cores of the CPU, and the maximum fan-out.
Of course, the integrated circuit automation logic synthesis system further includes: and the comprehensive optimization module is used for carrying out logic synthesis on the RTL code file to be synthesized according to the comprehensive parameters to obtain a preliminary synthesis result. Specifically, the comprehensive optimization module may include a design read-in sub-module, configured to read in the RTL code file to be synthesized, the comprehensive constraint file, and the library file according to a path of the RTL code file to be synthesized, a path of the comprehensive constraint file, and a path of the library file; the path group setting submodule is used for acquiring the preset number of path groups; and the comprehensive execution sub-module is used for performing logic synthesis on the RTL code file to be synthesized according to the comprehensive parameters, the comprehensive constraint file and the library file to obtain a preliminary synthesis result, wherein the preliminary synthesis result comprises a plurality of path groups of the preset path group.
That is, the design read-in sub-module reads the RTL code file to be integrated, the synthetic constraint file, and the library file according to the path of the RTL code file to be integrated, the path of the synthetic constraint file, and the path of the library file, and then the path group setting sub-module obtains the preset path group number S to improve the timing performance. And then, the comprehensive execution sub-module can perform logic synthesis on the RTL code file to be synthesized according to the comprehensive parameters, the comprehensive constraint file and the library file to obtain a preliminary synthesis result, wherein the preliminary synthesis result comprises S path groups of the preset path group number.
After the preliminary synthesis result is obtained, since it is not determined whether the preliminary synthesis result meets the requirement, the integrated circuit automatic logic synthesis system further needs to include a report generation module for generating a preliminary synthesis report according to the preliminary synthesis result. Specifically, the report generation module utilizes the time sequence of establishing each path in each path group in the preliminary synthesis resultViolation value and current utilization rate P of LVT standard cellnow% ULVT standard cell current utilization rate Qnow% integrated elapsed time TnowGenerating the preliminary consolidated report. The setup time sequence violation values of the paths in the path groups can be written into the preliminary comprehensive report in descending order.
After the preliminary comprehensive report is obtained, the report automatic analysis module is further required to analyze the preliminary comprehensive report to determine an optimized control parameter. Specifically, the report automatic analysis module includes: the report information analysis submodule is used for determining the maximum value of the set-up time sequence violation and the average value of the set-up time sequence violation of each path group according to the set-up time sequence violation values of each path; an analysis result output sub-module, configured to determine an optimized control variable tag of each path according to the violation value ratio of each path and the violation value ratio threshold, and output the optimized control variable tag, the maximum value of the violation of the setup time sequence, the current utilization rate of the LVT standard unit, the current utilization rate of the ULVT standard unit, and the comprehensive elapsed time as optimized control parameters; the violation value ratio of any one path is the ratio of the establishment time sequence violation value of the path to the establishment time sequence violation average value of the path group to which the path belongs, the optimization control variable tag is 1, which indicates that the violation value ratio of the corresponding path is greater than the violation value ratio threshold, the optimization control variable tag is 0, which indicates that the violation value ratio of the corresponding path is not greater than the violation value ratio threshold.
That is, the report information analysis submodule in the report automatic analysis module determines the maximum value of the setup time sequence violation and the average value of the setup time sequence violation of each path group according to the setup time sequence violation values of each path. Recording the total number of paths establishing time sequence violation in the s-th path group as CsThe average value of the time sequence violation values of the s-th path set-up is denoted as asAnd the value of the setup time sequence violation of the d-th path in the s-th path group is recorded as vsdThe d-th path in the s-th path groupThe optimized control variable of the diameter is recorded as tagsdThe maximum violation value of the setup time sequence of all paths is VmaxWherein S is more than or equal to 1 and less than or equal to S, d is more than or equal to 1 and less than or equal to Cs. The report information analysis submodule calculates v by using the preliminary comprehensive reportsd、asAnd Vmax. The analysis result output submodule of the report automatic analysis module compares vsd/asAnd the size of R when vsd/asIf the number of the paths is more than R, the optimization control variable tag of the d path in the s path group in the report is usedsdSetting to 1, otherwise setting to 0, traversing all violation paths in the report to complete the setting of all optimized control variables, and outputting tagsd、VmaxCurrent utilization rate P of LVT standard unitnow% ULVT standard cell current utilization rate Qnow% integrated elapsed time Tnow. That is, the optimization control parameter includes tagsd、VmaxCurrent utilization rate P of LVT standard unitnow% ULVT standard cell current utilization rate Qnow% integrated elapsed time Tnow。
And then, an iterative optimization command automatic generation module optimizes the path in the preliminary comprehensive result according to the optimization control parameters to obtain an optimized comprehensive result, after each optimization, the report generation module and the report automatic analysis module are called to update the optimization control parameters according to the optimized comprehensive result, and the optimized comprehensive result is iteratively optimized according to the updated optimization control parameters until the preset output conditions are met to obtain a target comprehensive result. That is, after each optimization is finished, the iterative optimization command automatic generation module calls back the optimized comprehensive report corresponding to the optimized comprehensive result generated by the report generation module, calls the report automatic analysis module to analyze the optimized comprehensive report so as to update the optimized control parameters to obtain updated optimized control parameters, and iteratively optimizes the optimized comprehensive result according to the updated optimized control parameters until a preset output condition is met to obtain a target comprehensive result, wherein the preset output condition comprises the consumed time of the integrationTnowReaching the preset maximum iteration time TmaxEstablishing a time sequence with a maximum violation value of VmaxAnd is smaller than the maximum violation threshold M of the preset establishment time sequence.
It is understood that after the target synthesis result is obtained, the target synthesis result may be output by the result output module, wherein the target synthesis result includes a gate-level netlist, a constraint file, and a synthesis report.
Referring to fig. 2, the iterative optimization command automatic generation module 15 includes:
the optimization control submodule 151 is configured to determine whether all the optimization control variables tag are 0 when the maximum value of the setup time sequence violation is not less than the preset maximum value of the setup time sequence violation threshold;
a path group generation submodule 152, configured to set, when the optimized control variable tag is not all 0, a path whose optimized control variable is 1 as a new path group;
the optimization control submodule is used for judging whether the current utilization rate of the LVT standard unit is less than the maximum utilization rate of the LVT standard unit when the optimization control variables tag are all 0;
an LVT standard cell utilization rate setting sub-module 153, configured to set, when the current utilization rate of the LVT standard cell is less than the maximum utilization rate of the LVT standard cell, an optimized LVT standard cell utilization rate according to the maximum utilization rate of the LVT standard cell, the maximum increment of each iteration of the LVT standard cell, and the current utilization rate of the LVT standard cell;
the optimization control sub-module is used for judging whether the current utilization rate of the ULVT standard unit is less than the maximum utilization rate of the ULVT standard unit or not when the current utilization rate of the LVT standard unit is not less than the maximum utilization rate of the LVT standard unit;
an ULVT standard cell utilization rate setting sub-module 154, configured to set, when the current utilization rate of the ULVT standard cell is less than the maximum utilization rate of the ULVT standard cell, an optimized ULVT standard cell utilization rate according to the maximum utilization rate of the ULVT standard cell, the maximum increment of each iteration of the ULVT standard cell, and the current utilization rate of the ULVT standard cell;
and the incremental optimization comprehensive execution sub-module 155 is configured to, when the comprehensive elapsed time is less than the preset longest iteration time, perform time sequence violation optimization on the new path group, and optimize a path in the preliminary comprehensive result according to the optimized LVT standard unit utilization rate and the optimized ULVT standard unit utilization rate to obtain the optimized comprehensive result.
Specifically, the optimization control sub-module in the iterative optimization command automatic generation module 16 first determines the maximum value V of the setup time sequence violationmaxAnd whether the time sequence is not less than the maximum violation threshold M of the preset establishing time sequence or not, if not, indicating that a preliminary comprehensive result meets the requirement, and directly outputting the preliminary comprehensive result as a target comprehensive result. If said maximum value of setup time sequence violation VmaxIf the time sequence is not less than the maximum violation threshold M of the preset setup time sequence, it indicates that optimization is still needed, and specifically, it may be determined whether all the optimization control variables tag are 0. A path group generation sub-module, configured to set, when the optimized control variable tag is not all 0, a path for which the optimized control variable tag is 1 as a new path group, specifically, a path for which each optimized control variable tag is not 0 is separately used as a path group, for example, the number S of path groups in the preliminary synthesis result is 5, and there are 3 paths for which the optimized control variable tag is not 0 in each path group, and then each of the 3 paths is separately used as a path group, and 3 new path groups are set, so that a total of 8 path groups are formed. When the optimization control variables tag are all 0, the optimization control submodule also needs to judge the current utilization rate P of the LVT standard unitnowWhether% is less than P% of the maximum utilization of the LVT standard cells. An LVT standard unit utilization rate setting submodule, wherein the current utilization rate P of the LVT standard unit isnowWhen the% is less than the maximum utilization rate P% of the LVT standard unit, according to the maximum utilization rate P% of the LVT standard unit and the maximum increment P of each iteration of the LVT standard unitstep% and current utilization rate P of LVT standard cellnow% sets the optimized LVT standard unit utilization rate. The optimization control submodule is used for optimizing the current utilization rate P of the LVT standard unitnow% is not less than maximum utilization rate P% of the LVT standard unit, and current utilization rate Q of the ULVT standard unit is required to be judgednowWhether% is less than Q% of the maximum utilization of the ULVT standard cell. ULVT standard cell utilization setting sub-module 154 at which the ULVT standard cell current utilization Q isnowAnd when the% is less than the maximum utilization rate Q% of the ULVT standard unit, setting the optimized ULVT standard unit utilization rate according to the maximum utilization rate of the ULVT standard unit, the maximum increment of each iteration of the ULVT standard unit and the current utilization rate of the ULVT standard unit.
The execution of sub-module 155 may then be performed by incremental optimization synthesis where the synthesis has elapsed time TnowLess than the preset maximum iteration time TmaxAnd then, establishing time sequence violation optimization on the new path group, and optimizing the paths in the preliminary comprehensive result according to the optimized LVT standard unit utilization rate and the optimized ULVT standard unit utilization rate to obtain the optimized comprehensive result.
Wherein, LVT standard cell utilization ratio sets up submodule piece for: taking the sum of the maximum increment of each iteration of the LVT standard unit and the current utilization rate of the LVT standard unit as the utilization rate of a preselected LVT standard unit; and setting the optimized LVT standard cell utilization rate according to the maximum value of the LVT standard cell maximum utilization rate and the preselected LVT standard cell utilization rate. That is, max (P)step％+PnowPercent, P%) the optimized LVT standard cell utilization. Correspondingly, the ULVT standard cell utilization setting sub-module 154 will be max (Q)step％+Qnow%, Q%) set the optimized ULVT standard cell utilization.
Referring to fig. 3, a flowchart of integrated circuit automation logic synthesis system operation is shown. Firstly, data path setting is performed, that is, the path information obtaining submodule in the environment configuration module obtains the path of the RTL code file to be synthesized, the path of the synthesis constraint file, and the path of the library file. And then, performing traditional comprehensive variable setting, namely acquiring comprehensive parameters except the optimized parameter threshold in the environment configuration module. Automatic comprehensive parameter setting is also required, that is, the first comprehensive variable setting submodule in the environment configuration module acquires the optimized parameter threshold.
Then, the design reading, the path group setting and the first optimization synthesis can be carried out, a comprehensive report is generated, and v is calculatedsd、asAnd VmaxAnd setting an optimized control variable tagsd. Judgment VmaxAnd if the sum is less than M, the comprehensive result can be directly output. If not, judging whether to optimize the control variable tagsdAll 0, if not all 0, tagsdSetting a new path group for each path corresponding to 1, and setting a new path group at TnowLess than TmaxThen, carrying out incremental comprehensive optimization, and if all 0 s are present, judging PnowWhether or not% is less than P%, if Pnow% is less than P%, the utilization rate of the LVT standard cell is set to max (P)step％+Pnow% P%) if Pnow% is not less than P%, then QnowWhether or not% is less than Q%, if Qnow% is less than Q%, then the ULVT standard cell utilization rate is set to max (Q)step％+Qnow%, Q%), and then a judgment T is performednowWhether or not less than TmaAt T, atnowLess than TmaxAnd then, performing incremental comprehensive optimization, and outputting a comprehensive result when a preset output condition is met.
Referring to fig. 4, an embodiment of the present application discloses a specific integrated circuit automation logic synthesis method, including:
step S11: and acquiring comprehensive parameters.
Step S12: and performing logic synthesis on the RTL code file to be synthesized according to the synthesis parameters to obtain a preliminary synthesis result.
Step S13: and generating a preliminary comprehensive report according to the preliminary comprehensive result.
Step S14: and analyzing the preliminary comprehensive report to determine an optimized control parameter.
Step S15: optimizing the path in the preliminary comprehensive result according to the optimization control parameters to obtain an optimized comprehensive result, updating the optimization control parameters according to the optimized comprehensive result, and performing iterative optimization on the optimized comprehensive result according to the updated optimization control parameters until the optimized comprehensive result meets preset output conditions to obtain a target comprehensive result.
Step S16: and outputting the target comprehensive result.
The specific implementation of the above steps can refer to the content disclosed in the foregoing embodiments, and details are not repeated herein.
Fig. 5 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present disclosure, where the electronic device 20 may specifically include, but is not limited to, a notebook computer or a desktop computer.
In general, the electronic device 20 in the present embodiment includes: a processor 21 and a memory 22.
The processor 21 may include one or more processing cores, such as a four-core processor, an eight-core processor, and so on. The processor 21 may be implemented by at least one hardware of a DSP (digital signal processing), an FPGA (field-programmable gate array), and a PLA (programmable logic array). The processor 21 may also include a main processor and a coprocessor, where the main processor is a processor for processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with a GPU (graphics processing unit) which is responsible for rendering and drawing images to be displayed on the display screen. In some embodiments, the processor 21 may include an AI (artificial intelligence) processor for processing computing operations related to machine learning.
Memory 22 may include one or more computer-readable storage media, which may be non-transitory. Memory 22 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 22 is at least used for storing the following computer program 221, wherein the steps of the integrated circuit automation logic synthesis method disclosed in any of the foregoing embodiments can be realized after the computer program is loaded and executed by the processor 21.
In some embodiments, the electronic device 20 may further include a display 23, an input/output interface 24, a communication interface 25, a sensor 26, a power supply 27, and a communication bus 28.
Those skilled in the art will appreciate that the configuration shown in FIG. 5 is not limiting of electronic device 20 and may include more or fewer components than those shown.
Further, the present application also discloses a computer readable storage medium for storing a computer program, wherein the computer program is executed by a processor to implement the integrated circuit automation logic synthesis method disclosed in any of the foregoing embodiments.
For the specific process of the integrated circuit automation logic synthesis method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and details are not repeated herein.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of other elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above detailed description is provided for an integrated circuit automation logic synthesis system, method, device and medium, and the present application applies specific examples to illustrate the principles and embodiments of the present application, and the above descriptions of the embodiments are only used to help understand the method and core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. An integrated circuit automated logic synthesis system, comprising:
the environment configuration module is used for acquiring comprehensive parameters;
the comprehensive optimization module is used for carrying out logic synthesis on the RTL code file to be synthesized according to the comprehensive parameters to obtain a preliminary synthesis result;
the report generating module is used for generating a preliminary comprehensive report according to the preliminary comprehensive result;
the report automatic analysis module is used for analyzing the preliminary comprehensive report and determining an optimized control parameter;
an iterative optimization command automatic generation module, configured to optimize a path in the preliminary comprehensive result according to the optimization control parameter to obtain an optimized comprehensive result, and invoke the report generation module and the report automatic analysis module to update the optimization control parameter according to the optimized comprehensive result, and perform iterative optimization on the optimized comprehensive result according to the updated optimization control parameter until a preset output condition is met, so as to obtain a target comprehensive result;
and the result output module is used for outputting the target comprehensive result.
2. The integrated circuit automated logic synthesis system of claim 1, wherein the environment configuration module comprises:
the path information acquisition submodule is used for acquiring the path of the RTL code file to be synthesized, the path of the synthesis constraint file and the path of the library file;
the first comprehensive variable setting submodule is used for acquiring an optimized parameter threshold, wherein the optimized parameter threshold comprises preset longest iteration time, a preset establishing time sequence maximum violation threshold, a violation value ratio threshold, the maximum utilization rate of an LVT standard unit, the maximum increment of each iteration of the LVT standard unit, the maximum utilization rate of an ULVT standard unit and the maximum increment of each iteration of the ULVT standard unit;
and the second comprehensive variable setting submodule is used for acquiring comprehensive parameters except the optimized parameter threshold.
3. The integrated circuit automated logic synthesis system of claim 2, wherein the synthesis optimization module comprises:
a design read-in submodule, configured to read in the RTL code file to be integrated, the comprehensive constraint file, and the library file according to the path of the RTL code file to be integrated, the path of the comprehensive constraint file, and the path of the library file;
the path group setting submodule is used for acquiring the preset number of path groups;
and the comprehensive execution sub-module is used for performing logic synthesis on the RTL code file to be synthesized according to the comprehensive parameters, the comprehensive constraint file and the library file to obtain a preliminary synthesis result, wherein the preliminary synthesis result comprises a plurality of path groups of the preset path group.
4. The integrated circuit automation logic synthesis system of claim 3, wherein the report generation module is to:
and generating the preliminary comprehensive report by utilizing the establishing time sequence violation values of all paths in all path groups, the current utilization rate of the LVT standard unit, the current utilization rate of the ULVT standard unit and the comprehensive elapsed time in the preliminary comprehensive result.
5. The integrated circuit automated logic synthesis system of claim 4, wherein the report auto-analysis module comprises:
the report information analysis submodule is used for determining the maximum value of the set-up time sequence violation and the average value of the set-up time sequence violation of each path group according to the set-up time sequence violation values of each path;
an analysis result output sub-module, configured to determine an optimized control variable tag of each path according to the violation value ratio of each path and the violation value ratio threshold, and output the optimized control variable tag, the maximum value of the violation of the setup time sequence, the current utilization rate of the LVT standard unit, the current utilization rate of the ULVT standard unit, and the comprehensive elapsed time as optimized control parameters;
the violation value ratio of any one path is the ratio of the establishment time sequence violation value of the path to the establishment time sequence violation average value of the path group to which the path belongs, the optimization control variable tag is 1, which indicates that the violation value ratio of the corresponding path is greater than the violation value ratio threshold, the optimization control variable tag is 0, which indicates that the violation value ratio of the corresponding path is not greater than the violation value ratio threshold.
6. The integrated circuit automated logic synthesis system of claim 5, wherein the iterative optimization command auto-generation module comprises:
the optimization control submodule is used for judging whether the optimization control variables tag are all 0 or not when the maximum value of the violation of the set time sequence is not less than the maximum violation threshold of the preset set time sequence;
a path group generation submodule, configured to set, when the optimized control variable tag is not all 0, a path for which the optimized control variable is 1 as a new path group;
the optimization control submodule is used for judging whether the current utilization rate of the LVT standard unit is less than the maximum utilization rate of the LVT standard unit when the optimization control variables tag are all 0;
the LVT standard unit utilization rate setting sub-module is used for setting optimized LVT standard unit utilization rates according to the LVT standard unit maximum utilization rate, the maximum increment of each iteration of the LVT standard unit and the LVT standard unit current utilization rate when the LVT standard unit current utilization rate is smaller than the LVT standard unit maximum utilization rate;
the optimization control sub-module is used for judging whether the current utilization rate of the ULVT standard unit is less than the maximum utilization rate of the ULVT standard unit or not when the current utilization rate of the LVT standard unit is not less than the maximum utilization rate of the LVT standard unit;
an ULVT standard unit utilization rate setting submodule, configured to set, when the current utilization rate of the ULVT standard unit is less than the maximum utilization rate of the ULVT standard unit, an optimized ULVT standard unit utilization rate according to the maximum utilization rate of the ULVT standard unit, the maximum increment of each iteration of the ULVT standard unit, and the current utilization rate of the ULVT standard unit;
and the increment optimization comprehensive execution submodule is used for carrying out establishment time sequence violation optimization on the new path group when the comprehensive elapsed time is less than the preset longest iteration time, and optimizing the path in the preliminary comprehensive result according to the optimized LVT standard unit utilization rate and the optimized ULVT standard unit utilization rate to obtain the optimized comprehensive result.
7. The integrated circuit automated logic synthesis system of claim 6, wherein the LVT standard cell utilization setting submodule is configured to:
taking the sum of the maximum increment of each iteration of the LVT standard unit and the current utilization rate of the LVT standard unit as the utilization rate of a preselected LVT standard unit;
and setting the optimized LVT standard cell utilization rate according to the maximum value of the LVT standard cell maximum utilization rate and the preselected LVT standard cell utilization rate.
8. An integrated circuit automated logic synthesis method, comprising:
acquiring comprehensive parameters;
performing logic synthesis on the RTL code file to be synthesized according to the synthesis parameters to obtain a preliminary synthesis result;
generating a preliminary comprehensive report according to the preliminary comprehensive result;
analyzing the preliminary comprehensive report to determine an optimized control parameter;
optimizing paths in the preliminary comprehensive result according to the optimization control parameters to obtain an optimized comprehensive result, updating the optimization control parameters according to the optimized comprehensive result, and performing iterative optimization on the optimized comprehensive result according to the updated optimization control parameters until the optimized comprehensive result meets preset output conditions to obtain a target comprehensive result;
and outputting the target comprehensive result.
9. An electronic device, comprising:
a memory and a processor;
wherein the memory is used for storing a computer program;
the processor configured to execute the computer program to implement the integrated circuit automation logic synthesis method of claim 8.
10. A computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the integrated circuit automation logic synthesis method of claim 8.
CN202110963117.XA 2021-08-20 2021-08-20 Integrated circuit automation logic synthesis system, method, device and medium Pending CN113705136A (en)

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* Cited by examiner, † Cited by third party
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CN114330205A (en) * 2021-12-24 2022-04-12 广东高云半导体科技股份有限公司 High-level integration method, integration device thereof and electronic equipment
CN115048885A (en) * 2022-08-12 2022-09-13 阿里巴巴（中国）有限公司 Circuit design parameter adjusting method and device, electronic equipment and storage medium
CN115796093A (en) * 2023-01-03 2023-03-14 摩尔线程智能科技(北京)有限责任公司 Circuit time sequence optimization method and device, electronic equipment and storage medium
CN116306418A (en) * 2023-05-24 2023-06-23 南京芯驰半导体科技有限公司 Timing sequence convergence method and device, electronic equipment and storage medium

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114330205A (en) * 2021-12-24 2022-04-12 广东高云半导体科技股份有限公司 High-level integration method, integration device thereof and electronic equipment
CN114330205B (en) * 2021-12-24 2024-05-17 广东高云半导体科技股份有限公司 High-level synthesis method, synthesis device thereof and electronic equipment
CN115048885A (en) * 2022-08-12 2022-09-13 阿里巴巴（中国）有限公司 Circuit design parameter adjusting method and device, electronic equipment and storage medium
CN115048885B (en) * 2022-08-12 2022-11-15 阿里巴巴（中国）有限公司 Circuit design parameter adjusting method and device, electronic equipment and storage medium
CN115796093A (en) * 2023-01-03 2023-03-14 摩尔线程智能科技(北京)有限责任公司 Circuit time sequence optimization method and device, electronic equipment and storage medium
CN115796093B (en) * 2023-01-03 2023-08-08 摩尔线程智能科技(北京)有限责任公司 Circuit time sequence optimization method and device, electronic equipment and storage medium
CN116306418A (en) * 2023-05-24 2023-06-23 南京芯驰半导体科技有限公司 Timing sequence convergence method and device, electronic equipment and storage medium

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