CN117435242B - Standard cell library generation method, device, terminal and medium - Google Patents

Standard cell library generation method, device, terminal and medium Download PDF

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CN117435242B
CN117435242B CN202311676384.4A CN202311676384A CN117435242B CN 117435242 B CN117435242 B CN 117435242B CN 202311676384 A CN202311676384 A CN 202311676384A CN 117435242 B CN117435242 B CN 117435242B
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time sequence
file
standard cell
sequence type
library
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CN117435242A (en
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张振华
郑君华
马亚奇
刘洋
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Hexin Technology Co ltd
Hexin Technology Suzhou Co ltd
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Hexin Technology Co ltd
Hexin Technology Suzhou Co ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/70Software maintenance or management
    • G06F8/71Version control; Configuration management
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/4401Bootstrapping
    • G06F9/4411Configuring for operating with peripheral devices; Loading of device drivers

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  • Computer Security & Cryptography (AREA)
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  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The application provides a standard cell library generation method, a standard cell library generation device, a standard cell library generation terminal and a standard cell library generation medium, wherein parameter setting is performed on an input target script file capable of adding constraint conditions based on acquired target project requirements; k library processing is carried out on the target script file after parameter setting according to the time sequence types so as to generate time sequence type standard unit library files corresponding to the time sequence types respectively; performing structure analysis operation on each time sequence type standard cell library file to obtain a structure analysis data set; performing matching operation on the structure analysis data set to obtain time sequence arc information corresponding to each time sequence type standard unit library file respectively; and synthesizing the time sequence arc information corresponding to each time sequence type standard cell library file respectively to obtain a final standard cell library file. The standard cell library generation method shortens the time of K library processing, can exponentially shorten the time after repeated for several times, and improves the processing efficiency.

Description

Standard cell library generation method, device, terminal and medium
Technical Field
The present disclosure relates to the field of integrated circuit design technologies, and in particular, to a method, an apparatus, a terminal, and a medium for generating a standard cell library.
Background
At present, the K library processing flow of the standard cell library file is that each parameter is set in a script, a task is submitted to a server end to run, standard cell library data file verification is carried out after standard cell library generation is waited, if the generated data does not meet the time sequence requirement, the problem is summarized, the flow is returned again, the initial parameters are modified, and verification is carried out on the file data generated again until the standard cell library of data such as reasonable time sequence is generated.
However, in the existing K library processing flow of the standard cell library file, since there are many cell modules, the K library processing time of the standard cell library is long, and the generated file is verified one by one, this process usually lasts for several tens of hours, if the time sequence and other data are not required, the parameters are modified again to re-perform the K library processing, and the processing time is doubled. Even if two K-pool processes were unsuccessful, the time span for performing K-pool processes again would be inconceivable.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present application is to provide a standard cell library generating method, device, terminal and medium, which are used for solving the problem of excessively long processing time of a K library in the prior art.
To achieve the above and other related objects, a first aspect of the present application provides a standard cell library generating method, including: based on the acquired target project requirement, parameter setting is carried out on an input target script file capable of adding constraint conditions; k library processing is carried out on the target script file after parameter setting according to the time sequence types so as to generate time sequence type standard unit library files corresponding to the time sequence types respectively; performing structure analysis operation on each time sequence type standard cell library file to obtain a structure analysis data set; performing matching operation on the structure analysis data set to obtain time sequence arc information corresponding to each time sequence type standard unit library file respectively; and synthesizing the time sequence arc information corresponding to each time sequence type standard cell library file respectively to obtain a final standard cell library file.
In some embodiments of the first aspect of the present application, performing K library processing on the target script file after parameter setting according to the time sequence type to generate a time sequence type standard cell library file corresponding to each time sequence type respectively includes: determining the time sequence type included in the target script file according to the pin type of each unit in the target script file after parameter setting; and carrying out unified K library processing on the time sequence arc information of the same time sequence type in the target script file after parameter setting so as to generate a time sequence type standard unit library file corresponding to each time sequence type respectively.
In some embodiments of the first aspect of the present application, performing a structure parsing operation on each timing type standard cell library file to obtain a structure parsed data set includes: and according to the file data structure of the time sequence type standard unit library file, carrying out information classification and attribution on each time sequence type standard unit library file to obtain a structure analysis data set.
In some embodiments of the first aspect of the present application, the file data structure of the timing type standard cell library file includes: header parameter attribute information and unit total information; wherein the unit total information includes: the pin information and the unit parameter attribute information; the said belonged pin information includes: pin parameter attribute information and timing arc information.
In some embodiments of the first aspect of the present application, performing a matching operation on the structural analysis data set, and obtaining timing arc information corresponding to each timing type standard cell library file includes: and matching the pin name corresponding to each unit name in the structure analysis data set to obtain the time sequence arc information corresponding to each time sequence type standard unit library file.
In some embodiments of the first aspect of the present application, synthesizing the timing arc information corresponding to each timing type standard cell library file to obtain a final standard cell library file includes: and carrying out information fusion on the time sequence arc information with the same unit name and pin name in each time sequence type standard unit library file so as to obtain a final standard unit library file.
In some embodiments of the first aspect of the present application, further comprising: after the final standard cell library file is obtained, data verification is carried out on the final standard cell library file so as to output the final standard cell library file which meets the sequential logic conditions and the target project requirements.
To achieve the above and other related objects, a second aspect of the present application provides a standard cell library generating device, including: the parameter setting module is used for setting parameters of the input target script file capable of adding constraint conditions based on the acquired target project requirements; the characterization module is connected with the parameter setting module and is used for carrying out K library processing on the target script file after parameter setting according to the time sequence types so as to generate time sequence type standard unit library files corresponding to the time sequence types respectively; the structure analysis module is connected with the characterization module and is used for executing structure analysis operation on each time sequence type standard unit library file so as to obtain a structure analysis data set; the time sequence arc module is connected with the structure analysis module and is used for executing matching operation on the structure analysis data set to obtain time sequence arc information corresponding to each time sequence type standard unit library file respectively; and the synthesis module is connected with the time sequence arc module and is used for synthesizing the time sequence arc information respectively corresponding to each time sequence type standard unit library file so as to obtain a final standard unit library file.
To achieve the above and other related objects, a third aspect of the present application provides a terminal, including: a processor and a memory; the memory is used for storing a computer program, and the processor is used for executing the computer program stored in the memory so as to enable the terminal to execute the standard cell library generation method.
To achieve the above and other related objects, a fourth aspect of the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the standard cell library generation method.
As described above, the standard cell library generation method, device, terminal and medium have the following beneficial effects: based on the acquired target project requirement, parameter setting is carried out on an input target script file capable of adding constraint conditions; k library processing is carried out on the target script file after parameter setting according to the time sequence types so as to generate time sequence type standard unit library files corresponding to the time sequence types respectively; performing structure analysis operation on each time sequence type standard cell library file to obtain a structure analysis data set; performing matching operation on the structure analysis data set to obtain time sequence arc information corresponding to each time sequence type standard unit library file respectively; and synthesizing the time sequence arc information corresponding to each time sequence type standard cell library file respectively to obtain a final standard cell library file. The standard cell library generation method shortens the time of K library processing, can exponentially shorten the time after repeated for several times, and improves the processing efficiency.
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Fig. 1 is a flowchart of a standard cell library generation method according to an embodiment of the present application.
FIG. 2 is a schematic diagram showing a file data structure of a timing type standard cell library file according to an embodiment of the present application.
FIG. 3 is a schematic diagram of a standard cell library generation flow in an embodiment of the present application.
Fig. 4 is a schematic structural diagram of a standard cell library generating device according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of an electronic terminal according to an embodiment of the present application.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It is noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present application. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "upper," and the like, may be used herein to facilitate a description of one element or feature as illustrated in the figures as being related to another element or feature.
In this application, unless specifically stated and limited otherwise, the terms "mounted," "connected," "secured," "held," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, operations, elements, components, items, categories, and/or groups. It will be further understood that the terms "or" and/or "as used herein are to be interpreted as inclusive, or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; A. b and C). An exception to this definition will occur only when a combination of elements, functions or operations are in some way inherently mutually exclusive.
The application provides a standard cell library generation method, a standard cell library generation device, a standard cell library generation terminal and a standard cell library generation medium, wherein parameter setting is performed on an input target script file capable of adding constraint conditions based on acquired target project requirements; k library processing is carried out on the target script file after parameter setting according to the time sequence types so as to generate time sequence type standard unit library files corresponding to the time sequence types respectively; performing structure analysis operation on each time sequence type standard cell library file to obtain a structure analysis data set; performing matching operation on the structure analysis data set to obtain time sequence arc information corresponding to each time sequence type standard unit library file respectively; and synthesizing the time sequence arc information corresponding to each time sequence type standard cell library file respectively to obtain a final standard cell library file. The standard cell library generation method shortens the time of K library processing, can exponentially shorten the time after repeated for several times, and improves the processing efficiency.
Before explaining the present invention in further detail, terms and terminology involved in the embodiments of the present invention will be explained, and the terms and terminology involved in the embodiments of the present invention are applicable to the following explanation:
(1) Timing Library file (Timing Library): the method is a library which is maintained and provided by a semiconductor process manufacturer and is expanded into ". Lib" (ASCIL code, readable) or expanded into ". Db" (binary, DC use) and is used for describing and storing the time sequence characteristics and delay information of each element in the circuit. Contained within the library are characteristics and functional information for each logic element (e.g., NAND gate, inverter, buffer, random access memory, etc.), including time unit, voltage unit, cell name, pin name, delay arc, pin load information, and power consumption information;
(2) A standard cell library (stdcell lib) is one of the timing library files. The standard cell is a pre-designed, reusable circuit cell such as a logic gate, flip-flop, etc. These standard cells have standardized interfaces and features that can be used in circuits that implement various logic functions, such as combinational logic circuits and sequential logic circuits. The standard cells in the standard cell library also contain characteristic information of each cell, such as timing characteristics, power consumption, area, and the like. Such information may help the designer evaluate the performance and limitations of the circuit and make corresponding optimizations and improvements. Standard cells are typically associated with a particular process. Different process recipes may have different standard cell libraries to accommodate different process requirements and limitations. The designer needs to select the corresponding standard cell library according to the actual process. Therefore, generally, when the chip process iteration is lifted, K library processing is performed on the standard cell library based on different parameters according to project requirements, so that a standard cell library file corresponding to the target parameters is generated;
(3) A Timing arc (Timing arc) for describing the indivisible path Timing information from one pin to another pin;
(4) K library (standard cell library characterization extraction): the characteristics of standard cells are characterized in lib form to form a ". Time Library file".
In order to make the objects, technical solutions and advantages of the present invention more apparent, further detailed description of the technical solutions in the embodiments of the present invention will be given by the following examples with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 1, a flowchart of a standard cell library generation method in an embodiment of the present invention is shown.
The standard cell library generation method comprises the following steps:
step S101: and setting parameters of the input target script file capable of adding constraint conditions based on the acquired target project requirements.
In one embodiment, the target item requirements are related to the process. Specifically, the library of standard cells is typically associated with a particular process. The process refers to a specific semiconductor manufacturing process and its design rules, and different processes mean different circuit characteristics. The kinds of the process include: 90nm, 65nm, 28nm, etc. Different process recipes may have different standard cell libraries to accommodate different process requirements and limitations. The designer usually needs to obtain the corresponding standard cell library by performing parameter setting according to the actual process.
In one embodiment, the target script files to which constraints can be added are char.tcl and ccs.tcl scripts that can generate lib files (standard cell library files).
In one embodiment, the parameter setting is actually adding a corresponding constraint in the target script file. Based on the acquired target project requirement, adding corresponding constraint conditions in the input target script file capable of adding the constraint conditions.
Step S102: and carrying out K library processing on the target script file after parameter setting according to the time sequence types to generate time sequence type standard unit library files corresponding to the time sequence types respectively.
In one embodiment, the timing types include, but are not limited to: setup time, hold time, and delay time.
In an embodiment, performing K library processing on the target script file after parameter setting according to the time sequence type to generate a time sequence type standard cell library file corresponding to each time sequence type respectively includes: determining the time sequence type included in the target script file according to the pin type of each unit in the target script file after parameter setting; and carrying out unified K library processing on the time sequence arc information of the same time sequence type in the target script file after parameter setting so as to generate a time sequence type standard unit library file corresponding to each time sequence type respectively.
In one embodiment, the object script file includes a plurality of cells (cells), each cell including: one or more pins (pins), each pin having a different timing type. And determining the time sequence types included in the target script file through the time sequence types of pins of all cells (cells) in the target script file after the parameter setting. For example, the target script file after the parameter setting includes an a unit, where the a unit includes three pins a, b, and c, the timing type of the pin a is the setup time, the timing type of the pin b is the hold time, and the type of the pin c is the setup time. Then, the timing type included in the target script file is the setup time as well as the hold time.
And after determining the time sequence types included in the target script file, respectively carrying out unified K library processing on the time sequence arc information of the same time sequence type in the target script file after parameter setting. It is assumed that there are n timing types in the parameter-set target script file, where the value of n depends on the timing types of pins of all units in the parameter-set target script file. Then, n K library processing tasks are required to be executed on the target script file after the parameter setting, and in each K library processing task, only one type of time sequence arc information is processed uniformly to generate a time sequence type standard unit library file corresponding to the type. The n K library processing tasks may be executed simultaneously, and after the execution of the n K library processing tasks is completed, n timing type standard unit library files may be generated.
For example, the timing type of the target script file after the parameter setting includes the setup time, the hold time, and the delay time, and then three K library processing tasks need to be performed on the target script file after the parameter setting. In a first K library processing task, uniformly processing time sequence arc information of the set-up time to generate a time sequence type standard unit library file corresponding to the set-up time; in a second K library processing task, uniformly processing the time sequence arc information of the holding time to generate a time sequence type standard unit library file corresponding to the holding time; and in the third K library processing task, uniformly processing the time sequence arc information of the delay time to generate a time sequence type standard unit library file corresponding to the delay time.
The method for respectively carrying out the K library processing according to the time sequence type can shorten the time of the K library processing, and the time can be shortened in an exponential form after repeated for several times, thereby improving the efficiency.
Step S103: and executing structure analysis operation on each time sequence type standard unit library file to obtain a structure analysis data set.
In one embodiment, performing a structure parsing operation on each timing type standard cell library file to obtain a data set includes: and according to the file data structure of the time sequence type standard unit library file, carrying out information classification and attribution on each time sequence type standard unit library file to obtain a structure analysis data set. After the structure analysis data set is obtained, a technician can take data in the structure analysis data set according to actual requirements.
In one embodiment, as shown in fig. 2, the file data structure of the time sequence type standard cell library file includes: header parameter attribute information and unit total information; wherein the unit total information includes: the pin information and the unit parameter attribute information; the said belonged pin information includes: pin parameter attribute information and timing arc information.
In one embodiment, the header parameter attribute information is constraint condition information added in the target script file; the unit total information includes: unit type information, unit parameter attribute information and belonging pin information; the unit parameter attribute information includes, but is not limited to: timing characteristics, power consumption, area, etc., are not exhaustive; the pin information includes: the attribution relation information of the pins and the units and the attribute information of the pin parameters; the pin parameter attribute information includes, but is not limited to: pin input load (input load), pin output load (output load), output type (output type), etc., which are not exhaustive herein. It should be noted that, the timing arc is data for describing delay information of two nodes, and the information of the timing arc is generally divided into a wire delay and a unit delay. The connection delay is delay information between the output port of the unit and the fan-out network load; the unit delay is delay information between the input port and the output port of the unit. Thus, the timing information calculation for a complete path consists of link delays and cell delays.
The structure-resolving operation will be explained in detail below by way of example: assuming that a time sequence type standard unit library file comprises A information, B information and C information, determining the category of the A information as pin parameter attribute information and attributing the A information to the pin parameter attribute information, determining the category of the B information as unit parameter attribute information and attributing the B information to the unit parameter attribute information, determining the category of the C information as time sequence arc information and attributing the C information to the time sequence arc information.
Step S104: and executing matching operation on the structure analysis data set to obtain the time sequence arc information corresponding to each time sequence type standard unit library file.
In an embodiment, a pin name (pin name) corresponding to each cell name (cell name) is matched in the structural analysis data set, so as to obtain timing arc information corresponding to each timing type standard cell library file.
Note that each unit name corresponds to a plurality of timing arc information.
Step S105: and synthesizing the time sequence arc information corresponding to each time sequence type standard cell library file respectively to obtain a final standard cell library file.
In one embodiment, synthesizing the timing arc information corresponding to each timing type standard cell library file to obtain a final standard cell library file includes: and carrying out information fusion on the time sequence arc information with the same unit name and pin name in each time sequence type standard unit library file so as to obtain a final standard unit library file.
Specifically, in the file structure of the standard cell library, the cells (cells) include pins (pins) that include timing arc information, so it is necessary to determine to which pin and which cell the timing arc information belongs. And then fusing various time sequence arc information with the same unit name and the same pin name in each time sequence type standard unit library file into one file, wherein the file is the final standard unit library file.
In one embodiment, the standard cell library generating method further includes: after the final standard cell library file is obtained, data verification is carried out on the final standard cell library file so as to output the final standard cell library file which meets the sequential logic conditions and the target project requirements.
It should be noted that, the data verification is to check and verify the data in the final standard cell library file to determine whether the final standard cell library file can meet the sequential logic condition and the requirement of the target item.
In one embodiment, if the final standard cell library file cannot pass the data verification, the parameter setting is performed again on the target script file to which the constraint condition can be added, and then step S102, step S103, step S104 and step S105 are repeatedly performed until the final standard cell library file meeting the sequential logic condition and the target project requirement is obtained and output.
To better illustrate the standard cell library generation method, a specific embodiment is now provided.
Embodiment one: a standard cell library generation flow diagram.
As shown in fig. 3, parameter setting is performed on the provided script file based on the acquired target item requirements. After the parameter setting is performed, based on each time sequence type (timing type), the script files after the parameter setting are respectively and simultaneously subjected to K library (charlib) processing so as to generate time sequence type standard unit library files (.lib files) corresponding to the time sequence types. And carrying out structural analysis on each time sequence type standard unit library file (.lib file) to obtain a structural analysis data set. Each timing arc information (timing arc) and a cell name (cell name) and a pin name (pin name) corresponding to each timing arc information (timing arc) are acquired. And (3) corresponding the unit names and the time sequence arc information with the same pin names in each time sequence type standard unit library file (lib file) one by one and synthesizing to obtain a new standard library file (new lib file). And (3) performing data verification (QA verification) on the new standard cell library file obtained after synthesis, and outputting the new standard cell library file if the new standard cell library file meets the requirements (meets the sequential logic conditions and the target project requirements). If not, setting parameters of the provided script file again and then carrying out K library processing.
Similar to the above-described embodiments, the present invention provides a standard cell library generating apparatus.
Specific embodiments are provided below with reference to the accompanying drawings:
as shown in fig. 4, a schematic structural diagram of a standard cell library generating device according to an embodiment of the present invention is shown.
The standard cell library generating device 4 includes:
the parameter setting module 41 is configured to perform parameter setting on an input target script file to which constraint conditions can be added based on the acquired target project requirement;
the characterization module 42 is connected with the parameter setting module 41, and is configured to perform K library processing on the target script file after parameter setting according to the time sequence type, so as to generate a time sequence type standard cell library file corresponding to each time sequence type respectively;
the structure analysis module 43 is connected with the characterization module 42 and is used for executing structure analysis operation on each time sequence type standard cell library file to obtain a structure analysis data set;
the time sequence arc module 44 is connected with the structure analysis module 43 and is used for executing matching operation on the structure analysis data set to obtain time sequence arc information corresponding to each time sequence type standard unit library file respectively;
and the synthesis module 45 is connected with the time sequence arc module 44, and is used for synthesizing the time sequence arc information respectively corresponding to each time sequence type standard unit library file so as to obtain a final standard unit library file.
It should be noted that, it should be understood that the division of the modules of the above apparatus is merely a division of a logic function, and may be fully or partially integrated into a physical entity or may be physically separated. And these modules may all be implemented in software in the form of calls by the processing element; or can be realized in hardware; the method can also be realized in a form of calling software by a processing element, and the method can be realized in a form of hardware by a part of modules. For example, the parameter setting module 41 may be a processing element that is set up separately, may be implemented in a chip of the above-described apparatus, or may be stored in a memory of the above-described apparatus in the form of program codes, and the functions of the parameter setting module 41 may be called and executed by a processing element of the above-described apparatus. The implementation of the other modules is similar. In addition, all or part of the modules can be integrated together or can be independently implemented. The processing element described herein may be an integrated circuit having signal processing capabilities. In implementation, each step of the above method or each module above may be implemented by an integrated logic circuit of hardware in a processor element or an instruction in a software form.
For example, the modules above may be one or more integrated circuits configured to implement the methods above, such as: one or more application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC), or one or more microprocessors (digital signal processor, abbreviated as DSP), or one or more field programmable gate arrays (Field Programmable Gate Array, abbreviated as FPGA), or the like. For another example, when a module above is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processor that may invoke the program code. For another example, the modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
In an embodiment, performing K library processing on the target script file after parameter setting according to the time sequence type to generate a time sequence type standard cell library file corresponding to each time sequence type respectively includes: determining the time sequence type included in the target script file according to the pin type of each unit in the target script file after parameter setting; and carrying out unified K library processing on the time sequence arc information of the same time sequence type in the target script file after parameter setting so as to generate a time sequence type standard unit library file corresponding to each time sequence type respectively.
In one embodiment, performing a structure parsing operation on each timing type standard cell library file to obtain a structure parsed data set includes: and according to the file data structure of the time sequence type standard unit library file, carrying out information classification and attribution on each time sequence type standard unit library file to obtain a structure analysis data set.
In one embodiment, the file data structure of the time sequence type standard cell library file includes: header parameter attribute information and unit total information; wherein the unit total information includes: the pin information and the unit parameter attribute information; the said belonged pin information includes: pin parameter attribute information and timing arc information.
In an embodiment, performing a matching operation on the structure analysis data set to obtain timing arc information corresponding to each timing type standard cell library file includes: and matching the pin name corresponding to each unit name in the structure analysis data set to obtain the time sequence arc information corresponding to each time sequence type standard unit library file.
In one embodiment, synthesizing the timing arc information corresponding to each timing type standard cell library file to obtain a final standard cell library file includes: and carrying out information fusion on the time sequence arc information with the same unit name and pin name in each time sequence type standard unit library file so as to obtain a final standard unit library file.
In an embodiment, the standard cell generating device further includes: the verification module is used for generating the standard cell library and further comprises the following steps: after the final standard cell library file is obtained, data verification is carried out on the final standard cell library file so as to output the final standard cell library file which meets the sequential logic conditions and the target project requirements.
It should be noted that, the modules provided in this embodiment may implement all the functions of the methods provided above, and the implementation manners are similar, so that the description is omitted.
Fig. 5 is a schematic structural diagram of a terminal according to an embodiment of the present invention.
The terminal 5 includes: a processor 52 and a memory 51; the memory 51 is used for storing a computer program; the processor 52 is configured to execute the computer program stored in the memory, so that the terminal 5 executes the standard cell library generating method as described in fig. 1.
Alternatively, the number of the memories 51 may be one or more, and the number of the processors 52 may be one or more, and one is taken as an example in fig. 5.
Optionally, the processor 52 in the control device loads one or more instructions corresponding to the process of the application program into the memory 51 according to the steps as described in fig. 1, and the processor 52 executes the application program stored in the first memory, thereby implementing various functions in the standard cell library generating method as described in fig. 1.
Optionally, the memory 51 may include, but is not limited to, high speed random access memory, nonvolatile memory. Such as one or more disk storage devices, flash memory devices, or other non-volatile solid-state storage devices; the processor 52 may include, but is not limited to, a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), etc.; but also digital signal processors (Digital Signal Processing, DSP for short), application specific integrated circuits (Application Specific Integrated Circuit, ASIC for short), field-programmable gate arrays (Field-Programmable Gate Array, FPGA for short) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
Alternatively, the processor 52 may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), etc.; but also digital signal processors (Digital Signal Processing, DSP for short), application specific integrated circuits (Application Specific Integrated Circuit, ASIC for short), field-programmable gate arrays (Field-Programmable Gate Array, FPGA for short) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
The present invention also provides a computer readable storage medium storing a computer program which when run implements a standard cell library generation method as described in fig. 1. The computer-readable storage medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs (compact disk-read only memories), magneto-optical disks, ROMs (read-only memories), RAMs (random access memories), EPROMs (erasable programmable read only memories), EEPROMs (electrically erasable programmable read only memories), magnetic or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing machine-executable instructions. The computer readable storage medium may be an article of manufacture that is not accessed by a computer device or may be a component used by an accessed computer device.
In some embodiments of the invention, the computer-readable and writable storage medium may include read-only memory, random-access memory, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, U-disk, removable hard disk, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. In addition, any connection is properly termed a computer-readable medium. For example, if the instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable and data storage media do not include connections, carrier waves, signals, or other transitory media, but are intended to be directed to non-transitory, tangible storage media. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.
In summary, the present application provides a standard cell library generating method, device, terminal and medium, which perform parameter setting on an input target script file capable of adding constraint conditions based on an acquired target project requirement; k library processing is carried out on the target script file after parameter setting according to the time sequence types so as to generate time sequence type standard unit library files corresponding to the time sequence types respectively; performing structure analysis operation on each time sequence type standard cell library file to obtain a structure analysis data set; performing matching operation on the structure analysis data set to obtain time sequence arc information corresponding to each time sequence type standard unit library file respectively; and synthesizing the time sequence arc information corresponding to each time sequence type standard cell library file respectively to obtain a final standard cell library file. The standard cell library generation method shortens the time of K library processing, can exponentially shorten the time after repeated for several times, and improves the processing efficiency. Therefore, the method effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles of the present application and their effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications and variations which may be accomplished by persons skilled in the art without departing from the spirit and technical spirit of the disclosure be covered by the claims of this application.

Claims (8)

1. A standard cell library generation method, comprising:
based on the acquired target project requirement, parameter setting is carried out on an input target script file capable of adding constraint conditions;
k library processing is carried out on the target script file after parameter setting according to the time sequence types so as to generate time sequence type standard unit library files corresponding to the time sequence types respectively;
k library processing is carried out on the target script file after parameter setting according to the time sequence types, so that the time sequence type standard unit library file corresponding to each time sequence type respectively is generated, and the method comprises the following steps: determining the time sequence type included in the target script file according to the pin type of each unit in the target script file after parameter setting; performing unified K library processing on time sequence arc information of the same time sequence type in the target script file after parameter setting so as to generate time sequence type standard unit library files corresponding to each time sequence type respectively;
performing structure analysis operation on each time sequence type standard cell library file to obtain a structure analysis data set;
wherein performing a structure parsing operation on each of the timing type standard cell library files to obtain a structure parsed data set includes: according to the file data structure of the time sequence type standard unit library file, carrying out information classification and attribution on each time sequence type standard unit library file to obtain a structure analysis data set;
performing matching operation on the structure analysis data set to obtain time sequence arc information corresponding to each time sequence type standard unit library file respectively;
and synthesizing the time sequence arc information corresponding to each time sequence type standard cell library file respectively to obtain a final standard cell library file.
2. The method of claim 1, wherein the file data structure of the time series type standard cell library file comprises: header parameter attribute information and unit total information; wherein the unit total information includes: the pin information and the unit parameter attribute information; the said belonged pin information includes: pin parameter attribute information and timing arc information.
3. The method of claim 1, wherein performing a matching operation on the set of structural analysis data to obtain timing arc information corresponding to each of the timing type standard cell library files comprises:
and matching the pin name corresponding to each unit name in the structure analysis data set to obtain the time sequence arc information corresponding to each time sequence type standard unit library file.
4. The method of claim 3, wherein synthesizing the timing arc information corresponding to each of the timing type standard cell library files to obtain a final standard cell library file comprises:
and carrying out information fusion on the time sequence arc information with the same unit name and pin name in each time sequence type standard unit library file so as to obtain a final standard unit library file.
5. The method as recited in claim 1, further comprising: after the final standard cell library file is obtained, data verification is carried out on the final standard cell library file so as to output the final standard cell library file which meets the sequential logic conditions and the target project requirements.
6. A standard cell library generating apparatus, comprising:
the parameter setting module is used for setting parameters of the input target script file capable of adding constraint conditions based on the acquired target project requirements;
the characterization module is connected with the parameter setting module and is used for carrying out K library processing on the target script file after parameter setting according to the time sequence types so as to generate time sequence type standard unit library files corresponding to the time sequence types respectively;
k library processing is carried out on the target script file after parameter setting according to the time sequence types, so that the time sequence type standard unit library file corresponding to each time sequence type respectively is generated, and the method comprises the following steps: determining the time sequence type included in the target script file according to the pin type of each unit in the target script file after parameter setting; performing unified K library processing on time sequence arc information of the same time sequence type in the target script file after parameter setting so as to generate time sequence type standard unit library files corresponding to each time sequence type respectively;
the structure analysis module is connected with the characterization module and is used for executing structure analysis operation on each time sequence type standard unit library file so as to obtain a structure analysis data set;
wherein performing a structure parsing operation on each of the timing type standard cell library files to obtain a structure parsed data set includes: according to the file data structure of the time sequence type standard unit library file, carrying out information classification and attribution on each time sequence type standard unit library file to obtain a structure analysis data set;
the time sequence arc module is connected with the structure analysis module and is used for executing matching operation on the structure analysis data set to obtain time sequence arc information corresponding to each time sequence type standard unit library file respectively;
and the synthesis module is connected with the time sequence arc module and is used for synthesizing the time sequence arc information respectively corresponding to each time sequence type standard unit library file so as to obtain a final standard unit library file.
7. A terminal, comprising: a processor and a memory;
the memory is used for storing a computer program;
the processor is configured to execute the computer program stored in the memory, so as to cause the terminal to perform the method according to any one of claims 1 to 5.
8. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the method of any one of claims 1 to 5.
CN202311676384.4A 2023-12-08 2023-12-08 Standard cell library generation method, device, terminal and medium Active CN117435242B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160055283A1 (en) * 2014-08-22 2016-02-25 Samsung Electronics Co., Ltd. Standard cell library, method of using the same, and method of designing semiconductor integrated circuit
CN112100158A (en) * 2020-09-21 2020-12-18 海光信息技术有限公司 Standard cell library establishing method and device, electronic equipment and storage medium
CN112149380A (en) * 2020-09-29 2020-12-29 海光信息技术股份有限公司 Index analysis method and device of standard cell library
CN114065676A (en) * 2021-11-24 2022-02-18 成都海光微电子技术有限公司 Standard cell library forming method and related device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160055283A1 (en) * 2014-08-22 2016-02-25 Samsung Electronics Co., Ltd. Standard cell library, method of using the same, and method of designing semiconductor integrated circuit
CN112100158A (en) * 2020-09-21 2020-12-18 海光信息技术有限公司 Standard cell library establishing method and device, electronic equipment and storage medium
CN112149380A (en) * 2020-09-29 2020-12-29 海光信息技术股份有限公司 Index analysis method and device of standard cell library
CN114065676A (en) * 2021-11-24 2022-02-18 成都海光微电子技术有限公司 Standard cell library forming method and related device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
A comprehensive standard cell library qualification to prevent lithographic challenges;Xinyi Hu等;SPIE;20200523;1-6 *
一种近阈值电压标准单元特征化建库方法;胡伟等;湖南大学学报;20190430;第46卷(第4期);1-6 *

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