CN117423736A - Semiconductor device, method of manufacturing the same, and method of forming continuous metal cap - Google Patents

Abstract

The semiconductor device includes: a gate structure above the semiconductor substrate, having a high dielectric coefficient dielectric layer, a P-type work function layer, an N-type work function layer, a dielectric anti-reaction layer and a glue layer; and a continuous metal cap over the gate structure, formed by: a metal material is deposited over the gate structure, portions of the anti-reaction layer are selectively removed, and additional metal material is deposited over the gate structure. The manufacturing method comprises the following steps: receiving a gate structure; planarizing the top layer of the gate structure; pre-cleaning and pre-treating the surface of the grid structure; depositing a metal material over the gate structure to form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer; depositing additional metal material over the gate structure to create a continuous metal cap; inhibit the growth of the metal cap. The present disclosure also relates to a method of forming a continuous metal cap over a metal gate structure.

Description

Semiconductor device, method of manufacturing the same, and method of forming continuous metal cap

Technical Field

The embodiment of the disclosure relates to a semiconductor device and a manufacturing method thereof.

Background

Semiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit features and elements thereon.

The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually shrinking the minimum feature size, which allows more features to be integrated into a given area. However, as the minimum component size shrinks, other problems that should be solved arise.

Disclosure of Invention

One embodiment of the present disclosure is a semiconductor device. The semiconductor device includes a gate structure over a semiconductor substrate and a continuous metal cap over the gate structure. The gate structure includes: a high-k dielectric layer; a P-type work function layer; an N-type work function layer; an anti-reaction layer comprising a dielectric material; and (5) an adhesive layer. The continuous metal cover is formed by: depositing a metal material over the gate structure during a plurality of first deposition operations, the metal material forming a discontinuous metal cap; selectively removing a portion of the anti-reaction layer during a plurality of first wet chemical operations; depositing additional metal material over the gate structure during a plurality of second deposition operations to create a continuous metal cap; and the continuous metal cap is inhibited from growing during the plurality of second wet chemical operations.

Another embodiment of the present disclosure is a method of forming a continuous metal cap over a metal gate structure, comprising: the gate structure is received and has a high-k dielectric layer, a P-work-function layer, an N-work-function layer, an anti-reaction layer comprising a dielectric material, and a glue layer. The method also includes pre-treating the surface of the gate structure with an oxidation or nitridation process; depositing a metal material over the gate structure using a plurality of first deposition operations, which form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer using a plurality of first wet chemical operations; depositing additional metal material over the gate structure using a plurality of second deposition operations to create a continuous metal cap; and inhibiting continued metal cap growth using a plurality of second wet chemistry operations.

Yet another embodiment of the present disclosure is a method of manufacturing a semiconductor device, comprising: the gate structure is received and comprises a high-dielectric-coefficient dielectric layer, a P-type work function layer, an N-type work function layer, a dielectric anti-reaction layer and a glue layer. The method for manufacturing the semiconductor device further comprises: using oxygen (O) ₂ ) Or hydrogen/nitrogen (H) ₂ /N ₂ ) The surface of the grid structure is pretreated by plasma treatment; depositing a first metal material comprising a tungsten (W) material or a molybdenum (Mo) material over the gate structure using a plurality of first atomic layer deposition ALD) operations, which form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer using dilute hydrofluoric acid; depositing a second metal material comprising tungsten or molybdenum over the gate structure using a plurality of second atomic layer deposition operations to create a continuous metal cap; inhibiting growth of the metal cap by removing unwanted metal material from the plurality of side spacers by a wet etching operation using an ozone solution; and forming a Via Gate (VG) over the metal cap. Forming a via gate over a metal cap includes forming an opening through an interlayer dielectric (ILD) material using a plurality of etching operations to contact the metal cap and depositing a metal material in the opening using a plurality of deposition operations.

Drawings

A full disclosure is provided in accordance with the following detailed description, taken in conjunction with the accompanying drawings. It should be noted that the various components are not necessarily drawn to scale in accordance with the general practice of the industry. In fact, the dimensions of the various features may be arbitrarily expanded or reduced for clarity.

Fig. 1 is a flow chart illustrating an exemplary method of semiconductor fabrication including the fabrication of a multi-gate device, in accordance with some embodiments.

Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A are isometric views depicting exemplary semiconductor devices according to some embodiments.

Fig. 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B are cross-sectional side views illustrating exemplary semiconductor devices along one embodiment of the first cut X-X' according to some embodiments.

Fig. 11 is a flow chart depicting an exemplary fabrication method for fabricating a continuous metal cap over a metal gate for use with subsequently fabricated Via Gate (VG) conductors, in accordance with some embodiments.

Fig. 12A-12H are diagrams depicting enlarged views of an exemplary semiconductor gate structure at various stages of fabrication of a continuous metal cap over a metal gate, in accordance with some embodiments.

Fig. 13 is a process flow diagram depicting an exemplary method of further semiconductor fabrication including metal drain fabrication and via gate fabrication, in accordance with some embodiments.

Fig. 14A-14E are diagrams depicting enlarged views of exemplary regions at various stages of semiconductor fabrication including metal drain fabrication and via gate fabrication, in accordance with some embodiments.

Fig. 15 is a graph showing that forming a continuous metal cap over a metal gate structure in a semiconductor device may result in a decrease in gate resistance.

Wherein reference numerals are as follows:

100, 1100, 1300: method of

102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118, 1120, 1122, 1302, 1304, 1306, 1308, 1310, 1312, 1314, 1316, 1318, 1320, 1322: block block

200: semiconductor device with a semiconductor device having a plurality of semiconductor chips

202: substrate board

204: epitaxial stacking

206 Epitaxial layer 208

210: fin-shaped element

302: STI component

304: gate stack

402: spacer material layer

602: oxide layer

702: source/drain feature

802: interlayer dielectric (ILD) layer

1002: gate stack

1004: high dielectric coefficient gate dielectric layer

1006: metal layer

1200: gate structure

1201: gate stack

1202: adhesive layer

1204: anti-reaction layer

1206: n-type work function layer

1208: p-type work function layer

1210: high dielectric coefficient interlayer dielectric material

1212: gate spacer

1214: plasma treatment

1215: average value of

1216: discontinuous metal cover

1217: additional metallic material

1218: concave part

1220: continuous metal cover

1222: through-hole grid (VG)

1224: interlayer dielectric (ILD)

1400: region(s)

1402: substrate board

1404: source/drain regions

1406: patterning mask

1409: silicide contacts

X-X': first incision

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. The following disclosure describes specific examples of various components and arrangements thereof to simplify the description. Of course, these specific examples are not intended to be limiting.

For the sake of brevity, conventional techniques related to conventional semiconductor device fabrication may not be described in detail herein. Moreover, the various operations and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. In particular, various processes in the manufacture of semiconductor devices are well known, and thus, for the sake of brevity, many conventional processes will only be briefly mentioned herein or will be omitted entirely without providing well known process details. As will be apparent to those skilled in the art upon a complete reading of the present disclosure, the structures disclosed herein may be used with a variety of techniques and may be incorporated in a variety of semiconductor devices and products. Further, it should be noted that the semiconductor device structure includes a different number of components, and that a single component shown in the drawings may represent multiple components.

Moreover, spatially relative terms such as "above," "overlying," "below," "upper," "top," "below," "under," "bottom," and the like in … … are used herein for convenience in describing the relationship of one element or component to another element(s) or component in the drawings. In addition to the orientations depicted in the drawings, these spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be turned to a different orientation (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly. When spatially relative terms such as those listed above are used to describe a first element relative to a second element, the first element may be directly on top of the other element or intervening elements or layers may be present. When an element or layer is referred to as being "on" or "over" another element or layer, it is directly on and in contact with the other element or layer.

Further, the present disclosure may repeat reference numerals and/or indicia in various examples. These repetition are for the purpose of simplicity and clarity and do not in itself dictate a particular relationship between the various embodiments and/or configurations discussed.

It should be noted that references in the specification to "one embodiment," "an example," etc., indicate that the embodiment described may include a particular element, structure, or characteristic, but every embodiment may not necessarily include the particular element, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular component, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such component, structure, or characteristic in connection with other embodiments whether or not explicitly described.

It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings herein.

Various embodiments are discussed herein in the specific context, namely, for forming semiconductor structures including fin-like field-effect transistor (FinFET) devices. The semiconductor structure may be, for example, a Complementary Metal Oxide Semiconductor (CMOS) device including a P-type metal oxide semiconductor (PMOS) FinFET device and an N-type metal oxide semiconductor (NMOS) FinFET device. Embodiments will now be described with respect to specific examples including FinFET fabrication procedures. However, the embodiments are not limited to the examples provided herein, and the concepts may be implemented in a wide variety of embodiments. Thus, various embodiments may be applied to other semiconductor devices/processes, such as planar transistors and the like. Furthermore, some embodiments discussed herein are discussed in the context of devices formed using a gate-last process. In other embodiments, a gate-first process (gate-first process) may be used.

Although the drawings depict various embodiments of the semiconductor device, additional components may be added to the semiconductor device depicted in the drawings, and in other embodiments of the semiconductor device, some of the components described below may be replaced, modified, or removed.

Additional operations may be provided before, during, and/or after the stages described in these embodiments. Some of the stages described may be replaced or eliminated for different embodiments. Additional components may be added to the semiconductor device structure. Some of the components described below may be replaced or eliminated for different embodiments. Although some embodiments are discussed as operations performed in a particular order, the operations may be performed in another logical order.

It should also be noted that the present disclosure presents embodiments in the form of a multi-gate transistor. The multi-gate transistor includes a transistor having a gate structure formed over at least two sides of a channel region. These multi-gate devices may include P-type metal oxide semiconductor devices or N-type metal oxide semiconductor multi-gate devices. Because of their fin structure, specific examples may be presented and referred to herein as finfets. Embodiments of a multi-gate transistor referred to as a gate-all-around (GAA) device are also presented herein. GAA devices include any device whose gate structure or portions thereof are formed on four sides of (e.g., around a portion of) a channel region. The devices presented herein also include embodiments having channel regions disposed in nanowire channels, stripe channels, and/or other suitable channel configurations. Presented herein are embodiments of devices that may have one or more channel regions (e.g., nanowires) associated with a single contiguous (configured) gate structure. However, one of ordinary skill will appreciate that this teaching may be applied to a single channel (e.g., a single nanowire) or any number of channels. One of ordinary skill in the art may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure.

Fig. 1 is a flow chart illustrating an exemplary method 100 of semiconductor fabrication including the fabrication of a multi-gate device. As used herein, the term "multi-gate device" is used to describe a device (e.g., a semiconductor transistor) having at least some gate material disposed over multiple sides of at least one channel of the device. In some examples, the multi-gate device may be referred to as a GAA device having gate material disposed over at least four sides of at least one channel of the device. The channel region may be referred to herein as a "nanowire," which includes channel regions of various geometries (e.g., cylindrical, bar-shaped) and various sizes.

Fig. 1 is described in conjunction with fig. 2A-2B, 3A-3B, 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9A-9B, and 10A-10B, which depict a structure of a semiconductor device 200 or various stages of fabrication, according to some embodiments. The method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly recited in the claims. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be moved, replaced, or eliminated for other embodiments of the method 100. Additional components may be added to the semiconductor device 200 depicted in the drawings, and some of the components described below may be replaced, modified, or eliminated in other embodiments.

As with the other method embodiments and example devices discussed herein, it should be appreciated that a portion of a semiconductor device may be manufactured by typical semiconductor technology process flows, and thus some processes are only briefly described herein. In addition, the exemplary semiconductor device may include various other devices and components, such as other types of devices, such as additional transistors, bipolar junction transistors (bipolar junction transistor), resistors, capacitors, inductors, dials, fuses, and/or other logic devices, etc., but are simplified for easier understanding of the concepts of the present disclosure. In some embodiments, an exemplary device includes a plurality of semiconductor devices (e.g., transistors), including PFETs, NFETs, etc., which may be interconnected. Furthermore, it should be noted that the process steps of method 100, including any description given with reference to the drawings, as well as the remainder of the methods and exemplary drawings provided in this disclosure, are exemplary only and are not intended to limit this disclosure to what is explicitly recited in the claims.

According to some embodiments, fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A are isometric views of an exemplary semiconductor device 200, while fig. 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B are cross-sectional side views of the exemplary semiconductor device 200 corresponding to one embodiment along a first kerf X-X' during one exemplary manufacturing process. In the drawings, some reference signs of the components or features depicted therein may be omitted to avoid obscuring other components or features; this is for convenience in drawing the drawings.

In block 102, the exemplary method 100 includes providing a substrate 202. Referring to the examples of fig. 2A and 2B, in an embodiment of block 102, a substrate 202 is provided. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon substrate. The substrate 202 may include various layers including a conductive layer or an insulating layer formed over a semiconductor substrate. The substrate 202 may comprise various doping configurations according to design requirements known in the art. For example, different doping profiles (e.g., n-well, p-well) may be formed over the substrate 202 in regions designed for different device types (e.g., n-type field effect transistor (NFET), p-type field effect transistor (PFET)), suitable doping may include ion implantation and/or diffusion processes of dopants.

Returning to fig. 1, the method 100 then proceeds to block 104 where one or more epitaxial layers are grown over the substrate. Referring to the example of fig. 2A and 2B, in the embodiment of block 104, an epitaxial stack 204 is formed over a substrate 202. The epitaxial stack 204 includes a plurality of epitaxial layers 206 of a first composition, the epitaxial layers 206 being interposed by a plurality of epitaxial layers 208 of a second composition. The first component and the second component may be different. In one embodiment, epitaxial layer 206 is silicon germanium and epitaxial layer 208 is silicon (Si). However, other embodiments may also include embodiments that provide the first component and the second component with different oxidation rates and/or etch selectivities. In some embodiments, epitaxial layer 206 comprises SiGe and where epitaxial layer 208 comprises Si, the oxidation rate of Si of epitaxial layer 208 is less than the oxidation rate of SiGe of epitaxial layer 206.

The epitaxial layer 208 or portions thereof may form a channel region of the multi-gate device 200. For example, the epitaxial layer 208 may be referred to as a "nanowire" for forming a channel region of a multi-gate device 200, such as a GAA device. These "nanowires" are also used to form part of the source/drain regions of the multi-gate device 200 as described below. The source/drain regions may refer to sources or drains, individually or collectively depending on the context. Also, as the term is used herein, "nanowire" refers to semiconductor layers of cylindrical shape and other configurations, such as strips. The use of epitaxial layer 208 to define one or more channels of the device is discussed further below.

It should be noted that the four (4) layers of each of epitaxial layers 206 and 208 are depicted in fig. 2A-2B and 3A-3B for illustrative purposes only and are not intended to limit the present disclosure to what is explicitly recited in the claims. It is understood that any number of epitaxial layers may be formed in epitaxial stack 204; the number of layers depends on the number of channel regions required for the device 200. In some embodiments, the number of epitaxial layers 208 is between 2 and 10.

In some embodiments, epitaxial layer 206 has a thickness in the range of about 2-6 nanometers (nm). The thickness of epitaxial layer 206 may be substantially uniform. In some embodiments, epitaxial layer 208 has a thickness in the range of about 6-12 nm. In some embodiments, the thickness of the stacked epitaxial layers 208 is substantially uniform. As described in more detail below, the epitaxial layer 208 may be used as a channel region for a subsequently formed multi-gate device, and its thickness is selected based on device performance considerations. Epitaxial layer 206 may be used to define the gap distance between adjacent channel regions for subsequently formed multi-gate devices, and its thickness is selected based on device performance considerations.

For example, epitaxial growth of the layers of stack 204 may be performed by a Molecular Beam Epitaxy (MBE) process, a Metal Organic Chemical Vapor Deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layer, such as layer 208, comprises the same material as substrate 202. In some embodiments, the epitaxially grown layers 206, 208 comprise a different material than the substrate 202. As described above, in at least some examples, epitaxial layer 206 comprises an epitaxially grown silicon germanium (SiGe) layer and epitaxial layer 208 comprises an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either of the epitaxial layers 206, 208 may include other materials such as germanium, compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide), alloy semiconductors (e.g., siGe, gaAsP, alInAs, alGaAs, inGaAs, gaInP and/or GaInAsP), or combinations thereof. As discussed, the material of the epitaxial layers 206, 208 may be selected based on providing different oxidation, etch selectivity characteristics. In various embodiments, the epitaxial layers 206, 208 are substantially free of dopants (i.e., have about 0cm ^-3 Up to about 1X 10 ¹⁷ cm ^-3 For example, no intentional doping is performed during the epitaxial growth process.

Next, the method 100 proceeds to block 106 where fin elements are patterned and formed. Referring to the example of fig. 2A, in the embodiment of block 106, a plurality of fin elements 210 extending from substrate 202 are formed. In various embodiments, each fin element 210 includes a substrate portion formed from substrate 202, and a portion of each epitaxial layer of the epitaxial stack includes epitaxial layers 206 and 208.

Fin element 210 may be fabricated using suitable processes including photolithography and etching processes. The photolithography process may include forming a photoresist layer over the substrate 202 (e.g., over the epitaxial stack 204), exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask element may be performed using an electron beam (e-beam) photolithography process. The regions of the substrate 202 and the layer 204 formed thereon may then be protected using a masking element, while an etching process forms trenches in the unprotected regions through the masking layer (e.g., a hard mask), leaving behind a plurality of extended fins. The trenches may be etched using dry etching (e.g., reactive ion etching), wet etching, and/or other suitable processes. The trenches may be filled with a dielectric material to form shallow trench isolation features, such as an interposed fin.

In some embodiments, the dielectric layer may comprise silicon dioxide (SiO ₂ ) Silicon nitride, silicon oxynitride, fluorine doped silicate glass (FSG), low-k dielectric, combinations thereof, and/or other suitable materials known in the art. In various examples, the dielectric layer may be deposited by a Chemical Vapor Deposition (CVD) process, a sub-atmospheric pressure chemical vapor deposition (sub-atmospheric chemical vapor deposition, SACVD) process, a flowable chemical vapor deposition process, an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, and/or other suitable processes. In some embodiments, after depositing the dielectric layer, the device 200 may be annealed, for example, to improve the quality of the dielectric layer. In some embodiments, the dielectric layer (and subsequently formed Shallow Trench Isolation (STI) feature 302) may comprise a multi-layer structure, for example, having one or more liners (liner layers).

In some embodiments, after depositing the dielectric layer, the deposited dielectric material is thinned and planarized, such as by a Chemical Mechanical Polishing (CMP) process, in some embodiments where isolation (STI) features are formed. The CMP process may planarize the top surface to form STI features 302. The STI feature 302 that inserts the fin-like element is recessed. Referring to the example of fig. 3A, STI feature 302 is recessed to provide fin element 210 extending over STI feature 302. In some embodiments, the recessing process may include a dry etching process, a wet etching process, and/or a combination thereof. In some embodiments, the recess depth is controlled (e.g., by controlling the etch time) to produce a desired height "H" of the exposed upper portions of fin elements 210. The height "H" exposes each layer of the epitaxial stack 204.

Many other embodiments of methods of forming fins over a substrate may also be used, including, for example, defining fin regions (e.g., through a mask or isolation region) and epitaxially growing epitaxial stack 204 in the form of fins. In some embodiments, forming the fins may include a trimming process to reduce the width of the fins. The trimming process may include a wet or dry etching process.

The method 100 then proceeds to block 108 where a sacrificial layer/feature, particularly a dummy gate structure, is formed. While the present discussion is directed to a replacement gate process whereby dummy gate structures are formed and subsequently replaced, other configurations are possible.

Referring to fig. 3A and 3B, a gate stack 304 is formed. In an embodiment, the gate stack 304 is a dummy (sacrificial) gate stack that is subsequently removed as discussed with reference to block 108 of method 100.

Thus, in some embodiments using a post-gate process, the gate stack 304 is a dummy gate stack and will be replaced with a final gate stack at a later stage of processing of the device 200. In particular, gate stack 304 may be replaced with a high-k dielectric layer (HK) and a metal gate electrode (MG) at a later stage of processing as described below. In some embodiments, gate stack 304 is formed over substrate 202 and is at least partially disposed over fin element 210. The portion of fin element 210 under gate stack 304 may be referred to as a channel region. The gate stack 304 may also define source/drain regions of the fin-shaped element 210, e.g., regions of the fin and epitaxial stack 204 adjacent to and on opposite sides of the channel region.

In some embodiments, the gate stack 304 includes a dielectric layer and a dummy electrode layer. The gate stack 304 may also include one or more hard mask layers (e.g., oxide, nitride). In some embodiments, the gate stack 304 is formed by various process steps, such as layer deposition, patterning, etching, and other suitable process steps. Exemplary layer deposition processes include chemical vapor deposition (including low pressure chemical vapor deposition and plasma-assisted chemical vapor deposition), physical vapor deposition, atomic layer deposition, thermal oxidation, electron beam evaporation, other suitable deposition techniques, or combinations thereof. For example, the patterning process may include a photolithography process (e.g., photolithography or e-beam lithography), which may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and/or hard baking), other suitable photolithography techniques, and/or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and/or other etching methods.

As described above, the gate stack 304 may include an additional gate dielectric layer. For example, the gate stack 304 may include silicon oxide. Alternatively or additionally, the gate dielectric layer of the gate stack 304 may comprise silicon nitride, a high-k dielectric material, or other suitable material. In some embodiments, the electrode layer of the gate stack 304 may comprise polysilicon (polysilicon). Hard mask layers, e.g. SiO ₂ 、Si ₃ N ₄ Silicon oxynitride, optionally comprising silicon carbide and/or may also comprise other suitable components.

Next, the method 100 proceeds to block 110 where a layer of spacer material is deposited over the substrate. Referring to the example of fig. 4A and 4B, a layer of spacer material 402 is disposed over the substrate 202. The layer of spacer material 402 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, siCN film, silicon oxycarbide, siOCN film, and/or combinations thereof. In some embodiments, the spacer material layer 402 includes multiple layers, such as main spacers, liners, and the like. For example, the layer of spacer material 402 may be formed by depositing a dielectric material over the gate stack 304 using, for example, a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. It should be noted that the spacer material layer 402 is depicted in fig. 4A and 4B as covering the epitaxial stack 204.

In some embodiments, depositing the layer of spacer material is followed by (e.g., anisotropically) etching back the dielectric spacer material. Referring to the example, referring to the example of fig. 5A, 5B, after forming the spacer material layer 402, the spacer material layer 402 may be etched back to expose portions (e.g., source/drain regions) of the fin element 210 adjacent to the gate stack 304 but not covered by the gate stack 304. A layer of spacer material may remain over the sidewalls of the gate stack 304 forming the spacer elements. In some embodiments, the etchback of the spacer material layer 402 may include a wet etch process, a dry etch process, a multi-step etch process, and/or combinations thereof. As shown in fig. 5A and 5B, the spacer material layer 402 may be removed from the top surface of the exposed epitaxial stack 204 and the side surfaces of the exposed epitaxial stack 204.

The method 100 then proceeds to block 112 where an oxidation process is performed. Due to the different oxidation rates of the multiple layers of epitaxial stack 204, the oxidation process may be referred to as selective oxidation, with particular layers being oxidized. In some examples, the oxidation process may be performed by exposing the apparatus 200 to a wet oxidation process, a dry oxidation process, or a combination thereof. In at least some embodiments, the apparatus 200 is exposed to a wet oxidation process using steam or steam as an oxidant at a pressure of about 1ATM for a time of about 0.5 to 2 hours at a temperature in the range of about 400 to 600 ℃. It should be noted that the oxidation process conditions provided herein are exemplary only and not intended to be limiting. It should be noted that in some embodiments, this oxidation process may be extended such that the oxidized portion of the stacked epitaxial layers abuts the sidewalls of gate stack 304.

Referring to the example of fig. 6A and 6B, in the embodiment of block 112, the device 200 is exposed to an oxidation process that fully oxidizes the epitaxial layer 206 of each of the plurality of fin elements 210. Epitaxial layer 206 is converted into oxide layer 602. The oxide layer 602 extends to the gate stack 304, including extending under the spacer elements 402. In some embodiments, the oxide layer 602 has a thickness in the range of about 5 to about 25 nanometers (nm). In one embodiment, the oxide layer 602 may comprise silicon germanium oxide (SiGeOx).

For example, in embodiments where epitaxial layer 206 comprises SiGe and epitaxial layer 208 comprises Si, a faster (i.e., compared to Si) SiGe oxidation rate ensures that epitaxial layer 206 is fully oxidized while minimizing or eliminating oxidation of other epitaxial layers 208. It should be appreciated that any of the various materials discussed above may be selected for each of the first epitaxial layer and the second epitaxial layer portions to provide different suitable oxidation rates.

The method 100 then proceeds to block 114 where source/drain features are formed over the substrate. The source/drain features may be formed by performing an epitaxial growth process by providing an epitaxial material over fin elements 210 in the source/drain regions. In one embodiment, the epitaxial material of the source/drain is formed to cover the portion of the epitaxial layer that remains in the source/drain regions of the fin. Referring to the example of fig. 7A and 7B, source/drain features 702 are formed on substrate 202, in/on fin element 210, adjacent to and associated with gate stack 304. The source/drain features 702 comprise a material formed by epitaxially growing a semiconductor material over the exposed epitaxial layer 208 and/or oxide layer 602. It should be noted that the shape of source/drain feature 702 is merely illustrative and not limiting; as will be appreciated by those of ordinary skill in the art, any epitaxial growth will occur over the semiconductor material (e.g., 208) rather than the dielectric material (e.g., 602), and the epitaxial growth may be grown as shown such that it merges over the dielectric layer (e.g., 602).

In various embodiments, the grown semiconductor material of source/drain features 702 may comprise Ge, si, gaAs, alGaAs, siGe, gaAsP, siP or other suitable materials. In some embodiments, the material of the source/drain features 702 may be in-situ (in-situ) doped during the epitaxial process. For example, in some embodiments, the epitaxially grown material may be doped with boron. In some embodiments, the epitaxially grown material may be doped with carbon to form Si: c source/drain features doped with phosphorus to form Si: p source/drain features, or carbon and phosphorus doped to form SiCP source/drain features. In one embodiment, the epitaxial material of source/drain feature 702 is silicon, as is layer 208. In some embodiments, layers 702 and 208 may comprise similar materials (e.g., si), but are doped differently. In other embodiments, the epitaxial layer for the source/drain features 702 comprises a first semiconductor material and the epitaxially grown material 208 comprises a second semiconductor material different from the first semiconductor material. In some embodiments, the epitaxially grown material of source/drain features 702 is not doped in situ, but rather, an implantation process is performed, for example.

The method 100 then proceeds to block 116 where an inter-layer dielectric (ILD) layer is formed over the substrate. Referring to the example of fig. 8A and 8B, in the embodiment of block 116, an interlayer dielectric layer 802 is formed over the substrate 202. In some embodiments, a contact etch stop layer (contact etch stop layer, CESL) is formed over the substrate 202 prior to forming the ILD layer 802. In some examples, the CESL includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and/or other materials known in the art. CESL may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation process. In some embodiments, ILD layer 802 comprises, for example, tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (e.g., borophosphosilicate glass (borophosphosilicate glass, BPSG), fused silica glass (fused silica glass, FSG), phosphosilicate glass (phosphosilicate glass, PSG), boron doped silicate glass (boron doped silicon glass, BSG)), and/or other suitable dielectric materials. ILD layer 802 may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after forming the ILD layer 802, the semiconductor device 200 may be subjected to a high thermal budget process (high thermal budget process) to anneal the ILD layer.

In some examples, after depositing the ILD (and/or CESL or other dielectric layer), a planarization process may be performed to expose the top surface of the gate stack 304. For example, the planarization process includes a chemical mechanical planarization (chemical mechanical planarization, CMP) process that removes portions of the ILD layer 802 (and CESL layer, if present) overlying the gate stack 304 and planarizes the top surface of the semiconductor device 200.

The method 100 then proceeds to block 118 where the dummy gate (see block 108) is removed. The gate and/or gate dielectric layer may be removed by a suitable etching process. In some embodiments, block 118 also includes selectively removing the epitaxial layer in the channel region of the device. In an embodiment, the selected epitaxial layer is removed in fin elements within the trench provided by removing the dummy electrode (e.g., the fin region, or channel region, over and above which the gate structure is to be formed). Referring to the example of fig. 9A and 9B, epitaxial layer 206 is removed from within the channel region and trench of substrate 202. In some embodiments, epitaxial layer 206 is removed by a selective wet etch process. In some embodiments, the selective wet etch includes HF. In an embodiment, epitaxial layer 206 is SiGe and epitaxial layer 208 is silicon, which allows SiGe epitaxial layer 206 to be selectively removed.

The method 100 then proceeds to block 120 where a gate structure is formed. The gate structure may be a gate of a multi-gate transistor. The final gate structure may be a high dielectric coefficient/metal gate stack, but other compositions are also possible. In some embodiments, the gate structure forms a gate associated with a multi-channel provided by a plurality of nanowires in the channel region (now with gaps therebetween). Exemplary embodiments of gate structures will be discussed in more detail.

Referring to the example of fig. 10A and 10B, in one embodiment of block 120, a high dielectric coefficient/metal gate stack 1002 is formed within a trench of device 200 provided by removing and/or releasing the dummy gate from the nanowire, as described above with reference to block 118. In various embodiments, the high-k/metal gate stack 1002 includes an interfacial layer, a high-k gate dielectric layer 1004 formed over the interfacial layer, and/or a metal layer 1006 formed over the high-k gate dielectric layer 1004. As used and described herein, a high-k gate dielectric layer comprises a dielectric material having a high dielectric coefficient, e.g., a dielectric coefficient greater than thermal silicon oxide (-3.9). The metal layer used within the high dielectric coefficient/metal gate stack may comprise a metal, a metal alloy, or a metal silicide. In addition, the formation of the high dielectric coefficient/metal gate stack may include deposition to form various gate materials, one or more liners, one or more CMP processes to remove excess gate materials, thereby planarizing the top surface of the semiconductor device 200.

In some embodiments, the interfacial layer of the gate stack 1002 may comprise a dielectric material, such as silicon oxide (SiO) ₂ ) HfSiO or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), and/or other suitable methods. The gate dielectric layer 1004 of the gate stack 1002 may comprise a high-k dielectric layer, such as hafnium oxide (HfO ₂ ). Alternatively, the gate dielectric layer 1004 of the gate stack 1002 may comprise other high-k dielectrics, such as TiO ₂ 、HfZrO、Ta ₂ O ₃ 、HfSiO ₄ 、ZrO ₂ 、ZrSiO ₂ 、LaO、AlO、ZrO、TiO、Ta ₂ O ₅ 、Y ₂ O ₃ 、SrTiO ₃ (STO)、BaTiO ₃ (BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba，Sr)TiO ₃ (BST)、Al ₂ O ₃ 、Si ₃ N ₄ Nitrogen oxides (e.g., siON), combinations thereof, or other suitable materials. The high-k gate dielectric layer 1004 may be formed by ALD, physical Vapor Deposition (PVD), CVD, oxidation, and/or other suitable methods. The metal layer of the high dielectric coefficient/metal gate stack 1002 may comprise a single layer or a multi-layer structure, such as a metal layer having a work function selected to enhance device performance (work function metal layer), an underlayer, a wetting layer, an adhesion layer, a metal alloy, or various combinations of metal silicides. For example, the metal layer of the gate stack 1002 may include Ti, ag, al, tiAlN, taC, taCN, taSiN, mn, zr, tiN, taN, ru, mo, al, WN, cu, W, re, ir, co, ni, other suitable metal materials, or a combination thereof. In various embodiments, the metal layer of the gate stack 1002 may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Furthermore, the metal layers of gate stack 1002 may be formed separately for N-FET and P-FET transistors that may use different metal layers. In various embodiments, a CMP process may be performed to remove excess metal from the metal layer of the gate stack 1002, providing a substantially planar top surface of the metal layer of the gate stack 1002. The metal layer 1006 of the gate stack 1002 is depicted in fig. 10A and 10B. In addition, the metal layer may provide an N-type or P-type work function, may be used as a transistor (e.g., finFET) gate electrode, and in at least some embodiments, a gate stack The metal layer of stack 1002 may comprise a polysilicon layer. The gate structure 1002 includes portions inserted into each epitaxial layer 306, each of which forms a channel of the multi-gate device 200.

In some embodiments, an anti-reactive layer may be included in the gate stack 1002 to prevent oxidation. In some embodiments, the anti-reactive layer may comprise a dielectric material. In some embodiments, the anti-reactive layer may comprise a silicon-based (silicon-based) material. In some embodiments, the anti-reaction layer may comprise silicon (Si), silicon oxide (SiO _x ) Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbide (SiC), combinations thereof, or multilayers or the like. However, any suitable material may be used. The anti-reactive layer may be conformally deposited using a deposition process such as ALD, CVD, PVD. The anti-reaction layer may be deposited to a thickness of about 0.3nm to about 5 nm.

In some embodiments, a glue layer may be included in the gate stack 1002. The glue layer may comprise any acceptable material to promote adhesion and prevent diffusion. For example, the glue layer may be formed of a metal or metal nitride, such as titanium nitride, titanium aluminide, titanium aluminum nitride, silicon doped titanium nitride, tantalum nitride, or the like, which may be deposited by a process similar to ALD, CVD, PVD.

In one embodiment, the gate structure includes a high-k dielectric layer, a p-type work function layer over the high-k dielectric layer, an n-type work function layer over the p-type work function layer, an anti-reaction layer over the n-type work function layer, and a glue layer over the anti-reaction layer. The gate structure may include different or additional layers, or the previously discussed layers may be omitted. The layers of the gate structure may also be deposited in a different order. The additional layers may include barrier layers, diffusion layers, adhesion layers, combinations thereof, or multilayers or the like. In some embodiments, the additional layer may comprise a chlorine (Cl) or similar containing material. Additional layers may be deposited by ALD, CVD, PVD or similar processes.

The method 100 then proceeds to block 122 where further fabrication is performed. The semiconductor device may undergo further processing to form various components and regions known in the art. For example, subsequent processing may form contact openings, contact metals, and various contacts/vias/lines and multi-layer interconnect features (e.g., metal layers and inter-layer dielectric layers) on the substrate configured to connect the various features to form functional circuits that may include one or more multi-gate devices. In further examples, the multi-level interconnect may include a vertical interconnect (e.g., a via or contact) and a horizontal interconnect (e.g., a metal line). Various interconnect features may employ various conductive materials, including copper, tungsten, and/or silicide. In one example, damascene and/or dual damascene processes are used to form copper-related multi-layer interconnect structures. Furthermore, additional process steps may be performed before, during, and after the method 100, and some of the process steps described previously may be replaced or removed according to various embodiments of the method 100.

Fig. 11 is a flow chart illustrating an exemplary method 1100 of further semiconductor fabrication after forming a metal gate structure, including fabricating a continuous metal cap for use with a subsequently fabricated via gate conductor. Fig. 11, described in conjunction with fig. 12A-12G, illustrates a semiconductor device or structure at various stages of fabrication in accordance with some embodiments. Method 1100 is merely an example and is not intended to limit the present disclosure to what is explicitly recited in the claims. Additional steps may be provided before, during, and after the method 1100, and some of the steps described may be moved, replaced, or deleted for other embodiments of the method 1100. Additional components may be added to the semiconductor device depicted in the drawings, and some of the components described below may be replaced, modified, or removed in other embodiments.

Fig. 12A-12G are diagrams depicting enlarged views of an exemplary gate structure 1200 (similar to the top shown in fig. 2B-10B) at various stages of fabricating a metal cap over a metal gate stack, in accordance with some embodiments. In the drawings, some reference signs of the components or features depicted therein may be omitted to avoid obscuring other components or features; this is for convenience in drawing the drawings.

A metal cap may be formed over the metal gate structure as a medium for connecting the Via Gate (VG) conductor to the metal gate structure. The use of a metal cap to connect the VG conductors to the metal gate structure may reduce gate resistance (Rg) compared to directly connecting the VG conductors to the metal gate structure. Thus, the use of a metal cover may improve device performance.

An anti-reaction layer may be included in the metal gate structure to prevent oxidation of the P-metal and N-metal and to improve device performance. However, the anti-reaction layer may prevent the formation of a metal cap over the metal gate structure. The method 1100 presents an exemplary process for forming a metal cap over a metal gate structure without impeding the formation of the metal cap, and also for gate height scaling with a metal cap thickness of about 3-4 nm.

At block 1102, the exemplary method 1100 includes receiving a gate structure having a high-k dielectric layer, a p-type work function layer over the high-k dielectric layer, an n-type work function layer over the p-type work function layer, an anti-reactive layer over the n-type work function layer, and a glue layer over the anti-reactive layer.

At block 1104, the top layer of the gate structure is planarized using a planarization process to create a horizontal surface by removing excess material. The planarization process may be, for example, a Chemical Mechanical Polishing (CMP) process, an etchback process, a combination thereof, or the like.

Fig. 12A shows an exemplary gate structure 1200 (similar to the top portion shown in fig. 2B-10B) after Metal Gate (MG) formation and after the planarization process is completed in block 1104. The example gate structure 1200 includes a plurality of gate spacers 1212 and an MG or gate stack 1201. The example gate stack 1201 includes a high-k interlayer dielectric material 1210, a p-type work function layer 1208 adjacent to the high-k interlayer dielectric (ILD) material 1210, an n-type work function layer 1206 adjacent to the p-type work function layer 1208, an anti-reaction layer 1204 adjacent to the n-type work function layer 1206, and a glue layer 1202 adjacent to the anti-reaction layer 1204.

The example gate stack 1201 may be used with an n-channel metal oxide semiconductor (NMOS) or a p-channel metal oxide semiconductor (PMOS). In embodiments for use with NMOS semiconductor devices, the gate stack 1201 may include an N-metal layer 1206 and a P-metal layer 1208, or the gate stack 1201 may include only the N-metal layer 1206 and no P-metal layer 1208. In embodiments for use with PMOS semiconductor devices, the gate stack 1201 may include an N-metal layer 1206 and a P-metal layer 1208, or the gate stack 1201 may include only the P-metal layer 1208 without the N-metal layer 1206.

At block 1106, the surface of the gate structure is pre-cleaned to remove any excess soil or particles to ensure successful coverage of the gate structure during subsequent deposition operations. In one embodiment, the surface of the gate structure is pre-cleaned by rinsing with Deionized (DI) aqueous solution. For example, in one embodiment, deionized water solution may be delivered for about 28 seconds. The cleaning solution may be at ambient temperature or may be heated or cooled to a different temperature.

At block 1108, the surface of the gate structure is pre-treated to achieve surface modification (surface modification) and selective growth assistance. In some embodiments, the pretreatment is a plasma treatment 1214, such as oxygen (O) ₂ ) Plasma or nitrogen/hydrogen (N) ₂ /H ₂ ) And (3) plasma. In some embodiments, a light plasma treatment (light plasma treatment) is applied. After the pretreatment process, a portion of the titanium nitride in the metal gate layers 1206 and 1208 has been converted to titanium oxide or titanium oxynitride. In various embodiments, the pretreatment may be used for metal gates such as nitride-based, carbide-based, and pure metals (e.g., co acid and Al base) based on an optimization process. O (O) ₂ And N ₂ /H ₂ The method is suitable for preprocessing TiN, taC and TiC-based metal gates through process adjustment.

The plasma treatment process may be a plasma cleaning operation comprising hydrogen (H) at a temperature of about 100 ℃ to 300 °c ₂ ) And nitrogen (N) ₂ ). In an exemplary embodiment, by controlling the gas flow, hydrogen: the ratio of nitrogen may range from about 10:1 to about 2:1, but other ratios may be used in other exemplary embodiments. In an exemplary embodiment, about 500 to about 5000 sccm H ₂ And about 500 to about 10000sscm N ₂ Can be used at pressures of about 0.5 torr to about 50 torr and at an inductively coupled plasma source power of 2500 watts. In other exemplary embodiments, the power used in the cleaning chamber may range from about 150W to about 3000W. Plasma pretreatment is used to passivate the surface of the gate structure rather than sputtering.

Fig. 12B shows the gate structure 1200 after the pre-cleaning in block 1106 and the pre-processing in block 1108 are completed. The pretreatment results in surface modification using plasma treatment 1214.

At block 1110, a metal material is deposited over the metal gate stack using selective deposition. The metallic material may be deposited by CVD or ALD. In an exemplary embodiment, the metallic material is deposited by an ALD process. During deposition, the chloride in the precursor reacts with the titanium oxide in the metal gate stack 1201, forming recesses in the P-metal 1208, N-metal 1206, and high dielectric material. The difference in etch rate (delta) between the metal and the high dielectric constant material affects the amount of high dielectric constant material etched and the slope of the recess in the high dielectric constant material. A metal material is selectively deposited in the recess and over the high dielectric coefficient material 1210, P-metal 1208 and N-metal 1206 layers of the gate stack 1201. In various embodiments, WCl ₅ WOCL which reacts with surface Ti-O to form vapor form _x And TiOCl _y 。TiOCl _y The steam is extracted to assist in forming the recess. The metal material forms a discontinuous metal cap 1216 over the gate stack 1201. Because the anti-reaction layer has dielectric-like properties, the growth of the metal cap over the anti-reaction layer is suppressed.

The metal cap 1216 may be, for example, tungsten (W) or molybdenum (Mo). In some examples, WCl ₅ For depositing a W cap over the anti-reaction layer 1204, the anti-reaction layer 1204 may be formed of, for example, silicon nitride (SiN) or silicon oxide (SiO _x ) Is composed of a silicon-containing material.

In embodiments where the conductive cover material comprises tungsten, tungsten chloride (WCl) may be used at a temperature ranging from about 300 ℃ to about 500 ℃ and a process pressure ranging from about 10 torr to about 50 torr ₅ ) Precursor, hydrogen (H) ₂ ) Deposition of conductive gases by reducing gas and argon (Ar) carrier gasAnd a cover material. The tungsten chloride precursor may be provided at a temperature in the range of about 100 ℃ to about 150 ℃. In some embodiments, the conductive cover material may further comprise chlorine in an atomic concentration ranging from about 0.5% to about 5%. Alternatively, a similar ALD process may be used with molybdenum chloride (MoCl) ₅ ) Precursor, hydrogen (H) ₂ ) The reducing gas and argon (Ar) carrier gas deposit Mo to form a Mo cap.

After the deposition process of block 1110 is completed, a discontinuous metal cap 1216 has been formed over the metal gate stack 1201. In some embodiments, the thickness of the discontinuous metal cap 1216 is about 1-2 nm. The thickness of the discontinuous metal cap 1216 may be non-uniform and may be determined by TEM analysis due to the high atomic order of W relative to the metal gate. Portions of metal cap 1216 are used as an etch mask during subsequent processing steps to ensure that P-metal 1208 and N-metal 1206 are not damaged during removal of a portion of anti-reactive layer 1204 by block 1112.

Fig. 12C depicts the gate structure 1200 after the deposition of metal material to form a portion of the metal cap at block 1110. The gate structure 1200 has been modified to include a discontinuous metal cap 1216.

The anti-reaction layer 1204 inhibits deposition of metallic material because WCl is compared to the rest of the gate stack ₅ The reactivity with the dielectric surface of the anti-reactive layer is low. A portion of the anti-reaction layer will be selectively removed to allow additional metal material to be deposited to create a continuous metal cap over the gate stack 1201. The anti-reactive layer 1204 may be composed of a silicon-containing material. In some embodiments, the anti-reactive layer 1204 may be SiN or SiO _x . The anti-reactive layer 1204 protects the P-metal 1208 and the N-metal 1206 from the etching process, improving characteristics of the metal cap 1220, such as threshold voltage shift (V _ts ) And prevents degradation (degradation). However, due to the dielectric properties of the silicon-containing material, the anti-reactive layer 1204 inhibits metal capping.

At block 1112, a portion of the anti-reactive layer 1204 is selectively removed to leave a plurality of recesses 1218. The removal of the anti-reaction layer 1204 proceeds to a depth where the discontinuous metal cap 1216 has been deposited, which may be about 1-2 nm, with the depth of the recesses being the average 1215, the recesses being defined as the gap toward the surface of the spacer. Thus, a portion of the anti-reaction layer 1204 is removed such that the depth of the resulting recess 1218 is approximately equal to the thickness of the discontinuous metal cap 1216. Removal of a portion of the anti-reaction layer 1204 may be accomplished by a wet chemical process. The wet chemical process dissolves and removes the anti-reaction layer 1204 (which may comprise silicon oxide or another dielectric material), but the wet chemical process does not dissolve a portion of the metal material of the metal cap 1216. The presence of the partial metal cap 1216 protects the P-metal 1208 and the N-metal 1206 from the wet chemical process. In one embodiment, the entire gate structure 1200 is rinsed with an etching solution.

The etching solution may be diluted hydrofluoric acid (HF). HF was diluted with deionized water. In some embodiments, the volume ratio of HF to deionized water is about 1:500. In other embodiments, the volume ratio of HF to deionized water is about 1:2000. Alternatively, the etching solution may be MR1, for example. Etching solution MR1 contains 1 part ammonium hydroxide (NH) ₄ OH), about 1 to about 10 parts hydrogen peroxide (H ₂ O ₂ ) And about 5 to about 30 parts of water (H ₂ O). In some embodiments, other etching solutions may be used, or the components of the etching solutions may be mixed in different proportions.

Fig. 12D illustrates the gate structure 1200 after a portion of the anti-reactive layer 1204 is selectively removed at block 1112 to form a recess 1218.

At block 1114, additional metal material is deposited to form a continuous metal cap 1220. In some embodiments, the process in block 1114 is the same as the process in block 1110. In other embodiments, variations of the process in block 1110 are used in block 1114. In other embodiments, a different deposition process is used in block 1114 than in block 1110.

Additional metal material is deposited over the metal gate structure 1200. The metallic material may be deposited by CVD, ALD, electroless deposition (electroless deposition, ELD), PVD, electroplating, combinations thereof, or another deposition technique. In an exemplary embodiment, the metallic material is deposited by an ALD process. The metal material deposited at block 1114 fills recess 1218 to form a continuous metal cap 1220 over metal gate stack 1201. The metal material may also partially cover the spacers 1212.

The metallic material deposited in block 1114 is the same as the metallic material deposited in block 1110 and may be, for example, W or Mo. In exemplary embodiments, tungsten chloride (WCl) may be used at a temperature ranging from about 300 ℃ to about 500 ℃ and a process pressure of about 10 torr to about 50 torr ₅ ) Precursor, hydrogen (H) ₂ ) The reduction gas and argon (Ar) carrier gas deposit W. In some embodiments, the conductive cover material may further comprise chlorine in an atomic concentration ranging from about 0.5% to about 5%. Alternatively, the precursor may be tungsten fluoride (WF) ₆ ) Or molybdenum chloride (MoCl) ₅ )。

The ALD cycle or other deposition process is controlled to obtain a desired thickness of the metal cap 1220. In some embodiments, the metal deposited in block 1114 has a thickness of about 2nm, such that the thickness of the entire metal cap 1220 is about 3-4 nm. In various embodiments, the thickness is limited to 3-4 nm to take advantage of gate reduction without affecting RC delay, as thicker metals may increase the overall gate height and gate capacitance. The first metal cap from the first metal cap deposition process serves as a protective layer to prevent metal damage from the wet process and to a final thickness through the second metal cap deposition process.

Fig. 12E illustrates the gate structure 1200 after additional metal material is deposited in block 1114 to create a continuous metal cap 1220. In some embodiments, the additional metallic material is the same type of metallic material as that used for the discontinuous metallic cover. In some embodiments, the additional metal material 1217 is different from the metal material of the discontinuous metal cap 1216, forming a double layer metal cap, such as Mo over W or W over Mo, as shown in fig. 12F.

At block 1116, lateral growth of the metal cap 1220 is reduced and excess material is removed using a wet chemical process. The metal cap 1220 is constrained so that it covers the metal gate stack 1201 but not the sidewall spacers 1212. The sidewall spacers 1212 may be constructed of, for example, silicon, carbide, or nitrideAnd (3) forming the finished product. In some embodiments, an ozone solution (e.g., ozone deionized water solution (DIO ₃ ) A) the growth of the metal cap 1220 is restricted. Alternatively, hot deionized water (HDI) may be used at a temperature of about 40 ℃ to about 80 ℃.

In one embodiment, the growth of the metal cap is inhibited by applying a solution of deionized water and ozone for a period of time ranging from about 5 seconds to about 60 seconds. In some embodiments, the solution comprises ozone and hydrochloric acid mixed in water. In an exemplary embodiment, the solution comprises DIO at a concentration of 5 to 100ppm at room temperature ₃ And HCl at a concentration of 1:1 to about 1:50 at a temperature of about 25 ℃ to about 50 ℃.

Fig. 12G depicts the gate structure 1200 after lateral growth reduction in block 1116. The continuous metal cap 1220 is now constrained so that it does not cover the spacers 1212.

One of the benefits of the continuous metal cap 1220 is that it can reduce the gate resistance of the metal gate stack 1201. The reduced gate resistance results in a higher overall performance of the semiconductor device. In an exemplary embodiment, the semiconductor device having the continuous metal cap 1220 has a gate resistance that is about 80% lower than a semiconductor device without the continuous metal cap 1220. Fig. 15 illustrates the difference between the gate resistance obtainable for a semiconductor device with a continuous metal cap 1220 and the gate resistance that may be experienced without the metal cap. In the example of fig. 15, the target gate resistance is about 300-400 ohms per square (Ω/sq), measured by a four-point probe, without the metal cap 1220. Using the metal cap 1220, the target resistance is reduced to about 80 Ω/sq.

At block 1118, the example method 1100 includes a metal drain fabrication operation to form a Metal Drain (MD) over the source/drain regions. The metal drain fabrication operations may include removing exposed portions of the ILD layer to form openings exposing underlying source/drain structures. The exposed portions of the ILD layer may be removed by a suitable etching process, such as wet etching, dry etching, or a combination thereof. During etching of the ILD layer, the etchant is selected to provide etch selectivity between the ILD layer and other structures (e.g., gate spacers 1212 and metal cap 1220). For example, the ILD layer has a lower etch resistance to the etchant than the gate spacer 1212 and the metal cap 1220 such that the ILD layer may be etched while leaving the gate spacer 1212 and the metal cap 1220 substantially intact.

The metal drain fabrication operations (block 1118) may also include removing the patterned mask and forming source/drain contacts in the openings. Forming the source/drain contacts in the openings may include filling the openings contacting the source/drain regions with a conductive material to form the source/drain contacts. The source/drain contacts may include one or more layers. For example, in some embodiments, the source/drain contacts include liners and metal fill materials deposited by, for example, CVD, ALD, electroless deposition (ELD), PVD, electroplating, or another deposition technique. The liner (e.g., diffusion barrier, adhesion layer, or the like) may comprise titanium, titanium nitride, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, ruthenium, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess liner and conductive material. The remaining liner and conductive material form source/drain contacts 702 in the openings.

At block 1120, the example method 1100 includes a via gate fabrication operation to form a Via Gate (VG). The via gate fabrication operations may include forming openings through an interlayer dielectric (ILD) material to contact the metal cap 1220. The openings for the via gate fabrication operations may be formed using acceptable photolithography and etching techniques. The via gates may be deposited by CVD, ALD, electroless deposition (ELD), PVD, electroplating, or other deposition techniques.

Fig. 12H shows the gate structure 1200 after forming VG 1222. Metal Drains (MD) (not shown) and inter-layer dielectric (ILD) 1224 have also been formed. VG 1222 may be or contain tungsten, cobalt, copper, ruthenium, aluminum, gold, silver, alloys thereof, analogues thereof or combinations thereof. MD may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, ruthenium, nickel, or the like. ILD 1224 is a low dielectric coefficient material such as an oxide.

At block 1122, the example method 1100 includes performing further manufacturing operations. The semiconductor device may undergo further processing to form various components and regions known in the art. For example, subsequent processing may form contact openings, contact metals, and various contacts/vias/lines and multi-layer interconnect features (e.g., metal layers and interlayer dielectrics) over the substrate configured to connect the various features to form functional circuits that may include one or more multi-gate devices. In further examples, the multi-layer interconnect may include a vertical interconnect (e.g., a via or contact) and a horizontal interconnect (e.g., a metal line). Various interconnect features may employ various conductive materials, including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper-related multi-layer interconnect structure. Furthermore, additional process steps may be performed before, during, and after the method 1100, and some of the process steps described previously may be replaced or removed according to various embodiments of the method 1100.

Fig. 13 is a process flow diagram depicting an exemplary method 1300 of semiconductor fabrication including Metal Drain (MD) fabrication and Via Gate (VG) fabrication, in accordance with some embodiments. Method 1300 is merely an example and is not intended to limit the present disclosure to what is explicitly recited in the claims. Additional steps may be provided before, during, and after method 1300, and some of the steps described may be moved, replaced, or deleted for other embodiments of method 1300. Additional components may be added to the semiconductor device depicted in the drawings, and some of the components described below may be replaced, modified, or removed in other embodiments.

Fig. 13 illustrates example operations that may be performed between block 1118 and block 1120 of fig. 11, according to some embodiments. Fig. 13 is described in conjunction with fig. 14A-14E, where fig. 14A-14E are enlarged views depicting an exemplary region 1400 at various stages of semiconductor fabrication including metal drain fabrication and via gate fabrication, in accordance with some embodiments. In the drawings, some reference signs of the components or features depicted therein may be omitted to avoid obscuring other components or features; this is for convenience in drawing the drawings.

At block 1302, the example method 1300 includes providing a substrate having a metal gate, a gate spacer on sides of the metal gate, a metal cap formed over the metal gate, an Etch Stop Layer (ESL), and an interlayer dielectric (ILD) material over the source/drain regions.

At block 1304, the example method 1300 includes forming a first ILD layer over the metal cap. The first ILD layer may comprise or be a material such as silicon nitride (SiN), although other suitable materials such as silicon oxide (SiO) ₂ ) Aluminum oxide (AlO), silicon oxycarbide (SiOC), silicon carbide (SiC), zirconium nitride (ZrN), zirconium oxide (ZrO), combinations thereof or the like. The first ILD layer may be deposited using a deposition process such as plasma-assisted atomic layer deposition (PEALD), thermal atomic layer deposition (thermal ALD), plasma-assisted chemical vapor deposition (PECVD), and the like. Any suitable deposition process and process conditions may be used.

At block 1306, the example method 1300 includes forming a patterned mask that exposes a portion of the ILD material over the source/drain regions. The patterned mask may include a photoresist layer. The patterned mask may be formed by photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, cleaning, drying (e.g., hard baking), and/or combinations thereof. In some other embodiments, various imaging assistance layers may be formed under the photoresist layer to assist in pattern transfer. The imaging assistance layer may comprise three layers, including a bottom organic layer, a middle inorganic layer, and a top organic layer. The imaging assistance layer may also comprise an anti-reflective coating (ARC) material, a polymer layer, an oxide from Tetraethylorthosilicate (TEOS), silicon oxide or a Si-containing anti-reflective coating (ARC) material, such as an ARC layer containing 42% Si. In still other embodiments, the patterned masking layer comprises a hard masking layer. The hard mask layer comprises an oxide material, silicon nitride, silicon oxynitride, amorphous carbon material, silicon carbide, or Tetraethylorthosilicate (TEOS).

Referring to the example of fig. 14A, in one embodiment after blocks 1302, 1304, and 1306 are completed, region 1400 is depicted comprising substrate 1402 with metal gate stack 1201, gate spacers 1212 on sides of metal gate stack 1201, metal cap 1220 formed over metal gate stack 1201, ESL 1416, ILD material 802 over source/drain region 1404, first ILD layer 1414 over metal cap 1220, and patterned mask 1406 exposing a portion of ILD material 802 over source/drain region 1404.

At block 1308, the example method 1300 includes removing ILD material over the source/drain regions to form openings exposing underlying source/drain regions. The exposed portions of the ILD material may be removed by a suitable etching process, such as wet etching, dry etching, or a combination thereof.

At block 1310, the example method 1300 includes optionally forming a plurality of silicide contacts over the exposed source/drain regions. The optional silicide contacts may comprise titanium (e.g., titanium silicide (TiSi)) to reduce the Schottky barrier height of the contacts. However, other metals may be used, such as nickel, cobalt, erbium, platinum, palladium, or the like. Silicidation may be performed by blanket deposition of a suitable metal layer followed by an annealing step that reacts the metal with the exposed silicon under the source/drain regions.

Referring to the example of fig. 14B, in one embodiment after completing blocks 1308 and 1310, region 1400 includes an opening 1408 exposing underlying source/drain regions 1404 and optionally silicide contacts 1409 formed over the exposed source/drain regions 1404. The figure depicts ILD material 802 over source/drain regions 1404 having been removed to form openings 1408 exposing underlying source/drain regions 1404.

At block 1312, the example method 1300 includes filling the openings contacting the source/drain regions with a conductive material to form a plurality of source/drain contacts. The source/drain contacts 702 may include one or more layers. For example, in some embodiments, the source/drain contacts include a liner and a metal fill material (not separately shown) deposited by, for example, CVD, ALD, electroless deposition (ELD), PVD, electroplating, or another deposition technique. The liner (e.g., diffusion barrier, adhesion layer, or the like) may comprise titanium, titanium nitride, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, ruthenium, nickel, or the like. A planarization process, such as CMP, may be performed to remove the excess liner and conductive material. The remaining liner and conductive material form source/drain contacts located in the openings.

Referring to the example of fig. 14C, in one embodiment after block 1312 is completed, region 1400 includes conductive material that fills opening 1408 and contacts source/drain region 1404 to form source/drain contact 702.

At block 1314, the example method 1300 includes forming a contact etch stop layer (contact etch stop layer, CESL) over the source/drain and gate regions. CESL may be deposited using one or more low temperature deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

At block 1316, the example method 1300 includes forming a second ILD layer over the CESL layer. The second ILD layer may be formed of, for example, an oxide (e.g., silicon oxide (SiO) ₂ ) A) and may be deposited over the CESL by any acceptable process, such as CVD, PEALD, thermal ALD, PECVD, or the like. The second ILD layer may also be formed of other suitable insulating materials (e.g., PSG, BSG, BPSG, USG or the like) deposited by any suitable method (e.g., CVD, PECVD, flowable CVD, or the like). After formation, the second ILD layer may be cured, for example, by an ultraviolet curing process.

Referring to the example of fig. 14D, in one embodiment after completing blocks 1314 and 1316, region 1400 includes CESL layer 1410 formed over the source/drain and gate regions and second ILD layer 1412 formed over CESL layer 1410.

At block 1318, the example method 1300 includes forming contact via openings in the CESL and the second ILD layer for via gate contacts and source/drain via contacts. The contact via openings for the via gate contacts and the source/drain via contacts are formed using one or more etching processes. According to some embodiments, openings for via gate contacts are formed through the second ILD layer, CESL and the first ILD layer, and openings for source/drain via contacts are formed through the second ILD layer and CESL. The openings may be formed using any combination of acceptable photolithography and suitable etching techniques, such as a dry etching process (e.g., plasma etching, reactive Ion Etching (RIE), physical etching (e.g., ion Beam Etching (IBE)), a wet etching process, combinations thereof, or the like. However, the contact via openings may be formed using any suitable etching process.

At block 1320, the example method 1300 includes forming a via gate contact and a source/drain via contact. A via gate contact is formed over and electrically coupled to the metal cap, and a source/drain via contact is formed over and electrically coupled to the source/drain contact. The via gate contacts and/or source/drain via contacts may be formed by depositing a metal material in the openings. The metallic material may be deposited by CVD, ALD, electroless deposition (ELD), PVD, electroplating, or another deposition technique. The via gate contact and/or source/drain via contact may be or include tungsten, cobalt, copper, ruthenium, aluminum, gold, silver, alloys thereof, the like, or combinations thereof.

Referring to the example of fig. 14E, in one embodiment after blocks 1318 and 1320 are completed, region 1400 includes via gate contacts 1222 and source/drain via contacts (not shown).

At block 1322, the example method 1300 includes performing further manufacturing operations. The semiconductor device may undergo further processing to form various components and regions known in the art. For example, subsequent processing may form various contact vias/lines and multi-layer interconnect features (e.g., metal layers and interlayer dielectrics) over the substrate that are configured to connect the various features to form functional circuits that may include one or more multi-gate devices. In further examples, the multi-layer interconnect may include a vertical interconnect (e.g., a via or contact) and a horizontal interconnect (e.g., a metal line). Various interconnect features may employ various conductive materials, including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper-related multi-layer interconnect structure. Furthermore, additional process steps may be performed before, during, and after method 1300, and some of the process steps described previously may be replaced or removed according to various embodiments of method 1300.

Improved systems, manufacturing methods, manufacturing techniques, and articles have been described. The described systems, methods, techniques, and articles may be used with a wide range of semiconductor devices, including GAA and FinFET devices.

In various embodiments, a semiconductor device includes a gate structure over a semiconductor substrate and a continuous metal cap over the gate structure. The gate structure includes: a high-k dielectric layer; a P-type work function layer; an N-type work function layer; an anti-reaction layer comprising a dielectric material; and (5) an adhesive layer. The continuous metal cover is formed by: depositing a metal material over the gate structure during a plurality of first deposition operations, the metal material forming a discontinuous metal cap; selectively removing a portion of the anti-reaction layer during a plurality of first wet chemical operations; depositing additional metal material over the gate structure during a plurality of second deposition operations to create a continuous metal cap; and the continuous metal cap is inhibited from growing during the plurality of second wet chemical operations.

In a particular embodiment of the semiconductor device, the continuous metal cap comprises a tungsten (W) or molybdenum (Mo) material.

In a particular embodiment of a semiconductor device, a gate structure is prepared to form a continuous metal cap over the gate structure, the gate structure prepared by: planarizing the top layer of the gate structure using a planarization operation; pre-cleaning the surface of the gate structure using a Deionized (DI) water rinse; and pre-treating the surface of the gate structure using an oxidation or nitridation process.

In particular embodiments of semiconductor devices, dilute hydrofluoric acid (HF) or a solution comprising ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H) ₂ O ₂ ) And water (H) ₂ O) selectively removes portions of the anti-reactive layer.

In a particular embodiment of a semiconductor device, the anti-reactive layer comprises a silicon-containing material.

In a particular embodiment of the semiconductor device, a gate resistance (Rg) of the gate structure is less than or equal to 80 ohms per square (Ω/sq).

In various embodiments, a method of forming a continuous metal cap over a metal gate structure, comprises: the gate structure is received and has a high-k dielectric layer, a P-work-function layer, an N-work-function layer, an anti-reaction layer comprising a dielectric material, and a glue layer. The method includes pretreating a surface of the gate structure with an oxidation or nitridation process; depositing a metal material over the gate structure using a plurality of first deposition operations, which form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer using a plurality of first wet chemical operations; depositing additional metal material over the gate structure using a plurality of second deposition operations to create a continuous metal cap; and inhibiting continued metal cap growth using a plurality of second wet chemistry operations.

In a particular embodiment of the method, a Via Gate (VG) is formed over the metal cap. Forming a via gate on the metal cap includes: forming an opening through the interlayer dielectric material using a plurality of etching operations to contact the metal cap; and depositing a metallic material in the opening using a plurality of deposition operations.

In a particular embodiment of this method, the first deposition operation and the second deposition operation comprise a plurality of Atomic Layer Deposition (ALD) operations, and the metal cap comprises a metal film deposited by tungsten chloride (WCl ₅ ) And hydrogen (H) ₂ ) Deposited tungsten (W).

In a particular embodiment of the method, the first deposition operation and the second deposition operation comprise a plurality of Atomic Layer (ALD) deposition operations, and the metal cap comprises a metal film deposited by tungsten fluoride (WF) ₆ ) And hydrogen (H) ₂ ) Deposited tungsten (W).

In a particular embodiment of this method, the first deposition operation and the second deposition operation comprise a plurality of Atomic Layer Deposition (ALD) operations, and the metal cap comprises a metal film deposited by molybdenum chloride (MoCl) ₅ ) And hydrogen (H) ₂ ) Deposited molybdenum (Mo).

In a particular embodiment of this method, the first wet chemical operation for removing the anti-reaction layer includes a rinse with dilute hydrofluoric acid (HF).

The method isIn a particular embodiment of (a) a first wet chemical operation for removing a portion of an anti-reactive layer includes rinsing with an etching solution, the etching solution including ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H) ₂ O ₂ ) And water (H) ₂ O)。

In a particular embodiment of this method, the second wet chemical operation for inhibiting growth of the metal cap includes a wet etching operation using an ozone solution.

In another embodiment, a method of manufacturing a semiconductor device includes: the gate structure is received and comprises a high-dielectric-coefficient dielectric layer, a P-type work function layer, an N-type work function layer, a dielectric anti-reaction layer and a glue layer. The method for manufacturing the semiconductor device further comprises: using oxygen (O) ₂ ) Or hydrogen/nitrogen (H) ₂ /N ₂ ) The surface of the grid structure is pretreated by plasma treatment; depositing a first metal material comprising a tungsten (W) material or a molybdenum (Mo) material over the gate structure using a plurality of first atomic layer deposition ALD) operations, which form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer using dilute hydrofluoric acid; depositing a second metal material comprising tungsten or molybdenum over the gate structure using a plurality of second atomic layer deposition operations to create a continuous metal cap; inhibiting growth of the metal cap by removing unwanted metal material from the plurality of side spacers by a wet etching operation using an ozone solution; and forming a Via Gate (VG) over the metal cap. Forming a via gate over a metal cap includes forming an opening through an interlayer dielectric (ILD) material using a plurality of etching operations to contact the metal cap and depositing a metal material in the opening using a plurality of deposition operations.

In a particular embodiment of the method of this semiconductor device, the first atomic layer deposition operation and the second atomic layer deposition operation include a process performed by tungsten chloride (WCl ₅ ) And hydrogen (H) ₂ ) Tungsten (W) is deposited.

In a particular embodiment of the method of the semiconductor device, the first atomic layer deposition operation and the second atomic layer deposition operation include a process performed by tungsten fluoride (WF) ₆ ) And hydrogen (H) ₂ ) Tungsten is deposited.

In a particular embodiment of the method of this semiconductor device, the first atomic layer deposition operation and the second atomic layer deposition operation comprise a process performed by molybdenum chloride (MoCl ₅ ) And hydrogen (H) ₂ ) Molybdenum (Mo) was deposited.

In a particular embodiment of the method of the semiconductor device, one of the first metal material and the second metal material comprises tungsten and the other of the first metal material and the second metal material comprises molybdenum.

In a particular embodiment of the method of the semiconductor device, the method further includes planarizing a top layer of the gate structure using a plurality of Chemical Mechanical Polishing (CMP) operations and pre-cleaning the surface of the gate structure using a Deionized (DI) water rinse prior to pre-treating the surface of the gate structure.

While at least one exemplary embodiment has been presented in the foregoing detailed description of the disclosure, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the disclosure. It being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the disclosure as set forth in the appended claims.

Claims (10)

1. A semiconductor device, comprising:

a gate structure over a semiconductor substrate, the gate structure comprising:

a high-k dielectric layer;

a P-type work function layer;

an N-type work function layer;

an anti-reaction layer comprising a dielectric material; a kind of electronic device with high-pressure air-conditioning system

A glue layer; and

a continuous metal cap over the gate structure, the continuous metal cap formed by:

depositing a metal material over the gate structure during a plurality of first deposition operations, the metal material forming a discontinuous metal cap;

selectively removing a portion of the anti-reaction layer during a plurality of first wet chemical operations;

depositing additional metal material over the gate structure during a plurality of second deposition operations to create the continuous metal cap; a kind of electronic device with high-pressure air-conditioning system

The continuous metal cap is inhibited from growing during a plurality of second wet chemical operations.

2. The semiconductor device of claim 1, wherein the gate structure is prepared to form the continuous metal cap over the gate structure, the gate structure prepared by:

planarizing a top layer of the gate structure using a planarization operation;

Pre-cleaning the surface of the grid structure by using deionized water for flushing; a kind of electronic device with high-pressure air-conditioning system

The surface of the gate structure is pre-treated with an oxidation or nitridation process.

3. The semiconductor device of claim 1, wherein a portion of the anti-reaction layer is selectively removed using dilute hydrofluoric acid or an etching solution comprising ammonium hydroxide, hydrogen peroxide, and water.

4. A method of forming a continuous metal cap over a metal gate structure, comprising:

a receiving gate structure, the gate structure comprising:

a high-k dielectric layer;

a P-type work function layer;

an N-type work function layer;

an anti-reaction layer comprising a dielectric material; a kind of electronic device with high-pressure air-conditioning system

A glue layer;

pre-treating the surface of the gate structure using an oxidation or nitridation process;

depositing a metal material over the gate structure using a plurality of first deposition operations, which form a discontinuous metal cap;

selectively removing a portion of the anti-reaction layer using a plurality of first wet chemical operations;

depositing additional metal material over the gate structure using a plurality of second deposition operations to create the continuous metal cap; and

the continuous metal cap growth is inhibited using a plurality of second wet chemical operations.

5. The method of forming the continuous metal cap over a metal gate structure of claim 4, further comprising forming a via gate over the metal cap, wherein forming the via gate over the metal cap comprises:

forming an opening through the interlayer dielectric material using a plurality of etching operations to contact the metal cap; a kind of electronic device with high-pressure air-conditioning system

A metallic material is deposited in the opening using a plurality of deposition operations.

6. The method of claim 4, wherein the plurality of first deposition operations and the plurality of second deposition operations comprise a plurality of atomic layer deposition operations, and wherein the metal cap comprises tungsten deposited by tungsten chloride and hydrogen.

7. The method of forming the continuous metal cap over a metal gate structure as recited in claim 4 wherein the plurality of first wet chemical operations for removing the anti-reaction layer comprises rinsing with dilute hydrofluoric acid.

8. The method of forming the continuous metal cap over a metal gate structure as recited in claim 4, wherein the plurality of second wet chemical operations for inhibiting growth of the metal cap comprises a wet etching operation using an ozone solution.

9. A method of manufacturing a semiconductor device, comprising:

a receiving gate structure, the gate structure comprising:

a high-k dielectric layer;

a P-type work function layer;

an N-type work function layer;

an anti-reaction layer comprising a dielectric material; a kind of electronic device with high-pressure air-conditioning system

A glue layer;

pretreating the surface of the gate structure with oxygen or hydrogen/nitrogen plasma treatment;

depositing a first metal material comprising a tungsten material or a molybdenum material over the gate structure using a plurality of first atomic layer deposition operations, which form a discontinuous metal cap;

selectively removing a portion of the anti-reaction layer using dilute hydrofluoric acid;

depositing a second metal material comprising tungsten or molybdenum over the gate structure using a plurality of second atomic layer deposition operations to create a continuous metal cap;

inhibiting growth of the metal cap by removing unwanted metal material from the plurality of side spacers by a wet etching operation using an ozone solution; and

forming a via gate over the metal cap, wherein forming the via gate over the metal cap comprises:

forming an opening through the interlayer dielectric material using a plurality of etching operations to contact the metal cap; a kind of electronic device with high-pressure air-conditioning system

A metallic material is deposited in the opening using a plurality of deposition operations.

10. The method of manufacturing a semiconductor device of claim 9, further comprising planarizing a top layer of the gate structure using a plurality of chemical mechanical polishing operations and pre-cleaning the surface of the gate structure using a deionized water rinse prior to pre-treating the surface of the gate structure.