CN117420419A - Open circuit or short circuit test method, system and platform for chip pins - Google Patents
Open circuit or short circuit test method, system and platform for chip pins Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2815—Functional tests, e.g. boundary scans, using the normal I/O contacts
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/54—Testing for continuity
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- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a method, a system and a platform for testing open circuit or short circuit among chip pins, wherein at least one matrix corresponding to the network point connection relation among the chip pins is created through the method; traversing the connection relation among all network points in the matrix, and generating a test path corresponding to the network points; generating test driving data which corresponds to the test path and is used for testing open circuit or short circuit among pins of the chip according to the test path; acquiring level state data corresponding to the test driving data, and judging the connection relation among the chip pins in real time according to the level state data; and the system and the platform corresponding to the method can improve the analysis efficiency of the test path and the test efficiency of open and short circuits.
Description
Technical Field
The invention belongs to the technical field of detection processing, and particularly relates to a method, a system and a platform for testing open circuits or short circuits among chip pins.
Background
The automatic boundary scanning test system software is a test software for server main board or relatively complex PCBA (circuit board) in jig industry, and has the main functions of automatically searching out test paths by analyzing board-making data, generating chip Pin driving data according to the paths, driving Jtag (a communication protocol) signals to a tested chip by a controller, outputting or receiving input by driving pins after the chip obtains corresponding data, and determining faulty pins or paths by analyzing the Jtag (a communication protocol) signals.
At present, the boundary scanning automatic test system has larger analysis data volume, is mainly widely based on the analysis of test paths on the level of a software integrated platform, has low analysis efficiency, long time consumption for open circuit or short circuit test and low test efficiency.
Therefore, in order to address the above technical drawbacks, there is an urgent need to design and develop a method, system and platform for testing open circuit or short circuit between chip pins.
Disclosure of Invention
In order to overcome the defects and difficulties in the prior art, the invention aims to provide a method, a system and a platform for testing open circuits or short circuits among chip pins, aiming at the technical defects of low analysis efficiency of test paths, long time consumption for open circuit or short circuit testing and low test efficiency, so as to improve the analysis efficiency of the test paths and the test efficiency of open circuits and short circuits.
The first object of the present invention is to provide a method for testing open circuit or short circuit between chip pins; a second object of the present invention is to provide a system for open or short testing between chip pins; a third object of the present invention is to provide a test platform for open or short circuits between chip pins.
The first object of the present invention is achieved by: the method comprises the following steps:
Creating at least one matrix corresponding to the network point connection relation among the chip pins;
traversing the connection relation among all network points in the matrix, and generating a test path corresponding to the network points;
generating test driving data which corresponds to the test path and is used for testing open circuit or short circuit among pins of the chip according to the test path;
acquiring level state data corresponding to the test driving data, and judging the connection relation among the chip pins in real time according to the level state data; wherein, the connection relation is open circuit connection or short circuit connection among chip pins.
Further, the creating at least one matrix corresponding to the network point connection relationship between the chip pins further includes:
creating at least one stack, at least one first array and at least one second array, respectively; the first array is used for storing index records; the second plurality of sets is used for storing paths;
clearing the stack and the first array and creating at least one third numerical variable; wherein the third numerical variation is used for storing row index data;
and acquiring the line data in the third numerical variable, and stacking the line data, and simultaneously placing the line data in the first array.
Further, the obtaining the line data in the third numerical variable, and stacking the line data, and placing the line data in the first array at the same time, further includes:
judging whether a connection relation exists according to the data of the rows, and if the connection relation exists and the first array does not exist, performing value-added processing on the data of the rows; otherwise, traversing and recording all elements in the current stack, storing the elements into a second array, and removing stack top elements.
Further, the traversing the connection relation between all the network points in the matrix and generating a test path corresponding to the network points further includes:
according to the connection relation between the network points, eliminating the repeated test path corresponding to the connection relation, and simultaneously creating at least one fourth array; the fourth array is used for storing the array after the repeated paths are eliminated;
traversing a second set and generating a first test path corresponding to the second set; the first test path is a test path before sorting processing;
according to the first test path, performing ascending arrangement processing in combination with the network point subscript, and generating a second test path corresponding to the first test path; the second test path is a test path after the sorting processing;
Acquiring path data in a fourth array, and judging whether the path data in the fourth array has the second test path or not; if not, the second test path is placed in the fourth array, otherwise, the next path is continuously traversed.
Further, the traversing the connection relation between all the network points in the matrix and generating a test path corresponding to the network points further includes:
integrating and combining the test paths, and generating corresponding test paths with unique IDs;
creating at least one fifth array, and placing the test path with the unique ID in the fifth array; wherein the fifth array is a key value pair array.
Further, the generating test driving data corresponding to the test path and used for testing open circuit or short circuit among pins of the chip according to the test path further includes:
acquiring data in a fifth array, and creating at least one sixth array; the sixth array is used for storing test driving data;
and assigning the sixth array, traversing the fifth array, and binarizing key data in the fifth array.
Further, the obtaining the level state data corresponding to the test driving data, and determining the connection relationship between the chip pins in real time according to the level state data, further includes:
traversing the column data in the sixth array and the test path set corresponding to the column data in sequence;
generating chip pin data corresponding to the network points according to the network point information corresponding to the test path set;
and according to the chip pin data, combining level signals sent by the pins, and sequentially sending test driving data.
The second object of the present invention is achieved by: the system is applied to the test method, and comprises the following steps:
the matrix creation unit is used for creating at least one matrix corresponding to the network point connection relation among the pins of the chip;
the first generation unit is used for traversing the connection relation among all network points in the matrix and generating a test path corresponding to the network points;
the second generating unit is used for generating test driving data which corresponds to the test path and is used for testing open circuit or short circuit among pins of the chip according to the test path;
the first judging unit is used for acquiring level state data corresponding to the test driving data and judging the connection relation among the chip pins in real time according to the level state data; wherein, the connection relation is open circuit connection or short circuit connection among chip pins.
Further, the matrix creation unit further includes:
a first creation module for creating at least one stack, at least one first array and at least one second array, respectively; the first array is used for storing index records; the second plurality of sets is used for storing paths;
a second creation module for flushing the stack and the first array and creating at least one third numerical variable; wherein the third numerical variation is used for storing row index data;
the first processing module is used for acquiring the line data in the third numerical variable, carrying out stack-joining processing on the line data, and simultaneously placing the line data in the first array;
and/or, the first processing module further comprises:
the first judging module is used for judging whether a connection relation exists according to the data of the data;
and/or, the first generating unit further comprises:
the third creation module is used for eliminating repeated test paths corresponding to the connection relation according to the connection relation between the network points, and creating at least one fourth array; the fourth array is used for storing the array after the repeated paths are eliminated;
The first generation module is used for traversing the second group and generating a first test path corresponding to the second group; the first test path is a test path before sorting processing;
the second generation module is used for carrying out ascending arrangement processing by combining network point subscripts according to the first test path and generating a second test path corresponding to the first test path; the second test path is a test path after the sorting processing;
the second judging module is used for acquiring the path data in the fourth array and judging whether the path data in the fourth array has the second test path or not; the method comprises the steps of carrying out a first treatment on the surface of the
And/or, the first generating unit further comprises:
the third generation module is used for integrating and combining the test paths and generating corresponding test paths with unique IDs;
a fourth creation module, configured to create at least one fifth array, and place the test path with the unique ID in the fifth array; wherein the fifth array is a key value pair array;
and/or, the second generating unit further includes:
a fifth creation module, configured to obtain the data in the fifth array, and create at least one sixth array; the sixth array is used for storing test driving data;
The second processing module is used for assigning and processing the sixth array, traversing the fifth array and binarizing and processing key data in the fifth array;
and/or, the first determination unit further includes:
the first traversing module is used for traversing the column data in the sixth array in sequence and the test path set corresponding to the column data;
a fourth generation module, configured to generate chip pin data corresponding to a network point according to network point information corresponding to the test path set;
and the first transmitting module is used for sequentially transmitting test driving data according to the chip pin data and the level signals sent by the pins.
The third object of the present invention is achieved by: the test platform control system comprises a processor, a memory and a test platform control program for open circuit or short circuit among pins of a chip; the processor executes the open circuit or short circuit test platform control program for the chip pins, the open circuit or short circuit test platform control program for the chip pins is stored in the memory, and the open circuit or short circuit test platform control program for the chip pins realizes the open circuit or short circuit test method for the chip pins.
The invention creates at least one matrix corresponding to the network point connection relation among the chip pins through a method; traversing the connection relation among all network points in the matrix, and generating a test path corresponding to the network points; generating test driving data which corresponds to the test path and is used for testing open circuit or short circuit among pins of the chip according to the test path; acquiring level state data corresponding to the test driving data, and judging the connection relation among the chip pins in real time according to the level state data; and the system and the platform corresponding to the method can improve the analysis efficiency of the test path and the test efficiency of open and short circuits.
That is, the problem of searching the open-short circuit test path is solved by the scheme of the invention, compared with the traditional processing method, the analysis time is greatly reduced, the experience of software is enhanced, and the productivity is improved to a certain extent; in addition, the algorithm process related by the invention is independent of programming language and operating system, and can be easily transplanted into any practically needed development environment. The related generation processing algorithm of the open-short circuit test driving data greatly reduces the test times, and in the actual production process, the direct embodiment is that the test time is greatly shortened, and the production efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for testing open or short circuit between pins of a chip according to the present invention;
FIG. 2 is a schematic diagram of a chip connection for an embodiment of a method for testing open or short circuits between chip pins according to the present invention;
FIG. 3 is a schematic diagram of a matrix of an embodiment of a method for testing open or short circuits between pins of a chip according to the present invention;
FIG. 4 is a schematic diagram of a push-up process for an embodiment of a method for testing open or short circuits between pins of a chip according to the present invention;
FIG. 5 is a schematic diagram of driving data and expected data for an embodiment of a method for testing open or short circuits between pins of a chip according to the present invention;
FIG. 6 is a schematic diagram of a chip scan register used in an embodiment of a method for testing open or short circuits between chip pins according to the present invention;
FIG. 7 is a schematic diagram of test data for an embodiment of an open or short circuit test method between chip pins according to the present invention;
FIG. 8 is a schematic diagram of an open or short circuit test system architecture for use between chip pins according to the present invention;
FIG. 9 is a schematic diagram of an open or short circuit test platform architecture for use between chip pins according to the present invention;
the achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
For a better understanding of the present invention, its objects, technical solutions and advantages, further description of the present invention will be made with reference to the drawings and detailed description, and further advantages and effects will be readily apparent to those skilled in the art from the present disclosure.
The invention may be practiced or carried out in other embodiments and details within the scope and range of equivalents of the various features and advantages of the invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and rear … …) are included in the embodiments of the present invention, the directional indications are merely used to explain the relative positional relationship, movement conditions, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. Secondly, the technical solutions of the embodiments may be combined with each other, but it is necessary to be based on the fact that those skilled in the art can realize the technical solutions, and when the technical solutions are contradictory or cannot be realized, the technical solutions are considered to be absent and are not within the scope of protection claimed in the present invention.
Preferably, the method for testing open or short circuits among chip pins is applied to one or more terminals or servers. The terminal is a device capable of automatically performing numerical calculation and/or information processing according to a preset or stored instruction, and its hardware includes, but is not limited to, a microprocessor, an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a programmable gate array (Field-Programmable Gate Array, FPGA), a digital processor (Digital Signal Processor, DSP), an embedded device, etc.
The terminal can be a computing device such as a desktop computer, a notebook computer, a palm computer, a cloud server and the like. The terminal can perform man-machine interaction with a client through a keyboard, a mouse, a remote controller, a touch pad or voice control equipment and the like.
The invention discloses a method, a system and a platform for testing open circuit or short circuit among chip pins.
Fig. 1 is a flowchart of a method for testing open or short circuit between chip pins according to an embodiment of the present invention.
In this embodiment, the method for testing open circuit or short circuit between chip pins may be applied to a terminal or a fixed terminal with a display function, where the terminal is not limited to a personal computer, a smart phone, a tablet computer, a desktop computer or an all-in-one machine with a camera, etc.
The method for testing open circuit or short circuit between chip pins can also be applied to a hardware environment formed by a terminal and a server connected with the terminal through a network. Networks include, but are not limited to: a wide area network, a metropolitan area network, or a local area network. The open circuit or short circuit test method used between the chip pins in the embodiment of the invention can be executed by a server, a terminal or both.
For example, for terminals that need to be tested for open or short circuits between chip pins, the open or short circuit test functions provided by the method of the present invention for chip pins may be integrated directly on the terminals, or clients for implementing the method of the present invention may be installed. For another example, the method provided by the invention can also be operated on a server and other devices in the form of software development kits (Software Development Kit, SDK), an interface for testing the open circuit or short circuit among the chip pins is provided in the form of SDK, and the terminal or other devices can realize the function for testing the open circuit or short circuit among the chip pins through the provided interface. The invention is further elucidated below in connection with the accompanying drawings.
As shown in fig. 1-9, the present invention provides a method for testing open circuit or short circuit between chip pins, the method comprising the steps of:
s1, creating at least one matrix corresponding to a network point connection relation among chip pins;
s2, traversing connection relations among all network points in the matrix, and generating test paths corresponding to the network points;
s3, generating test driving data which corresponds to the test path and is used for testing open circuit or short circuit among pins of the chip according to the test path;
S4, acquiring level state data corresponding to the test driving data, and judging the connection relation among the pins of the chip in real time according to the level state data; wherein, the connection relation is open circuit connection or short circuit connection among chip pins.
The creating at least one matrix corresponding to the network point connection relation among the chip pins further comprises:
s11, respectively creating at least one stack, at least one first array and at least one second array; the first array is used for storing index records; the second plurality of sets is used for storing paths;
s12, emptying the stack and the first array, and creating at least one third numerical variable; wherein the third numerical variation is used for storing row index data;
s13, acquiring row data in the third numerical variable, and stacking the row data, and simultaneously placing the row data in the first array.
The step of obtaining the line data in the third numerical variable, and stacking the line data, and simultaneously placing the line data in the first array, further includes:
s131, judging whether a connection relation exists according to the data of the data, and if the connection relation exists and the first array does not exist, performing value-added processing on the data of the data; otherwise, traversing and recording all elements in the current stack, storing the elements into a second array, and removing stack top elements.
Traversing the connection relation among all the network points in the matrix, generating a test path corresponding to the network points, and further comprising:
s21, according to the connection relation between the network points, eliminating a repeated test path corresponding to the connection relation, and simultaneously creating at least one fourth array; the fourth array is used for storing the array after the repeated paths are eliminated;
s22, traversing a second array, and generating a first test path corresponding to the second array; the first test path is a test path before sorting processing;
s23, according to the first test path, carrying out ascending arrangement processing by combining with network point subscripts, and generating a second test path corresponding to the first test path; the second test path is a test path after the sorting processing;
s24, acquiring path data in a fourth array, and judging whether the path data in the fourth array has the second test path or not; if not, the second test path is placed in the fourth array, otherwise, the next path is continuously traversed.
Traversing the connection relation among all the network points in the matrix, generating a test path corresponding to the network points, and further comprising:
S25, integrating and combining the test paths, and generating corresponding test paths with unique IDs;
s26, creating at least one fifth array, and placing the test path with the unique ID in the fifth array; wherein the fifth array is a key value pair array.
The generating test driving data corresponding to the test path and used for testing open circuit or short circuit among chip pins according to the test path further comprises:
s31, acquiring data in a fifth array, and creating at least one sixth array; the sixth array is used for storing test driving data;
s32, assigning and processing the sixth array, traversing the fifth array, and binarizing and processing key data in the fifth array.
The step of obtaining the level state data corresponding to the test driving data, and determining the connection relation between the chip pins in real time according to the level state data, and the step of further comprises:
s41, traversing the column data in the sixth array and a test path set corresponding to the column data in sequence;
s42, generating chip pin data corresponding to the network points according to the network point information corresponding to the test path set;
S43, according to the chip pin data, combining the level signals sent by the pins, and sequentially sending test driving data.
Specifically, in the embodiment of the present invention, as shown in fig. 2, which is an example of two chip interconnections, pin (Pin) 10 of chip a and Pin (Pin) 2 of chip B are connected through resistors R1, R2; pin 8 of chip A and Pin 4 of chip B are connected by resistor R3, while Pin 3 and Pin 4 of chip B are connected by R4, pin 7 of chip A and Pin 5 of chip B are connected by resistor R5; pin 5 of chip A is connected with GND (ground); the remaining pins are suspended. In addition, A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T are all network points.
The method comprises the following specific steps: s01, as shown in fig. 3, all connection relations are abstracted into a matrix a, which may be very large in practical application, where only a part is extracted as an example, and J, K, L, I, H, N, M, G, T represents a network point, "1" represents a connection relation, and "0" represents no connection relation. For ease of description, the matrix is deformed into a matrix b here. The row index references j and the column index references i.
S02, applying a Stack, applying an array sen (first array) for storing index records, applying an array TestPaths (second array) for storing paths, and initializing.
S03, taking out the data of the j line, clearing Stack, and clearing array sen (index record array). Applying for a temporary RowIndex (row index) for holding the row index (third numerical variable) and assigning the value of j to the RowIndex; rowIndex is a numeric variable in the code that is used to temporarily hold row index values.
S04, taking the ith data of RowIndex row, namely n [ i ], pushing n [ i ] into Stack as shown in fig. 4, adding n [ i ] into a Seen (index record array) array, assigning i to RowIndex when n [ i ] = 1 is present, namely a connection relation exists in the Seen (index record array) array, adding i by 1, repeating the steps, otherwise traversing and recording all elements in the current Stack, saving the elements into a path array TestPaths (test path array), and removing Stack top elements. When an element in the Stack is empty, j is incremented by 1, and the process returns to S03, and the path search of the next row is performed. When all rows have been traversed, the process continues.
S05, from S03, it is known that a line of data is actually all directly connected sets of network points, and because the network points are searched one by one, the test paths have repetition, such as n0→n1→n2 and n2→n1→n0, which are actually identical and only have different directions after the execution of S04. The repeated path is removed, and a new test path array testpaths remove (fourth array) is applied for storing the array after removing the repeated path.
S06, traversing the TestPaths (test path array) array, arranging the traversed paths in ascending order according to the network point subscript, thus obtaining a new path, searching whether the path exists in the TestPathsRemoval (path array after eliminating repeated paths), if not, adding the path into the TestPathsRemoval (path array after eliminating repeated paths), and if so, ignoring the path. The next traversal continues until all paths have been traversed.
S07, so far, all effective and unique paths are obtained, but the paths are still required to be continuously integrated, because the paths are all independent and cannot represent the real interconnection situation, for example, as shown in fig. 2, for Pin (Pin) 8 of ChipA (chip A), pin (Pin) 3 of ChipB (chip B), pin (Pin) 4 of ChipB (chip B), the three Pin (pins) are mutually connected, and through the steps, the three paths H- & gtN, H- & gtN- & gtM, M- & gtN can be obtained, but in the path array after the repeated paths are removed, the paths are all present as 3 independent elements, but are equivalent from the view of hardware connection, so that the paths are required to be combined, the combined set is called PathLock ID (PathID), for example, the three paths are combined to form a set, and the PathID of the set is equal to the PathID of 1. The specific path merging method is as follows:
A. Applying a key value to the PathBlocks (test path set array) (fifth array), wherein keys in the array elements store pathblock IDs (path unique IDs), and values in the array elements store the merged path set.
B. Traversing the TestPathsRemoval (path array after eliminating duplicate paths) array, creating a key value pair, wherein the key is PathBlockID (path unique ID), acquiring all network points in the current path, traversing the network points, searching the path containing the network points in the TestPathsRemoval (path array after eliminating duplicate paths), adding the path into the key value pair, and deleting the path in the TestPathsRemoval (path array after eliminating duplicate paths). After the testpaths remove (path array after eliminating duplicate paths) completes one traversal, add this key pair to PathBlocks (test path set array) and increment pathblock ID (path unique ID) by 1. Until all paths in the testpaths remove (path array after duplicate paths are removed) are traversed.
S08, after PathBlocks (test path set array) is obtained, open and short circuit test driving data can be generated. The method comprises the steps of firstly obtaining the number P of PathBlocks (test path set array) arrays, and testing times A two-dimensional boolean array driver data (sixth array) is applied for storing test driving data, the number of rows is P, and the number of columns is Q.
S09, assigning a two-dimensional array, traversing PathBlocks (Path set array) array, converting the current key PathBlockID (Path unique ID) into a binary representation, for example, when PathBlockID (Path unique ID) =2, the binary representation method is 10, and it should be noted that the number of binary digits is equal to Q, and taking the above example, the number of PathBlocks (Path set array) is 4, and the method is implemented byIt can be seen that q=2+1, i.e., q=3, indicates that the number of tests is 3, so the corresponding binary should be expressed as 010 when pathblock ID (path unique ID) =2. It is to be noted that the data of the last column needs to be copied one copy to the last column of the DriverDatas. The end result is 0100. The reason why this column needs to be added is see item 2 in S010.
As shown in fig. 5, S010 is the driving data in S09, the values of boolean elements in the two-dimensional array of the driving data determine the level states of the corresponding network points, and the specific conversion process is to traverse the columns of the driving data from left to right, where the meaning of the columns is mentioned, the columns represent the test times, and the data of the first column represents the driving data of all the network points tested for the first time. The data of the first column is 1001, the path set with pathblock ID (path unique ID) 1 needs to drive a high level, the path set with pathblock ID (path unique ID) 2 needs to drive a low level, the path set with pathblock ID 3 needs to drive a low level, and the path set with pathblock ID (path unique ID) 4 needs to drive a high level. The state of the level of each set of paths at each test is now known, but the following two points need to be noted:
1. Often more than one point in the path set, but there is really only one output ≡! For convenience of description, in this example, the first network point in a path set is defined as output, and the rest are all inputs.
2. Because of the characteristics of the on-chip boundary scan register, the value of the current input needs to be acquired next time, in other words, when the expected value of the current time is actually the last output value, as shown in fig. 5, taking the first network point as an example, the driving data is 4, the first output value is 0, the expected value is uncertain, marked as X, the second output value is 0, the expected value is 0, the third output value is 1, the expected value is 0, the fourth output value is 1, and the expected value is 1.
S011, it is now known how the DriverDatas boolean array is converted into the driving of the network point and the expected data. These driving data then need to be loaded onto the on-chip boundary scan registers and output.
First, a column of DriverDatas is traversed, then a path set in this column is traversed, for example, a first value is 0, a second value is 0, a third value is 0, a fourth value is 1, according to network point information in the corresponding path set, it is known that the network points correspond to chip pins, as shown in fig. 2, the chip pins corresponding to the network point J are Pin (pins) 10 of chip a, according to the first principle in S010, pin (pins) 10 of chip a is an output Pin, pin (pins) 2 of chip B is an input Pin, and in view of the driving data, pin 10 of ChipA (chip A) outputs 0, pin 2 of ChipB (chip B) should receive an X (don't care), pin 9 of ChipA (chip A) outputs 0, pin 9 of ChipA (chip A) itself should receive an X (don't care), pin 8 of ChipA (chip A) outputs 0, pin 3 and Pin 4 of ChipB (chip B) should receive an X (don't care), pin 7 of ChipA (chip A) outputs 1, pin 5 of ChipB (chip B) should receive an X (don't care), as a result of traversing the first column. The result of traversing the second column is that Pin 10 of ChipA (chip A) should receive a 0, pin 2 of ChipB (chip B) should receive a 0, pin 9 of ChipA (chip A) should receive a 0, pin 8 of ChipA (chip A) should receive a 1, pin 3 and Pin 4 of ChipB (chip B) should receive a 0, pin 7 of ChipA (chip A) should output a 0, pin 5 of ChipB (chip B) should receive a 1, and so on.
As is known from the BSDL file of the chip, S012, all the pins correspond to a set of boundary scan registers, and these registers are referred to as cells (boundary scan registers), as shown in fig. 6, the chip a and the chip B each have 10 pins, but the cells (boundary scan registers) have 16 pins, and according to the actual situation of the chip, these cells (boundary scan registers) have their own functions and functions, and here, the relationship between these cells (boundary scan registers) and pins is not separately described, and in this example, it can be considered that the cells (boundary scan registers) directly behind pins can change the Pin status. The foregoing two-dimensional array driving data of the driving datas needs to load the corresponding data into the cells (boundary scan registers) by traversing the column data thereof, for example, as shown in fig. 7, the first time of testing data is shown, the chip a Pin 10 is 0, the chip a Pin 9 is 0, the chip a Pin 8 is 0, the chip a Pin 7 is 1, the corresponding expected data is X, it is noted that the values of the cells (boundary scan registers) corresponding to those input pins need not be concerned, and the loading of 0 or 1 is all possible because the cells (boundary scan registers) will collect the level signals sent from the pins on the chip a, then these level signals are locked in the corresponding cells (boundary scan registers), and the values of these cells (boundary scan registers) can be obtained in the next operation.
And S013, transmitting the driving data according to times through upper computer software, and finally detecting the open and short circuit condition among the chip pins. The specific decision rule is that, when each test is executed, the obtained corresponding cell (boundary scan register) value is compared with the expected value, if the cell (boundary scan register) value is the same, the PASS (test PASS) is performed, and if the cell (boundary scan register) value is different, the FAIL (test FAIL) is performed.
In general, when analyzing network paths, the algorithm process of the scheme needs to first establish a large matrix, the matrix contains detailed information of network points and the interconnection relation of the network points, search all test paths by traversing the network points continuously, then repeat path elimination for the test paths, then perform collective operation for items containing the same network points in the paths, then create each test and expected data of the network points according to the number of the collections, finally drive the data to pins of a chip according to times, and simultaneously acquire level states on pins in the input modes, compare the acquired level states with expected values, PASS the test if the obtained level states are the same, and FAIL the test if the obtained level states are different. The method solves the problem of path searching of PCBA (circuit board) open-short circuit test through an algorithm, and can greatly improve analysis efficiency. Meanwhile, the invention relates to the problem of an open-short circuit test driving data algorithm, and the open-short circuit condition can be measured in a shorter time by using the algorithm.
In order to achieve the above objective, the present invention further provides a system for testing open circuit or short circuit between pins of a chip, where the system is applied to the testing method, as shown in fig. 8, and the system specifically includes:
the matrix creation unit is used for creating at least one matrix corresponding to the network point connection relation among the pins of the chip;
the first generation unit is used for traversing the connection relation among all network points in the matrix and generating a test path corresponding to the network points;
the second generating unit is used for generating test driving data which corresponds to the test path and is used for testing open circuit or short circuit among pins of the chip according to the test path;
the first judging unit is used for acquiring level state data corresponding to the test driving data and judging the connection relation among the chip pins in real time according to the level state data; wherein, the connection relation is open circuit connection or short circuit connection among chip pins.
The matrix creation unit further includes:
a first creation module for creating at least one stack, at least one first array and at least one second array, respectively; the first array is used for storing index records; the second plurality of sets is used for storing paths;
A second creation module for flushing the stack and the first array and creating at least one third numerical variable; wherein the third numerical variation is used for storing row index data;
the first processing module is used for acquiring the line data in the third numerical variable, carrying out stack-joining processing on the line data, and simultaneously placing the line data in the first array;
and/or, the first processing module further comprises:
the first judging module is used for judging whether a connection relation exists according to the data of the data;
and/or, the first generating unit further comprises:
the third creation module is used for eliminating repeated test paths corresponding to the connection relation according to the connection relation between the network points, and creating at least one fourth array; the fourth array is used for storing the array after the repeated paths are eliminated;
the first generation module is used for traversing the second group and generating a first test path corresponding to the second group; the first test path is a test path before sorting processing;
the second generation module is used for carrying out ascending arrangement processing by combining network point subscripts according to the first test path and generating a second test path corresponding to the first test path; the second test path is a test path after the sorting processing;
The second judging module is used for acquiring the path data in the fourth array and judging whether the path data in the fourth array has the second test path or not; the method comprises the steps of carrying out a first treatment on the surface of the
And/or, the first generating unit further comprises:
the third generation module is used for integrating and combining the test paths and generating corresponding test paths with unique IDs;
a fourth creation module, configured to create at least one fifth array, and place the test path with the unique ID in the fifth array; wherein the fifth array is a key value pair array;
and/or, the second generating unit further includes:
a fifth creation module, configured to obtain the data in the fifth array, and create at least one sixth array; the sixth array is used for storing test driving data;
the second processing module is used for assigning and processing the sixth array, traversing the fifth array and binarizing and processing key data in the fifth array;
and/or, the first determination unit further includes:
the first traversing module is used for traversing the column data in the sixth array in sequence and the test path set corresponding to the column data;
A fourth generation module, configured to generate chip pin data corresponding to a network point according to network point information corresponding to the test path set;
and the first transmitting module is used for sequentially transmitting test driving data according to the chip pin data and the level signals sent by the pins.
In the embodiment of the system of the present invention, the specific details of the method steps involved in the open circuit or short circuit test between the pins of the chip are described above, that is, the functional modules in the system are used to implement the steps or sub-steps in the embodiment of the method, which are not described herein.
In order to achieve the above objective, the present invention further provides an open circuit or short circuit test platform for chip pins, as shown in fig. 9, including a processor, a memory, and an open circuit or short circuit test platform control program for chip pins; the processor executes the open circuit or short circuit test platform control program for the chip pins, the open circuit or short circuit test platform control program for the chip pins is stored in the memory, and the open circuit or short circuit test platform control program for the chip pins realizes the open circuit or short circuit test method steps for the chip pins. For example:
S1, creating at least one matrix corresponding to a network point connection relation among chip pins;
s2, traversing connection relations among all network points in the matrix, and generating test paths corresponding to the network points;
s3, generating test driving data which corresponds to the test path and is used for testing open circuit or short circuit among pins of the chip according to the test path;
s4, acquiring level state data corresponding to the test driving data, and judging the connection relation among the pins of the chip in real time according to the level state data; wherein, the connection relation is open circuit connection or short circuit connection among chip pins.
The details of the steps are set forth above and are not repeated here.
In the embodiment of the invention, the built-in processor for the open circuit or short circuit test platform between the chip pins can be composed of integrated circuits, for example, can be composed of integrated circuits packaged singly or can be composed of a plurality of integrated circuits packaged with the same function or different functions, and comprises one or a plurality of central processing units (Central Processing unit, CPU), microprocessors, digital processing chips, graphic processors, various control chips and the like. The processor uses various interfaces and line connections to take various components, by running or executing programs or units stored in the memory, and invoking data stored in the memory to perform various functions and process data for open or short circuit testing between the chip pins;
The memory is used for storing program codes and various data, is installed in an open circuit or short circuit test platform used among chip pins, and realizes high-speed and automatic program or data access in the running process.
The Memory includes Read-Only Memory (ROM), random-access Memory (Random Access Memory, RAM), programmable Read-Only Memory (Programmable Read-Only Memory, PROM), erasable programmable Read-Only Memory (EPROM), one-time programmable Read-Only Memory (OTPROM), electrically erasable programmable Read-Only Memory (EEPROM), compact disc Read-Only Memory (Compact Disc Read-Only Memory, CD-ROM) or other optical disc Memory, magnetic disk Memory, tape Memory, or any other medium from which a computer can be used to carry or store data.
The invention creates at least one matrix corresponding to the network point connection relation among the chip pins through a method; traversing the connection relation among all network points in the matrix, and generating a test path corresponding to the network points; generating test driving data which corresponds to the test path and is used for testing open circuit or short circuit among pins of the chip according to the test path; acquiring level state data corresponding to the test driving data, and judging the connection relation among the chip pins in real time according to the level state data; and the system and the platform corresponding to the method can improve the analysis efficiency of the test path and the test efficiency of open and short circuits.
That is, the problem of searching the open-short circuit test path is solved by the scheme of the invention, compared with the traditional processing method, the analysis time is greatly reduced, the experience of software is enhanced, and the productivity is improved to a certain extent; in addition, the algorithm process related by the invention is independent of programming language and operating system, and can be easily transplanted into any practically needed development environment. The related generation processing algorithm of the open-short circuit test driving data greatly reduces the test times, and in the actual production process, the direct embodiment is that the test time is greatly shortened, and the production efficiency is improved.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. A method for testing open or short circuits between pins of a chip, the method comprising the steps of:
Creating at least one matrix corresponding to the network point connection relation among the chip pins;
traversing the connection relation among all network points in the matrix, and generating a test path corresponding to the network points;
generating test driving data which corresponds to the test path and is used for testing open circuit or short circuit among pins of the chip according to the test path;
acquiring level state data corresponding to the test driving data, and judging the connection relation among the chip pins in real time according to the level state data; wherein, the connection relation is open circuit connection or short circuit connection among chip pins.
2. The method for testing open or short circuits between pins of a chip according to claim 1, wherein said creating at least one matrix corresponding to network point connections between pins of the chip further comprises:
creating at least one stack, at least one first array and at least one second array, respectively; the first array is used for storing index records; the second plurality of sets is used for storing paths;
clearing the stack and the first array and creating at least one third numerical variable; wherein the third numerical variation is used for storing row index data;
And acquiring the line data in the third numerical variable, and stacking the line data, and simultaneously placing the line data in the first array.
3. The method for testing open or short circuit between chip pins according to claim 2, wherein said obtaining row data in said third numerical variable and stacking said row data while placing said row data in said first array further comprises:
judging whether a connection relation exists according to the data of the rows, and if the connection relation exists and the first array does not exist, performing value-added processing on the data of the rows; otherwise, traversing and recording all elements in the current stack, storing the elements into a second array, and removing stack top elements.
4. The method for testing open circuit or short circuit between pins of a chip according to claim 1, wherein said traversing connection relationships between all network points in the matrix and generating test paths corresponding to network points further comprises:
according to the connection relation between the network points, eliminating the repeated test path corresponding to the connection relation, and simultaneously creating at least one fourth array; the fourth array is used for storing the array after the repeated paths are eliminated;
Traversing a second set and generating a first test path corresponding to the second set; the first test path is a test path before sorting processing;
according to the first test path, performing ascending arrangement processing in combination with the network point subscript, and generating a second test path corresponding to the first test path; the second test path is a test path after the sorting processing;
acquiring path data in a fourth array, and judging whether the path data in the fourth array has the second test path or not; if not, the second test path is placed in the fourth array, otherwise, the next path is continuously traversed.
5. The method for testing open circuit or short circuit between pins of a chip according to claim 1 or 4, wherein said traversing connection relationships between all network points in the matrix and generating test paths corresponding to network points further comprises:
integrating and combining the test paths, and generating corresponding test paths with unique IDs;
creating at least one fifth array, and placing the test path with the unique ID in the fifth array; wherein the fifth array is a key value pair array.
6. The method for testing open or short circuits between pins of a chip according to claim 1, wherein said generating test driving data corresponding to said test path for testing open or short circuits between pins of a chip according to said test path, further comprises:
acquiring data in a fifth array, and creating at least one sixth array; the sixth array is used for storing test driving data;
and assigning the sixth array, traversing the fifth array, and binarizing key data in the fifth array.
7. The method for testing open or short circuits between chip pins according to claim 1, wherein said obtaining level state data corresponding to test driving data and determining connection relations between chip pins in real time based on said level state data, further comprises:
traversing the column data in the sixth array and the test path set corresponding to the column data in sequence;
generating chip pin data corresponding to the network points according to the network point information corresponding to the test path set;
and according to the chip pin data, combining level signals sent by the pins, and sequentially sending test driving data.
8. An open or short circuit test system for use between chip pins, the system being applied to the test method of any one of claims 1 to 7, the system comprising:
the matrix creation unit is used for creating at least one matrix corresponding to the network point connection relation among the pins of the chip;
the first generation unit is used for traversing the connection relation among all network points in the matrix and generating a test path corresponding to the network points;
the second generating unit is used for generating test driving data which corresponds to the test path and is used for testing open circuit or short circuit among pins of the chip according to the test path;
the first judging unit is used for acquiring level state data corresponding to the test driving data and judging the connection relation among the chip pins in real time according to the level state data; wherein, the connection relation is open circuit connection or short circuit connection among chip pins.
9. The open or short test system for chip pins according to claim 8, wherein said matrix creation unit further comprises:
a first creation module for creating at least one stack, at least one first array and at least one second array, respectively; the first array is used for storing index records; the second plurality of sets is used for storing paths;
A second creation module for flushing the stack and the first array and creating at least one third numerical variable; wherein the third numerical variation is used for storing row index data;
the first processing module is used for acquiring the line data in the third numerical variable, carrying out stack-joining processing on the line data, and simultaneously placing the line data in the first array;
and/or, the first processing module further comprises:
the first judging module is used for judging whether a connection relation exists according to the data of the data;
and/or, the first generating unit further comprises:
the third creation module is used for eliminating repeated test paths corresponding to the connection relation according to the connection relation between the network points, and creating at least one fourth array; the fourth array is used for storing the array after the repeated paths are eliminated;
the first generation module is used for traversing the second group and generating a first test path corresponding to the second group; the first test path is a test path before sorting processing;
the second generation module is used for carrying out ascending arrangement processing by combining network point subscripts according to the first test path and generating a second test path corresponding to the first test path; the second test path is a test path after the sorting processing;
The second judging module is used for acquiring the path data in the fourth array and judging whether the path data in the fourth array has the second test path or not; the method comprises the steps of carrying out a first treatment on the surface of the
And/or, the first generating unit further comprises:
the third generation module is used for integrating and combining the test paths and generating corresponding test paths with unique IDs;
a fourth creation module, configured to create at least one fifth array, and place the test path with the unique ID in the fifth array; wherein the fifth array is a key value pair array;
and/or, the second generating unit further includes:
a fifth creation module, configured to obtain the data in the fifth array, and create at least one sixth array; the sixth array is used for storing test driving data;
the second processing module is used for assigning and processing the sixth array, traversing the fifth array and binarizing and processing key data in the fifth array;
and/or, the first determination unit further includes:
the first traversing module is used for traversing the column data in the sixth array in sequence and the test path set corresponding to the column data;
A fourth generation module, configured to generate chip pin data corresponding to a network point according to network point information corresponding to the test path set;
and the first transmitting module is used for sequentially transmitting test driving data according to the chip pin data and the level signals sent by the pins.
10. The open circuit or short circuit test platform for the chip pins is characterized by comprising a processor, a memory and a control program of the open circuit or short circuit test platform for the chip pins; wherein the processor executes the open circuit or short circuit test platform control program for chip pins, the open circuit or short circuit test platform control program for chip pins is stored in the memory, and the open circuit or short circuit test platform control program for chip pins realizes the open circuit or short circuit test method for chip pins according to any one of claims 1 to 7.
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