CN117411582A - Time synchronization method and device - Google Patents
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- 108700009949 PTP protocol Proteins 0.000 claims abstract description 53
- 238000004891 communication Methods 0.000 claims description 25
- 230000001360 synchronised effect Effects 0.000 claims description 9
- 230000005540 biological transmission Effects 0.000 claims description 8
- 238000012545 processing Methods 0.000 claims description 6
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
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Abstract
The application provides a time synchronization method and a device, wherein the method comprises the following steps: receiving a first PTP protocol message sent by a main device, wherein the first PTP protocol message comprises a first timestamp with a first sub-timestamp and a second sub-timestamp; transmitting the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp into a first time register; the first sub-time stamp is periodically acquired from the first time register and transmitted to the exchange chip through the software task, the exchange chip stores the first sub-time stamp into the second time register, the clock chip is also enabled to generate the hardware task, the hardware task is used for enabling the clock chip to periodically acquire the second sub-time stamp from the first time register and transmit the second sub-time stamp to the exchange chip and the PHY chip, the exchange chip stores the second sub-time stamp into the second time register, and the PHY chip stores the second sub-time stamp into the third time register.
Description
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a time synchronization method and apparatus.
Background
The precision time protocol (English: precision Time Protocol, abbreviated as PTP) is a time synchronization protocol that can be used for high precision time synchronization and frequency synchronization between devices. The time synchronization accuracy of PTP is on the order of sub-microseconds.
Currently, networks that employ the PTP protocol are referred to as PTP domains. There is and only one clock source in the PTP domain, and all devices in the domain remain synchronized to this clock. The above clock source refers to the time set in the master (master) device. Other devices within the domain than the master device are called slave (slave) devices, which need to synchronize time with the master device via PTP.
The master/slave device obtains the current timestamp from the local PHY chip and carries the current timestamp in a PTP protocol message to be sent to the opposite terminal. After receiving the PTP protocol message sent by the master device, the slave device acquires the current time stamp from the PTP protocol message and modifies a time register in the local PHY chip according to the current time stamp so as to ensure time synchronization with the master device.
However, in the conventional time synchronization method, the following problems are also exposed: 1) The slave device includes not only PHY chip but also clock chip, switching chip, etc. When the slave device synchronizes the master device time, only the time registers in the PHY chip are modified, while the time registers in other chips are not modified, which causes a phase difference among a plurality of chips included in the slave device; 2) The presence of a phase difference will also result in the current timestamp obtained from the device being inaccurate. Since the clock chip provides the reference clock and the 1PPS signal to the PHY chip inside the slave device, the clock chip can again modify the time register in the PHY chip through the reference clock and the 1PPS signal after the time register in the PHY chip is modified.
Disclosure of Invention
In view of this, the present application provides a time synchronization method and apparatus, which are used to solve the problems that in the existing time synchronization method, there are phase differences among a plurality of chips inside a slave device and the current time stamp obtained from the slave device is inaccurate.
In a first aspect, the present application provides a time synchronization method, where the method is applied to a slave device, where the slave device is in a PTP domain, and the PTP domain further includes a master device, and the slave device includes a clock chip, a PHY chip, and a switch chip, and the method includes:
receiving a first PTP protocol message sent by the main equipment, wherein the first PTP protocol message comprises a first timestamp, and the first timestamp comprises a first sub-timestamp and a second sub-timestamp;
transmitting the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp into a first time register in the clock chip;
the first sub-time stamp is periodically acquired from the first time register and transmitted to the switching chip through a software task, the switching chip stores the first sub-time stamp into a second time register in the switching chip, the clock chip is also enabled to generate a hardware task, the hardware task is used for enabling the clock chip to periodically acquire from the first time register and transmit the second sub-time stamp to the switching chip and the PHY chip, the switching chip stores the second sub-time stamp into the second time register, and the PHY chip stores the second sub-time stamp into a third time register in the PHY chip.
In a second aspect, the present application provides a time synchronization apparatus, where the apparatus is applied to a slave device, where the slave device is in a PTP domain, and the PTP domain further includes a master device, and the slave device includes a clock chip, a PHY chip, and a switch chip, and the apparatus includes:
the receiving unit is used for receiving a first PTP protocol message sent by the main equipment, wherein the first PTP protocol message comprises a first timestamp, and the first timestamp comprises a first sub-timestamp and a second sub-timestamp;
a transmission unit, configured to transmit the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp into a first time register in the clock chip;
the transmission unit is further configured to periodically acquire the first sub-timestamp from the first time register and transmit the first sub-timestamp to the switch chip through a software task, where the switch chip stores the first sub-timestamp into a second time register in the switch chip, and also causes the clock chip to generate a hardware task, where the hardware task is configured to periodically acquire the clock chip from the first time register and transmit the second sub-timestamp to the switch chip and the PHY chip, where the switch chip stores the second sub-timestamp into the second time register, and where the PHY chip stores the second sub-timestamp into a third time register in the PHY chip.
In a third aspect, the present application provides a network device, where the network device is a slave device in a PTP domain, and the PTP domain further includes a master device, where the slave device includes a processor, a communication interface, a memory, a communication bus, a clock chip, a PHY chip, and a switch chip, where the processor, the communication interface, the memory, the clock chip, the PHY chip, and the switch chip complete communication with each other through the communication bus;
the communication interface is configured to receive a first PTP protocol packet sent by the master device, and transmit the first PTP protocol packet to the processor, where the first PTP protocol packet includes a first timestamp, and the first timestamp includes a first sub-timestamp and a second sub-timestamp;
the memory is used for storing a computer program;
the processor is configured to transmit the first sub-timestamp and the second sub-timestamp to the clock chip when executing the program stored in the memory;
the clock chip is used for storing the first sub-time stamp and the second sub-time stamp into a first time register in the clock chip;
the processor is further configured to periodically acquire, by a software task, the first sub-timestamp from the first time register and transmit the first sub-timestamp to the switch chip when executing the program stored in the memory;
the clock chip is further used for generating a hardware task according to the software task, wherein the hardware task periodically acquires the second sub-time stamp from the first time register and transmits the second sub-time stamp to the switching chip and the PHY chip;
the exchange chip is used for storing the first sub-time stamp into a second time register in the exchange chip and storing the second sub-time stamp into the second time register;
the PHY chip is configured to store the second sub-timestamp into a third time register in the PHY chip.
Therefore, by applying the time synchronization method and device provided by the application, the slave device receives the first PTP protocol message sent by the master device, wherein the first PTP protocol message comprises a first time stamp, and the first time stamp comprises a first sub time stamp and a second sub time stamp; the slave device transmits the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp into a first time register in the clock chip; the slave device periodically acquires and transmits a first sub-timestamp from the first time register to the exchange chip through a software task, the exchange chip stores the first sub-timestamp into a second time register in the exchange chip, and also enables the clock chip to generate a hardware task, wherein the hardware task is used for enabling the clock chip to periodically acquire and transmit a second sub-timestamp from the first time register to the exchange chip and the PHY chip, the exchange chip stores the second sub-timestamp into the second time register, and the PHY chip stores the second sub-timestamp into a third time register in the PHY chip.
Thus, the time synchronization between the slave device and the master device is realized through PTP; meanwhile, the time synchronization among the clock chip, the PHY chip and other chips in the slave device is realized. The method solves the problems that in the existing time synchronization mode, a plurality of chips inside the slave device have phase differences and the current time stamp acquired by the slave device is inaccurate.
Drawings
Fig. 1 is a flowchart of a time synchronization method provided in an embodiment of the present application;
fig. 2 is a connection relationship and a task transmission diagram between multiple chips in a slave device according to an embodiment of the present application;
FIG. 3 is a block diagram of a time synchronization apparatus according to an embodiment of the present application;
fig. 4 is a hardware structure of a network device according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the corresponding listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first message may also be referred to as a second message, and similarly, a second message may also be referred to as a first message, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.
The time synchronization method provided in the embodiment of the present application is described in detail below. Referring to fig. 1, fig. 1 is a flowchart of a time synchronization method provided in an embodiment of the present application. The method is applied to the slave equipment, and the time synchronization method provided by the embodiment of the application can comprise the following steps.
Step 110, receiving a first PTP protocol packet sent by the master device, where the first PTP protocol packet includes a first timestamp, and the first timestamp includes a first sub-timestamp and a second sub-timestamp;
specifically, the slave device is in a PTP domain, which also includes the master device. There is and only one clock source in the PTP domain, and all devices in the domain remain synchronized to this clock. The clock source refers to the time configured in the master device. Other devices within the domain than the master device are called slave (slave) devices, which need to synchronize time with the master device via PTP.
The master device obtains a first timestamp from the local PHY chip, and sends the first timestamp to the slave device with the first timestamp carried in a first PTP protocol message. After receiving a first PTP protocol message sent by a master device, a slave device obtains a first timestamp from the first PTP protocol message, wherein the first timestamp comprises a first sub-timestamp and a second sub-timestamp.
The first sub-time stamp refers to a time value which is included in the first time stamp and takes a year, a month, a day, a time, a minute and a second as a measurement unit, and the second sub-time stamp refers to a time value which is included in the first time stamp and takes a millisecond, a microsecond and a nanosecond as a measurement unit. The first sub-time stamp is in units of seconds and the second sub-time stamp is in units of nanoseconds.
Step 120, transmitting the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp into a first time register in the clock chip;
specifically, after the first timestamp is obtained from the device according to the description of step 110, the time values of different measurement units are converted into seconds or nanoseconds, and the first sub-timestamp and the second sub-timestamp are obtained.
The slave device transmits the first sub-timestamp and the second sub-timestamp to the clock chip respectively. After the clock chip acquires the first sub-time stamp and the second sub-time stamp, the first sub-time stamp and the second sub-time stamp are respectively stored in the positions corresponding to the first time register.
It should be noted that the first time register may be divided into a plurality of areas, and different areas are used for storing different sub-time stamps.
Step 130, periodically acquiring the first sub-timestamp from the first time register and transmitting the first sub-timestamp to the switch chip through a software task, wherein the switch chip stores the first sub-timestamp into a second time register in the switch chip, and also enables the clock chip to generate a hardware task, the hardware task is used for enabling the clock chip to periodically acquire the second sub-timestamp from the first time register and transmitting the second sub-timestamp to the switch chip and the PHY chip, the switch chip stores the second sub-timestamp into the second time register, and the PHY chip stores the second sub-timestamp into a third time register in the PHY chip.
Specifically, a periodic software task (i.e., a task generated by a processor in the slave device in the form of software) is initiated within the slave device. With this task, the slave periodically retrieves the first sub-timestamp from the first time register and transmits the first sub-timestamp to the switch chip. The switch chip stores the first sub-timestamp into a second time register in the switch chip.
Meanwhile, the task can trigger the clock chip to generate a hardware task (namely, a task generated by a logic circuit mode among components), and the hardware task is used for enabling the clock chip to periodically acquire the second sub-time stamp from the first time register and transmitting the second sub-time stamp to the exchange chip and the PHY chip. The switch chip stores the second sub-timestamp into a second time register and the PHY chip stores the second sub-timestamp into a third time register in the PHY chip.
Thus, the PHY chip stores the first sub-timestamp, and the exchange chip stores the first sub-timestamp and the second sub-timestamp. It will be appreciated that the second physical register may also be divided into a plurality of regions, with different regions being used to store different sub-time stamps.
Further, the hardware task is specifically that the clock chip periodically transmits a 1PPS signal, where the 1PPS signal includes a second sub-timestamp.
Further, in the embodiment of the present application, when the second sub-time stamp stored in the first time register in the clock chip is accumulated to a whole second, the clock chip generates the hardware task again, that is, generates and outputs a 1PPS signal to the switch chip and the PHY chip. And after the exchange chip and the PHY chip receive the 1PPS signal, resetting the second sub-time stamp stored in the local time register.
In the embodiment of the application, the clock chip also provides reference clocks for the PHY chip and the exchange chip respectively; the PHY chip and the exchange chip are started according to the reference clock and start working.
As shown in fig. 2, fig. 2 is a connection relationship and a task transmission diagram between multiple chips in a slave device according to an embodiment of the present application. In fig. 2, a time register is provided in each chip. Wherein the S part represents a first sub-timestamp and the NS part represents a second sub-timestamp. The S part is synchronized or acquired by the clock chip through a software task and a software reading mode, and the NS part is synchronized or acquired by the clock chip through a 1PPS signal.
Therefore, by applying the time synchronization method provided by the application, the slave device receives a first PTP protocol message sent by the master device, wherein the first PTP protocol message comprises a first time stamp, and the first time stamp comprises a first sub time stamp and a second sub time stamp; the slave device transmits the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp into a first time register in the clock chip; the slave device periodically acquires and transmits a first sub-timestamp from the first time register to the exchange chip through a software task, the exchange chip stores the first sub-timestamp into a second time register in the exchange chip, and also enables the clock chip to generate a hardware task, wherein the hardware task is used for enabling the clock chip to periodically acquire and transmit a second sub-timestamp from the first time register to the exchange chip and the PHY chip, the exchange chip stores the second sub-timestamp into the second time register, and the PHY chip stores the second sub-timestamp into a third time register in the PHY chip.
Thus, the time synchronization between the slave device and the master device is realized through PTP; meanwhile, the time synchronization among the clock chip, the PHY chip and other chips in the slave device is realized. The method solves the problems that in the existing time synchronization mode, a plurality of chips inside the slave device have phase differences and the current time stamp acquired by the slave device is inaccurate.
Optionally, in the embodiment of the present application, the method further includes a process that the slave device obtains a local current timestamp of the slave device and sends a second PTP protocol packet to the master device.
Specifically, after receiving the second PTP protocol packet, the slave device obtains a first timestamp local to the master device from the second PTP protocol packet. According to the existing PTP specification, the slave device needs to acquire its own local current timestamp and send a second PTP protocol message to the master device.
The slave device obtains a third sub-timestamp stored currently from the first time register in a software reading mode, and obtains a fourth sub-timestamp stored currently from the third time register; the slave device performs splicing and combining processing on the third sub-time stamp and the fourth sub-time stamp to obtain a second time stamp; the slave device generates and transmits a second PTP protocol message to the master device, the second PTP protocol message including a second timestamp.
Wherein the third sub-time stamp is measured in seconds, and the fourth sub-time stamp is measured in nanoseconds. The slave device can convert the third sub-time stamp into a time value taking the year, month, day, time, minute and second as measurement units; the fourth sub-timestamp is converted into a time value in units of milliseconds, microseconds, and nanoseconds. And the slave equipment performs splicing and combining processing on the converted time value to obtain a second time stamp.
Optionally, in an embodiment of the present application, a process of configuring the clock protocol locally by the slave device is further included.
Specifically, the user inputs configuration instructions in the form of command lines, which include a clock protocol. The slave device configures the clock protocol locally so that after receiving the time stamp synchronized by the master device, the slave device stores the time stamp into the first time register, the second time register and the third time register through the clock chip, the PHY chip and the interaction chip.
Based on the same inventive concept, the embodiment of the application also provides a time synchronization device corresponding to the time synchronization method. Referring to fig. 3, fig. 3 is a time synchronization apparatus provided in an embodiment of the present application, where the apparatus is applied to a slave device, where the slave device is in a PTP domain, and the PTP domain further includes a master device, and the slave device includes a clock chip, a PHY chip, and a switch chip, and the apparatus includes:
a receiving unit 310, configured to receive a first PTP protocol packet sent by the master device, where the first PTP protocol packet includes a first timestamp, and the first timestamp includes a first sub-timestamp and a second sub-timestamp;
a transmission unit 320, configured to transmit the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp into a first time register in the clock chip;
the transmission unit 320 is further configured to periodically obtain, by a software task, the first sub-timestamp from the first time register and transmit the first sub-timestamp to the switch chip, where the switch chip stores the first sub-timestamp into a second time register in the switch chip, and also causes the clock chip to generate a hardware task, where the hardware task is configured to periodically obtain, by the clock chip, the second sub-timestamp from the first time register and transmit the second sub-timestamp to the switch chip and the PHY chip, where the switch chip stores the second sub-timestamp into the second time register, and where the PHY chip stores the second sub-timestamp into a third time register in the PHY chip.
Optionally, the apparatus further comprises: an obtaining unit (not shown in the figure) configured to obtain, by means of software reading, a third sub-timestamp currently stored from the first time register, and obtain a fourth sub-timestamp currently stored from the third time register;
a splicing unit (not shown in the figure) for performing a splicing and combining process on the third sub-timestamp and the fourth sub-timestamp to obtain a second timestamp;
a sending unit (not shown in the figure) configured to send a second PTP protocol packet to the master device, where the second PTP protocol packet includes the second timestamp.
Optionally, the receiving unit 310 is further configured to receive a configuration instruction input by a user, where the configuration instruction includes a clock protocol, and the clock protocol is configured to store, after the slave device receives a timestamp synchronized by the master device, the timestamp into the first time register, the second time register, and the third time register through the clock chip, the PHY chip, and the switching chip.
Therefore, by applying the time synchronization device provided by the application, the slave device receives the first PTP protocol message sent by the master device, wherein the first PTP protocol message comprises a first time stamp, and the first time stamp comprises a first sub time stamp and a second sub time stamp; the slave device transmits the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp into a first time register in the clock chip; the slave device periodically acquires and transmits a first sub-timestamp from the first time register to the exchange chip through a software task, the exchange chip stores the first sub-timestamp into a second time register in the exchange chip, and also enables the clock chip to generate a hardware task, wherein the hardware task is used for enabling the clock chip to periodically acquire and transmit a second sub-timestamp from the first time register to the exchange chip and the PHY chip, the exchange chip stores the second sub-timestamp into the second time register, and the PHY chip stores the second sub-timestamp into a third time register in the PHY chip.
Thus, the time synchronization between the slave device and the master device is realized through PTP; meanwhile, the time synchronization among the clock chip, the PHY chip and other chips in the slave device is realized. The method solves the problems that in the existing time synchronization mode, a plurality of chips inside the slave device have phase differences and the current time stamp acquired by the slave device is inaccurate.
Based on the same inventive concept, the embodiment of the application also provides a network device, wherein the network device is a slave device in a PTP domain, and the PTP domain also comprises a master device. As shown in fig. 4, the slave device includes a processor 410, a communication interface 420, a memory 430, a communication bus 440, a clock chip 450, a PHY chip 460, and a switch chip 470. Wherein the processor 410, the communication interface 420, the memory 430, the clock chip 450, the PHY chip 460, and the switching chip 470 perform communication with each other through the communication bus 440;
the communication interface 420 is configured to receive a first PTP protocol packet sent by the master device, and transmit the first PTP protocol packet to the processor 410, where the first PTP protocol packet includes a first timestamp, and the first timestamp includes a first sub-timestamp and a second sub-timestamp;
the memory 430 is used for storing a computer program;
the processor 410 is configured to transmit the first sub-timestamp and the second sub-timestamp to the clock chip 450 when executing the program stored on the memory 430;
the clock chip 450 is configured to store the first sub-timestamp and the second sub-timestamp into a first time register in the clock chip 450;
the processor 410 is further configured to periodically obtain, by a software task, the first sub-timestamp from the first time register and transmit the first sub-timestamp to the switch chip 470 when executing the program stored on the memory 430;
the clock chip 450 is further configured to generate a hardware task according to the software task, where the hardware task is periodically obtained from the first time register and transmits the second sub-timestamp to the switch chip 470 and the PHY chip 460;
the switch chip 470 is configured to store the first sub-timestamp into a second time register in the switch chip 470, and store the second sub-timestamp into the second time register;
the PHY chip 460 is configured to store the second sub-timestamp into a third time register in the PHY chip 460.
Optionally, the processor 410 is further configured to obtain, by means of software reading, a third sub-timestamp currently stored from the first time register and a fourth sub-timestamp currently stored from the third time register when executing the program stored in the memory 430;
performing splicing and combining processing on the third sub-timestamp and the fourth sub-timestamp to obtain a second timestamp, and transmitting the second timestamp to the communication interface 420;
the communication interface 420 is further configured to send a second PTP protocol packet to the master device, where the second PTP protocol packet includes the second timestamp.
Optionally, the communication interface 420 is further configured to receive a configuration instruction input by a user, and transmit the configuration instruction to the processor 410, where the configuration instruction includes a clock protocol;
the processor 410 is further configured to, when executing the program stored in the memory 430, configure the clock protocol locally, and after the clock protocol is used to enable the processor 410 to obtain the timestamp synchronized with the master device, store the timestamp into the first time register, the second time register, and the third time register through the clock chip 450, the PHY chip 460, and the switch chip 470.
Optionally, the clock chip 450 is specifically configured to periodically obtain the second sub-timestamp from the first time register, generate and send 1PPS signals to the switch chip 470 and the PHY chip 460, where each 1PPS signal includes the second sub-timestamp.
Optionally, the clock chip 450 is further configured to send 1PPS information to the PHY chip 460 and the switching chip 470 when the first time register reaches the full second time;
the PHY chip 460 is configured to clear the second sub-timestamp stored in the third time register;
the switch chip 470 is configured to clear the second sub-timestamp stored in the second time register.
Optionally, the clock chip 450 is further configured to provide reference clocks to the PHY chip 460 and the switching chip 470, respectively;
the PHY chip 460 is further configured to start according to the reference clock;
the switching chip 470 is further configured to start according to the reference clock.
The time synchronization device shown in fig. 3 may be implemented by using a hardware structure of the network device shown in fig. 4. The Memory 430 may include a random access Memory (Random Access Memory, abbreviated as RAM) or a nonvolatile Memory (NVM), such as at least one magnetic disk Memory. Optionally, the memory 430 may also be at least one storage device located remotely from the aforementioned processor 410.
The processor 410 may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), etc.; it may also be a digital signal processor (English: digital Signal Processor; DSP; for short), an application specific integrated circuit (English: application Specific Integrated Circuit; ASIC; for short), a Field programmable gate array (English: field-Programmable Gate Array; FPGA; for short), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components.
The implementation process of the functions and roles of each unit in the above device is specifically shown in the implementation process of the corresponding steps in the above method, and will not be described herein again.
For the device embodiments, reference is made to the description of the method embodiments for the relevant points, since they essentially correspond to the method embodiments. The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purposes of the present application. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
For the time synchronization apparatus and the machine-readable storage medium embodiments, since the method content involved is substantially similar to the method embodiments described above, the description is relatively simple, and reference will only be made to part of the description of the method embodiments.
The foregoing description of the preferred embodiments of the present invention is not intended to limit the invention to the precise form disclosed, and any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (12)
1. A method of time synchronization, the method being applied to a slave device, the slave device being in a PTP domain, the PTP domain further including a master device, the slave device including a clock chip, a PHY chip, and a switching chip, the method comprising:
receiving a first PTP protocol message sent by the main equipment, wherein the first PTP protocol message comprises a first timestamp, and the first timestamp comprises a first sub-timestamp and a second sub-timestamp;
transmitting the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp into a first time register in the clock chip;
the first sub-time stamp is periodically acquired from the first time register and transmitted to the switching chip through a software task, the switching chip stores the first sub-time stamp into a second time register in the switching chip, the clock chip is also enabled to generate a hardware task, the hardware task is used for enabling the clock chip to periodically acquire from the first time register and transmit the second sub-time stamp to the switching chip and the PHY chip, the switching chip stores the second sub-time stamp into the second time register, and the PHY chip stores the second sub-time stamp into a third time register in the PHY chip.
2. The method according to claim 1, wherein the method further comprises:
acquiring a third sub-timestamp stored currently from the first time register in a software reading mode, and acquiring a fourth sub-timestamp stored currently from the third time register;
performing splicing and combining treatment on the third sub-time stamp and the fourth sub-time stamp to obtain a second time stamp;
and sending a second PTP protocol message to the master device, wherein the second PTP protocol message comprises the second timestamp.
3. The method of claim 1, wherein prior to receiving the first PTP protocol packet sent by the master device, the method further comprises:
and receiving a configuration instruction input by a user, wherein the configuration instruction comprises a clock protocol, and the clock protocol is used for storing the time stamp into the first time register, the second time register and the third time register through the clock chip, the PHY chip and the switching chip after the slave device receives the time stamp synchronized with the master device.
4. A time synchronization apparatus, the apparatus being applied to a slave device, the slave device being in a PTP domain, the PTP domain further including a master device, the slave device including a clock chip, a PHY chip, and a switching chip, the apparatus comprising:
the receiving unit is used for receiving a first PTP protocol message sent by the main equipment, wherein the first PTP protocol message comprises a first timestamp, and the first timestamp comprises a first sub-timestamp and a second sub-timestamp;
a transmission unit, configured to transmit the first sub-timestamp and the second sub-timestamp to the clock chip, so that the clock chip stores the first sub-timestamp and the second sub-timestamp into a first time register in the clock chip;
the transmission unit is further configured to periodically acquire the first sub-timestamp from the first time register and transmit the first sub-timestamp to the switch chip through a software task, where the switch chip stores the first sub-timestamp into a second time register in the switch chip, and also causes the clock chip to generate a hardware task, where the hardware task is configured to periodically acquire the clock chip from the first time register and transmit the second sub-timestamp to the switch chip and the PHY chip, where the switch chip stores the second sub-timestamp into the second time register, and where the PHY chip stores the second sub-timestamp into a third time register in the PHY chip.
5. The apparatus of claim 4, wherein the apparatus further comprises:
the acquisition unit is used for acquiring a third sub-timestamp stored currently from the first time register in a software reading mode and acquiring a fourth sub-timestamp stored currently from the third time register;
the splicing unit is used for carrying out splicing and combining treatment on the third sub-time stamp and the fourth sub-time stamp to obtain a second time stamp;
and the sending unit is used for sending a second PTP protocol message to the master equipment, wherein the second PTP protocol message comprises the second timestamp.
6. The apparatus of claim 4, wherein the receiving unit is further configured to receive a configuration instruction input by a user, the configuration instruction including a clock protocol, the clock protocol configured to store, after receiving, by the slave device, a timestamp of the master device synchronization, the timestamp into the first time register, the second time register, and the third time register via the clock chip, the PHY chip, and the switch chip.
7. The network device is characterized in that the network device is a slave device in a PTP domain, the PTP domain further comprises a master device, and the slave device comprises a processor, a communication interface, a memory, a communication bus, a clock chip, a PHY chip and a switching chip, wherein the processor, the communication interface, the memory, the clock chip, the PHY chip and the switching chip complete communication with each other through the communication bus;
the communication interface is configured to receive a first PTP protocol packet sent by the master device, and transmit the first PTP protocol packet to the processor, where the first PTP protocol packet includes a first timestamp, and the first timestamp includes a first sub-timestamp and a second sub-timestamp;
the memory is used for storing a computer program;
the processor is configured to transmit the first sub-timestamp and the second sub-timestamp to the clock chip when executing the program stored in the memory;
the clock chip is used for storing the first sub-time stamp and the second sub-time stamp into a first time register in the clock chip;
the processor is further configured to periodically acquire, by a software task, the first sub-timestamp from the first time register and transmit the first sub-timestamp to the switch chip when executing the program stored in the memory;
the clock chip is further used for generating a hardware task according to the software task, wherein the hardware task periodically acquires the second sub-time stamp from the first time register and transmits the second sub-time stamp to the switching chip and the PHY chip;
the exchange chip is used for storing the first sub-time stamp into a second time register in the exchange chip and storing the second sub-time stamp into the second time register;
the PHY chip is configured to store the second sub-timestamp into a third time register in the PHY chip.
8. The network device of claim 7, wherein the processor is further configured to obtain, by means of software reading, a third sub-timestamp currently stored from the first time register and a fourth sub-timestamp currently stored from the third time register when executing the program stored on the memory;
performing splicing and combining processing on the third sub-time stamp and the fourth sub-time stamp to obtain a second time stamp, and transmitting the second time stamp to the communication interface;
the communication interface is further configured to send a second PTP protocol packet to the master device, where the second PTP protocol packet includes the second timestamp.
9. The network device of claim 7, wherein the communication interface is further configured to receive a configuration instruction entered by a user and transmit the configuration instruction to the processor, the configuration instruction comprising a clock protocol;
the processor is further configured to configure the clock protocol locally when executing the program stored in the memory, where the clock protocol is configured to store the time stamp into the first time register, the second time register, and the third time register through the clock chip, the PHY chip, and the switch chip after the processor obtains the time stamp synchronized with the master device.
10. The network device of claim 7, wherein the clock chip is configured to periodically obtain the second sub-time stamp from the first time register, generate and send 1PPS signals to the switch chip and the PHY chip, respectively, and each 1PPS signal includes the second sub-time stamp.
11. The network device of claim 7, wherein the clock chip is further configured to send 1PPS information to the PHY chip and the switching chip, respectively, when the first time register reaches a full second time;
the PHY chip is used for resetting the second sub-time stamp stored in the third time register;
the exchange chip is used for resetting the second sub-time stamp stored in the second time register.
12. The network device of claim 7, wherein the clock chip is further configured to provide reference clocks for the PHY chip and the switching chip, respectively;
the PHY chip is further used for starting according to the reference clock;
the switching chip is also used for starting according to the reference clock.
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