CN117411322A - Automatic control method for staggered phases of asymmetric resonant half-bridge - Google Patents
Automatic control method for staggered phases of asymmetric resonant half-bridge Download PDFInfo
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- CN117411322A CN117411322A CN202311258352.2A CN202311258352A CN117411322A CN 117411322 A CN117411322 A CN 117411322A CN 202311258352 A CN202311258352 A CN 202311258352A CN 117411322 A CN117411322 A CN 117411322A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
- H02M3/33571—Half-bridge at primary side of an isolation transformer
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Abstract
The invention discloses an automatic control method for the staggered phase of an asymmetric resonant half-bridge, which comprises the following steps: respectively obtaining a first sampling current value, a second sampling current value and a sampling voltage value; performing first logic processing on the first sampling current value and the sampling voltage value to obtain a first time sequence pulse, and performing second logic processing on the second sampling current value and the sampling voltage value to obtain a second time sequence pulse; performing first cycle control on the on and off of a first high-side switch and a first low-side switch of a first half bridge by using a first timing pulse so as to output a first half sine phase current on a secondary side; and performing second cycle control on the on and off of a second high-side switch and a second low-side switch of the second half bridge by using the two time sequence pulses so as to output a second half sine phase current by the secondary side when the first half sine phase current drops to zero. By implementing the invention, the two-way or multi-way staggered asymmetric resonant half-bridge is operated at the optimal phase staggered angle, and the output power is improved.
Description
Technical Field
The invention relates to the technical field of switching power supplies, in particular to an automatic control method for staggered phases of asymmetric resonant half-bridges.
Background
As shown in fig. 1, fig. 1 is a circuit diagram of an asymmetric resonant half-bridge converter in the prior art, and an output side of the asymmetric resonant half-bridge converter releases energy to the output side only after a switch is turned off by resonant inductance and capacitive resonance discharge, in output power, a transformer winding is larger in loss due to an oversized transformer, and current stress of a rectifier diode is limited and cannot be continuously lifted. Although the converter is modulated by PWM, the pulse width range of the output voltage can be well regulated, and better gain regulating capability is obtained. However, compared with the LLC resonant half-bridge, as shown in fig. 2, although the output voltage adjustment range of the LLC is narrower, the output side of the secondary side of the transformer is full-wave rectification, so that a larger power and a lower output voltage ripple can be output, as shown in fig. 6, fig. 6 is a schematic waveform diagram of a resonant half-bridge circuit in the prior art, C11 in fig. 6 is the resonant current of a single half-bridge, V11 is the bridge arm voltage of the single half-bridge, and C12 is the corresponding diode output current. By adopting a similar output side rectification scheme of the LLC converter, the output power of the asymmetric resonant half-bridge converter can be well expanded, and therefore, in order to increase the output power of the asymmetric resonant half-bridge converter, a multiphase interleaving technology is required. However, unlike the PWM interleaving technique of the common topology, the switching frequency and the duty ratio of the asymmetric resonant converter in operation are both converted along with different output voltages and load conditions, so it is very difficult to set a full load range by a fixed phase difference, otherwise, it cannot be ensured that the rectified side current waveforms of the two-phase asymmetric resonant half-bridge converter after interleaving operation are exactly arranged in two half sine waves, so that the purposes of optimizing output ripple waves and maximizing ripple current reduction of the output capacitor are achieved in circuit and control, as shown in fig. 8, fig. 8 is a simulated waveform diagram in which the phase interleaving of the asymmetric resonant half-bridge is not performed by automatic control, in fig. 8, C31 and C32 are respectively resonant currents of two half-bridges, P31 and P32 are respectively bridge arm voltages of two half-bridges, C33 and C34 are respectively output currents of secondary diodes (D1 and D2), and V31 is an output voltage, and the output power is not maximized due to the fact that the automatic control of the phase interleaving is not performed.
If the fixed phase difference achieves staggered synchronous operation, both the switching frequency and resonant discharge time will change as the output load changes, and thus the operating waveform will necessarily deviate from the optimum operating region. When the working phases of the two staggered asymmetrical resonant converters are not located in the optimal interval, one of the phases outputs more power, so that the problem of unbalanced heat is generated.
Since the frequency and duty cycle of the interleaved asymmetrical resonant converter will vary during operation, the optimum operating waveform cannot be obtained by conventional fixed phase interleaved control methods.
Disclosure of Invention
In the prior art, since the frequency and the duty ratio are changed when the staggered asymmetrical resonant converter works, one of the phases outputs more power by the conventional staggered control method with fixed phases, so that the problem of unbalanced heat is generated.
Aiming at the problems, an automatic control method of the staggered phase of the asymmetric resonant half-bridge is provided, wherein the peak current and the output voltage flowing through a first high-side switch and a second high-side switch are sampled to obtain a first sampling current value, a second sampling current value and a sampling voltage value, and the first logic processing is performed to obtain a first time sequence pulse, and the second logic processing is performed to obtain a second time sequence pulse; the first time sequence pulse and the second time sequence pulse are utilized to respectively carry out circulation control on the high-side switch and the low-side switch of the first half bridge and the second half bridge, so that the two-way or multi-way staggered asymmetric resonance half bridge operates at the optimal phase staggered angle, the output power is improved, and the heat and power balance of a wide output adjusting range, low output ripple current and multi-way AHB is realized.
An automatic control method for the staggered phase of an asymmetric resonant half-bridge comprises the following steps:
step 100, respectively sampling peak currents and output voltages flowing through a first high-side switch and a second high-side switch to obtain a first sampling current value, a second sampling current value and a sampling voltage value;
step 200, performing first logic processing on the first sampling current value and the sampling voltage value to obtain a first time sequence pulse, and performing second logic processing on the second sampling current value and the sampling voltage value to obtain a second time sequence pulse;
step 300, performing a first cycle control on the on/off of a first high-side switch and a first low-side switch of a first half bridge by using a first timing pulse to output a first half sine phase current on a secondary side;
step 400, performing a second cycle control on the on/off of a second high-side switch and a second low-side switch of a second half bridge by using two time sequence pulses, so that a secondary side outputs a second half sine phase current when the first half sine phase current drops to a zero point;
step 500, cycling steps 100-400 to output a first half sinusoidal phase current and a second half sinusoidal phase current of staggered phases to a load at the secondary side;
the output power of the first half sine phase and the output power of the second half sine phase are the same.
In combination with the automatic control method of the staggering phase according to the present invention, in a first possible implementation manner, the step 200 includes:
step 210, inputting the sampled voltage value and the set value of the output voltage into an adder for processing, and obtaining a first output value;
and 220, inputting the first output value into a proportional-integral controller for processing, and obtaining the output value of the voltage ring.
In combination with the first possible embodiment of the present invention, in a second possible embodiment, the step 200 further includes:
step 230, inputting the voltage loop output value to the negative terminal of the first comparator;
step 240, inputting the first sampling current value into a positive terminal of the first comparator;
step 250, inputting the output value of the first comparator to a first rising edge value unit, and obtaining a first rising edge output value.
In combination with the second possible embodiment of the present invention, in a third possible embodiment, the step 200 further includes:
step 260, resetting the first integrator by using the first rising edge output value;
step 270, comparing the output value of the first integrator with a first set value of the on-time of the first low side switch by using a second comparator;
step 280, if the first set value is reached, the second comparator outputs a first high level;
step 290, controlling the first driving unit to output a first driving pulse by using the first high level to drive the first high-side switch to be turned on.
In combination with the first possible embodiment of the present invention, in a fourth possible embodiment, the step 200 further includes:
step 291, outputting a second high level by using the second comparator;
step 292, using the second high level to control the first driving unit to output a second driving pulse to drive the first low-side switch to be turned on;
the second driving pulse is complementary with the first driving pulse after dead time, and the second driving pulse and the first driving pulse form a first timing pulse.
In combination with the first possible embodiment of the present invention, in a fifth possible embodiment, the step 200 further includes:
step 230a, inputting the voltage loop output value to the negative terminal of the third comparator;
step 240a, inputting the second sampling current value to the positive terminal of the third comparator;
step 250a, inputting the output value of the third comparator and the synchronization compensation value of the synchronization module into an and gate processing unit, and inputting the output value of the and gate processing unit into a second rising edge value taking unit to obtain a second rising edge output value;
the synchronous module is used for starting a second diode of the second half bridge to output a second half sine phase current when the first half sine phase current output by a first diode of the first half bridge drops to 0 point.
In combination with the fifth possible embodiment of the present invention, in a sixth possible embodiment, the step 200 further includes:
step 260a, resetting the second integrator by using the second rising edge output value;
step 270a, comparing the output value of the second integrator with a second set value of the on-time of the second low side switch by using a fourth comparator;
step 280a, if the second set value is reached, the fourth comparator outputs a third high level;
step 290a, using the third high level to control the second driving unit to output a third driving pulse to drive the second high-side switch.
In combination with the sixth possible embodiment of the present invention, in a seventh possible embodiment, the step 200 further includes:
step 291a, outputting a fourth high level by the fourth comparator;
step 292a, using the fourth high level to control the second driving unit to output a fourth driving pulse to drive the second low-side switch to be turned on;
the fourth driving pulse is complementary with the third driving pulse after dead time, and the fourth driving pulse and the third driving pulse form a second time sequence pulse.
In combination with the seventh possible embodiment of the present invention, in an eighth possible embodiment, the step 250a includes:
step 251, inputting a slope output value of a first integrator into a low-pass filter, and averaging the slope output value by using the low-pass filter to obtain a first average value;
step 252, subtracting the second set value from the first average value which is 2 times of the first average value to obtain a first synchronous output value;
step 253, performing slope compensation on the first synchronous output value to obtain a second synchronous output value;
step 254, comparing the second synchronous output value with the ramp output value using a fifth comparator: and outputting a synchronous compensation value if the slope output value is larger than the second synchronous output value.
By implementing the asymmetric resonant half-bridge staggered phase automatic control method, the peak current and the output voltage flowing through the first high-side switch and the second high-side switch are sampled to obtain a first sampling current value, a second sampling current value and a sampling voltage value, and the first logic processing is performed to obtain a first time sequence pulse, and the second logic processing is performed to obtain a second time sequence pulse; the first time sequence pulse and the second time sequence pulse are utilized to respectively carry out circulation control on the high-side switch and the low-side switch of the first half bridge and the second half bridge, so that the two-way or multi-way staggered asymmetric resonance half bridge operates at the optimal phase staggered angle, the output power is improved, and the heat and power balance of a wide output adjusting range, low output ripple current and multi-way AHB is realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a resonant half-bridge circuit of the prior art;
FIG. 2 is a schematic diagram of a prior art LLC circuit;
FIG. 3 is a schematic diagram of an asymmetric resonant half-bridge circuit of the present invention;
FIG. 4 is a schematic diagram of an asymmetric resonant half-bridge interleaved phase auto-control phase interleaving in accordance with the present invention;
FIG. 5 is a schematic diagram of the logic control of the asymmetric resonant half-bridge interleaved phase auto-control phase interleaving of the present invention;
FIG. 6 is a schematic diagram of a simulated waveform of a resonant half-bridge circuit of the prior art;
FIG. 7 is a schematic diagram of simulated waveforms of an asymmetric resonant half-bridge interleaved phase auto-control phase interleaving in accordance with the present invention;
FIG. 8 is a schematic diagram of simulated waveforms of the asymmetric resonant half-bridge interleaved phase without automatic control phase interleaving in accordance with the present invention;
FIG. 9 is a first schematic diagram of an interleaved control simulation waveform of an asymmetric resonant half-bridge of the present invention passing through a first timing pulse and a second timing pulse;
FIG. 10 is a schematic diagram of simulated waveforms for ramp interleave control of first and second timing pulses of an asymmetric resonant half-bridge in accordance with the present invention;
FIG. 11 is a second schematic diagram of an interleaved control simulation waveform of an asymmetric resonant half-bridge of the present invention passing through a first timing pulse and a second timing pulse;
FIG. 12 is a schematic diagram of a ramp compensated interleaved control simulation waveform of an asymmetric resonant half-bridge of the present invention with first and second timing pulses;
FIG. 13 is a schematic diagram of a low side switching ramp compensation waveform for an asymmetric resonant half-bridge of the present invention;
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. Based on the embodiments of the present invention, other embodiments that may be obtained by those of ordinary skill in the art without undue burden are within the scope of the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
In the prior art, since the frequency and the duty ratio are changed when the staggered asymmetrical resonant converter works, one of the phases outputs more power by the conventional staggered control method with fixed phases, so that the problem of unbalanced heat is generated.
Aiming at the problems, an automatic control method for the staggered phase of the asymmetric resonant half-bridge is provided.
Example 1
Aiming at the problems, an automatic control method for the staggered phase of the asymmetric resonant half-bridge is provided.
In a first aspect, as shown in fig. 3, fig. 3 is a schematic diagram of an asymmetric resonant half-bridge circuit of the present invention; an automatic control method for the staggered phase of an asymmetric resonant half-bridge comprises the following steps:
step 100, sampling peak currents and output voltages flowing through the first high-side switch and the second high-side switch respectively, and obtaining a first sampling current value, a second sampling current value and a sampling voltage value. Step 200, performing a first logic process 10 on the first sampled current value and the sampled voltage value to obtain a first time sequence pulse, and performing a second logic process 20 on the second sampled current value and the sampled voltage value to obtain a second time sequence pulse, as shown in fig. 5, fig. 5 is a logic control schematic diagram of the automatic control phase interleaving of the asymmetric resonant half-bridge interleaving phase in the present invention.
Upon acquisition of the first timing pulse, step 200 preferably includes:
step 210, inputting the sampled voltage value (Vout, after analog-to-digital ADC conversion) and the set value vo_set (28V) of the output voltage into an adder for processing, to obtain a first output value; and 220, inputting the first output value into a proportional-integral controller PI3 for processing, and obtaining the output value of the voltage ring.
And sampling the switching current peak value when the high-side switch of the first half bridge/the second half bridge is conducted, and performing loop control of a peak current mode. The sampled output voltage is used as a voltage stabilizing control loop of the output voltage.
The half-bridge high-side switches (Q1, Q3) of the two-phase asymmetric resonant half-bridge (AHB) are controlled by using a peak current mode, the output value of the voltage outer ring determines the current peak value flowing through the primary sides of the high-side switches (Q1, Q3) and the transformers (Tr 2, tr 3), and an isolation sampling method can also be directly used for directly controlling the output voltage in a closed loop manner at the high voltage side. The output of PI3 (proportional integral controller) in fig. 5 is the voltage loop output value for direct comparison with the peak current of the two-phase AHB when the high-side switches (Q1, Q3) are on, thereby achieving the switching control of the first high-side switch Q1/the second high-side switch Q3.
After the first high-side switch Q1/second high-side switch Q3 is turned off, the dead time TD is inserted, and then the first low-side switch Q2/second low-side switch Q4 of the corresponding bridge arm is turned on.
Preferably, step 200 further comprises:
step 230, inputting the output value of the voltage loop to the negative terminal of the first comparator Comp 1; step 240, inputting the first sampling current value to the positive terminal of the first comparator Comp 1; in step 250, the first comparator Comp1 outputs the first rising edge value to the first rising edge value unit ed1 to obtain a first rising edge output value.
Preferably, step 200 further comprises:
step 260, resetting the first Integrator1 by using the first rising edge output value; step 270, comparing the output value of the first Integrator1 with a first set value toff_set1 of the on-time of the first low-side switch by using a second comparator re; step 280, if the first set value toff_set1 is reached, the second comparator re outputs a first high level; in step 290, the first driving unit DT is controlled to output a first driving pulse by using the first high level to drive the first high-side switch Q1 to turn on.
The first Integrator1 is reset to 0 value and then accumulated continuously, and compares its output value with a first set value toff_set1, and outputs a first high level after reaching the first set value toff_set1.
Wherein ramp is a ramp output value of a first timing pulse (PWM of PHASE a), cc in the diagram is used to limit the lowest frequency of the first high-side switch Q1, and then the first Integrator1 is reset by the OR gate processing unit OR1 with the first rising edge output value.
The first set value toff_set1 is the on-time set value of the first low-side switch Q2.
Preferably, step 200 further comprises: step 291, outputting a second high level by the second comparator re;
step 292, controlling the first driving unit DT to output a second driving pulse by using a second high level to drive the first low-side switch Q2 to be turned on; the second driving pulse is complementary to the first driving pulse after the dead time TD, and the first driving pulse and the second driving pulse form a first timing pulse.
Preferably, step 200 further comprises: step 230a, inputting the output value of the voltage loop to the negative terminal of the third comparator Comp; step 240a, inputting the second sampling current value to the positive terminal of the third comparator Comp; step 250a, inputting the output value of the third comparator Comp AND the synchronization compensation value of the synchronization module into the AND gate processing unit AND, AND inputting the output value of the AND gate processing unit AND into the second rising edge value unit ed to obtain a second rising edge output value; the synchronization module is configured to start the second diode D2 of the second half bridge to output the second half sinusoidal phase current when the first half sinusoidal phase current output by the first diode D1 of the first half bridge drops to 0 point.
Preferably, as shown in fig. 10, fig. 10 is a schematic diagram of simulation waveforms of Ramp stagger control of first timing pulse and second timing pulse of an asymmetric resonant half-bridge according to the present invention, in fig. 10, C51 and C52 are respectively resonant currents of two half-bridges, P51 and P52 are respectively PWM of high side tubes of two half-bridges, and R51 and R52 are respectively Ramp (Ramp) outputs of two PHASEs (PHASE a and PHASE B); step 200 further comprises: step 260a, resetting the second Integrator1 by using the second rising edge output value; step 270a, comparing the output value of the second Integrator1 with a second set value toff_set2 of the on time of the second low side switch Q4 by using a fourth comparator re 1; step 280a, if the second set value toff_set2 is reached, the fourth comparator ed1 outputs the third high level; in step 290a, the second driving unit DT1 is controlled to output a third driving pulse to drive the second high-side switch Q2.
The same principle is adopted, the second Integrator2 is reset to 0 value and then accumulated continuously, the output value of the second Integrator is compared with the second set value toff_set2, and the third high level is output after the output value is reached.
Cc1 in the figure is used to limit the lowest frequency of the second high-side switch Q3, and then resets the second Integrator2 by the OR gate processing unit OR2 using the first rising edge output value.
Preferably, step 200 further comprises: step 291a, outputting a fourth high level by the fourth comparator ed 1; step 292a, using a fourth high level to control the second driving unit DT1 to output a fourth driving pulse to drive the second low-side switch to turn on; the fourth driving pulse is complementary with the third driving pulse after dead time, and the third driving pulse and the fourth driving pulse form a second time sequence pulse.
Preferably, as shown in fig. 12, fig. 12 is a schematic diagram of a ramp compensated interleaved control simulation waveform of the asymmetric resonant half-bridge of the present invention passing through a first timing pulse and a second timing pulse; in fig. 12, T71 is the period length of PHASE a, R72 and R71 are the ramp output value ramp of PHASE a and the TOFF-SET off time of PHASE a, respectively, P71 is the PWM of one of the half-bridges, and C71 and C72 are the output currents after rectification by the secondary diodes (D1 and D2), respectively.
Step 250a includes: step 251, inputting the ramp output value ramp of the first Integrator1 to a low-pass filter lpf, and averaging the ramp output value ramp by using the low-pass filter lpf to obtain a first average value; step 252, subtracting the second set value toff_set2 from the first average value of 2 times to obtain a first synchronous output value; step 253, performing slope compensation on the first synchronous output value to obtain a second synchronous output value; step 254, comparing the second synchronous output value with the ramp output value ramp by the fifth comparator Comp 2: and if the ramp output value ramp is larger than the second synchronous output value, outputting a synchronous compensation value.
Fig. 13 is a schematic diagram of a low-side switching slope compensation waveform of the asymmetric resonant half-bridge according to the present invention, wherein in fig. 13, R81, T81, and P81 are respectively an integrator output slope signal (ramp), a turn-on duration of a low-side switching tube, and PWM of the low-side switching tube; the ramp output value ramp of the PWM is filtered by a low-pass filter lpf to obtain an average value, and then multiplied by 2 to change the average value into a periodic peak value. Then, the on-length of the second high-side switch Q3 can be determined by subtracting the set value toff_set2 of the on-length of the second low-side switch Q4. In addition, since the transformer Tr4 does not transmit power to the secondary side immediately after the second high-side switch Q3 is actually turned off, and the current release is generally turned on after a delay of several hundred nanoseconds, it is also necessary to compensate for the delay of current release into the transformer in the phase interleaving control.
The second synchronous output value (compensated PHASE difference delay) is then compared with the ramp output value ramp of PHASE a, and when the first timing pulse (PWM of PHASE a) ramp output value ramp is higher than the second synchronous output value (PHASE difference control amount), the synchronous compensation value (high level control signal) is output. The synchronization compensation value (high level control signal) AND the second timing pulse (PHASE B PWM) off time are anded to determine the PHASE B second high side switch Q3 off time, which is also the time following the PHASE a discharge current approaching zero.
Step 300, as shown in fig. 9, fig. 9 is a first schematic diagram of an interleaved control simulation waveform of the asymmetric resonant half-bridge of the present invention passing through a first time sequence pulse and a second time sequence pulse, in fig. 9, C41 and C42 are respectively resonant currents of two half-bridges, P41 and P42 are respectively high-side tube PWM of the two half-bridges, PWM of a low-side tube is complementary to the high-side tube, and V41 is an output voltage; performing a first cycle control on the on and off of a first high-side switch Q1 and a first low-side switch Q2 of the first half bridge by using a first timing pulse so as to output a first half sine phase current on the secondary side; step 400, performing a second cycle control on the on/off of the second high-side switch Q3 and the second low-side switch Q4 of the second half bridge by using the two timing pulses, so as to output a second half sinusoidal phase current from the secondary side when the first half sinusoidal phase current drops to zero; step 500, cycling steps 100-400 to output a first half sinusoidal phase current and a second half sinusoidal phase current of staggered phases to a load at the secondary side; the output power of the first half sine phase and the output power of the second half sine phase are the same.
The first half-bridge is a first asymmetric resonant half-bridge, the first asymmetric resonant half-bridge comprises a first high-side switch Q1, a first low-side switch Q2, a midpoint capacitor (C1) and resonant inductors (L1 and L2), time sequence pulses input on the first half-bridge comprise a first sub-time sequence pulse and a second sub-time sequence pulse, and first cycle control is carried out on the first high-side switch Q1 and the first low-side switch Q2 respectively, so that current of a first half sine phase is output on the secondary side.
The second half-bridge is a second asymmetric resonant half-bridge, the second asymmetric resonant half-bridge comprises a second high-side switch Q3, a second low-side switch Q4, a midpoint capacitor (C3) and resonant inductors (L3 and L4), time sequence pulses input on the second half-bridge comprise a third sub-sequence pulse and a fourth sub-sequence pulse, and second cycle control is conducted on the second high-side switch Q3 and the second low-side switch Q4 respectively, so that currents of a second half sine phase are output on the secondary side.
FIG. 4 is a schematic diagram of an asymmetrical resonant half-bridge interleaved phase auto-control phase interleaving in accordance with the present invention; the first half sine phase current is the half sine phase current output by the first half bridge, the second half sine phase current is the half sine phase current output by the second half bridge, and the two half sine phase currents are output in a staggered way, namely when the first half sine phase current drops to zero point, the second half sine phase current is output, and then when the second half sine phase current drops to zero point, the first half sine phase current … is output
In this embodiment, as shown in fig. 11, fig. 11 is a second schematic diagram of an interleaved control simulation waveform of the asymmetric resonant half-bridge according to the present invention passing through a first time sequence pulse and a second time sequence pulse, in fig. 11, C61 and C62 are respectively resonant currents of two half-bridges, P61 and P62 are respectively PWM of high side tubes of two half-bridges, and C63 and C64 are output currents after rectification by secondary side diodes (D1 and D2); the secondary output current of the two-PHASE asymmetric resonant half bridge (AHB) is distributed in an optimal PHASE through the synchronization module, specifically, after the first high-side switch Q1 of the first half sine PHASE (PHASE A) is closed, the transformer is transferred to a PHASE of resonance and outputting power to the secondary side, and when the demagnetizing current of the transformer is lower than the resonant discharging current, the transformer stops transmitting power to the secondary side. At this time, the current of the secondary rectifying diode of the first half sine PHASE (PHASE a) is reduced to be close to the zero point, and through synchronous compensation, the high-side switch is closed at the time point to enter the closing stage at the second half sine PHASE (PHASE B), and after the transformer starts resonant discharge, the output currents of the two staggered asymmetric resonant half-bridge (AHB) converters can reach the optimal PHASE difference working state in the secondary side. Before a first low-side switch Q2 of a first half sine PHASE (PHASE A) is closed, a synchronous module is utilized to determine the on time of a second high-side switch Q3 in advance, so that when the output current of the first half sine PHASE (PHASE A) drops to the zero moment of a sine wave, the output current of the second half sine PHASE (PHASE B) is just started, as shown in fig. 7, fig. 7 is a simulation waveform diagram of the automatic control PHASE staggering of the asymmetric resonant half-bridge staggered PHASE, in fig. 7, C21 and C22 are respectively resonant currents of two half-bridges, P21 and P22 are respectively bridge arm voltages of the two half-bridges, C23 and C24 are respectively output currents rectified by secondary side diodes (D1 and D2), and V21 is an output voltage.
The first conduction time length is enough time length needed by the first low-side switch Q2, ZVS operation of the first high-side switch Q1 is achieved after the first conduction time length is conducted, and the first low-side switch Q2 can only have enough current to charge a midpoint capacitor (C1) of the first half-bridge after the first conduction time length is enough to operate, so that ZVS operation of the first high-side switch Q1 is achieved.
When the current of the transformer runs to the negative direction, the required demagnetization time is calculated according to the demagnetization voltage of the transformer, which is obtained by the current peak value and the output voltage turn ratio when the first high-side switch Q1 is conducted, and the demagnetization time is the conduction time length of the first low-side switch Q2, namely the first conduction time length. The time required to achieve ZVS can thus be calculated from the inductance of the transformer at the nominal output voltage and the nominal power in the initial state.
When the output voltage changes, the resulting transformer demagnetizing voltage obtained by multiplying the output voltage by the turn ratio will also change, so the time required for the exciting inductance of the transformer to drop below zero will be longer, but the exciting inductance will not change substantially in normal operation, so the ratio of the output voltage to the highest output voltage can be used as the set value for increasing the conduction time of the first low side switch Q2 of the first half bridge.
By implementing the automatic control method of the asymmetric resonant half-bridge staggered phase, the peak current and the output voltage flowing through the first high-side switch Q1 and the second high-side switch Q2 are sampled to obtain a first sampling current value, a second sampling current value and a sampling voltage value, and the first logic processing is performed to obtain a first time sequence pulse, and the second logic processing is performed to obtain a second time sequence pulse; the first time sequence pulse and the second time sequence pulse are utilized to respectively carry out circulation control on the high-side switch and the low-side switch of the first half bridge and the second half bridge, so that the two-way or multi-way staggered asymmetric resonance half bridge operates at the optimal phase staggered angle, the output power is improved, and the heat and power balance of a wide output adjusting range, low output ripple current and multi-way AHB is realized.
The foregoing is only illustrative of the present invention and is not to be construed as limiting thereof, but rather as various modifications, equivalent arrangements, improvements, etc., within the spirit and principles of the present invention.
Claims (9)
1. An automatic control method for the staggered phase of an asymmetric resonant half-bridge is characterized by comprising the following steps:
step 100, respectively sampling peak currents and output voltages flowing through a first high-side switch and a second high-side switch to obtain a first sampling current value, a second sampling current value and a sampling voltage value;
step 200, performing first logic processing on the first sampling current value and the sampling voltage value to obtain a first time sequence pulse, and performing second logic processing on the second sampling current value and the sampling voltage value to obtain a second time sequence pulse;
step 300, performing a first cycle control on the on/off of a first high-side switch and a first low-side switch of a first half bridge by using a first timing pulse to output a first half sine phase current on a secondary side;
step 400, performing a second cycle control on the on/off of a second high-side switch and a second low-side switch of a second half bridge by using two time sequence pulses, so that a secondary side outputs a second half sine phase current when the first half sine phase current drops to a zero point;
step 500, cycling steps 100-400 to output a first half sinusoidal phase current and a second half sinusoidal phase current of staggered phases to a load at the secondary side;
the output power of the first half sine phase and the output power of the second half sine phase are the same.
2. The method of automatic control of the phase of the interleaved asymmetric resonant half-bridge as recited in claim 1 wherein said step 200 comprises:
step 210, inputting the sampled voltage value and the set value of the output voltage into an adder for processing, and obtaining a first output value;
and 220, inputting the first output value into a proportional-integral controller for processing, and obtaining the output value of the voltage ring.
3. The method of automatic phase control of an asymmetrical resonant half-bridge interleaved phase according to claim 2 wherein step 200 further comprises:
step 230, inputting the voltage loop output value to the negative terminal of the first comparator;
step 240, inputting the first sampling current value into a positive terminal of the first comparator;
step 250, inputting the output value of the first comparator to a first rising edge value unit, and obtaining a first rising edge output value.
4. The method of automatic control of the phase of interleaved asymmetric resonant half-bridge according to claim 3 wherein step 200 further comprises:
step 260, resetting the first integrator by using the first rising edge output value;
step 270, comparing the output value of the first integrator with a first set value of the on-time of the first low side switch by using a second comparator;
step 280, if the first set value is reached, the second comparator outputs a first high level;
step 290, controlling the first driving unit to output a first driving pulse by using the first high level to drive the first high-side switch to be turned on.
5. The method of automatic phase control of an asymmetrical resonant half-bridge interleaved phase according to claim 4 wherein step 200 further comprises:
step 291, outputting a second high level by using the second comparator;
step 292, using the second high level to control the first driving unit to output a second driving pulse to drive the first low-side switch to be turned on;
the second driving pulse is complementary with the first driving pulse after dead time, and the second driving pulse and the first driving pulse form a first timing pulse.
6. The method of automatic phase control of an asymmetrical resonant half-bridge interleaved phase according to claim 2 wherein step 200 further comprises:
step 230a, inputting the voltage loop output value to the negative terminal of the third comparator;
step 240a, inputting the second sampling current value to the positive terminal of the third comparator;
step 250a, inputting the output value of the third comparator and the synchronization compensation value of the synchronization module to an and gate processing unit, and inputting the output value of the and gate processing unit to a second rising edge value taking unit to obtain a second rising edge output value;
the synchronous module is used for starting a second diode of the second half bridge to output a second half sine phase current when the first half sine phase current output by a first diode of the first half bridge drops to 0 point.
7. The method of automatic phase control of an asymmetrical resonant half-bridge interleaved phase according to claim 6 wherein step 200 further comprises:
step 260a, resetting the second integrator by using the second rising edge output value;
step 270a, comparing the output value of the second integrator with a second set value of the on-time of the second low side switch by using a fourth comparator;
step 280a, if the second set value is reached, the fourth comparator outputs a third high level;
step 290a, using the third high level to control the second driving unit to output a third driving pulse to drive the second high-side switch.
8. The method of automatic phase control of an asymmetrical resonant half-bridge interleaved phase according to claim 7 wherein step 200 further comprises:
step 291a, outputting a fourth high level by the fourth comparator;
step 292a, using the fourth high level to control the second driving unit to output a fourth driving pulse to drive the second low-side switch to be turned on;
the fourth driving pulse is complementary with the third driving pulse after dead time, and the fourth driving pulse and the third driving pulse form a second time sequence pulse.
9. The method of automatic phase control of an asymmetrical resonant half-bridge interleaved phase according to claim 8 wherein step 250a comprises:
step 251, inputting the slope output value of the first integrator into a low-pass filter, and averaging the slope output value by using the low-pass filter to obtain a first average value;
step 252, subtracting the second set value from the first average value which is 2 times of the first average value to obtain a first synchronous output value;
step 253, performing slope compensation on the first synchronous output value to obtain a second synchronous output value;
step 254, comparing the second synchronous output value with the ramp output value using a fifth comparator: and outputting a synchronous compensation value if the slope output value is larger than the second synchronous output value.
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| WO2018097820A1 (en) * | 2016-11-22 | 2018-05-31 | Power Integrations, Inc. | Switch control for resonant power converter |
| WO2018157796A1 (en) * | 2017-02-28 | 2018-09-07 | 深圳市皓文电子有限公司 | Resonant converter |
| CN114448263A (en) * | 2022-04-12 | 2022-05-06 | 茂睿芯（深圳）科技有限公司 | Converter based on asymmetric half-bridge flyback circuit and control method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018097820A1 (en) * | 2016-11-22 | 2018-05-31 | Power Integrations, Inc. | Switch control for resonant power converter |
| WO2018157796A1 (en) * | 2017-02-28 | 2018-09-07 | 深圳市皓文电子有限公司 | Resonant converter |
| CN114448263A (en) * | 2022-04-12 | 2022-05-06 | 茂睿芯（深圳）科技有限公司 | Converter based on asymmetric half-bridge flyback circuit and control method thereof |
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