CN117410231A - Fuse wire monitoring structure, manufacturing method thereof and semiconductor wafer - Google Patents
Fuse wire monitoring structure, manufacturing method thereof and semiconductor wafer Download PDFInfo
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- CN117410231A CN117410231A CN202311426730.3A CN202311426730A CN117410231A CN 117410231 A CN117410231 A CN 117410231A CN 202311426730 A CN202311426730 A CN 202311426730A CN 117410231 A CN117410231 A CN 117410231A
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- 238000004519 manufacturing process Methods 0.000 title claims description 15
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- 238000002360 preparation method Methods 0.000 claims abstract description 4
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
Abstract
The invention provides a fuse monitoring structure, a preparation method thereof and a semiconductor wafer. Simultaneously, the bonding pad, the conductive plug and the metal block which are vertically connected form a polar plate unit, two opposite polar plate units form a test capacitor as a monitoring element, a first groove is formed above the window layer, a second groove is formed between the two polar plate units, and the depth of the first groove is the same as that of the second groove. The change of the depth of the second groove can cause the change of the comprehensive dielectric constant of the dielectric material layers between the polar plate units so as to influence the capacitance value, so that the change of the depth of the second groove can be reflected by the change of the capacitance value of the test capacitor, and whether the thickness of the window layer is in a preset range or not is judged, and the monitoring of the fuse structure is realized. The method and the device monitor the stability and uniformity of the etching process reversely through the electrical test, so that the product trimming yield is improved more effectively.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a fuse monitoring structure, a method for manufacturing the same, and a semiconductor wafer.
Background
With the improvement of the semiconductor technology level and the increase of the complexity of the integrated circuit, the number of devices in a chip is continuously increased, and the failure of a single component such as a transistor or a memory cell often leads to the functional failure of the whole integrated circuit. In order to ensure that the functions of the whole integrated circuit are not affected when the individual components are damaged, a Fuse structure (Fuse) is often arranged inside the integrated circuit and is used for fusing certain specific structures to adjust the output voltage or the output current of the circuit so as to achieve the purpose of adjusting the functions of the circuit, and the fusing process is generally called trimming. According to the method of blowing fuses, fuses can be classified into electric fuses (electric fuses) and Laser fuses (Laser fuses), wherein the Laser fuses are generally blown by irradiating the fuses with a Laser beam of a certain energy.
As shown in fig. 1, a conventional fuse structure includes a fuse 110 and a window layer 133 covering the fuse, wherein the window layer 133 is usually obtained by etching a portion of a thickness of the dielectric layer 102, and a recess is formed above the window layer 133 after etching. The thickness of the window layer 133 is thinner, so that the laser beam irradiates the window layer 133 through the groove during the subsequent laser trimming, and the fuse 110 is blown. The material of the fuse is usually Al, and when trimming, because the boiling point of Al (2327 ℃) is low, laser is beaten on the fuse to enable the fuse to be gasified and expanded, and when internal pressure is accumulated to a certain degree, a window layer (usually oxide) on the surface of the fuse is exploded, so that Al steam escapes. Controlling the thickness of the window layer above the fuse wire has great influence on the subsequent repair and adjustment of the fuse wire, if the window layer is too thick, the gasified Al steam can not fry open the surface oxide and further cause repair and adjustment failure, if the window layer is too thin, the adjustment window of laser beam energy can be smaller, and the repair and adjustment effect is poor; in addition, if the thickness of the window layer is not suitable, mechanical stress generated by expansion of the laser vaporization fuse during laser trimming can directly lead to cracks and even fracture of the nearby dielectric layer. It can be seen that the thickness of the window layer has a significant impact on the overall trimming process and thus on the stability of the overall integrated circuit.
Therefore, there is a need to design a monitoring structure to better and more effectively monitor window layer thickness.
It should be noted that the foregoing description of the technical background is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a fuse monitoring structure for solving the problem of monitoring the thickness of a window layer above a fuse in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing a fuse monitoring structure, the method comprising the steps of:
s1: providing a substrate, forming a fuse and a metal interconnection layer on the surface of the substrate, wherein the metal interconnection layer comprises at least two mutually independent metal blocks, and a dielectric layer coating the fuse and the metal interconnection layer is also formed on the surface of the substrate;
s2: forming a conductive plug penetrating through the dielectric layer from top to bottom, wherein the conductive plug is in electrical contact with the metal block;
s3: forming an electric lead-out layer and a passivation layer on the surface of the dielectric layer, wherein the electric lead-out layer comprises at least two mutually independent bonding pads, and the bonding pads are electrically connected with the metal block through the conductive plugs; the passivation layer coats the electric lead-out layer;
s4: forming a photoresist layer on the surface of the passivation layer, and synchronously removing the passivation layer covered on the surface of the bonding pad, the passivation layer positioned above the fuse wire and the passivation layer positioned between two adjacent bonding pads through an etching process;
s5: and etching again, and synchronously removing the dielectric layer with partial thickness above the fuse and the dielectric layer with partial thickness between two adjacent bonding pads, so that a first groove is formed above the fuse, a second groove is formed between two adjacent bonding pads, the depths of the first groove and the second groove are the same, and the bottom surfaces of the first groove and the second groove are positioned on the same horizontal plane.
Preferably, the vertically connected bonding pad, the conductive plug and the metal block form a polar plate unit of the test capacitor, and the dielectric layer between two adjacent polar plate units and the second groove form a dielectric material layer of the test capacitor; the dielectric layer reserved above the fuse is a window layer;
the change of the capacitance value of the test capacitor reflects the change of the depth of the second groove, and the depth of the first groove is the same as that of the second groove, so that whether the thickness of the window layer below is in a preset range is judged through the change of the depth of the first groove, and the monitoring of the fuse structure is realized.
Preferably, the cross-sectional area of the second groove is not less than half of the cross-sectional area between the two plate units.
Preferably, the test capacitor is formed on a scribe line of the wafer, and the fuse and window layer is formed on a die of the wafer.
Preferably, in step S4, the passivation layer covering the surface of the bonding pad is a first thickness, the removed passivation layer above the fuse is also a first thickness and forms a first opening, and the removed passivation layer between two adjacent bonding pads is also a first thickness and forms a second opening;
in step S5, etching is continued along the first opening and the second opening to obtain a first groove and a second groove.
The present invention also provides a fuse monitoring structure including:
a substrate, wherein a fuse and a metal interconnection layer are formed on the surface of the substrate, and the metal interconnection layer comprises at least two mutually independent metal blocks;
a dielectric layer on the surface of the substrate, the dielectric layer coating the fuse and metal interconnect layer, a conductive plug being formed in the dielectric layer and being in electrical contact with the metal block;
the electric lead-out layer and the passivation layer are positioned on the surface of the dielectric layer, the electric lead-out layer comprises at least two mutually independent bonding pads, and the bonding pads are electrically connected with the metal block through the conductive plugs; the passivation layer coats the side wall of the bonding pad;
wherein, the first groove penetrating through the passivation layer and part of the thickness dielectric layer is formed above the fuse, and a window layer is formed between the bottom surface of the first groove and the dielectric layer between the fuse; a second groove with the same depth as the first groove is formed between two adjacent bonding pads, the first groove and the second groove are formed by synchronous etching, and the bottom surfaces of the first groove and the second groove are positioned on the same horizontal plane.
Preferably, the vertically connected bonding pad, the conductive plug and the metal block form a polar plate unit of the test capacitor, and the dielectric layer between two adjacent polar plate units and the second groove form a dielectric material layer of the test capacitor;
the change of the capacitance value of the test capacitor reflects the change of the depth of the second groove, and the depth of the first groove is the same as that of the second groove, so that whether the thickness of the window layer below is in a preset range is judged through the change of the depth of the first groove, and the monitoring of the fuse structure is realized.
Preferably, the cross-sectional area of the second groove is not less than half of the cross-sectional area between the two plate units.
Preferably, the fuse monitoring structure includes one or more fuses, and the fuses are sequentially arranged in a lateral direction or in a longitudinal direction.
The invention also provides a semiconductor wafer, wherein a plurality of exposure units are divided in the semiconductor wafer, a plurality of core particles are divided in a single exposure unit, and cutting channels are arranged between adjacent exposure units and between adjacent core particles;
the semiconductor wafer comprises the fuse monitoring structure, the fuse is formed on the core particle, and the test capacitor is formed on the dicing channel.
As described above, the invention provides a fuse monitoring structure, a method for manufacturing the same and a semiconductor wafer. Simultaneously, the bonding pad, the conductive plug and the metal block which are vertically connected form a polar plate unit, two opposite polar plate units form a test capacitor as a monitoring element, a first groove is formed above the window layer, a second groove is formed between the two polar plate units, and the depth of the first groove is the same as that of the second groove. Under the condition that the section of the second groove is kept unchanged, the change of the depth of the second groove can lead to the change of the comprehensive dielectric constant of the dielectric material layers among the polar plate units, so that the capacitance value is influenced, and the change of the depth of the second groove can be reflected through the change of the capacitance value of the test capacitor. And because the depth of the first groove is the same as that of the second groove, whether the thickness of the window layer below is in a preset range is judged through the depth change of the first groove, and the monitoring of the fuse structure is realized. The method and the device monitor the stability and uniformity of the etching process reversely through the electrical test, so that the product trimming yield is improved more effectively.
Drawings
FIG. 1 is a schematic diagram of a fuse and window layer structure in the prior art.
Fig. 2 is a schematic diagram showing a structure of forming a fuse and a metal interconnection layer on a substrate surface according to the present invention.
Fig. 3 is a schematic structural diagram illustrating formation of a conductive plug in a dielectric layer according to the present invention.
Fig. 4 is a schematic structural diagram of forming an electrical extraction layer and a passivation layer on a surface of a dielectric layer according to the present invention.
Fig. 5 is a schematic structural view illustrating a photoresist layer formed on a passivation layer according to the present invention.
Fig. 6 is a schematic structural diagram of forming a first opening and a second opening by etching according to the present invention.
Fig. 7 is a schematic structural diagram of forming a first groove and a second groove by etching according to the present invention.
FIG. 8 is a schematic side view of the fuse monitor structure formed by removing the photoresist layer according to the present invention.
FIG. 9 is a schematic top view of the fuse monitor structure formed by removing the photoresist layer according to the present invention.
Fig. 10 is a schematic view of a wafer with a fuse monitor structure according to the present invention.
Description of element reference numerals
10. Wafer with a plurality of wafers
11. Exposure unit
12. Core particle
101. Substrate and method for manufacturing the same
102. Dielectric layer
103. Passivation layer
104. Photoresist layer
110. Fuse wire
111. First metal block
112. Second metal block
113. Conductive plug
121. First bonding pad
122. Second bonding pad
131. First groove
132. Second groove
133. Window layer
1310. A first opening
1320. A second opening
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
Example 1
As shown in fig. 2 to 8, the present embodiment provides a method for manufacturing a fuse monitoring structure, which includes the following steps:
s1: as shown in fig. 2, a substrate 101 is provided, a fuse 110 and a metal interconnection layer are formed on the surface of the substrate 101, the metal interconnection layer includes at least two mutually independent metal blocks, and a dielectric layer 102 covering the fuse 110 and the metal interconnection layer is further formed on the surface of the substrate 101;
specifically, the substrate 101 may be a single-layer or multi-layer structure, for example, may be silicon, germanium, silicon On Insulator (SOI), or silicon carbide substrate, or may be a substrate including other element semiconductors or compound semiconductors, for example, gallium arsenide, indium phosphide, or the like, and a silicon material is preferable in this embodiment. The dielectric layer may be an interlayer dielectric layer commonly used in integrated circuit support such as silicon oxide, silicon oxynitride, silicon oxycarbide, or may be an amorphous carbon, porous silicon oxide, or other low-K dielectric material.
The material of the metal interconnection layer can be one or any of copper, aluminum, gold, silver, nickel and cobalt; the fuse 110 is preferably made of aluminum, and the dielectric layer 102 thinned above the fuse 110 is irradiated by laser to make the fuse 110 gasified and expanded by utilizing the low boiling point characteristic of aluminum, so that Al vapor escapes to finish trimming. As the conductive interconnection structure, aluminum material has advantages of low resistance, easy deposition and etching, and the like, and when the metal interconnection layer is made of the same aluminum material as the fuse 110, both can be formed by simultaneous deposition. As an example, the metal interconnection layer is a first interconnection layer of a bottom layer, and the fuse 110 is formed in the first interconnection layer, so that a connection line between the fuse 110 and the semiconductor device is shortest, the resistance is low, and the trimming effect is good. For the metal interconnection layer, in this embodiment, two mutually independent metal blocks are taken as an example, and the metal interconnection layer includes a first metal block 111 and a second metal block 112.
Next, step S2 is performed: as shown in fig. 3, a conductive plug 113 penetrating from top to bottom is formed in the dielectric layer 102, and the conductive plug 113 is in electrical contact with the metal block;
specifically, the conductive plugs 113 may be made of metal materials such as tungsten, copper or silver, preferably tungsten, which is commonly used to make the conductive plugs 113 connect adjacent metal layers due to its good conductivity and step coverage. After depositing the metal tungsten, a process of planarizing the surface of the dielectric layer 102 may be included, such as removing the metal tungsten outside the vertical vias by chemical mechanical polishing, or thinning the dielectric layer 102 to a desired thickness to further obtain a planarized surface. In addition, before depositing the metal tungsten, a metal barrier layer is formed in the vertical through hole so as to avoid the diffusion of atoms in the metal material. The material of the metal barrier layer can be at least one of TiN and TaN.
Next, step S3 is performed: as shown in fig. 4, an electrical extraction layer and a passivation layer 103 are formed on the surface of the dielectric layer 102, where the electrical extraction layer includes at least two mutually independent pads, and the pads are electrically connected with the metal block through the conductive plugs 113; the passivation layer 103 coats the electrical extraction layer;
like the metal interconnect layer, the electrical extraction layer may be one or any of copper, aluminum, gold, silver, nickel, cobalt. The passivation layer 103 may be a silicon nitride material, which is used to strengthen the tightness of the device and shield the device from the harmful effects of external impurities, ion charge moisture, and the like. The packaging yield of the device is improved, and the mechanical protection of the surface is provided for the subsequent process treatments such as scribing, mounting, bonding and the like. In this embodiment, two pads independent of each other are taken as an example, and the electrical extraction layer includes a first pad 121 and a second pad 122.
Next, step S4 is performed: as shown in fig. 5 to 6, a photoresist layer 104 is formed on the surface of the passivation layer 103, and the passivation layer 103 covering the surface of the bonding pad, the passivation layer 103 located above the fuse 110, and the passivation layer 103 located between two adjacent bonding pads are simultaneously removed by an etching process;
next, step S5 is performed: as shown in fig. 7 to 9, etching is performed again to simultaneously remove the dielectric layer 102 of a partial thickness located above the fuse 110 and the dielectric layer 102 of a partial thickness located between two adjacent pads, thereby forming a first groove 131 above the fuse 110 and a second groove 132 between two adjacent pads, the depths of the first groove 131 and the second groove 132 are the same, and the bottom surfaces of the first groove 131 and the second groove 132 are at the same level.
Specifically, in step S4, the thickness of the passivation layer 103 removed simultaneously is the same, for example, the thickness of the passivation layer 103 covering the surface of the bonding pad is the first thickness, the thickness of the passivation layer 103 removed above the fuse 110 is also the first thickness and forms the first opening 1310, the thickness of the passivation layer 103 removed between two adjacent bonding pads is also the first thickness and forms the second opening 1320, and the depth of the first opening 1310 is the same as the depth of the second opening 1320. And exposing the bonding pad through etching for subsequent electrical testing.
In step S5, the etching is continued along the first opening 1310 and the second opening 1320, and the passivation layer 103 at the first opening 1310 and the second opening 1320 is not completely removed in step S4, so that the passivation layer 103 at the first opening 1310 and the second opening 1320 needs to be removed by etching, and then a part of the dielectric layer 102 is removed by etching down along the openings, so as to obtain the first groove 131 and the second groove 132. The dielectric layer 102 remaining over the fuse 110 is the window layer 133. When trimming, laser irradiates the window layer 133 to vaporize the fuse 110, and the window layer 133 on the surface of the fuse 110 is blasted to realize circuit adjustment.
Further, the vertically connected pads, the conductive plugs 113 and the metal blocks form a plate unit, correspondingly, the first metal block 111, the conductive plugs 113 and the first pad 121 form a plate unit, the second metal block 112, the conductive plugs 113 and the second pad 122 form another plate unit, the dielectric layer 102 and the second groove 132 between two adjacent plate units form a dielectric material layer of the test capacitor, and according to a capacitance calculation formula:
wherein epsilon-permittivity; s-effective area between two polar plates; a k-electrostatic force constant; d-distance between two polar plates; in the case that the cross section of the second groove 132 remains unchanged, the change in depth will cause the overall dielectric constant of the dielectric material layer to change, thereby affecting the capacitance value, so that the change in capacitance value of the test capacitor can reflect the change in depth of the second groove 132. Because the depth of the first groove 131 is the same as that of the second groove 132, whether the thickness of the lower window layer 133 is within the preset range is determined by the depth change of the first groove 131, so as to monitor the fuse structure.
When testing, the capacitance value of the test capacitor can be obtained by adding the probe to the two bonding pads for testing, the capacitance value of the test capacitor corresponding to the thickness of the window layer 133 in the normal range is set as the standard value, when the actually measured capacitance value deviates from the standard value by a certain degree, the thickness of the window layer 133 is determined to be inconsistent with the process requirement, namely, the stability and uniformity of the etching process in the step 5 are monitored reversely through the electrical test, so that the product trimming yield is improved more effectively.
It should be noted that, for the cross-sectional area of the second groove 132, it should be not less than half of the cross-sectional area between the two polar plate units, that is, a certain duty ratio is ensured, so that when the depth of the second groove 132 changes, the final capacitance value can be reflected, otherwise, if the cross-sectional area of the second groove 132 is too small, the depth change is insufficient to cause the capacitance value change, and the purpose of monitoring cannot be achieved.
Further, as a monitor element, the test capacitor is formed on the scribe line of the wafer, and the fuse 110 and the window layer 133 are formed on the die of the wafer to achieve the effect of adjusting the circuits in the die.
Example two
On the basis of the first embodiment, the present embodiment provides a fuse monitoring structure, which may be formed by the manufacturing method in the first embodiment, but is not limited to the manufacturing method. As shown in fig. 8 to 9, the fuse monitoring structure includes:
a substrate 101; a fuse 110 and a metal interconnection layer are formed on the surface of the substrate 101, and the metal interconnection layer comprises at least two mutually independent metal blocks;
a dielectric layer 102 formed on the surface of the substrate 101, wherein the dielectric layer 102 covers the fuse 110 and the metal interconnection layer, and a conductive plug 113 electrically contacting the metal block is formed in the dielectric layer 102;
the electric extraction layer and the passivation layer 103 are formed on the surface of the dielectric layer 102, and the electric extraction layer comprises at least two mutually independent bonding pads, and the bonding pads are electrically connected with the metal block through the conductive plugs 113; the passivation layer 103 coats the pad side wall;
wherein, the first groove 131 penetrating the passivation layer 103 and part of the thickness of the dielectric layer 102 is formed above the fuse 110, and the window layer 133 is formed on the dielectric layer 102 between the bottom surface of the first groove 131 and the fuse 110; a second groove 132 with the same depth as the first groove 131 is formed between two adjacent bonding pads, the first groove 131 and the second groove 132 are formed by synchronous etching, and the bottom surfaces are positioned on the same horizontal plane.
Further, the vertically connected pads, conductive plugs 113, and metal blocks form a plate unit, and correspondingly, the first metal block 111, conductive plugs 113, and first pad 121 form a plate unit, and the second metal block 112, conductive plugs 113, and second pad 122 form a further plate unit.
In the case that the cross section of the second groove 132 remains unchanged, the change in depth will cause the overall dielectric constant of the dielectric material layer to change, thereby affecting the capacitance value, so that the change in capacitance value of the test capacitor can reflect the change in depth of the second groove 132. Because the depth of the first groove 131 is the same as that of the second groove 132, whether the thickness of the lower window layer 133 is within the preset range is determined by the depth change of the first groove 131, so as to monitor the structure of the fuse 110.
When testing, the capacitance value of the test capacitor can be obtained by adding the probe on the two bonding pads for testing, the capacitance value of the test capacitor corresponding to the thickness of the window layer 133 in the normal range is set as the standard value, when the actually measured capacitance value deviates from the standard value by a certain degree, the thickness of the window layer 133 is determined to be inconsistent with the process requirement, namely, the stability and uniformity of the etching process are reversely monitored through the electrical test, so that the product trimming yield is more effectively improved.
Further, as shown in fig. 9, the fuse 110 monitoring structure includes one or more fuses 110, where the fuses 110 are sequentially arranged in a transverse direction or in a longitudinal direction, and the fuses 110 are equal in size. More specifically, when the fuses 110 are arranged in the lateral direction, the top ends of the fuses 110 are flush; when the fuses 110 are arranged in the longitudinal direction, the left end of each fuse 110 is flush.
It should be noted that, the process for forming each material layer in the fuse monitoring structure may refer to the above-mentioned preparation method, and will not be repeated here.
Example III
On the basis of the above embodiment, this embodiment provides a semiconductor wafer, as shown in fig. 10, in which a plurality of exposure units 11 (Shot) are divided, and since the size of a single exposure area of an exposure system is limited in a photolithography process, it is necessary to divide one wafer 10 into a plurality of exposure units 11 for exposure imaging during exposure, and a plurality of dies 12 (Die) are divided into a single exposure unit 11, the exposure units 11 and the dies 12 are generally rectangular in shape and are arranged in an array. Cutting lines are provided between the adjacent exposure units 11 and between the adjacent core particles 12.
The semiconductor wafer is provided with the fuse monitoring structure, the fuse 110 is formed on the die 12, and the test capacitor is formed on the scribe line. The test capacitors can be formed in each cutting channel or randomly distributed, for example, one test capacitor is respectively arranged in the upper direction, the lower direction, the left direction, the right direction and the center direction of a single exposure unit, and at least one test capacitor is arranged in each exposure unit to ensure that each exposure unit can be monitored.
In summary, the present invention provides a fuse monitoring structure, a method for manufacturing the same, and a semiconductor wafer, wherein the fuse monitoring structure includes a fuse on a surface of a substrate and a window layer obtained by etching a portion of a dielectric layer over the fuse. Simultaneously, the bonding pad, the conductive plug and the metal block which are vertically connected form a polar plate unit, two opposite polar plate units form a test capacitor as a monitoring element, a first groove is formed above the window layer, a second groove is formed between the two polar plate units, and the depth of the first groove is the same as that of the second groove. Under the condition that the section of the second groove is kept unchanged, the change of the depth of the second groove can lead to the change of the comprehensive dielectric constant of the dielectric material layers among the polar plate units, so that the capacitance value is influenced, and the change of the depth of the second groove can be reflected through the change of the capacitance value of the test capacitor. And because the depth of the first groove is the same as that of the second groove, whether the thickness of the window layer below is in a preset range is judged through the depth change of the first groove, and the monitoring of the fuse structure is realized. The method and the device monitor the stability and uniformity of the etching process reversely through the electrical test, so that the product trimming yield is improved more effectively.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A method of fabricating a fuse monitor structure, the method comprising the steps of:
s1: providing a substrate, forming a fuse and a metal interconnection layer on the surface of the substrate, wherein the metal interconnection layer comprises at least two mutually independent metal blocks, and a dielectric layer coating the fuse and the metal interconnection layer is also formed on the surface of the substrate;
s2: forming a conductive plug penetrating through the dielectric layer from top to bottom, wherein the conductive plug is in electrical contact with the metal block;
s3: forming an electric lead-out layer and a passivation layer on the surface of the dielectric layer, wherein the electric lead-out layer comprises at least two mutually independent bonding pads, and the bonding pads are electrically connected with the metal block through the conductive plugs; the passivation layer coats the electric lead-out layer;
s4: forming a photoresist layer on the surface of the passivation layer, and synchronously removing the passivation layer covered on the surface of the bonding pad, the passivation layer positioned above the fuse wire and the passivation layer positioned between two adjacent bonding pads through an etching process;
s5: and etching again, and synchronously removing the dielectric layer with partial thickness above the fuse and the dielectric layer with partial thickness between two adjacent bonding pads, so that a first groove is formed above the fuse, a second groove is formed between two adjacent bonding pads, the depths of the first groove and the second groove are the same, and the bottom surfaces of the first groove and the second groove are positioned on the same horizontal plane.
2. The method of manufacturing according to claim 1, characterized in that: the bonding pad, the conductive plug and the metal block which are vertically connected form polar plate units of the test capacitor, and a dielectric layer and a second groove between two adjacent polar plate units form a dielectric material layer of the test capacitor; the dielectric layer reserved above the fuse is a window layer;
the change of the capacitance value of the test capacitor reflects the change of the depth of the second groove, and the depth of the first groove is the same as that of the second groove, so that whether the thickness of the window layer below is in a preset range is judged through the change of the depth of the first groove, and the monitoring of the fuse structure is realized.
3. The preparation method according to claim 2, characterized in that: the cross-sectional area of the second groove is not less than half of the cross-sectional area between the two polar plate units.
4. The preparation method according to claim 2, characterized in that: the test capacitor is formed on a dicing street of the wafer, and the fuse and window layer are formed on a die of the wafer.
5. The method of manufacturing according to claim 1, characterized in that: in step S4, the passivation layer covering the surface of the bonding pad has a first thickness, the passivation layer above the fuse is removed to form a first opening, and the passivation layer between two adjacent bonding pads is removed to form a second opening;
in step S5, etching is continued along the first opening and the second opening to obtain a first groove and a second groove.
6. A fuse monitor structure, the fuse monitor structure comprising:
a substrate, wherein a fuse and a metal interconnection layer are formed on the surface of the substrate, and the metal interconnection layer comprises at least two mutually independent metal blocks;
a dielectric layer on the surface of the substrate, the dielectric layer coating the fuse and metal interconnect layer, a conductive plug being formed in the dielectric layer and being in electrical contact with the metal block;
the electric lead-out layer and the passivation layer are positioned on the surface of the dielectric layer, the electric lead-out layer comprises at least two mutually independent bonding pads, and the bonding pads are electrically connected with the metal block through the conductive plugs; the passivation layer coats the side wall of the bonding pad;
wherein, the first groove penetrating through the passivation layer and part of the thickness dielectric layer is formed above the fuse, and a window layer is formed between the bottom surface of the first groove and the dielectric layer between the fuse; a second groove with the same depth as the first groove is formed between two adjacent bonding pads, the first groove and the second groove are formed by synchronous etching, and the bottom surfaces of the first groove and the second groove are positioned on the same horizontal plane.
7. The fuse monitor structure of claim 6, wherein: the bonding pad, the conductive plug and the metal block which are vertically connected form polar plate units of the test capacitor, and a dielectric layer and a second groove between two adjacent polar plate units form a dielectric material layer of the test capacitor;
the change of the capacitance value of the test capacitor reflects the change of the depth of the second groove, and the depth of the first groove is the same as that of the second groove, so that whether the thickness of the window layer below is in a preset range is judged through the change of the depth of the first groove, and the monitoring of the fuse structure is realized.
8. The fuse monitor structure of claim 6, wherein: the cross-sectional area of the second groove is not less than half of the cross-sectional area between the two polar plate units.
9. The fuse monitor structure of claim 6, wherein: the fuse monitoring structure comprises one or more fuses, and the fuses are sequentially arranged along the transverse direction or the longitudinal direction.
10. A semiconductor wafer, characterized in that: a plurality of exposure units are divided in the semiconductor wafer, a plurality of core particles are divided in a single exposure unit, and cutting channels are arranged between adjacent exposure units and between adjacent core particles;
the semiconductor wafer comprising the fuse monitor structure of any of claims 7-9, the fuse being formed on a die, the test capacitor being formed on the scribe line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311426730.3A CN117410231A (en) | 2023-10-30 | 2023-10-30 | Fuse wire monitoring structure, manufacturing method thereof and semiconductor wafer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311426730.3A CN117410231A (en) | 2023-10-30 | 2023-10-30 | Fuse wire monitoring structure, manufacturing method thereof and semiconductor wafer |
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| CN117410231A true CN117410231A (en) | 2024-01-16 |
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| CN202311426730.3A Pending CN117410231A (en) | 2023-10-30 | 2023-10-30 | Fuse wire monitoring structure, manufacturing method thereof and semiconductor wafer |
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| CN (1) | CN117410231A (en) |
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