CN117409715A

CN117409715A - Display device and method of driving pixels of the same

Info

Publication number: CN117409715A
Application number: CN202310865866.8A
Authority: CN
Inventors: 金学镇; 智光焕; 崔秉德; 金凡植; 金东荣; 金容德; 李雋熙
Original assignee: LG Display Co Ltd; Industry University Cooperation Foundation IUCF HYU
Current assignee: LG Display Co Ltd; Industry University Cooperation Foundation IUCF HYU
Priority date: 2022-07-14
Filing date: 2023-07-14
Publication date: 2024-01-16
Also published as: KR20240009793A; US20240029651A1

Abstract

A display device and a method of driving a pixel of the display device are disclosed. The display apparatus and method can secure a time to sense a threshold voltage of a driving transistor during an operation of the pixel and compensate for the threshold voltage. Each of the plurality of pixels has a 5T1C structure including first to fourth transistors and a driving transistor. The first to fourth transistors are configured to apply driving signals through the first to fourth scan lines, respectively. Therefore, even if the number of driving signals applied to each pixel is not increased, a long time for sensing the threshold voltage of each pixel can be ensured.

Description

Display device and method of driving pixels of the same

Technical Field

The present disclosure relates to a display device and a method of driving a pixel of the display device, and more particularly, for example, but not limited to, to a display device capable of securing a sensing time of a threshold voltage of a driving transistor during a pixel operation and a method of driving a pixel of the display device.

Background

An Organic Light Emitting Diode (OLED) as a self-light emitting element includes an anode electrode and a cathode electrode, and an organic compound layer formed between the anode electrode and the cathode electrode. The organic compound layer is composed of a Hole Transport Layer (HTL), an emission layer (EML), and an Electron Transport Layer (ETL).

When a driving voltage is applied to the anode electrode and the cathode electrode, holes that have passed through a Hole Transport Layer (HTL) and electrons that have passed through an Electron Transport Layer (ETL) move to the light emitting layer EML and combine with each other to form excitons. As a result, the light emitting layer EML generates visible light.

An active matrix type organic light emitting display device includes an organic light emitting element (organic light emitting diode OLED) that emits light by itself, and is used in various ways due to its fast response speed, high light emitting efficiency, high luminance, and wide viewing angle.

In an organic light emitting display device, pixels each including an organic light emitting element are arranged in a matrix form. The brightness of the pixel is adjusted according to the gray level of the video data. Each pixel includes an organic light emitting element, a driving transistor controlling a driving current flowing through the organic light emitting element according to a voltage difference between a gate and a source, and at least one switching transistor programming the voltage difference between the gate and the source of the driving transistor. A pixel circuit including an organic light emitting element, a driving transistor, and at least one or more switching transistors operates according to a scan signal and a light emitting signal.

Accordingly, the pixel circuit supplies a driving current to the organic light emitting element according to the scan signal and the light emitting signal. In this regard, the driving signal of the pixel circuit uses a continuous signal such as, for example, n-H time of four horizontal periods (4H) to secure time for sensing the threshold voltage. In this regard, as n increases, the compensation rate of the threshold voltage increases. Therefore, a minimum of 4H and a maximum of 16H are required.

When the duty ratio is 50%, 8 signal waveforms are required for a signal at 4H time, and 32 signal waveforms are required for a signal at 16H time. That is, there is a problem in that the number of signals input to the pixels increases as n increases.

The description provided in the description of the background section should not be assumed to be prior art merely because it was mentioned in or associated with the description of the background section. The description of the background section may include information describing one or more aspects of the subject technology and the description of this section is not intended to limit the invention.

Disclosure of Invention

The inventors have recognized the above-mentioned requirements and other limitations associated with the background art. Accordingly, in order to solve the above-described problems, the inventors of the present disclosure have invented a display device capable of securing a sensing time of a threshold voltage of a driving transistor when driving each pixel in an OLED display device.

Another object of the present disclosure is to provide a method for driving a pixel of a display device, which is capable of securing a time to sense a threshold voltage of a driving transistor and compensating for the threshold voltage when a gate driver of the display device applies a scan signal to a pixel of an organic light emitting diode to drive the pixel.

The object according to the present disclosure is not limited to the above object. Other objects and advantages according to the present disclosure, which are not mentioned, may be understood based on the following description, and may be more clearly understood based on the embodiments according to the present disclosure. Furthermore, it will be readily understood that the objects and advantages according to the present disclosure may be achieved using the means shown in the claims or combinations thereof.

A display device according to one embodiment of the present disclosure may be provided. The display device may include: a display panel in which a plurality of pixels are disposed; a gate driver configured to supply a scan signal to each of the plurality of pixels; a data driver configured to supply a data voltage to each of the plurality of pixels; a light-emitting signal supplier configured to supply a light-emitting signal to each of the plurality of pixels; and a timing controller configured to control the gate driver, the data driver, and the light emitting signal supplier, wherein each of the plurality of pixels includes: an organic light emitting element configured to emit light based on a driving current; a driving transistor configured to control the driving current, and including a first electrode as a first node, a gate electrode as a second node, and a second electrode as a third node; a first transistor including a first gate electrode connected to a first scan signal line transmitting a first scan signal; a second transistor including a second gate electrode connected to a second scan signal line transmitting a second scan signal; a third transistor including a third gate electrode connected to a third scan signal line transmitting a third scan signal; a fourth transistor including a fourth gate electrode connected to a fourth scan signal line transmitting a fourth scan signal; and a storage capacitor connecting the second node and the third node to each other.

A method for driving a pixel of a display device may be provided. The method may include: during a threshold voltage sensing period of each of a plurality of pixels, (a) outputting a first scan signal of a high level and a second scan signal of a high level to each of the plurality of pixels simultaneously and in an overlapping manner by a gate driver; (b) Applying the first scan signal of the high level to the first gate electrode to turn on the first transistor, and applying the second scan signal of the high level to the second gate electrode to turn on the second transistor; (c) Applying a first reference voltage to a gate electrode of a driving transistor through the first transistor and the second transistor; and (d) compensating for a threshold voltage of the drive transistor.

Details of other embodiments are included in the detailed description and the accompanying drawings.

According to the embodiments of the present disclosure, even if the number of driving signals applied to each pixel is not increased when the gate driver of the display device applies the driving signals to each pixel to drive the pixel, a long time for sensing the threshold voltage of each pixel can be ensured.

Thus, according to the embodiments of the present disclosure, a sufficient time for sensing the threshold voltage of each pixel can be ensured, so that the compensation rate for the threshold voltage of each pixel can be improved.

Further, according to the embodiments of the present disclosure, a sufficient time for sensing the threshold voltage of each pixel may be ensured so that the number of external clock signals to each pixel in the display panel may not be increased.

Further, according to the embodiments of the present disclosure, the number of external clock signals for each pixel in the display panel may not be increased, so that the thickness of the bezel may be reduced, and the control load of the timing controller may be reduced.

Further, according to the embodiments of the present disclosure, the number of external clock signals for each pixel in the display panel may not be increased, and the thickness of the bezel may be reduced, so that the GIP circuit of the display device may be implemented in a simple manner.

The effects of the present disclosure are not limited to the above-described effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

In addition to the effects described above, specific effects of the present disclosure are described together while describing specific details for performing the present disclosure.

Drawings

The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

Fig. 1 is a block diagram schematically illustrating a display apparatus according to an exemplary embodiment of the present disclosure.

Fig. 2 is an explanatory circuit diagram of a pixel circuit in a display device according to an exemplary embodiment of the present disclosure.

Fig. 3 is a diagram illustrating an operation of a scan signal during 1 frame in a display device according to an exemplary embodiment of the present disclosure.

Fig. 4 is a diagram showing an operation flowchart for illustrating a pixel driving method of a display device according to an exemplary embodiment of the present disclosure.

Fig. 5A and 5B are diagrams illustrating an operation of each transistor and a signal waveform during an initialization period of an organic light emitting element according to an exemplary embodiment of the present disclosure.

Fig. 6A and 6B are diagrams illustrating an operation of each transistor and a signal waveform during an initialization period of a driving transistor according to an exemplary embodiment of the present disclosure.

Fig. 7A and 7B are diagrams illustrating an operation of each transistor and a signal waveform during a threshold voltage sensing period according to an exemplary embodiment of the present disclosure.

Fig. 8A and 8B are diagrams illustrating an operation and a signal waveform of each transistor during a data input time and a mobility sensing period according to an exemplary embodiment of the present disclosure.

Fig. 9A and 9B are diagrams illustrating an operation of each transistor and a signal waveform during a light emission period according to an exemplary embodiment of the present disclosure.

Fig. 10A and 10B are diagrams comparing a result of continuously applying a driving signal during a threshold voltage sensing period with a result of discretely applying the driving signal in a display device according to an exemplary embodiment of the present disclosure.

Fig. 11A is a diagram illustrating an example of an 8T1C circuit configuration of one stage in a gate driver according to an exemplary embodiment of the present disclosure. Fig. 11B is a diagram illustrating waveforms of a clock signal and a scan signal output from a stage of an 8T1C circuit configuration according to an exemplary embodiment of the present disclosure.

Fig. 12A is a diagram illustrating an example of a 14T2C circuit configuration of one stage in a gate driver according to an exemplary embodiment of the present disclosure. Fig. 12B is a diagram illustrating waveforms of a clock signal and a scan signal output from a stage of a 14T2C circuit configuration according to an exemplary embodiment of the present disclosure.

Fig. 13A is a diagram illustrating an example of an 18T2C circuit configuration of one stage in a gate driver according to an exemplary embodiment of the present disclosure. Fig. 13B is a diagram illustrating waveforms of a clock signal and a scan signal output from a stage of an 18T2C circuit configuration according to an exemplary embodiment of the present disclosure.

Fig. 14 is a diagram of stages of a gate driver included in a display device according to an exemplary embodiment of the present disclosure.

Fig. 15 is a cross-sectional view illustrating a stacked form of a display device according to an exemplary embodiment of the present disclosure.

Throughout the drawings and detailed description, unless otherwise indicated, like reference numerals should be understood to refer to like elements, features and structures. The relative sizes and descriptions of these elements may be exaggerated for clarity, explanation, and convenience.

Detailed Description

The advantages and features of the present disclosure and methods of accomplishing the same will become apparent with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but may be implemented in various forms. Accordingly, these embodiments are set forth merely to complete the disclosure and to fully convey the scope of the disclosure to those of ordinary skill in the art to which the disclosure pertains, and the disclosure is limited only by the scope of the appended claims.

For simplicity and clarity of illustration, elements in the figures have not necessarily been drawn to scale. The same reference numbers in different drawings identify the same or similar elements and, thus, perform similar functions. Further, descriptions and details of well-known steps and elements are omitted for simplicity of the description. Furthermore, in the following detailed description of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it is understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present disclosure. Examples of the various embodiments are illustrated and further described below. It is to be understood that the description herein is not intended to limit the claims to the particular embodiments described. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure as defined by the appended claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing embodiments of the present disclosure are illustrative, and the present disclosure is not limited thereto. Like reference numerals refer to like elements throughout. Moreover, descriptions and details of well-known steps and elements are omitted for simplicity of the description. Furthermore, in the following detailed description of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it is understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that terms, such as "comprises," "comprising," "includes," "including," "made of …," "formed of …," "including," and the like, when used in this specification, specify the presence of stated features, integers, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and/or groups thereof unless expressly indicated otherwise. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When an expression such as "at least one" is located in front of an element of a list, the element of the entire list may be modified and a single element of the list may not be modified. In interpreting the values, errors or tolerances can occur even when there is no explicit description of the values.

In addition, it will be understood that when a first element or layer is referred to as being present on a second element or layer, the first element can be directly on the second element or layer, or can be indirectly on the second element, with a third element or layer disposed between the first element or layer and the second element or layer. It will be understood that when an element or layer is referred to as being "connected" or "coupled" to another element or layer, it can be directly connected or coupled to the other element or layer or one or more intervening elements or layers may be present. In addition, it will be further understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers or one or more intervening elements may also be present.

When terms such as "on," "above," "below," "beside," "under," "near," "adjacent," "on side," and "near" are used to describe a positional relationship between two components, one or more components may be positioned between the two components unless terms such as "immediately" or "directly" are used.

Spatially relative terms, such as "under …," "under …," "under …," "lower," "over …," "upper," and the like, may be used herein to facilitate a description of one element or feature relative to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms may be intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. For example, if an element in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" may include both below and above orientations. Similarly, the exemplary terms "above" or "over" can include orientations of "above" and "below.

Further, as used herein, when a layer, film, region, plate, etc., is disposed "on" or "on top of" another layer, film, region, plate, etc., the layer, film, region, plate, etc., can directly contact the other layer, film, region, plate, etc., or other layers, films, regions, plates, etc., can be disposed between the layer, film, region, plate, etc., and the other layer, film, region, plate, etc. As used herein, when a layer, film, region, plate, etc., is disposed directly "on" or "on top of another layer, film, region, plate, etc., the layer, film, region, plate, etc., directly contacts the other layer, film, region, plate, etc., and no other layer, film, region, plate, etc., is disposed between the layer, film, region, plate, etc., and the other layer, film, region, plate, etc. Further, as used herein, when a layer, film, region, plate, etc., is disposed "under" or "beneath" another layer, film, region, plate, etc., the layer, film, region, plate, etc., can directly contact the other layer, film, region, plate, etc., or other layers, films, regions, plates, etc., can be disposed between the layer, film, region, plate, etc., and the other layer, film, region, plate, etc. As used herein, when a layer, film, region, plate, etc., is disposed "under" or "beneath" another layer, film, region, plate, etc., the layer, film, region, plate, etc., directly contacts the other layer, film, region, plate, etc., and no other layer, film, region, plate, etc., is disposed between the layer, film, region, plate, etc., and the other layer, film, region, plate, etc.

In describing a temporal relationship, for example, a temporal precedent relationship between two events such as "after", "subsequent", "following", "preceding", etc., unless "directly after", "directly subsequent", "directly following", "directly preceding" is indicated, another event may occur between them.

When a particular embodiment may be implemented differently, the functions or operations specified in the particular block may occur in a different order than that specified in the flowchart. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may be executed in the reverse order, depending upon the functionality or acts involved.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Accordingly, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure.

Features of various embodiments of the present disclosure may be combined with each other, either partially or fully, and may be technically associated with each other or operated with each other. Embodiments may be implemented independently of each other and together in association.

In interpreting the values, unless explicitly stated otherwise, the values are to be construed as including error ranges.

It will be understood that when an element or layer is referred to as being "connected" or "coupled" to another element or layer, it can be directly connected or coupled to the other element or layer or one or more intervening elements or layers may be present. In addition, it will be further understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers or one or more intervening elements may also be present.

Unless defined otherwise, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, "implementations," "examples," "aspects," and the like are not to be construed as making any aspect or design described superior or preferred to other aspects or designs.

Furthermore, the term 'or' is intended to mean 'including or' rather than 'exclusive or'. That is, unless otherwise indicated or clear from the context, the expression ' x ' using a or b ' means any one of the natural inclusive permutations.

The term "device" as used herein may refer to a display device including a display panel and a driver for driving the display panel. Examples of the display device may include an Organic Light Emitting Diode (OLED) and the like. In addition, examples of the apparatus may include a notebook computer, a television, a computer monitor, an automobile apparatus, a wearable apparatus, and an automobile device, and a complete electronic apparatus (or device) or a complete apparatus (or device) including an OLED or the like as a complete product or a final product, respectively, for example, a mobile electronic apparatus such as a smart phone or an electronic tablet, but embodiments of the present disclosure are not limited thereto.

The terminology used in the following description is selected to be general and generic in the relevant art. However, other terms are possible depending on the development and/or variation of the technology, practices, preferences of the skilled artisan, and the like. Accordingly, the terms used in the following description should not be construed as limiting the technical concept, but should be construed as examples of terms used to describe embodiments. Furthermore, in certain cases, the terms may be arbitrarily selected by the applicant, and in such cases, the detailed meanings thereof will be described in the corresponding description section. Accordingly, the terms used in the following description should not be construed simply based on the names of the terms, but rather based on the meanings of the terms and the contents throughout the detailed description.

Hereinafter, a display panel and a display device including the same according to exemplary embodiments of the present disclosure will be described.

Fig. 1 is a block diagram schematically illustrating a display apparatus according to an exemplary embodiment of the present disclosure. All components of each display device according to all embodiments of the present disclosure are operably coupled and configured.

Referring to fig. 1, a display device 100 according to an exemplary embodiment of the present disclosure may include a display panel 10, a timing controller 20, a gate driver 30, a data driver 40, and a light emitting signal supplier 50.

The display panel 10 may include a display area or active area AA and an inactive area or inactive area N/a. A plurality of pixels P may be disposed in the display area a/a of the display panel 10. For example, a plurality of gate lines GL and a plurality of data lines DL may be disposed in the display panel 10, and the pixels P may be disposed in regions where the gate lines GL and the data lines DL cross each other. Each pixel P may include at least one of the sub-pixels SP respectively emitting red (R), green (G) and blue (B) light beams, but the embodiment of the present disclosure is not limited thereto, and for example, each pixel P may also include at least one of the sub-pixels SP respectively emitting white (W), red (R), green (G) and blue (B) light beams.

In the display panel 10, the plurality of gate lines GL and the plurality of light-emitting lines EL may cross the plurality of data lines DL. Each of the plurality of pixels is connected to the gate line GL, the light-emitting line EL, and the data line DL.

Specifically, one pixel receives a gate signal from the gate driver 300 via the gate line GL, receives a data signal from the data driver 400 via the data line DL, receives a light emitting signal EM (N) via the light emitting line EL, and receives various power via the power supply line.

In this regard, the gate line GL supplies the scan signal SC. The light emitting line EL supplies a light emitting signal EM (N). The data line DL supplies a data voltage V _Data 。

However, according to various embodiments, the gate line GL may include a plurality of scan signal lines. The data line DL may additionally include a plurality of power supply lines VL.

Further, the light emitting line EL may include a plurality of light emitting signal lines. In addition, one pixel receives the first driving power ELVDD and the second driving power ELVSS.

Further, one pixel receives the first bias voltage V1 and the second bias voltage V2 via one power supply line VL.

Further, each pixel includes a light emitting element ELD and a pixel circuit controlling an operation of the light emitting element ELD. In this regard, the light emitting element is composed of an anode, a cathode, and an organic light emitting layer between the anode and the cathode.

The pixel circuit includes a plurality of switching elements, a driving element, and a capacitor. In this regard, the switching element may be implemented as a Thin Film Transistor (TFT). In the pixel circuit, the driving element may be implemented as a Thin Film Transistor (TFT), and the amount of current supplied to the light emitting element ELD may be controlled according to a difference between a data voltage charged in the capacitor and a reference voltage to control the amount of light emitted from the light emitting element ELD. Further, the plurality of switching TFTs receive the scan signal SC supplied via the gate line GL and the light emitting signal EM (N) supplied via the light emitting line EL to apply the data voltage V _Data Charging the capacitor.

In order to drive the display panel 10 including a plurality of pixels, the display device 100 according to an exemplary embodiment of the present disclosure may further include a gate driver 30, a data driver 40, a light emitting signal supplier 50, and a timing controller 20 for controlling the gate driver 30, the data driver 40, and the light emitting signal supplier 50.

In this regard, the light emission signal supplier 50 is configured to adjust the duty ratio of the light emission signal EM (N). For example, the light emitting signal supplier 50 may include a latch and a shift register for adjusting the duty ratio of the light emitting signal EM (N). Under the light emission control signal ECS generated from the timing controller 20, the light emission signal supplier 50 generates and supplies a light emission signal having a first duty ratio to the pixel circuit when the pixel circuit operates at a first refresh rate, and generates and supplies a light emission signal EM (n) having a second duty ratio different from the first duty ratio to the pixel circuit when the pixel circuit operates at a second refresh rate.

The timing controller 20 controls each of the gate driver 30, the data driver 40, and the light emitting signal supplier 50.

The timing controller 20 processes image data RGB input from an external source to fit the size and resolution of the display panel 10 and supplies the image data RGB to the data driver 40.

The timing controller 20 generates a gate control signal GCS, a data control signal DCS, and a light emission control signal ECS using synchronization signals SYNC (e.g., a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from an external source. The timing controller 20 supplies the generated gate control signal GCS, data control signal DCS, and light emission control signal ECS to the gate driver 30, data driver 40, and light emission signal supplier 50, respectively, to control the gate driver 30, data driver 40, and light emission signal supplier 50.

The timing controller 20 may be configured to be combined with various processors (e.g., a microprocessor, a mobile processor, an application processor, etc.) according to the type of device on which the timing controller is installed.

The timing controller 20 generates signals so that the pixels can operate at various refresh rates. That is, the timing controller 20 generates signals related to the operation of the pixels such that the pixels operate in a Variable Refresh Rate (VRR) mode, or the operation mode thereof can be switched between a first refresh rate and a second refresh rate. For example, the timing controller 20 simply changes the speed of the clock signal, generates the synchronization signal such that horizontal blanking or vertical blanking occurs, or drives the gate driver 30 in a masking scheme to allow the pixels to operate at different refresh rates.

In addition, the timing controller 20 generates various signals to allow the pixels to operate at the first refresh rate. Specifically, the timing controller 20 generates the light emission control signal ECS such that the light emission signal supplier 50 generates the light emission signal EM (N) having the first duty ratio when the pixels operate at the first refresh rate. The timing controller 20 then operates to allow the pixels to operate at the second refresh rate. To this end, the timing controller 20 generates various signals to allow the pixels to operate at the second refresh rate. Specifically, the timing controller 20 generates the light emission control signal ECS such that when the pixel operates at the second refresh rate, the light emission signal supplier 50 generates the light emission signal EM (N) having a second duty ratio different from the first duty ratio.

The gate driver 30 may supply a scan signal to each of the plurality of pixels.

The gate driver 30 supplies the scan signal SC to the gate line GL according to the gate control signal GCS supplied from the timing controller 20. In fig. 1, the gate driver 30 is shown disposed at one side of the display panel 10 and spaced apart from the display panel 10. However, the number and arrangement positions of the gate drivers 30 are not limited thereto. For example, the gate driver 30 may be disposed on each of one side or opposite sides of the display panel 10 in an intra-panel gate GIP scheme. Alternatively, the gate drivers 30 may be integrated and arranged on the display panel 10, or each gate driver 30 may be implemented by a chip-on-film COF scheme in which elements are mounted on a film connected to the display panel 10. Alternatively, the gate driver 30 may be separately mounted on a circuit film, which may be bonded and connected to the display panel 10 in a tape automated bonding TAB scheme. Alternatively, the gate driver 30 may be mounted on the display panel 10 in a chip on glass COG scheme.

The gate driver 30 may include a plurality of stages STk 60 that sequentially output gate pulses (or scan pulses). For example, the gate driver 30 includes a shift register, a level shifter for converting an output signal of the shift register into a signal having a swing width suitable for an operation of a thin film transistor of each pixel, and an output buffer connected to and disposed between the level shifter and the gate line GL. The gate driver may sequentially output gate (scan) pulses having a pulse width of about 1 horizontal period.

A start signal VST swinging between the gate high voltage VGH and the gate low voltage VGL, shift clocks CLK1 to CLK3 (hereinafter simply referred to as clocks), and the like may be input to each stage STk.

The stage STk may start outputting the second SCAN signal SCAN2 in response to the start signal VST, and may shift the output according to the clocks CLK1 to GCLK 3. The second SCAN signal SCAN2 sequentially output from the stage STk is supplied to the gate line GL.

One or more of the scan signals of the current stage may be input to at least one of the next stages as a start signal, and may be further input to one of the previous stages as a reset signal. The stage STk may output a carry signal CRY separated from the scan signal, and may supply the carry signal as a control signal to a previous stage or a next stage. For example, the carry signal may be supplied to a lower stage as a start signal, or may be supplied to a previous stage as a reset signal.

In addition, the gate driver 30 may be formed in the substrate together with the thin film transistor array of the display area a/a, and may be implemented as an intra-panel gate GIP circuit directly formed in the bezel area or the non-display area N/a of the display panel 10.

The gate driver 30 may be formed in a substrate together with a thin film transistor array constituting a pixel array of the display panel 10, and may be embedded in a GIP scheme in a non-display region on each of opposite sides or one side of a display region of the display panel 10. For example, in fig. 1, the data driver 40 is shown as a separate component from the display panel 10. However, the present disclosure is not limited thereto, and the data driver 40 may be embedded in the bezel area and may be integrally formed with the display panel 10, and thus may be configured in a GIP scheme.

The gate driver 30 shifts the gate signals using a shift register so that the gate signals may be sequentially supplied to the gate lines GL. The strobe signal may include a scan (strobe) signal and a light emission control signal EM. The gate line GL may include a gate line to which a scan (gate) signal is applied and a gate line to which a light emission control signal is applied.

Further, the gate driver 30 may be located on only one side of the display panel 10, or may be located on each of opposite sides of the display panel 10, depending on a driving scheme or design of the display panel 10. The gate driver 30 according to an exemplary embodiment of the present disclosure is composed of one or more gate ICs (integrated circuits). In this regard, the gate ICs may be individually mounted on a circuit film, which may be bonded and connected to the display panel 10 in a TAB scheme, by the COF scheme. Alternatively, the gate IC may be mounted on the display panel 10 in a COG scheme.

The data driver 40 may supply a data voltage to each of the plurality of pixels P. For example, the data driver 40 may supply source data signals to a plurality of data lines DL in each pixel P.

The data line DL may be connected to the data driver 40 through a data pad. Although the data driver 40 is illustrated in fig. 1 as being disposed at one side of the display panel 10, the number and positions of the data driver 40 are not limited thereto.

The data driver 40 converts the image data RGB into the data voltage V according to the data control signal DCS supplied from the timing controller 20 _Data And converts the converted data voltage V via the data line DL _Data To the pixels.

That is, the data driver 40 receives an image signal of a digital waveform, for example, applied from the timing controller 20, and converts the received image signal into a data voltage in the form of an analog voltage having a gradation value that the pixel P can process. Further, in response to the input data control signal DCS, the data driver 40 may supply a data voltage to each pixel P via the data line DL. In this regard, the data driver 40 may convert the image signal into the data voltage using a plurality of reference voltages supplied from a reference voltage supplier (not shown).

The light emitting signal supplier 50 may supply a light emitting signal to each of the plurality of pixels. In this regard, the light emitting signal provider 50 is configured as a separate component in fig. 1. However, the present disclosure is not limited thereto, and the light emitting signal supplier 50 may be configured to be included in the gate driver 30. In addition, the light emitting signal supplier 50 may be referred to as a 'light emitting control signal driver 50'.

Fig. 2 shows, by way of example, a pixel circuit for illustration. The pixel circuit may have any structure in which a light emission signal EM (N) is applied to the pixel circuit to control light emission of the light emitting element OELD. For example, the pixel circuit may include an additional scan signal, a switching TFT connected to the additional scan signal, and a switching TFT to which an additional initialization voltage is applied. The connection relation of the switching elements or the connection position of the capacitor may be changed. That is, pixel circuits having various structures may be used as long as the light emission of the light emitting element ELD is controlled according to the change of the duty ratio of the light emission signal EM (N) so that the light emission is controlled according to the refresh rate. For example, various pixel circuits such as 3T1C, 4T1C, 6T1C, 7T1C, and 7T2C configurations may be used. Hereinafter, for convenience of explanation, a display device having a pixel circuit of a 5T1C structure in fig. 2 will be described.

The pixel circuit may control a driving current Id flowing in the organic light emitting element OELD to drive the organic light emitting element OELD. The pixel circuit may include a driving transistor DT, first through fourth transistors T1 through T4, and a storage capacitor C _ST . When the first scan signal and the second scan signal of the high level are simultaneously applied to the pixel circuit in an overlapping manner, the threshold voltage compensation is performed at least two or more times based on the threshold voltage sensing.

Referring to fig. 2, each of the plurality of pixels according to the present disclosure may include an organic light emitting element OLED emitting light based on a driving current, a driving transistor DT, and first to fourth transistors T1 to T4.

The organic light emitting element OLED may include a pixel electrode (or an anode electrode) and a cathode electrode. The pixel electrode of the organic light emitting element OELD may be connected to the third node N3, and the cathode electrode thereof may be connected to the second driving power, i.e., the low potential driving voltage ELVSS.

Each of the transistors DT, T1 to T4 may be implemented as a PMOS transistor or an NMOS transistor. For example, each of the driving transistor DT and the first to fourth transistors T1 to T4 may be implemented as an n-type MOSFET NMOS or a p-type MOSFET PMOS. The PMOS transistor is turned on based on a low-level voltage applied thereto. The NMOS transistor is turned on based on a high-level voltage applied thereto.

In addition, each of the driving transistor DT and the first to fourth transistors T1 to T4 may be implemented as an oxide thin film transistor, a Low Temperature Polysilicon (LTPS) thin film transistor, or a crystalline silicon (c-Si) transistor.

The oxide thin film transistor TFT may have excellent effects of preventing or at least reducing leakage current and relatively inexpensive manufacturing costs. Thus, according to embodiments of the present disclosure, the driving TFT may be manufactured using an oxide semiconductor material, and the at least one switching TFT may also be manufactured using an oxide semiconductor material.

The oxide semiconductor may be made of a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or a combination of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), and an oxide thereof. Specifically, the oxide semiconductor may include zinc oxide (ZnO), zinc Tin Oxide (ZTO), zinc Indium Oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium Gallium Zinc Oxide (IGZO), indium Zinc Tin Oxide (IZTO), indium Zinc Oxide (IZO), indium Gallium Tin Oxide (IGTO), and Indium Gallium Oxide (IGO), but is not limited thereto.

The driving transistor DT controls a driving current, and may include a first electrode as a first node N1, a gate electrode as a second node N2, and a second electrode as a third node N3. In this regard, one of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The driving transistor DT may have a first electrode connected to a high-potential driving voltage line which is transferred as a first driving powerThe high potential of the force drives the voltage ELVDD. The driving transistor DT may have a second electrode connected to the second transistor T2 and a storage capacitor C _ST A gate electrode of the first electrode of (a). The driving transistor DT may have a first electrode connected to the organic light emitting element OLED, a first electrode of the third transistor T3, and a storage capacitor C _ST A second electrode of the second electrodes of (a).

The driving transistor DT may be based on the voltage of the second node N2 (or stored in the storage capacitor C as described later _ST Data voltage of (a) supplies the driving current Id to the organic light emitting element OELD.

The first transistor T1 may include a first gate electrode connected to a first Scan signal line Scan1 transmitting the first Scan signal Scan1 (n). The first transistor T1 may have a first voltage reference V _REF And a second electrode connected to the first electrode of the second transistor T2 and the second electrode of the fourth transistor T4.

The second transistor T2 may include a second gate electrode connected to a second Scan signal line Scan2 transmitting the second Scan signal Scan2 (n). The second transistor T2 may have a first electrode connected to the second electrode of the first transistor and the second electrode of the fourth transistor, and a second electrode connected to the second node and one electrode of the first capacitor.

The third transistor T3 may include a third gate electrode connected to a third Scan signal line Scan3 transmitting a third Scan signal Scan3 (n). The third transistor T3 may have a first electrode connected to the third node N3 and a second reference voltage V _REF2 A second electrode of a second reference voltage line. That is, the first electrode of the third transistor T3 may be connected to the third electrode of the driving transistor DT, the anode of the organic light emitting element OLED, and the storage capacitor C _ST Is provided.

The fourth transistor T4 may include a fourth gate electrode connected to a fourth Scan signal line Scan4 transmitting a fourth Scan signal Scan4 (n). The fourth transistor T4 may have a first electrode connected to a Data voltage line Data transmitting the Data voltage Data (m), and a second electrode connected to the second electrode of the first transistor T1 and the first electrode of the second transistor T2.

Storage capacitor C _ST The second node N2 and the third node N3 may be connected to each other. For example, the storage capacitor CST may connect the gate electrode and the source electrode of the driving transistor DT to each other.

Storage capacitor C _ST May be connected to the second node N2 and the third node N3 and disposed between the second node N2 and the third node N3. Storage capacitor C _ST In which the data signal V supplied thereto can be stored or maintained _Data 。

Referring to fig. 3, each of a plurality of pixels P in the display apparatus 100 according to an exemplary embodiment of the present disclosure may operate in the following separate periods: an initialization period (OLED initialization) (1) of an organic light emitting element (OLED), an initialization period (drive transistor initialization) (2) of a drive transistor, a threshold voltage sensing period (V _TH Sensing) (3) and (4), data input time and mobility sensing period (data input&μ sense) (5), and a light emission period (light emission) (6). This is just one example, and the present disclosure is not necessarily limited to this order.

Each of the plurality of pixels P may initialize a voltage charged in the pixel circuit or a voltage remaining in the pixel circuit. Specifically, the data voltage V stored in the previous frame can be removed _Data And an influence of the first driving power ELVDD. Thus, each of the plurality of pixels P may display the new data voltage V _Data Corresponding images.

The exemplary embodiment shown in fig. 3 shows an example in which a pulse signal having a width of 1 horizontal period (1H) or a pulse signal having a width of 2 horizontal periods (2H) is applied to one pixel P during the first time t1 to the 16 th time t 16.

During the initialization period (OLED initialization) (1) of the organic light emitting element, the third Scan signal Scan3 (n) may be applied to the pixel P as a high-level pulse signal via the third Scan signal line Scan3 at the third time t 3.

During the initialization period (driving transistor initialization) (2) of the driving transistor DT, each of the first Scan signal Scan1 (n), the second Scan signal Scan2 (n), and the third Scan signal Scan3 (n) may be applied to the pixel P as a high-level pulse signal.

The first Scan signal Scan1 (n) may be applied to the pixel P as a high-level pulse signal via the first Scan signal line Scan1 at each of the first time t1, the fourth time t4, the seventh time t7, and the tenth time t 10. That is, the first Scan signal Scan1 (n) may be applied every 3 horizontal periods (3H) or more.

The second Scan signal Scan2 (n) may be applied to the pixel P as a high-level pulse signal via the second Scan signal line Scan2 at each of the fourth time t4, the seventh time t7, the tenth time t10, and the 13 th time t 13. That is, the second Scan signal Scan2 (n) may be applied every 3 horizontal periods (3H) or more.

The third Scan signal Scan3 (n) may be applied to the pixel P as a high-level pulse signal via the third Scan signal line Scan3 at the third time t3 and the fourth time t 4.

As described above, during the initialization period (driving transistor initialization) (2) of the driving transistor DT, the first Scan signal Scan1 (n), the second Scan signal Scan2 (n), and the third Scan signal Scan3 (n) may be simultaneously applied to the pixel P in an overlapping manner at the fourth time t 4.

During the threshold voltage sensing period (V _TH During each of the sensing) (3) and (4), the first Scan signal Scan1 (n) and the second Scan signal Scan2 (n) may be simultaneously applied to the pixel P as high-level pulse signals in an overlapping manner at each of the seventh time t7 and the tenth time t 10.

At this time, the gate driver 30 may output the high-level clock pulse related to each of the first Scan signal Scan1 (n) and the second Scan signal Scan2 (n) at least twice or more every 3 horizontal periods (3H) or more.

In each of the plurality of pixels, when the data input time and the mobility sensing time (data input) are combined in the initialization period (driving transistor initialization) of the driving transistor DT (2) &μ sense) (5) threshold voltage sensing period (V _TH When the first Scan signal Scan1 (n) and the second Scan signal Scan2 (n) have high levels and overlap each other during each of the sensing (3) and (4), the sensing (V) may be based on the threshold voltage _TH Sensing) performs threshold voltage compensation.

In this regard, the threshold voltage sensing period may repeatedly occur. For example, the threshold voltage sensing period (V _TH Sensing) (3) and (4) may occur at seventh time t7 and tenth time t10, respectively. That is, the number of times that the first Scan signal Scan1 (n) and the second Scan signal Scan2 (n) having the high level overlap each other may increase every time the threshold voltage sensing period is repeated.

Therefore, in each of the plurality of pixels, the pixel voltage is reduced as the pixel voltage is reduced in the threshold voltage sensing period (V _TH Sensing (3) and (4) the number of times the first Scan signal Scan1 (n) and the second Scan signal Scan2 (n) having high levels overlap each other increases, the threshold voltage V may be increased _TH The compensation rate (or compensation amount) of (a) the compensation amount.

During the data input time and the mobility sensing period (data input & μ sensing) (5), each of the second Scan signal Scan2 (n) and the fourth Scan signal Scan4 (n) may be applied to the pixel P as a high-level pulse signal at 13 th time t 13.

During the light Emission (Emission) period (6), the fourth Scan signal Scan4 (n) may be applied to the pixel P as a high-level pulse signal via the fourth Scan signal line Scan4 at the 14 th time t 4.

Fig. 4 is a diagram showing an operation flowchart for illustrating a method for driving a pixel of a display device according to an exemplary embodiment of the present disclosure.

Referring to fig. 4, in the display device 100 according to the exemplary embodiment of the present disclosure, the gate driver 30 is at a threshold value in S410Voltage sense period (V _TH The sensing period) outputs the first Scan signal Scan1 (n) of the high level and the second Scan signal Scan2 (n) of the high level to each of the plurality of pixels simultaneously in an overlapping manner.

In S410, the gate driver 30 may output each of the third Scan signal Scan3 (n) and the fourth Scan signal Scan4 (n) of a low level to each of the plurality of pixels. Accordingly, the third Scan signal Scan3 (n) of a low level may be applied to the third gate electrode, and the fourth Scan signal Scan4 (n) of a low level may be applied to the fourth gate electrode. Thus, each of the third transistor and the fourth transistor may be turned off during the threshold voltage sensing period.

Subsequently, in S420, the first Scan signal Scan1 (n) of a high level is applied to the first gate electrode to turn on the first transistor, and the second Scan signal Scan2 (n) of a high level is applied to the second gate electrode to turn on the second transistor.

Subsequently, in S430, a first reference voltage is applied to the gate electrode of the driving transistor through the first transistor and the second transistor.

Subsequently, in S440, when a threshold voltage between the gate electrode and the source electrode of the driving transistor DT is sensed, the threshold voltage of the driving transistor DT is compensated.

In this respect, a storage capacitor C _ST The voltage difference across may be a threshold voltage.

Further, the voltage of the anode electrode of the organic light emitting element OLED may be a voltage obtained by subtracting the threshold voltage of the driving transistor from the first reference voltage.

Referring to fig. 5A and 5B, during an initialization period (OLED initialization) (1) of an organic light emitting element (OLED) according to an exemplary embodiment of the present disclosure, a third Scan signal Scan3 (n) may be applied to a third gate electrode of the third transistor T3 as a high-level pulse signal via a third Scan signal line Scan3 at a third time T3.

Therefore, the third transistor T3 is turned on based on the high-level pulse signal of the third Scan signal Scan3 (n). Second reference voltage V _REF2 The anode electrode of the organic light emitting element OLED as the third node N3 is applied through the third transistor T3.

In this regard, the organic light emitting element OLED provided in each pixel may be formed using a thermal evaporation process using a shadow mask or using a solution process such as inkjet. The organic light emitting element OLED may include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Emitting Material Layer (EML), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL). However, the present disclosure is not limited thereto.

For example, in the vertical cross-sectional structure of each pixel, the cathode electrode layer constitutes the top of the organic light emitting element OLED. A planarization layer may be disposed on top of the cathode electrode layer.

The anode electrode layer may be made of molybdenum (Mo), indium Tin Oxide (ITO), indium Zinc Oxide (IZO), indium Tin Zinc Oxide (ITZO), tin oxide (SnO), zinc oxide (ZnO), zinc Tin Oxide (ZTO), zinc Indium Oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium Gallium Zinc Oxide (IGZO), indium Zinc Tin Oxide (IZTO), indium Zinc Oxide (IZO), indium Gallium Tin Oxide (IGTO), and Indium Gallium Oxide (IGO), but is not limited thereto.

The cathode electrode may also be made of at least one of magnesium (Mg), calcium (Ca), sodium (Na), titanium (Ti), indium (In), yttrium (Y), lithium (Li), aluminum (Al), silver (Ag), tin (Sn), lead (Pb), or an alloy thereof.

In fig. 5A and 5B, the third Scan signal Scan3 (n) may be applied to the third gate electrode of the third transistor T3 as a high level pulse signal for 2 horizontal periods (2H) or more.

Second reference voltage V _REF2 Can be applied to the third node N3 through the third transistor T3 so that the anode electrode of the organic light emitting element OLED can pass through the second reference voltage V _REF2 Is initialized.

Thus, during the initialization period (OLED initialization) (1) of the organic light emitting element (OLED), the organic light emitting element OVoltage V of anode electrode of LED _AN Can become the second reference voltage V _REF2 。

Fig. 6A and 6B are diagrams illustrating an operation of each transistor and a signal waveform during an initialization period of the driving transistor DT according to an exemplary embodiment of the present disclosure.

Referring to fig. 6A and 6B, during an initialization period (driving transistor initialization) (2) of the driving transistor DT according to an exemplary embodiment of the present disclosure, the first Scan signal Scan1 (n), the second Scan signal Scan2 (n), and the third Scan signal Scan3 (n) may be simultaneously applied to the pixels P as high-level pulse signals in an overlapping manner at a fourth time t 4.

The first Scan signal Scan1 (n) of a high level may be applied to the first gate electrode of the first transistor T1, so that the first transistor T1 is turned on. The second Scan signal Scan2 (n) of a high level may be applied to the second gate electrode of the second transistor T2 to turn on the second transistor T2. The third Scan signal Scan3 (n) of a high level may be applied to the third gate electrode of the third transistor T3, so that the third transistor T3 is turned on.

Thus, the first reference voltage V _REF Can be applied to the gate electrode of the driving transistor DT as the second node N2 by the first transistor T1 and the second transistor T2 such that the gate electrode of the driving transistor DT passes the first reference voltage V _REF Is initialized.

In addition, a second reference voltage V _REF2 Can be applied to the second electrode of the driving transistor DT as the third node N3 by the third transistor T3 such that the second electrode of the driving transistor DT passes the second reference voltage V _REF2 Is initialized.

In this regard, the first Scan signal Scan1 (n) of a high level may be applied to the first gate electrode for 1 horizontal period (1H). The second Scan signal Scan2 (n) of a high level may be applied to the second gate electrode for 1 horizontal period (1H). The third Scan signal Scan3 (n) of a high level may be applied to the third gate electrode for 2 horizontal periods (2H).

Thus, during the initialization period (2) of the driving transistor DT, the first transistor T1 and the second transistorThe body transistor T2 is turned on and the gate electrode of the driving transistor DT passes the first reference voltage V _REF Is initialized so that the gate electrode voltage V of the driving transistor DT _G2 Can become the first reference voltage V _REF 。

Further, during the initialization period (2) of the driving transistor DT, the third transistor T3 is turned on and the second electrode of the driving transistor DT passes the second reference voltage V _REF2 Is initialized so that the voltage V of the anode electrode of the organic light emitting element OLED _AN Can become the second reference voltage V _REF2 。

In this case, the voltage VGS between the gate electrode and the source electrode of the driving transistor DT may become lower than the first reference voltage V _REF Subtracting the second reference voltage V _REF2 And the obtained voltage (V _REF -V _REF2 )。

Referring to fig. 7A and 7B, in the threshold voltage sensing period (V _TH During sensing) (3) and (4), a high-level first Scan signal Scan1 (n) may be applied to the first gate electrode to turn on the first transistor T1, and a high-level second Scan signal Scan2 (n) may be applied to the second gate electrode to turn on the second transistor T2.

Thus, the first reference voltage V _REF Is applied to the gate electrode of the driving transistor DT through the first transistor T1 and the second transistor T2.

Thus, when the threshold voltage between the gate electrode and the source electrode of the driving transistor DT is sensed, the threshold voltage V of the driving transistor DT is compensated _TH 。

At this time, the third Scan signal Scan3 (n) of a low level is applied to the third transistor T3 via the third Scan line Scan3, and the fourth Scan signal Scan4 (n) of a low level is applied to the fourth transistor T4 via the fourth Scan line Scan4, so that the third transistor T3 and the fourth transistor T4 are turned off, respectively.

Organic compoundVoltage V of anode electrode of light emitting element OLED _AN May become by being derived from the first reference voltage V _REF Subtracting the threshold voltage V of the driving transistor DT _TH And the obtained voltage (V _REF -V _TH )。

At this time, the driving transistor DT performs a source follower operation, and stores the capacitor C _ST The voltage difference between the two ends can become the threshold voltage V _TH 。

As shown in fig. 7A and 7B, regarding the threshold voltage sensing period (V _TH Sensing) (3) and (4), a first threshold voltage sensing period may occur after a certain horizontal period, for example, at a seventh time t7, and then a second threshold voltage sensing period may occur after two horizontal periods (2H), for example, at a tenth time t 10. In this way, the threshold voltage sensing period may be repeated at least once.

In this respect, the threshold voltage V of the driving transistor DT _TH The compensation rate of (a) may be changed based on the number of times the first Scan signal Scan1 (n) and the second Scan signal Scan2 (n) having a high level overlap each other or based on the number of repetitions of the driving signal.

Thus, it can be recognized that the threshold voltage sensing period (V _TH Sense), the threshold voltage V of the driving transistor DT _TH The compensation rate of (a) increases with the number of repetitions of the drive signal.

Referring to fig. 8A and 8B, during a data input time and mobility sensing period (data input & μ sensing) (5) according to an exemplary embodiment of the present disclosure, a high-level second Scan signal Scan2 (n) is applied to the second gate electrode so that the second transistor T2 is turned on, and a high-level fourth Scan signal Scan4 (n) is applied to the fourth gate electrode so that the fourth transistor T4 is turned on.

Accordingly, the Data voltage Data (m) is applied to the gate electrode of the driving transistor DT through the fourth transistor T4 and the second transistor T2.

In this regard, the voltage of the gate electrode of the driving transistor DT (i.e., the voltage of the second node N2) has a data voltage V _Data 。

Storage capacitor C _ST Is connected to and disposed between the gate electrode of the driving transistor DT and the anode electrode of the organic light emitting element OLED. That is, the storage capacitor C _ST Is connected to the gate electrode of the driving transistor DT and the storage capacitor C _ST Is connected to the anode electrode of the organic light emitting element OLED. Thus, the storage capacitor C _ST The first capacitance of (c) acts between the gate electrode of the driving transistor DT and the anode electrode of the organic light emitting element OLED.

In addition, a second capacitance acts on the storage capacitor C _ST As if the second capacitor C is an invisible organic light emitting element capacitor between the second electrode of (C) and the cathode electrode of the organic light emitting element OLED _OLED Arranged in the storage capacitor C _ST Is connected to the storage capacitor C between the second electrode of the organic light emitting element OLED and the cathode electrode of the organic light emitting element OLED _ST And a cathode electrode of the organic light emitting element OLED.

Therefore, the storage capacitor C as the first capacitor can be used _ST An organic light emitting element capacitor C as a second capacitor _OLED Second capacitance value of (2), data voltage V _Data From the first reference voltage V _REF Subtracting the threshold voltage V _TH And the obtained voltage is calculated to be connected to the storage capacitor C based on the following equation 1 _ST Voltage V of anode electrode of organic light emitting element OLED of second electrode of (a) _AN ，

[ 1]

That is, the voltage V of the anode electrode of the organic light emitting element OLED _AN =va (t) can be calculated by: will pass throughA capacitor C _ST And data voltage V _Data The value obtained by multiplying is divided by the first capacitance C _ST And a second capacitor C _OLED The values obtained by adding to each other to generate a first value, which is derived from a first reference voltage V _REF Subtracting the threshold voltage V _TH To generate a second value, the second capacitor C is used for the capacitor _OLED And a value obtained by multiplying the second value by the first capacitance C _ST And a second capacitor C _OLED The obtained values are added to each other to produce a third value, and then the first value and the third value are added.

For example, a second capacitor C _OLED 2pF, and a first capacitor C _ST 0.2pE. Voltage V of gate electrode of driving transistor DT _G2 Is the data voltage V _Data . In this case, the voltage V of the anode electrode of the organic light emitting element OLED _AN =va (t) can be calculated as 0.09×data voltage V _Data +0.91× [ first reference voltage V ] _REF Threshold voltage V _TH ]. Thus, the storage capacitor C _ST The voltage difference across it may be 0.91 x data voltage V _Data -a first reference voltage V _REF ]+0.91×threshold voltage V _TH 。

Regarding the sensing of mobility between the gate electrode and the source electrode of the driving transistor DT, the voltage V of the anode electrode of the organic light emitting element OLED may be recognized _AN And changes based on a change in mobility between the gate electrode and the source electrode of the driving transistor DT for a predetermined time.

In this case, when the mobility is high, the voltage V of the anode electrode of the organic light emitting element OLED _AN Is charged rapidly to a high level and relatively reduced from the high level to the voltage VGS between the gate electrode and the source electrode of the driving transistor DT. In this regard, the voltage VGS between the gate electrode and the source electrode of the driving transistor DT is obtained by supplying the data voltage V _Data A voltage (V) obtained by subtracting the voltage VA (t) of the anode electrode of the organic light emitting element OLED _Data -VA(t))。

In addition, when the mobility is low, the voltage V of the anode electrode of the organic light emitting element OLED _AN Is slowly charged to a low level and is lowThe level is relatively increased to the voltage VGS between the gate electrode and the source electrode of the driving transistor DT. In this regard, the voltage VGS between the gate electrode and the source electrode of the driving transistor DT is obtained by supplying the data voltage V _Data A voltage (V) obtained by subtracting the voltage VA (t) of the anode electrode of the organic light emitting element OLED _Data -VA(t))。

Referring to fig. 9A and 9B, during the light emission period (6) according to the exemplary embodiment of the present disclosure, the fourth Scan signal Scan4 (n) is applied to the fourth gate electrode of the fourth transistor T4 as a high-level pulse signal via the fourth Scan signal line Scan4 at the 14 th time T14 to turn on the fourth transistor T4.

Accordingly, the Data voltage Data (m) is applied to the fourth node N4 through the fourth transistor T4 via the Data line Data.

In this regard, the voltage V of the second node N2 as the gate electrode of the driving transistor DT _G2 Becomes a data voltage V _Data Storage capacitor _CST Voltage V between the second electrode of (a) and the anode electrode of the organic light emitting element OLED _B And (3) summing.

Accordingly, the voltage of the gate electrode of the driving transistor DT becomes higher than the threshold voltage, so that the driving transistor DT is turned on, and the data power ELVDD is applied from the first node N1 to the third node N3.

Current I flowing through the drive transistor DT _DT Can be calculated based on the following equation 2:

[ 2]

In formula 2, μ _n Represents mobility of the driving transistor DT, and C _ox The capacitance value of oxide per unit area is shown. Further, W represents the width of the driving transistor DT, and L represents the length of the driving transistor DT. In addition, C _ST Is expressed as a first electricityA first capacitance value of a storage capacitor of the container, and C _OLED A second capacitance value of the organic light emitting element capacitor as the second capacitor is represented. In addition, V _TH Represents the threshold voltage, V, of the drive transistor DT _Data Represents the data voltage, and V _B Representing a storage capacitor C _ST And the anode electrode of the organic light emitting element OLED.

In this regard, the data power ELVDD passes through the anode electrode of the organic light emitting element OLED in contact with the third node N3 and then flows to the cathode electrode via the organic light emitting layer.

When a current flows through the organic light emitting layer of the organic light emitting element OLED, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the organic light emitting layer and combine with each other, so that excitons are generated. As a result, the organic light emitting layer emits visible light, and thus the organic light emitting element OLED emits light.

Fig. 10A is a graph of a result of continuously applying a driving signal (continuous time) during a threshold voltage sensing period in a display device according to an exemplary embodiment of the present disclosure, and fig. 10B is a graph of a result of discretely applying a driving signal (discrete time) during a threshold voltage sensing period in a display device according to an exemplary embodiment of the present disclosure.

Referring to fig. 10A and 10B, it can be recognized that in the display device 100 according to the exemplary embodiment of the present disclosure, a current difference when a driving signal is applied to the driving transistor DT of one pixel P in a repeated discrete manner as a pulse signal for 1 horizontal period (1H) during a threshold voltage sensing period of, for example, 56 μs is similar to a current difference when a driving signal is applied to the driving transistor DT of one pixel P in a continuous manner as a pulse signal for 16 horizontal periods (16H) during a threshold voltage sensing period of, for example, 56 μs, and thus, a compensation rate in a discrete manner is similar to a compensation rate in a continuous manner.

Thus, according to the present disclosure, the number of driving signals applied to the gate driver 30 is reduced, and a structure in which 32 signal waveforms are required to create a pulse signal of 16 horizontal periods (16H) is not required.

Accordingly, the thickness of the bezel can be reduced, and the burden of the timing controller 20 related to the driving signal generation can be reduced.

The gate driver 30 according to an exemplary embodiment of the present disclosure generates one or more gate signals (or scan signals) based on the gate control signal GCS. For example, the gate driver 30 generates and outputs the first and second SCAN signals SCAN1 and SCAN2 and the light emission signal EM to each pixel P in fig. 1. During the display period, the gate driver 30 generates a scan signal and a light emitting signal in a row sequential scheme and sequentially supplies them to the gate lines GL connected to each pixel row. The scan signal and the light emitting signal of the gate line GL are supplied in synchronization with the data voltage of the data line DL. Each of the scan signal and the light emission signal swings between the gate-on voltage VGL and the gate-off voltage VGH.

Referring to fig. 11A and 11B, one stage STk 60 in the gate driver 30 according to an exemplary embodiment of the present disclosure has, for example, an 8T1C structure including a first switch M1 controlling a Q node and second to sixth switches M2 to M6 controlling a QB node, and seventh and eighth switches M7 and M8 controlling outputs.

Each of the first through eighth switches M1 through M8 may be implemented as an n-type MOSFET NMOS or a p-type MOSFET PMOS.

In addition, each of the first to eighth switches M1 to M8 may be implemented as an oxide thin film transistor or a Low Temperature Polysilicon (LTPS) thin film transistor.

The first switch M1 has a first electrode connected to a high-potential driving voltage line transmitting a high-potential driving voltage VDD, a gate electrode connected to a first Scan signal line Scan1 transmitting an (N-2) -th Scan signal Scan N-2, and a second electrode connected to a Q node. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The second switch M2 has a first electrode connected to the Q node, a gate electrode connected to the second Scan signal line Scan2 transmitting the (n+2) th Scan signal Scan [ n+2], and a second electrode connected to the low potential driving voltage line transmitting the low potential driving voltage VSS. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The third switch M3 has a first electrode connected to a high-potential driving voltage line transmitting the high-potential driving voltage VDD, a gate electrode connected to the high-potential driving voltage line, and a second electrode connected to a fifth node N5 which is a connection point between the fourth switch M4 and the fifth switch M5. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The fourth switch M4 has a first electrode connected to a fifth node N5 which is a connection point between the third switch M3 and the fifth switch M5, a gate electrode connected to the Q node, and a second electrode connected to a low potential driving voltage line transmitting the low potential driving voltage VSS. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The fifth switch M5 has a first electrode connected to a high-potential driving voltage line transmitting the high-potential driving voltage VDD, a gate electrode connected to a fifth node N5 which is a connection point of the third switch M3 and the fifth switch M5, and a second electrode connected to the QB node. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The sixth switch M6 has a first electrode connected to the QB node, a gate electrode connected to the Q node, and a second electrode connected to a low-potential driving voltage line transmitting the low-potential driving voltage VSS. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The seventh switch M7 has a first electrode connected to a clock signal line transmitting the clock signal CLK, a gate electrode connected to the Q node, and a second electrode connected to the eighth switch M8 and the Scan output line Scan [ n ]. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode. The capacitor CB may be connected to the gate electrode and the second electrode of the seventh switch M7 and disposed between the gate electrode and the second electrode of the seventh switch M7.

The eighth switch M8 has a first electrode connected to the seventh switch M7 and the Scan output line Scan [ n ], a gate electrode connected to the QB node, and a second electrode connected to a low potential driving voltage line transmitting the low potential driving voltage VSS. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

In the stage STk 60 configured as described above, during the precharge period, the clock signal CLK is at a low level, the (N-2) th Scan signal Scan [ N-2] is at a high level, and the (n+2) th Scan signal Scan [ n+2] is at a low level, so that the first switch M1 is turned on.

Therefore, the high potential driving voltage VDD is applied to the Q node through the first switch M1, and the voltage of the Q node becomes by subtracting the threshold voltage V from the high potential driving voltage VDD _TH And the obtained voltage (VDD-V _TH ). At this time, the QB node is in a low level state.

Subsequently, during the bootstrap period, the clock signal CLK is at a high level, and each of the (n-2) th Scan signal Scan [ n-2] and the (n+2) th Scan signal Scan [ n+2] is at a low level, and the Q node is at a high level, so that the seventh switch M7 is turned on.

Accordingly, the high-level clock signal CLK is output to the Scan output line Scan [ n ] through the seventh switch M7, so that the Scan output line Scan [ n ] becomes a high-level state.

At this time, the voltage of the Q node connected to the gate electrode of the seventh switch M7 becomes a voltage obtained by subtracting the threshold voltage V from the double high potential driving voltage 2VDD _TH And the obtained voltage (2 VDD-V _TH )。

In one example, during the pull-down period, the clock signal CLK is at a low level, the (n-2) th Scan signal Scan [ n-2] is at a low level, and the (n+2) th Scan signal Scan [ n+2] is at a high level, so that the second switch M2 is turned on.

Accordingly, the low potential driving voltage VSS is applied to the Q node through the second switch M2 by the low potential driving Voltage (VSS) line connected to the second electrode of the second switch M2, so that the fourth switch M4 and the sixth switch M6 are turned on.

At this time, the low potential driving voltage VSS is applied to the QB node via the sixth switch M6, so that the QB node becomes a high level state. Thus, the eighth switch M8 is turned on.

Accordingly, the low potential driving voltage VSS is output to the Scan output line Scan [ n ] via the eighth switch M8, so that the Scan output line Scan [ n ] becomes a low level state.

As described above, one stage STk 60 in the gate driver 30 according to an exemplary embodiment of the present disclosure may adjust the waveform of the output signal by adjusting the waveform of the carry input signal. That is, the applied clock signal is unchanged.

Referring to fig. 12A and 12B, one stage STk 60 in the gate driver 30 according to an exemplary embodiment of the present disclosure has, for example, a 14T2C structure including first to fourth switches M1 to M4 controlling the Q node, fifth to tenth switches M5 to M10 controlling the QB node, and 11 th to 14 th switches M11 to M14 controlling the output.

Each of the first through 14 th switches M1 through M14 may be implemented as an n-type MOSFET NMOS or a p-type MOSFET PMOS.

In addition, each of the first through 14 th switches M1 through M14 may be implemented as an oxide thin film transistor or a Low Temperature Polysilicon (LTPS) thin film transistor.

The first switch M1 has a first electrode connected to a high-potential driving voltage line transmitting a high-potential driving voltage VDD, a gate electrode connected to a first Carry line Carry1 transmitting an (n-2) th Carry signal Carry [ n-2], and a second electrode connected to the second switch M2. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The second switch M2 has a first electrode connected to the first switch M1, a gate electrode connected to a first Carry line Carry1 transmitting the (n-2) th Carry signal Carry [ n-2], and a second electrode connected to the Q node. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The third switch M3 has a first electrode connected to a high-potential driving voltage line transmitting the high-potential driving voltage VDD, a gate electrode connected to a connection point between the first switch M1 and the second switch M2, and a second electrode connected to the Q node. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The fourth switch M4 has a first electrode connected to a high-potential driving voltage line transmitting the high-potential driving voltage VDD, a gate electrode connected to the Q node, and a second electrode connected to a connection point between the first switch M1 and the second switch M2. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The fifth switch M5 has a first electrode connected to the Q node, a gate electrode connected to the second Carry line Carry2 transmitting the (n+2) -th Carry signal Carry [ n+2], and a second electrode connected to the sixth switch M6. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The sixth switch M6 has a first electrode connected to the fifth switch M5, a gate electrode connected to the second Carry line Carry2 transmitting the (n+2) th Carry signal Carry [ n+2], and a second electrode connected to the low potential driving voltage line transmitting the low potential driving voltage VSS. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The seventh switch M7 has a first electrode and a gate electrode connected to a high-potential driving voltage line transmitting the high-potential driving voltage VDD, and a second electrode connected to the eighth switch M8 and the ninth switch M9. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The eighth switch M8 has a first electrode connected to the seventh switch M7 and the ninth switch M9, a gate electrode connected to the Q node, and a second electrode connected to a low-potential driving voltage line transmitting the low-potential driving voltage VSS. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The ninth switch M9 has a first electrode connected to a high-potential driving voltage line transmitting the high-potential driving voltage VDD, gate electrodes connected to the seventh and eighth switches M7 and M8, and a second electrode connected to the QB node. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The tenth switch M10 has a first electrode connected to the QB node, a gate electrode connected to the Q node, and a second electrode connected to a low-potential driving voltage line transmitting the low-potential driving voltage VSS. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The 11 th switch M11 has a first electrode connected to a clock signal line transmitting the clock signal CLK, a gate electrode connected to the Q node, and a second electrode connected to the Carry output line Carry [ n ]. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

Capacitor C _BC May be connected to the gate electrode and the second electrode of the 11 th switch M11 and disposed between the gate electrode and the second electrode of the 11 th switch M11.

The 12 th switch M12 has a first electrode connected to the Carry output line Carry [ n ], a gate electrode connected to the QB node, and a second electrode connected to a low potential driving voltage line transmitting the low potential driving voltage VSS. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The 13 th switch M13 has a first electrode connected to a clock signal line transmitting the clock signal CLK, a gate electrode connected to the Q node, and a second electrode connected to the Scan output line Scan [ n ]. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

Capacitor C _BS May be connected to and disposed between the gate electrode and the second electrode of the 13 th switch M13.

The 14 th switch M14 has a first electrode connected to the Scan output line Scan [ n ], a gate electrode connected to the QB node, and a second electrode connected to a low-potential driving voltage line transmitting the low-potential driving voltage VSSL. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

In the stage STk 60 configured as described above, during the precharge period, the clock signal CLK is at a low level, and the (n-2) th Carry signal Carry [ n-2] is at a high level, so that the first switch M1 and the second switch M2 are turned on.

Accordingly, the high potential driving voltage VDD is applied to the Q node through the first and second switches M1 and M2 such that the voltage of the Q node becomes a voltage obtained by subtracting the threshold voltage V from the high potential driving voltage VDD _TH And the obtained voltage (VDD-V _TH ). At this time, the QB node is in a low level state.

Subsequently, during the bootstrap period, the clock signal CLK is at a high level, each of the (n-2) th Carry signal Carry [ n-2] and the (n+2) th Carry signal Carry [ n+2] is at a low level, and the Q node is at a high level, so that the 11 th switch M11 and the 13 th switch M13 are turned on.

Accordingly, the high-level clock signal CLK is output to the Scan output line Scan [ n ] and the Carry output line Carry [ n ] through the 11 th switch M11 and the 13 th switch M13, respectively, and thus each of the Scan output line Scan [ n ] and the Carry output line Carry [ n ] becomes a high-level state.

At this time, the voltage of the Q node connected to the gate electrode of each of the 11 th switch M11 and the 13 th switch M13 becomes passingSubtracting the threshold voltage V from twice the high potential driving voltage 2VDD _TH And the obtained voltage (2 VDD-V _TH ). The QB node is in a low state. That is, the QB node is in a low level state during both the precharge period and the bootstrap period.

In one example, during the pull-down period, the clock signal CLK is at a low level, and the (n-2) th Carry signal Carry [ n-2] has a low level, and the (n+2) th Carry signal Carry [ n+2] has a high level, so that the fifth and sixth switches M5 and M6 are turned on.

Accordingly, the low potential driving Voltage (VSS) is applied to the Q node via each of the fifth and sixth switches M5 and M6 through a low potential driving Voltage (VSS) line connected to the second electrode of each of the fifth and sixth switches M5 and M6. Accordingly, the eighth switch M8 and the tenth switch M10 are turned on.

At this time, the low potential driving voltage VSS is applied to the QB node via the tenth switch M10, so that the QB node becomes a high level state. Thus, the 12 th switch M12 and the 14 th switch M14 are turned on.

Accordingly, the low potential driving voltage VSS is output to the Scan output line Scan [ n ] and the Carry output line Carry [ n ] via the 12 th switch M12 and the 14 th switch M14, respectively, so that each of the Scan output line Scan [ n ] and the Carry output line Carry [ n ] becomes a low level state.

Referring to fig. 13A and 13B, one stage STk 60 in the gate driver 30 according to an exemplary embodiment of the present disclosure has, for example, an 18T2C structure including first to fifth switches M1 to M5 controlling the Q node, sixth to 14 switches M6 to M14 controlling the QB node, and 15 to 18 th switches M18 controlling the output.

Each of the first through 18 th switches M1 through M18 may be implemented as an n-type MOSFET NMOS or a p-type MOSFET PMOS.

In addition, each of the first through 18 th switches M1 through M18 may be implemented as an oxide thin film transistor or a Low Temperature Polysilicon (LTPS) thin film transistor.

The third switch M3 has a first electrode connected to a high-potential driving voltage line transmitting the high-potential driving voltage VDD, a gate electrode connected to a first Carry line Carry1 transmitting the (n-2) th Carry signal Carry [ n-2], and a second electrode connected to the Q node. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The fourth switch M4 has a first electrode connected to a high-potential driving voltage line transmitting the high-potential driving voltage VDD, a gate electrode connected to a connection point between the first switch M1 and the second switch M2, and a second electrode connected to the Q node. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The fifth switch M5 has a first electrode connected to a high-potential driving voltage line transmitting the high-potential driving voltage VDD, a gate electrode connected to the Q node, and a second electrode connected to a connection point between the first switch M1 and the second switch M2. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The sixth switch M6 has a first electrode connected to a high-potential driving voltage line transmitting the high-potential driving voltage VDD, a gate electrode connected to the Q node, and a second electrode connected to a connection point between the 13 th switch M13 and the 14 th switch M14. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The seventh switch M7 has a first electrode connected to the Q node, a gate electrode connected to the second Carry line Carry2 transmitting the (n+2) -th Carry signal Carry [ n+2], and a second electrode connected to the eighth switch M8. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The eighth switch M8 has a first electrode connected to the seventh switch M7, a gate electrode connected to the second Carry line Carry2 transmitting the (n+2) th Carry signal Carry [ n+2], and a second electrode connected to the low potential driving voltage line transmitting the low potential driving voltage VSS. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The ninth switch M9 has a first electrode and a gate electrode connected to a high-potential driving voltage line transmitting a high-potential driving voltage VDD, and a second electrode connected to the tenth switch M10 and the 11 th switch M11. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The tenth switch M10 has a first electrode connected to the ninth switch M9 and the eleventh switch M11, a gate electrode connected to the Q node, and a second electrode connected to a low-potential driving voltage line transmitting the low-potential driving voltage VSS. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The 11 th switch M11 has a first electrode connected to a high-potential driving voltage line transmitting the high-potential driving voltage VDD, gate electrodes connected to the ninth switch M9 and the tenth switch M10, and a second electrode connected to the QB node. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The 12 th switch M12 has a first electrode connected to the QB node, a gate electrode connected to the Q node, and a second electrode connected to a low-potential driving voltage line transmitting the low-potential driving voltage VSS. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The 13 th switch M13 has a first electrode connected to a connection point of the sixth switch M6 and the 14 th switch M14, a gate electrode connected to the QB node, and a second electrode connected to a low potential driving voltage line transmitting the low potential driving voltage VSS. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The 14 th switch M14 has a first electrode connected to the Q node, a gate electrode connected to the QB node, and a second electrode connected to a connection point of the sixth switch M6 and the 13 th switch M13. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The 15 th switch M15 has a first electrode connected to a clock signal line transmitting the clock signal CLK, a gate electrode connected to the Q node, and a second electrode connected to the Carry output line Carry [ n ]. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

Capacitor C _BC Can be connected to the gate electrode and the second electrode of the 15 th switch M15 and arranged on the gate electrode and the second electrode of the 15 th switch M15Between the poles.

The 16 th switch M16 has a first electrode connected to the Carry output line Carry [ n ], a gate electrode connected to the QB node, and a second electrode connected to a low potential driving voltage line transmitting the low potential driving voltage VSS. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

The 17 th switch M17 has a first electrode connected to a clock signal line transmitting the clock signal CLK, a gate electrode connected to the Q node, and a second electrode connected to the Scan output line Scan [ n ]. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

Capacitor C _BS May be connected to the gate electrode and the second electrode of the 17 th switch M17 and disposed between the gate electrode and the second electrode of the 17 th switch M17.

The 18 th switch M18 has a first electrode connected to the Scan output line Scan [ n ], a gate electrode connected to the QB node, and a second electrode connected to a low-potential driving voltage line transmitting the low-potential driving voltage VSSL. One of the first electrode and the second electrode may serve as a source electrode, and the other of the first electrode and the second electrode may serve as a drain electrode.

In the stage STk 60 configured as described above, during the precharge period, the clock signal CLK is at a low level, and the (n-2) -th Carry signal Carry [ n-2] has a high level, so that the first to third switches M1 to M3 are turned on.

Accordingly, the high potential driving voltage VDD is applied to the Q node through the first to third switches M1 to M3 such that the voltage of the Q node becomes a voltage obtained by subtracting the threshold voltage V from the high potential driving voltage VDD _TH And the obtained voltage (VDD-V _TH ). At this time, the QB node is in a low level state.

Subsequently, during the bootstrap period, the clock signal CLK is at a high level, each of the (n-2) th Carry signal Carry [ n-2] and the (n+2) th Carry signal Carry [ n+2] is at a low level, and the Q node is at a high level, so that the 15 th switch M15 and the 17 th switch M17 are turned on.

Accordingly, the high-level clock signal CLK is output to the Scan output line Scan [ n ] and the Carry output line Carry [ n ] through the 15 th switch M15 and the 17 th switch M17, respectively, and thus, each of the Scan output line Scan [ n ] and the Carry output line Carry [ n ] becomes a high-level state.

At this time, the voltage of the Q node connected to the gate electrode of each of the 15 th switch M15 and the 17 th switch M17 becomes a voltage obtained by subtracting the threshold voltage V from the twice high potential driving voltage 2VDD _TH And the obtained voltage (2 VDD-V _TH ). The QB node is in a low state. That is, the QB node is in a low level state during both the precharge period and the bootstrap period.

In one example, during the pull-down period, the clock signal CLK is at a low level, and the (n-2) th Carry signal Carry [ n-2] has a low level, and the (n+2) th Carry signal Carry [ n+2] has a high level, so that the seventh and eighth switches M7 and M8 are turned on.

Accordingly, the low potential driving Voltage (VSS) is applied to the Q node via each of the seventh switch M7 and the eighth switch M8 through the low potential driving Voltage (VSS) line connected to the second electrode of each of the seventh switch M7 and the eighth switch M8. Thus, the tenth switch M10 and the 12 th switch M12 are turned on.

At this time, the low potential driving voltage VSS is applied to the QB node via the 12 th switch M12, so that the QB node becomes a high level state. Thus, the 16 th switch M16 and the 18 th switch M18 are turned on.

Accordingly, the low potential driving voltage VSS/VSSL is output to the Scan output line Scan [ n ] and the Carry output line Carry [ n ] via the 16 th switch M16 and the 18 th switch M18, respectively, so that each of the Scan output line Scan [ n ] and the Carry output line Carry [ n ] becomes a low level state.

As described above, one stage STk 60 in the gate driver 30 according to the exemplary embodiment of the present disclosure may adjust the waveform of the output signal through the adjustment of the waveform of the carry input signal. That is, the applied clock signal is unchanged.

Referring to fig. 14, in the gate driver 30 including the light emission control signal driver, the first scan driver, and the second scan driver, the stages ST1 to STn of the shift register may include first scan signal generators SC1 (1) to SC1 (n), second scan signal generators SC2 (1) to SC2 (n), and light emission control signal generators EM (1) to EM (n), respectively. In one example, the first stage ST1 of the shift register may include a first scan signal generator SC1 (1) outputting a first scan signal SC1 (1), a second scan signal generator SC2 (1) outputting a second scan signal SC2 (2), and a light emission control signal generator EM (1) outputting a light emission control signal EM (1).

The first scan signal generators SC1 (1) to SC1 (n) output first scan signals SC1 (1) to SC1 (n), respectively, via the first scan lines SCL1 of the display panel 10. The second scan signal generators SC2 (1) to SC2 (n) output the second scan signals SC2 (1) to SC2 (n), respectively, via the second scan lines SCL2 of the display panel 10. The light emission control signal generators EM (1) to EM (n) output light emission control signals EM (1) to EM (n), respectively, via light emission control lines EML of the display panel 10.

The first scan signals SC1 (1) to SC1 (n) may be used as signals for driving an a-th transistor (e.g., a switching transistor) included in the pixel. The second scan signals SC2 (1) to SC2 (n) may be used as signals for driving a B-th transistor (e.g., a sensing transistor) included in the pixel.

The light emission control signals EEM (1) to EM (n) may be used as signals for driving a C-th transistor (e.g., a transistor for controlling light emission) included in the pixel. For example, when the light emission control signals EM (1) to EM (n) are used to control transistors for controlling light emission of pixels, the light emission time of the light emitting element changes.

Fig. 14 is an example, and the number (SC 1 to SC 4) or arrangement of the gate drivers (or scan drivers) is not limited thereto.

Fig. 15 is a cross-sectional view illustrating a stacked form of the display device 100 according to an exemplary embodiment of the present disclosure.

Referring to fig. 15, a thin film transistor TFT for driving the light emitting element 170 may be disposed in the display area AA and on the substrate 101. The thin film transistor TFT may include a semiconductor layer 115, a gate electrode 125, and source/drain electrodes 140. The thin film transistor TFT may be used as a driving transistor. For convenience of explanation, only the driving transistor among various thin film transistors that may be included in the display device 100 is shown. However, other thin film transistors such as switching transistors may also be included in the display device 100. Further, in the present disclosure, an example in which the thin film transistor TFT has a coplanar structure is described. However, the thin film transistor may be implemented to have another structure such as a staggered structure. However, the present disclosure is not limited thereto.

The driving transistor DT may receive the high potential driving voltage EVDD in response to a data signal supplied to the gate electrode 125 of the driving transistor to control the amount of current supplied to the light emitting element 170, thereby adjusting the amount of light emitted from the light emitting element 170. The driving transistor may supply a constant current based on a voltage charged in a storage capacitor (not shown) to maintain light emission of the light emitting element 170 until a data signal of a next frame is supplied. The high potential supply line may extend in parallel with the data line.

As shown in fig. 15, the thin film transistor TFT includes: a semiconductor layer 115 disposed on the first insulating layer 110; a gate electrode 125, the gate electrode 125 overlapping the semiconductor layer 115 with the second insulating layer 120 interposed between the gate electrode 125 and the semiconductor layer 115; and a source/drain electrode 140 formed on the third insulating layer 135 and contacting the semiconductor layer 115.

The semiconductor layer 115 may serve as a region where a channel is formed during operation of the thin film transistor TFT. The semiconductor layer 115 may be made of an oxide semiconductor, or may be made of various organic semiconductors such as amorphous silicon (a-Si), polycrystalline silicon (poly Si), or pentacene. The present disclosure is not limited thereto. The semiconductor layer 115 may be formed on the first insulating layer 110. The semiconductor layer 115 may include a channel region, a source region, and a drain region. The channel region may overlap the gate electrode 125 while the second insulating layer 120 is interposed between the channel region and the gate electrode 125. A channel region may be formed between the source/drain electrodes 140. The source region may be electrically connected to the source electrode 140 via a contact hole extending through the second insulating layer 120 and the third insulating layer 135. The drain region may be electrically connected to the drain electrode 140 via a contact hole extending through the second insulating layer 120 and the third insulating layer 135. The buffer layer 105 and the first insulating layer 110 may be disposed between the semiconductor layer 115 and the substrate 101. The buffer layer 105 may delay diffusion of moisture and/or oxygen that intrudes into the substrate 101. The first insulating layer 110 may protect the semiconductor layer 115 and may block various types of defects introduced from the substrate 101.

The uppermost layer of the buffer layer 105, which is in contact with the first insulating layer 110, may be made of a material having etching characteristics different from those of each of the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135. The uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of silicon nitride (SiN _x ) And silicon oxide (SiO) _x ) Is made of one of the materials. Each of the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 may be made of silicon nitride (SiN _x ) And silicon oxide (SiO) _x ) Is made of the other of the above materials. For example, the uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of silicon nitride (SiN _x ) Is made, and each of the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 may be made of silicon oxide (SiO _x ) Is prepared. The present disclosure is not limited thereto.

The gate electrode 125 may be formed on the second insulating layer 120 and may overlap a channel region of the semiconductor layer 115 while the second insulating layer 120 is interposed between the gate electrode 125 and the channel region of the semiconductor layer 115. The gate electrode 125 may be made of a first conductive material, and may be implemented as a single layer or multiple layers made of magnesium (Mg), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. The present disclosure is not limited thereto.

The source electrode 140 may be connected to the exposed source region of the semiconductor layer 115 via a contact hole extending through the second and third insulating layers 120 and 135. The drain electrode 140 may be opposite to the source electrode 140, and may be connected to a drain region of the semiconductor layer 115 via a contact hole extending through the second and third insulating layers 120 and 135. Each of the source electrode 140 and the drain electrode 140 may be made of a second conductive material, and may be implemented as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. The present disclosure is not limited thereto.

The connection electrode 155 may be disposed between the first and second intermediate layers 150 and 160. The connection electrode 155 may be connected to the drain electrode 140 via a connection electrode contact hole 156 extending through the protective film/layer 145 and the first interlayer 150. The connection electrode 155 may be made of a material having low resistivity and the same as or similar to that of the drain electrode 140. The present disclosure is not limited thereto.

Referring to fig. 15, a light emitting element 170 including a light emitting layer 172 may be disposed on the second intermediate layer 160 and the bank layer 165. The light emitting element 170 may include an anode electrode 171, at least one light emitting layer 172 formed on the anode electrode 171, and a cathode electrode 173 formed on the light emitting layer 172.

The anode electrode 171 may be electrically connected to the exposed portion of the connection electrode 155 via a contact hole extending through the second interlayer 160 disposed on the first interlayer 150.

The anode electrode 171 of each pixel is not covered by the bank layer 165 to be exposed. The bank layer 165 may be made of an opaque material (e.g., black) to prevent or at least reduce light interference between adjacent pixels. In this case, the bank layer 165 may include a light shielding material including at least one of color pigment, organic black, and carbon black. The present disclosure is not limited thereto.

Referring to fig. 15, at least one light emitting layer 172 may be formed on a portion of the anode electrode 171 corresponding to the light emitting region defined by the bank layer 165. The at least one light emitting layer 172 may include a hole transporting layer, a hole injecting layer, a hole blocking layer, a light emitting layer 172, an electron injecting layer, an electron blocking layer, and an electron transporting layer on the anode electrode 171. The order of lamination of the hole transport layer, the hole injection layer, the hole blocking layer, the light emitting layer 172, the electron injection layer, the electron blocking layer, and the electron transport layer may be based on the light emitting direction. In addition, the light emitting layer 172 may include a first light emitting stack and a second light emitting stack facing each other with a charge generating layer interposed therebetween. In this case, the light emitting layer 172 of one of the first and second light emitting stacks may generate blue light, and the light emitting layer 172 of the other of the first and second light emitting stacks may generate yellow-green light, so that white light may be generated from the combination of the first and second light emitting stacks. White light generated from the combination of the first and second light emitting stacks may be incident on the color filters located above or below the light emitting layer 172, so that a color image may be realized. In another example, each light emitting layer 172 may generate each color of light corresponding to each pixel without a separate color filter, so that a color image may be presented. For example, the light emitting layer 172 of the red (R) pixel emits red light, the light emitting layer 170 of the green (G) pixel emits green light, and the light emitting layer 172 of the blue (B) pixel emits blue light.

Referring to fig. 15, the cathode electrode 173 may be formed to face the anode electrode 171 while the light emitting layer 172 is disposed between the cathode electrode 173 and the anode electrode 171, and the cathode electrode 173 may receive the high potential driving voltage EVDD.

The encapsulation layer 180 may block or at least reduce the penetration of external moisture or oxygen into the light emitting element 170 susceptible to the external moisture and oxygen. To this end, the encapsulation layer 180 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. The present disclosure is not limited thereto. In the present disclosure, the structure of the encapsulation layer 180 is described by way of example, in which the first encapsulation layer 181, the second encapsulation layer 182, and the third encapsulation layer 183 are sequentially stacked on the substrate 101.

The substrate 101 may comprise glass, plastic or a flexible polymer film. For example, the flexible polymer film may be made of any one of Polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), cyclic Olefin Copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, and Polystyrene (PS), and the present disclosure is not limited thereto.

The first encapsulation layer 181 is formed on the substrate 101 on which the cathode electrode 173 has been formed. The third encapsulation layer 183 is formed on the substrate 101 on which the second encapsulation layer 182 has been formed. The third encapsulation layer 183 and the first encapsulation layer 181 may surround the top, bottom, and side surfaces of the second encapsulation layer 182. The first and third encapsulation layers 181 and 183 may minimize or prevent external moisture or oxygen from penetrating into the light emitting element 170. Each of the first and third encapsulation layers 181 and 183 may be made of an inorganic insulating material, such as silicon nitride (SiN), which may be deposited at a low temperature _x ) Silicon oxide (SiO) _x ) Silicon oxynitride (SiON) or aluminum oxide (Al) ₂ O ₃ ). Each of the first encapsulation layer 181 and the third encapsulation layer 183 is deposited in a low temperature atmosphere. Accordingly, the light emitting element 170 susceptible to a high temperature atmosphere can be prevented from being damaged during the deposition process of the first and third encapsulation layers 181 and 183.

The second encapsulation layer 182 serves as a shock absorbing layer to relieve interlayer stress due to bending of the display device 100, and may planarize steps between the layers. The second encapsulation layer 182 may be made of a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon oxygen carbon (SiOC), or a photosensitive organic insulating layer material such as photo acryl. The present disclosure is not limited thereto. When the second encapsulation layer 182 is formed using the inkjet method, a DAM may be provided to prevent the second encapsulation film 182 in a liquid state from diffusing to the edge of the substrate 101. The DAM may be closer to the edge of the substrate 101 than the second encapsulation layer 182. The DAM may prevent the second encapsulation layer 182 in a liquid state from diffusing to a pad region where the conductive pad disposed at the outermost side of the substrate 101 is located.

The DAM is designed to prevent or at least reduce diffusion of the second encapsulation layer 182. However, when the second encapsulation layer 182 overflows the DAM during the process, the second encapsulation film 182 as an organic layer may be exposed to the outside, so that moisture or the like may invade the light emitting element. Therefore, in order to prevent intrusion, at least eight or more DAM can be stacked.

Referring to fig. 15, a DAM may be disposed on the protective layer/film 145 and in the non-display area NA.

Further, the DAM and the first and second intermediate layers 150 and 160 may be formed simultaneously. The first intermediate layer 150 and the lower layer of the DAM may be formed simultaneously. The second intermediate layer 160 and the upper layer of the DAM may be formed simultaneously. Accordingly, the DAM may have a double-layered structure.

Accordingly, the DAM may be made of the same material as that of each of the first and second intermediate layers 150 and 160. However, the present disclosure is not limited thereto.

Referring to fig. 15, the DAM may overlap the low-potential driving power line VSS. For example, the low-potential driving power line VSS may be formed in a layer under the DAM and in the non-display area NA.

The low-potential driving power line VSS and the gate driver 30 in the form of intra-panel Gate (GIP) may surround the periphery of the display panel. The low potential driving power line VSS may be located outside the gate driver 30. Further, the low potential driving power line VSS may be connected to the anode electrode 171 to apply a common voltage thereto. The gate driver 30 is simply illustrated in plan view and cross-sectional view. However, the gate driver 30 may be configured using a thin film transistor TFT having the same structure as that of the thin film transistor TFT of the display area AA.

Referring to fig. 15, the low-potential driving power line VSS is disposed outside the gate driver 30. The low potential driving power line VSS is disposed outside the gate driver 30 and surrounds the display area AA. The low-potential driving power line VSS may be made of the same material as that of each of the source electrode and the drain electrode 140 of the thin film transistor TFT. The present disclosure is not limited thereto. For example, the low-potential driving power line VSS may be made of the same material as that of the gate electrode 125.

Further, the low potential driving power line VSS may be electrically connected to the anode electrode 171. The low-potential driving power line VSS may supply the low-potential driving voltage EVSS to a plurality of pixels in the display area AA.

According to the embodiments of the present disclosure, a long time for sensing the threshold voltage of each pixel can be ensured. Therefore, the compensation rate for the threshold voltage of each pixel can be increased. Further, the number of external clock signals per pixel in the display panel may not be increased. Further, the number of external clock signals per pixel in the display panel may not be increased, so that the thickness of the bezel may be reduced, and the control load of the timing controller may be reduced.

Further, according to the embodiments of the present disclosure, a method for driving a pixel of a display device, which can secure a time to sense a threshold voltage of a driving transistor and compensate for the threshold voltage when a gate driver of the display device applies a scan signal to a pixel of an organic light emitting diode to drive the pixel, may be implemented.

Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments, and may be modified in various ways within the scope of the technical spirit of the present disclosure. Accordingly, the embodiments disclosed in the present disclosure are intended to describe, but not limit, the technical concepts of the present disclosure, and the scope of the technical concepts of the present disclosure is not limited by these embodiments. The above embodiments are, therefore, to be understood as not being limiting in all respects but as illustrative.

Claims

1. A display device, the display device comprising:

a display panel including a plurality of pixels,

each of the plurality of pixels includes:

a light emitting element configured to emit light based on a driving current;

a pixel circuit configured to control the drive current,

Wherein threshold voltage compensation is performed at least twice based on threshold voltage sensing in response to the first scan signal of a high level and the second scan signal of a high level being simultaneously applied to the pixel circuit in an overlapping manner.

2. The display device according to claim 1, further comprising:

a gate driver configured to supply a scan signal to each of the plurality of pixels;

a data driver configured to supply a data voltage to each of the plurality of pixels;

a light-emitting signal supplier configured to supply a light-emitting signal to each of the plurality of pixels; and

a timing controller configured to control the gate driver, the data driver, and the light emitting signal supplier.

3. The display device according to claim 2, wherein the pixel circuit includes:

a driving transistor configured to control the driving current, and including a first electrode as a first node, a gate electrode as a second node, and a second electrode as a third node;

A first transistor including a first gate electrode connected to a first scan signal line transmitting a first scan signal;

a second transistor including a second gate electrode connected to a second scan signal line transmitting a second scan signal;

a third transistor including a third gate electrode connected to a third scan signal line transmitting a third scan signal;

a fourth transistor including a fourth gate electrode connected to a fourth scan signal line transmitting a fourth scan signal; and

a storage capacitor connecting the second node and the third node to each other.

4. The display device of claim 3, wherein the gate driver outputs the high-level clock pulse associated with each of the first and second scan signals at least twice every 3 horizontal periods or every more horizontal periods,

wherein in each of the plurality of pixels, a threshold voltage is compensated for the pixel based on the threshold voltage sensing in response to the first scan signal having a high level and the second scan signal having a high level overlapping each other during a threshold voltage sensing period between an initialization period and a data input time and a mobility sensing period of the driving transistor.

5. The display device according to claim 4, wherein, in each of the plurality of pixels, a compensation rate of the threshold voltage increases as the number of times the first scan signal having a high level and the second scan signal having a high level overlap each other during the threshold voltage sensing period increases.

6. A display device according to claim 3, wherein the driving transistor and each of the first to fourth transistors are implemented as an n-type MOSFET NMOS or a p-type MOSFET PMOS.

7. A display device according to claim 3, wherein each of the driving transistor and the first to fourth transistors is an oxide thin film transistor, a low temperature polysilicon LTPS thin film transistor, or a crystalline silicon c-Si transistor.

8. The display device according to claim 3, wherein,

a first electrode of the driving transistor is connected to a high-potential driving voltage line transmitting a high-potential driving voltage;

a gate electrode of the driving transistor is connected to a second electrode of the second transistor and a first electrode of the storage capacitor; and is also provided with

A second electrode of the driving transistor is connected to the first electrode of the light emitting element, the first electrode of the third transistor and the second electrode of the storage capacitor,

Wherein the first transistor includes:

a first electrode connected to a first reference voltage line transmitting a first reference voltage; and

a second electrode connected to the first electrode of the second transistor and the second electrode of the fourth transistor,

wherein the second transistor includes:

a first electrode connected to the second electrode of the first transistor and the second electrode of the fourth transistor; and

a second electrode connected to the second node and to the first electrode of the storage capacitor,

wherein the third transistor includes:

a first electrode connected to the third node; and

a second electrode connected to a second reference voltage line transmitting a second reference voltage,

wherein the fourth transistor includes:

a first electrode connected to a data voltage line transmitting the data voltage; and

a second electrode connected to the second electrode of the first transistor and the first electrode of the second transistor.

9. A display device according to claim 3, wherein each of the plurality of pixels operates in separate operating periods, wherein the separate operating periods of each pixel include an initialization period of the light emitting element of the pixel, an initialization period of the driving transistor of the pixel, a threshold voltage sensing period, a data input time and mobility sensing period, and a light emitting period.

10. The display device according to claim 9, wherein during an initialization period of the light emitting element of the pixel, the third scan signal of a high level is applied to the third gate electrode to turn on the third transistor, and a second reference voltage is applied to an anode electrode of the light emitting element through the third transistor.

11. The display device according to claim 10, wherein the third scan signal of a high level is applied to the third gate electrode for 2 horizontal periods or more.

12. The display device according to claim 9, wherein, during the initialization period of the driving transistor,

the first scan signal of a high level is applied to the first gate electrode to turn on the first transistor,

the second scan signal of a high level is applied to the second gate electrode to turn on the second transistor,

the third scan signal of a high level is applied to the third gate electrode to turn on the third transistor,

a first reference voltage is applied to the gate electrode of the driving transistor through the first transistor and the second transistor such that the gate electrode of the driving transistor is initialized by the first reference voltage, and

A second reference voltage is applied to the second electrode of the driving transistor through the third transistor such that the second electrode of the driving transistor is initialized by the second reference voltage.

13. The display device of claim 12, wherein the first scan signal of a high level is applied to the first gate electrode for 1 horizontal period,

the second scan signal of high level is applied to the second gate electrode for 1 horizontal period, and

the third scan signal of a high level is applied to the third gate electrode for 2 horizontal periods.

14. The display device of claim 9, wherein, during the threshold voltage sensing period,

each of the third transistor and the fourth transistor is turned off,

a first reference voltage is applied to the gate electrode of the driving transistor through the first transistor and the second transistor, and

the voltage of the anode electrode of the light emitting element has a value based on a difference between the first reference voltage and a threshold voltage of the driving transistor.

15. The display device of claim 14, wherein the threshold voltage sensing period is repeated at least once after a predetermined horizontal period.

16. The display device of claim 15, wherein the threshold voltage sensing period is repeated at least twice after the predetermined horizontal period.

17. The display device of claim 9, wherein, during the data input time and mobility sensing period,

the fourth scan signal of a high level is applied to the fourth gate electrode to turn on the fourth transistor,

the data voltage is applied to the gate electrode of the driving transistor through the fourth transistor and the second transistor, and

the voltage of the anode electrode of the light emitting element is calculated based on a capacitance value of a first capacitor that is the storage capacitor, a capacitance value of a second capacitor that is a parasitic light emitting element capacitor that is provided between and connected to the second electrode of the storage capacitor and the cathode electrode of the light emitting element, the data voltage, and a voltage obtained based on a difference between a first reference voltage and a threshold voltage.

18. The display device according to claim 17, wherein a voltage of an anode electrode of the light-emitting element is based on a result of the following calculation: dividing a value obtained by multiplying a first capacitance value of the first capacitor by a data voltage by a value obtained by adding a second capacitance value of the first capacitor and the second capacitor to each other to generate a first value, subtracting the threshold voltage from the first reference voltage to generate a second value, then dividing a value obtained by multiplying the second capacitance value and the second value by a value obtained by adding the first capacitance value and the second capacitance value to each other to generate a third value, and then adding the first value and the third value as the result.

19. A method for driving a pixel of a display device, wherein the display device comprises:

a display panel in which a plurality of pixels are disposed; and

a gate driver configured to supply a scan signal to each of the plurality of pixels, wherein,

each of the plurality of pixels includes:

a light emitting element configured to emit light based on a driving current;

a first transistor including a first gate electrode connected to a first scan signal line transmitting a first scan signal; and

wherein the method comprises the following steps:

during the threshold voltage sensing period of each of the plurality of pixels,

outputting the first scan signal of a high level and the second scan signal of a high level to each of the plurality of pixels simultaneously and in an overlapping manner by the gate driver;

applying the first scan signal of a high level to the first gate electrode to turn on the first transistor, and applying the second scan signal of a high level to the second gate electrode to turn on the second transistor;

applying a first reference voltage to a gate electrode of the driving transistor through the first transistor and the second transistor; and

Compensating for a threshold voltage of the drive transistor.

20. The method of claim 19, wherein each of the plurality of pixels further comprises:

a storage capacitor connecting the second node and the third node to each other,

wherein the step of outputting the first scan signal includes: the gate driver outputs the third scan signal of a low level and the fourth scan signal of a low level to each of the plurality of pixels,

the third scan signal of a low level is applied to the third gate electrode, and the fourth scan signal of a low level is applied to the fourth gate electrode,

such that each of the third transistor and the fourth transistor is turned off during the threshold voltage sensing period.

21. The method of claim 20, wherein the threshold voltage comprises a voltage difference across the storage capacitor.

22. The method of claim 19, wherein during compensation of the threshold voltage, a voltage of an anode electrode of the light emitting element has a value based on a difference between the first reference voltage and the threshold voltage of the drive transistor.

23. The method of claim 20, wherein a data voltage is applied to a gate electrode of the driving transistor through the fourth transistor and the second transistor, and

wherein, during the compensation of the threshold voltage, the voltage of the anode electrode of the light emitting element has a value calculated based on a capacitance value of a first capacitor as the storage capacitor, a capacitance value of a second capacitor, which is an invisible parasitic light emitting element capacitor provided between and connected to the second electrode of the storage capacitor and the cathode electrode of the light emitting element, the data voltage, and a voltage obtained by subtracting the threshold voltage from a first reference voltage.

24. The method of claim 23, wherein the voltage of the anode electrode of the light emitting element is based on the result of the following calculation: dividing a value obtained by multiplying a first capacitance value of the first capacitor by a data voltage by a value obtained by adding a second capacitance value of the first capacitor and the second capacitor to each other to generate a first value, subtracting the threshold voltage from the first reference voltage to generate a second value, then dividing a value obtained by multiplying the second capacitance value and the second value by a value obtained by adding the first capacitance value and the second capacitance value to each other to generate a third value, and then adding the first value and the third value as the result.