CN117408222A - Simulation test circuit of time sequence unit and simulation test method thereof - Google Patents

Simulation test circuit of time sequence unit and simulation test method thereof Download PDF

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CN117408222A
CN117408222A CN202311309032.5A CN202311309032A CN117408222A CN 117408222 A CN117408222 A CN 117408222A CN 202311309032 A CN202311309032 A CN 202311309032A CN 117408222 A CN117408222 A CN 117408222A
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delay difference
expectation
time
unit
clock signal
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徐晓航
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SG Micro Beijing Co Ltd
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SG Micro Beijing Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

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  • Tests Of Electronic Circuits (AREA)

Abstract

The invention discloses a simulation test circuit and a simulation test method of a time sequence unit, wherein the simulation test circuit comprises a clock signal and input data, wherein the input data and the clock signal have a first delay difference; obtaining output data of a time sequence unit, obtaining second delay difference of the output data and a clock signal, sequentially judging whether the output data accords with a first expectation, judging whether the second delay difference accords with a second expectation and judging whether an adjustment step length accords with a third expectation, if any judging process judges that the output data does not accord with the expectation, directly and dynamically adjusting the first delay difference to obtain new input data and the clock signal without carrying out subsequent judgment, starting the next simulation, ending the test until all three judging processes accord with the expectation, and taking the first delay difference at the moment as time sequence information of the time sequence unit, thereby obtaining establishment time and/or holding time with higher precision by using less times of simulation and saving cost.

Description

Simulation test circuit of time sequence unit and simulation test method thereof
Technical Field
The present invention relates to the field of integrated circuit simulation technologies, and in particular, to a simulation test circuit and a simulation test method for a timing unit.
Background
In the circuit design, a setup time Tsu (setup time) and a hold time Th (hold time) need to be acquired in advance for the timing unit. The set-up time Tsu refers to the time required for the input data at the data input end to remain stable and unchanged before the clock effective edge of the time sequence unit arrives, if the set-up time Tsu is insufficient, the input data cannot be stably driven into the time sequence unit, and the holding time Th refers to the time required for the input data at the data input end to remain stable and unchanged after the clock effective edge of the time sequence unit arrives, if the holding time Th is insufficient, the input data cannot be driven into the time sequence unit.
The prior art generally simulates a sequential unit by means of the parameter scanning function of EDA to obtain a setup time Tsu and a hold time Th. However, the simulation method not only needs multiple scans and excessive simulation times, but also has the disadvantage that the simulation result is not visual enough.
Therefore, a new simulation test circuit of a timing unit and a simulation test method thereof are proposed to solve the above problems.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a simulation test circuit and a simulation test method thereof, so that a simulation result with higher accuracy can be obtained by using fewer simulations.
According to an aspect of the present invention, there is provided a simulation test method of a timing unit, including providing a clock signal and input data to the timing unit, the input data and the clock signal having a first delay difference; obtaining output data of the time sequence unit, judging whether the output data accords with a first expectation or not, if the output data does not accord with the first expectation, changing an adjustment step length, dynamically adjusting the first delay time difference according to the changed adjustment step length to obtain a new clock signal and input data, and starting the next simulation until the output data accords with the first expectation; if the output data accords with a first expectation, obtaining a second delay difference between the output data and the clock signal, judging whether the second delay difference accords with the second expectation, and if the second delay difference does not accord with the second expectation, dynamically adjusting the first delay difference according to a set adjusting step length to obtain a new clock signal and input data, and starting the next simulation until the second delay difference accords with the second expectation; if the second delay difference accords with the second expectation, judging whether the adjustment step length accords with a third expectation or not, if the adjustment step length does not accord with the third expectation, changing the adjustment step length, dynamically adjusting the first delay difference according to the changed adjustment step length to obtain a new clock signal and input data, and starting the next simulation until the adjustment step length accords with the third expectation, and obtaining the time sequence information of the time sequence unit according to the first delay difference of the input data and the clock signal at the moment.
Optionally, the determining whether the output data meets a first expectation comprises: judging whether the output data reaches an expected value within a preset time after the effective edge of the clock signal appears, if so, conforming to the first expected, otherwise, failing to conform to the first expected.
Optionally, the determining whether the second delay difference meets a second expectation comprises: taking the second delay difference obtained by the first simulation as a reference delay difference; judging whether the obtained second delay difference is equal to a reference delay difference of a preset multiple, if the second delay difference is greater than or equal to the reference delay difference of the preset multiple, the second delay difference accords with the second expectation, otherwise, the second delay difference does not accord with the second expectation, wherein the second delay difference represents that the edge of the output data delays the time when the effective edge of the clock signal appears, and the edge of the output data represents that the edge of the output data reaches an expected value from an unexpected value.
Optionally, the determining whether the adjustment step size meets a third expectation comprises: acquiring precision; judging whether the adjustment step length is equal to the precision, if the adjustment step length is equal to the precision, the adjustment step length accords with a third expectation, otherwise, the adjustment step length does not accord with the third expectation, wherein if the parameter input related to the precision exists, the precision is obtained through the parameter input, and if the parameter input related to the precision does not exist, the precision adopts a default value.
Optionally, the timing information includes a setup time and/or a hold time, and the first delay difference indicates that the valid edge of the clock signal is delayed from a time when the input data appears when the setup time of the timing information is tested; the first delay difference represents a time for which the input data is held after the occurrence of a valid edge of the clock signal when testing a holding time of the timing information.
Optionally, the dynamically adjusting the first delay difference according to the changed adjustment step length includes: changing the adjustment step length to be one half of the original one, and adjusting the first delay difference to be t n+1 ＝t n +step+tp＝(t n +t n-1 ) 2+tp, where t n Representing the first delay difference, t, at the nth simulation n-1 A first delay difference representing the n-1 th simulation, tp representing the accuracy; the step of dynamically adjusting the first delay difference according to a set adjustment step length comprises the step of adjusting the first delay difference to t n+1 ＝t n Step, wherein step represents a preset adjustment step, t n The first delay difference at the nth simulation is shown.
According to another aspect of the present invention, there is provided a simulation test circuit of a timing unit, including an output unit that supplies a clock signal and input data to the timing unit, the input data and the clock signal having a first delay difference; a second delay difference obtaining unit, configured to obtain output data of the timing unit, and obtain a second delay difference between the output data and the clock signal; the judging and adjusting unit is configured to obtain output data of the time sequence unit, judge whether the output data accords with a first expectation, change an adjusting step length if the output data does not accord with the first expectation, dynamically adjust the first delay time difference according to the changed adjusting step length to obtain a new clock signal and input data, start the next simulation, judge whether the second delay time difference accords with a second expectation if the output data accords with the first expectation, dynamically adjust the first delay time difference according to the set adjusting step length if the second delay time difference does not accord with the second expectation, obtain the new clock signal and input data, and start the next simulation; if the second delay difference accords with the second expectation, judging whether the adjustment step length accords with a third expectation or not, if the adjustment step length does not accord with the third expectation, changing the adjustment step length, dynamically adjusting the first delay difference according to the changed adjustment step length to obtain a new clock signal and input data, starting the next simulation, and if the adjustment step length accords with the third expectation, obtaining the time sequence information of the time sequence unit according to the first delay difference of the input data and the clock signal at the moment.
Optionally, the judging and adjusting unit includes: the first judging unit is connected with the time sequence unit and is used for judging whether the output data reaches an expected value in a preset time after the effective edge of the clock signal appears, if the output data reaches the expected value in the preset time after the effective edge of the clock signal appears, the output data accords with a first expected, otherwise, the output data does not accord with the first expected; the second judging unit is connected with the first judging unit and is used for judging whether the acquired second delay difference is equal to a preset multiple of reference delay difference or not when the output data accords with a first expectation, if the second delay difference is equal to the preset multiple of reference delay difference, the second delay difference accords with the second expectation, otherwise, the second delay difference does not accord with the second expectation, wherein the reference delay difference is the second delay difference acquired by the first simulation; the third judging unit is connected with the second judging unit and is used for acquiring precision, judging whether the adjustment step length is equal to the precision or not when the second delay difference accords with the third expectation, if so, the adjustment step length accords with the third expectation, otherwise, the adjustment step length does not accord with the third expectation; the adjusting unit is connected with the first judging unit, the second judging unit, the third judging unit and the output unit and is used for adjusting the first delay difference according to the judging results of the first judging unit, the second judging unit, the third judging unit and the output unit and providing the first delay difference to the output unit until the adjusting step length accords with a third expectation.
Optionally, the adjustment unit receives the output data not meeting the first expectation and the adjustment stepWhen the length does not meet the third expectation, changing the adjustment step length into one half of the original length, and adjusting the first delay difference into t according to the changed adjustment step length n+1 ＝t n +step+tp＝(t n +t n-1 ) 2+tp, where t n Representing the first delay difference, t, at the nth simulation n-1 A first delay difference representing the n-1 th simulation, tp representing the accuracy; when the second delay difference is received to be not in accordance with the second expected value, the first delay difference is adjusted to be t n+1 ＝t n Step, wherein step represents a preset adjustment step, t n The first delay difference at the nth simulation is shown.
Optionally, the timing information of the timing unit includes a setup time and/or a hold time, and the first delay difference indicates that the valid edge of the clock signal is delayed from the time when the input data appears when the setup time of the timing information is tested; the first delay difference represents a time for which the input data is held after the occurrence of a valid edge of the clock signal when testing a holding time of the timing information.
Optionally, the simulation test circuit further includes: the EDA graphical interface is connected with the judging and adjusting unit and used for receiving and displaying the first delay difference; and the storage module is used for receiving and storing the first delay difference and the second delay difference.
Optionally, the output unit, the second delay difference acquiring unit, and the judging and adjusting unit need to receive a plurality of parameters for initialization before the test starts, so as to adapt to different time sequence units.
The invention provides a simulation test circuit and a simulation test method of a time sequence unit, which comprises the steps of providing a clock signal and input data for the time sequence unit, wherein the input data and the clock signal have a first delay difference; obtaining output data of a time sequence unit, obtaining second delay time difference of the output data and a clock signal, sequentially judging whether the output data accords with first expectation, judging whether second delay time difference accords with second expectation and adjusting step length accords with third expectation, if any judging process judges that the output data does not accord with the expectation, directly and dynamically adjusting the first delay time difference without carrying out subsequent judgment to obtain new input data and the clock signal, starting the next round of simulation, stopping testing until all three judging processes accord with the expectation, taking the first delay time difference at the moment as time sequence information of the time sequence unit, and therefore, setting up time and/or holding time with higher precision can be obtained by dynamically adjusting the first delay time difference and using less times of simulation, and the cost is saved.
In the preferred embodiment, the simulation test circuit can also be initialized by receiving various parameters, so that the power supply voltage, the clock signal, the input data, the simulation precision and the like can be flexibly adjusted, the embodiment of the invention can be applied to various requirements, the simulation result can be directly displayed by an EDA graphical interface, and the simulation test circuit is simple and clear, and can also obtain finer data in the storage result of the storage module so as to check or other data requirements.
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The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows t of a timing cell C-Q A graph varying with tsu;
FIG. 2 shows a schematic diagram of a simulation test circuit of a timing cell in accordance with an embodiment of the present invention;
FIG. 3 shows a timing diagram of a simulation test circuit of a timing cell in accordance with an embodiment of the present invention;
fig. 4 shows a test flow chart of a simulation test method of a timing unit according to an embodiment of the invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same elements or modules are denoted by the same or similar reference numerals in the various figures. For clarity, the various features of the drawings are not drawn to scale.
It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" another element or circuit is "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.
Also, certain terms are used throughout the description and claims to refer to particular components. It will be appreciated by those of ordinary skill in the art that a hardware manufacturer may refer to the same component by different names. The present patent specification and claims do not take the form of an element or components as a functional element or components as a rule.
Furthermore, it should be noted that relational terms such as first and second are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The inventor of the present invention found that when using EDA scan to perform simulation test on a timing unit to obtain timing information (such as setup time and/or hold time) of the timing unit, under the condition that the circuit speed requirement of the timing unit is high, the simulation test of the setup time Tsu of the timing unit is generally: acquiring input data of a sequential unitThe edge of the output data is delayed by a delay difference t from the active edge of the clock signal, provided that the time tsu preceding the active edge of the clock signal is sufficiently large C-Q0 The edge of the output data is delayed by a delay difference t from the active edge of the clock signal under the condition of smaller rescanning tsu C-Q When t C-Q At t C-Q0 When 1.05 times of the time Tsu is set as the set-up time Tsu; the simulation test for the hold time Th of the sequential cells is typically: under the condition that the time th for keeping the input data after the effective edge of the clock signal of the time sequence unit is obtained is large enough, the edge delay of the output data is longer than the delay difference t of the effective edge of the clock signal C-Q0 The edge of the output data is delayed by a delay difference t from the effective edge of the clock signal under the condition of smaller rescanning th C-Q When t C-Q At t C-Q0 1.05 times the holding time Th, the corresponding Th at this time is defined as the holding time Th. The simulation method needs to obtain t first C-Q0 In case the setup time Tsu and/or the hold time Th range is not determined, several simulations need to be performed first to get a close t C-Q Can be considered t obtained in a sufficient time C-Q0 . Wherein an edge of the output data refers to an edge at which the output data transitions from an unexpected value to an expected value.
Taking a simulation test of the set-up time Tsh as an example, see FIG. 1, at an uncertainty t C-Q Under the condition of the emergency data rising range, in order to ensure the accuracy of the acquired set-up time Tsu, a smaller scanning step length is required to be selected during simulation, so that most of simulation falls in the same area, and the simulation cost is increased.
Under the condition that the circuit speed requirement of the time sequence unit is not high, the influence on the increase of the output delay caused by the fact that Tsu and/or Th are small is not needed to be considered, whether the Tsu and/or Th are enough or not is judged to be whether the output data accords with an expected value or not, when Tsu and/or Th are small, the phenomenon of output data errors can occur, therefore, tsu and/or Th need to be scanned from large to small, and then the minimum Tsu and/or Th capable of maintaining the correct output value is taken as the set-up time Tsu and/or the holding time Th. In order to obtain the high-precision set-up time Tsu and/or hold time Th, the method also needs to perform multiple simulations, and the range of the set-up time Tsu and/or hold time Th obtained by the method is wider, and when the method is finally applied to an actual circuit, the nominal value needs to be increased by more margins on the basis of the simulation value, and the margins are not well controlled.
The simulation step comprises scanning a certain range with tsu and/or th as parameters by using EDA parameter scanning function, and observing t C-Q Whether the magnitude change or output value is correct. In the actual operation process, since the scanning range is uncertain, one rough scanning is required to roughly determine the range; if the result with higher precision is to be obtained in the second scanning, the step length of the second scanning needs to be set to be the expected precision, and if the range width obtained in the first scanning is larger, the simulation number of times needed to be carried out in the second scanning is excessive, and the cost is higher. In order to reduce the cost, a third or even more scans may be required, gradually reducing the step size and approximating the accuracy. In addition, from the viewpoint of intuitiveness, the acquisition result first needs to be obtained as t C-Q0 According to t C-Q0 The 1.05 times of the process angle is used as a criterion to obtain the establishment time Tsu and/or the holding time Th, the criterion is required to be modified aiming at various temperature and process angle conditions, and the result cannot be intuitively obtained.
Accordingly, the inventors of the present invention have provided a simulation test circuit and a simulation test method of a sequential unit as follows to solve the above-described problems.
Fig. 2 shows a schematic structure of a simulation test circuit of a timing unit according to an embodiment of the present invention.
Referring to fig. 2, the simulation test circuit includes an EDA graphical interface 100, a memory module 200, a test module including an output unit 310, a second delay difference acquisition unit 320, and a judgment and adjustment unit 330, and a timing unit 400. The test module can be edited by using Verilog A language. The timing unit 400 may be a register, a latch, a flip-flop, or the like, which relates to the set-up time Tsh and/or the hold time Th, and the embodiment of the present invention is described by taking the timing unit 400 as a D flip-flop as an example, where the expected value of the output data Q is the same as the input data D.
Before the test starts, the test module needs to be initialized by receiving various parameters, such as data parameters, which are used for determining the value of the output input data D, and since the values of the corresponding time sequence information (i.e. the setup time Tsu and/or the hold time Th) when the input data D is 1 valid and the input data D is 0 valid are different, the test module can test that the input data is 1 valid and the input data is 0 valid respectively during the test, and then select a larger value as the final setup time Tsu and/or the hold time Th of the time sequence unit 400, and the data parameters are provided to the output unit 310; a power parameter for determining a voltage domain of the test module to adapt the timing unit 400 of the different voltage domains, the power parameter being provided to the output unit 310, for example. A time parameter for determining an initial value of the first delay difference of the input data D and the clock signal CLK, an initial value of the adjustment step, and a frequency of the clock signal CLK to be close to an actual use situation of the timing unit 400 in the circuit, wherein the time parameter related to the initial value of the first delay difference and the time parameter related to the frequency of the clock signal CLK are provided to the output unit 310, for example, and the time parameter related to the initial value of the adjustment step is provided to the judging and adjusting unit 330, for example; and a precision parameter for determining the final simulation end condition of the test module, ensuring the precision tp of the obtained setup time Tsu and/or hold time Th, the precision parameter being provided to the judging and adjusting unit 330, for example.
Of course, the test module may not be initialized, and at this time, the test module adopts a preset default value to perform the simulation test of the timing unit 400.
The output unit 310 is configured to provide the clock signal CLK and the input data D to the timing unit 400 according to the first delay difference. The output unit 310 may be considered as a simulation every time the clock signal CLK and the input data D are provided, and in the first simulation, if there is a parameter input related to the initial value of the first delay difference, the first delay difference is obtained through the parameter input, and in the absence of the parameter input related to the initial value of the first delay difference, the first delay difference adopts a default value, for example, 5ns, and the initial value of the first delay difference is generally selected to be a sufficiently large value.
A second delay acquiring unit 320 connected to the timing unit 400 for acquiring the output data Q of the timing unit 400 and acquiring a second delay t of the output data Q and the clock signal CLK C-Q . Wherein the second delay time t C-Q Specifically, the edge of the output data Q is delayed from the active edge of the clock signal CLK, and the edge of the output data Q refers to the edge at which the output data Q transitions from an unexpected value to an expected value.
The judging and adjusting unit 330 is connected to the second delay difference obtaining unit 320, and is configured to, when obtaining the output data Q of the timing unit 400, judge whether the output data Q meets the first expectation, if the output data Q does not meet the first expectation, change the adjustment step, and dynamically adjust the first delay difference according to the changed adjustment step, so as to obtain a new clock signal CLK and input data D, and perform the next simulation; if the output data Q meets the first expectation, determining a second delay difference t C-Q Whether or not the second delay time t is in accordance with the second expectation C-Q If the first delay time does not meet the second expectation, dynamically adjusting the first delay time according to the set adjustment step length to obtain a new clock signal CLK and input data D, and performing the next simulation; if the second delay time is t C-Q And judging whether the adjustment step length meets the second expectation or not, if the adjustment step length does not meet the third expectation, changing the adjustment step length, dynamically adjusting the first delay difference according to the changed adjustment step length to obtain a new clock signal CLK and input data D, performing the next simulation, and if the adjustment step length meets the third expectation, obtaining the time sequence information of the time sequence unit 400 according to the first delay difference of the input data D and the clock signal CLK.
The time sequence information comprises a set-up time Tsu and/or a holding time Th, and when the time sequence information is the set-up time Tsu, the first delay difference represents the time that the effective edge of the clock signal CLK is delayed from the input data D; when the timing information is the holding time Th, the first delay difference represents the time for which the input data D is held after the occurrence of the active edge of the clock signal CLK.
The EDA graphical interface 100 is connected to a judging and adjusting unit 330 for receiving and displaying the first delay difference. After the simulation test circuit finishes the simulation, the final display result of the EDA graphical interface 100 is the time sequence information of the time sequence unit 400 obtained by the test, and the display of the time sequence information of the time sequence unit 400 is more visual.
The memory module 200 is used for receiving the first delay time difference and the second delay time difference t C-Q To map a second delay time t C-Q The graph as a function of the first delay difference may thus provide needed timing information when the EDA graphical interface 100 fails, or provide a record when more detailed data is needed to make more efficient use of this simulation data. The storage module 200 may be, for example, a log file.
The timing unit 400 is used for generating output data Q according to the clock signal CLK and the input data D, and outputting the output data Q.
Further, the determining and adjusting unit 330 outputs the first delay difference in voltage form, for example, the first delay difference is 20ps, and then 20pV is correspondingly output, and then the EDA graphical interface 100 displays 20pV.
The judging and adjusting unit 330 includes a first judging unit 341, a second judging unit 342, a third judging unit 343, and an adjusting unit 344 sequentially connected between the output terminal of the timing unit 400 and the input terminal of the output unit 310.
The first judging unit 341 is connected to the timing unit 400, and is configured to judge whether the output data Q reaches the expected value within a preset time after the valid edge of the clock signal CLK, if the output data Q reaches the expected value within the preset time after the valid edge of the clock signal CLK, the output data Q meets the first expectation, otherwise, the output data Q does not meet the first expectation. The preset time is, for example, half a clock cycle.
A second judging unit 342 connected to the first judging unit 341 for judging the obtained second delay time t when the output data Q meets the first expectation C-Q Whether or not the reference delay time t is greater than or equal to a preset multiple C-Q0 If the second delay time is t C-Q A reference delay time t greater than or equal to a preset multiple C-Q0 ThenSecond delay time t C-Q0 Meets a second expectation, otherwise, a second delay difference t C-Q Does not meet the second expectation. Wherein the reference delay time t C-Q0 Second delay time t obtained for the first simulation C-Q 。
A third judging unit 343 connected to the second judging unit 342 for performing a second delay time t C-Q If the second expectation is met, judging whether the adjustment step is equal to the precision tp, if the adjustment step is equal to the precision tp, the adjustment step meets a third expectation, otherwise, the adjustment step does not meet the third expectation. If the parameter related to the precision tp is input, the precision tp is obtained through parameter input, and if the parameter related to the precision tp is not input, a default value is adopted for the precision tp. The default value of the precision tp is 10p, and the method is suitable for simulation test of the time sequence unit 400 with low requirement on circuit speed.
The adjusting unit 344 is connected to the first judging unit 341, the second judging unit 342, the third judging unit 343, and the output unit 310, and is configured to adjust the first delay difference according to the judging results of the first to third judging units, and provide the first delay difference to the output unit 310 until the adjustment step size step meets the third expectation.
When the output data Q does not meet the first expectation, the adjusting unit 344 changes the adjusting step and adjusts the first delay difference according to the changed adjusting step. For example, the adjustment step is changed to one-half of the original. If the output data Q does not meet the first expected value in the nth simulation, the adjustment step is changed to one half of the original value, and the first delay difference of the next simulation is adjusted to t n+1 ＝t n +step+tp＝(t n +t n-1 ) 2+tp, where t n Representing the first delay difference, t, at the nth simulation n-1 The first delay difference at the n-1 th simulation is shown, step shows the changed adjustment step length, and tp shows the accuracy.
The adjusting unit 344 is at the second delay time t C-Q0 And when the first delay time does not meet the second expectation, adjusting the first delay time according to a preset adjusting step length step. Assume that at the nth simulation, the second delay time t C- Q0 does not correspond toThe first delay difference of the next simulation is adjusted to t if the second expectation is met n+1 ＝t n Step, wherein t n Representing the first delay difference at the nth simulation, step represents the changed adjustment step.
The adjusting unit 344 changes the adjusting step size step when the adjusting step size step does not meet the third expectation, and adjusts the first delay difference according to the changed adjusting step size step. For example, the adjustment step is changed to one-half of the original. If the adjustment step does not meet the first expectation in the r-th simulation, the adjustment step is changed to be one half of the original one, and the first delay difference of the next simulation is adjusted to be t n+1 ＝t n +step+tp＝(t n +t n-1 ) And/2+tp, wherein the first delay difference at the nth simulation is represented, step represents the changed adjustment step length, and tp represents the precision.
Compared with the prior art that the first delay time difference is adjusted according to a certain step length for simulation, the method and the device can quickly reduce the range of the time sequence information by continuously changing the adjustment step length and adjusting the first delay time difference according to the changed adjustment step length step, so that fewer simulation times are adopted, and the time sequence information with higher simulation precision is obtained.
FIG. 3 shows a timing diagram of a simulated test circuit according to an embodiment of the invention.
In the following description of the simulation test circuit according to the embodiment of the present invention with reference to fig. 3, taking the setup time Tsu of the test timing unit 400 as an example, the T1 phase and the T2 phase respectively correspond to the first two simulations, and since the first delay time Tsu is large enough in the first simulation (TI phase), the output data Q reaches the preset value in the preset time, and the second delay time T delayed from the effective edge of the clock signal CLK according to the edge of the output data Q C-Q Obtaining a reference delay difference t C-Q0 Due to the second delay difference t C-Q Not meeting the second expectation, it is therefore necessary to adjust the first delay difference tsu to tsu2=tsu1-step 0, where tsu1 represents the first delay difference of the first simulation, i.e., the initial value of the first delay difference, step0 represents the initial value of the adjustment step (e.g., 1 ns), and then perform the second simulation according to the adjusted first delay difference tsu2 (see TStage 2), if the second delay time t is simulated for the second time C-Q Continuing to adjust the first delay difference tsu3=tsu2-step 0=tsu1-2 step0 … … if, during the nth simulation (stage T3), the output data Q does not reach the preset value within the preset time after the valid edge of the clock signal CLK occurs (the actual output data Q is shown as L2, the expected output data Q is shown as L1), changing the adjustment step size step to be one-half of the original, and adjusting the first delay difference of the next simulation to be tsu n+1 ＝tsu n +step+tp, … … if in the nth simulation, the second delay time t C-Q If the adjustment step is not in accordance with the third expectation, changing the adjustment step to be one half of the original adjustment step, and adjusting the first delay difference of the next simulation to be tsu n+1 ＝tsu n +step+tp … … until the final adjustment step corresponds to the third expectation, the first delay difference Tsu at this time is taken as the setup time Tsu.
In addition, fig. 3 is only a timing diagram of an ideal simulation test circuit, and in practical applications, the edges of the output data Q and the clock signal CLK may also be configured to slowly rise and slowly fall within a certain time through parameters, so that the simulation conditions are closer to reality.
Fig. 4 shows a test flow chart of a simulation test method of a timing unit according to an embodiment of the invention.
The following describes a simulation test method for testing the sequential unit 400 by using the test module according to the present invention with reference to fig. 4, and the specific simulation test method includes:
s1: the clock signal CLK and the input data D are provided to the timing unit 400, and the input data D and the clock signal CLK have a first delay difference.
Wherein, the initial information can be obtained by receiving a plurality of parameters before the test starts; in the present invention, it is not necessary to acquire initial information, and it may be determined whether the initial information needs to be acquired according to actual situations, and if a plurality of parameters are not received, default information is used for the initial information, where the initial information includes: the level value of the input data, the simulation accuracy, the initial value of the first delay difference, the initial value of the adjustment step size, etc.
In this application, the level value of the input data may be 0 or 1, when the timing information is acquired, two tests are generally performed, when the level value of the input data is 1, one test is performed, and when the level value of the input data is 0, one test is performed again, and finally, a larger value is selected as the timing information. The initial value of the first delay difference is, for example, 5ns by default and the initial value of the adjustment step is, for example, 1ns by default.
S2: obtaining output data Q of the time sequence unit 400, judging whether the output data Q accords with a first expectation, if the output data Q does not accord with the first expectation, changing an adjustment step length step, dynamically adjusting a first delay difference according to the changed adjustment step length to obtain a new clock signal CLK and input data D, and starting the next simulation until the output data Q accords with the first expectation.
Wherein determining whether the output data Q meets the first expectation comprises: judging whether the output data Q reaches an expected value within a preset time after the effective edge of the clock signal CLK, if the output data Q reaches the expected value within the preset time after the effective edge of the clock signal CLK, the output data Q accords with the first expectation, otherwise, the output data Q does not accord with the first expectation.
S3: if the output data Q meets the first expectation, a second delay time t between the output data Q and the clock signal CLK is obtained C-Q Judging the second delay time t C-Q Whether or not the second delay time t is in accordance with the second expectation C-Q If the first delay time does not meet the second expectation, dynamically adjusting the first delay time according to the set adjustment step to obtain a new clock signal CLK and the input data D, and starting the next simulation until the second delay time t C-Q Meets a second expectation;
wherein the second delay time t C-Q Indicating the time that the edge of the output data Q is delayed from the active edge of the clock signal CLK, the edge of the output data Q refers to the edge at which the output data Q transitions from an unexpected value to an expected value.
Judging the second delay time t C-Q Whether the second expectation is met includes: judging the obtained second delay time t C-Q Whether or not the reference delay time t is greater than or equal to a preset multiple C-Q0 If the second delay time is t C-Q A reference delay time t greater than or equal to a preset multiple C-Q0 Then the second delay time t C-Q Meets a second expectation, otherwise, a second delay difference t C-Q Does not meet the second expectation. Wherein the preset multiple is 1.05 times, and the reference delay time is t C-Q0 Second delay time t obtained for first simulation C-Q 。
S4: if the second delay time is t C-Q And judging whether the adjustment step accords with the second expectation or not, if the adjustment step does not accord with the third expectation, changing the adjustment step, dynamically adjusting the first delay difference according to the changed adjustment step to obtain a new clock signal CLK and input data D, and starting the next simulation until the adjustment step accords with the third expectation, and obtaining the time sequence information of the time sequence unit 400 according to the first delay difference of the input data D and the clock signal CLK at the moment.
Wherein determining whether the adjustment step corresponds to the third expectation comprises: acquiring precision tp; judging whether the adjustment step length step is equal to the precision tp or not, if the adjustment step length step is equal to the precision tp, the adjustment step length step accords with a third expectation, otherwise, the adjustment step length step does not accord with the third expectation, wherein if the parameter input related to the precision tp exists, the precision tp is obtained through the parameter input, and if the parameter input related to the precision tp does not exist, a default value is adopted for the precision tp. The default value of the precision tp is 10p, and the method is suitable for simulation test of a time sequence unit with low requirement on circuit speed.
Further, the timing information includes a setup time Tsu and/or a hold time Th, and at the time of testing the setup time Tsu of the timing information, the first delay difference indicates a time when the active edge of the clock signal CLK occurs later than the input data D; at the time of testing the holding time Th of the timing information, the first delay difference represents the time for which the input data d is held after the occurrence of the active edge of the clock signal CLK.
The simulation test circuit and the simulation test method provided by the embodiment of the invention comprise the steps of providing a clock signal CLK and input data D to a time sequence unit 400, wherein the input data D and the clock signal CLK have the following characteristics A first delay difference; obtaining output data Q of the time sequence unit 400, and sequentially judging whether the output data Q accords with a first expected time difference t and a second time difference t C-Q If the step meets the second expectation and the step length step meets the third expectation, if any judging process judges that the step length step does not meet the expectation, the subsequent judgment is not performed, the first delay time is directly and dynamically adjusted to obtain new input data D and clock signals CLK, the next simulation is started until all three judging processes meet the expectation, the first delay time at the moment is used as the time sequence information of the time sequence unit, so that the establishment time Tsu/the holding time Th of the tp with higher precision can be obtained by using less times of simulation, and the cost is saved.
In addition, the test module can also be initialized by receiving various parameters, so that the power supply voltage, the clock signal, the input data, the precision and the like can be flexibly adjusted, the embodiment of the invention can be applied to various requirements, the simulation result can be directly displayed by an EDA graphical interface, and the method is simple and clear, and can also obtain finer data in the storage result of the storage module for inspection or other data requirements.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The scope of the invention should be determined by the appended claims and their equivalents.

Claims (12)

1. A simulation test method of a time sequence unit comprises the following steps:
providing a clock signal and input data to the timing unit, the input data having a first delay difference from the clock signal;
obtaining output data of the time sequence unit, judging whether the output data accords with a first expectation or not, if the output data does not accord with the first expectation, changing an adjustment step length, dynamically adjusting the first delay time difference according to the changed adjustment step length to obtain a new clock signal and input data, and starting the next simulation until the output data accords with the first expectation;
if the output data accords with a first expectation, obtaining a second delay difference between the output data and the clock signal, judging whether the second delay difference accords with the second expectation, and if the second delay difference does not accord with the second expectation, dynamically adjusting the first delay difference according to a set adjusting step length to obtain a new clock signal and input data, and starting the next simulation until the second delay difference accords with the second expectation;
if the second delay difference accords with the second expectation, judging whether the adjustment step length accords with a third expectation or not, if the adjustment step length does not accord with the third expectation, changing the adjustment step length, dynamically adjusting the first delay difference according to the changed adjustment step length to obtain a new clock signal and input data, and starting the next simulation until the adjustment step length accords with the third expectation, and obtaining the time sequence information of the time sequence unit according to the first delay difference of the input data and the clock signal at the moment.
2. The simulation test method of claim 1, wherein the determining whether the output data meets a first expectation comprises:
judging whether the output data reaches an expected value within a preset time after the effective edge of the clock signal appears, if so, conforming to the first expected, otherwise, failing to conform to the first expected.
3. The simulation test method of claim 1, wherein the determining whether the second delay difference meets a second expectation comprises:
taking the second delay difference obtained by the first simulation as a reference delay difference;
judging whether the obtained second delay difference is equal to the reference delay difference of a preset multiple, if the second delay difference is more than or equal to the reference delay difference of the preset multiple, the second delay difference accords with the second expectation, otherwise, the second delay difference does not accord with the second expectation,
wherein the second delay difference represents a time when an edge of the output data is delayed from an active edge of the clock signal to occur, the edge of the output data representing an edge of the output data from an unexpected value to an expected value.
4. The simulation test method of claim 1, wherein the determining whether the adjustment step size meets a third expectation comprises:
acquiring precision;
judging whether the adjustment step length is equal to the precision, if the adjustment step length is equal to the precision, the adjustment step length accords with a third expectation, otherwise, the adjustment step length does not accord with the third expectation,
and if the parameter related to the precision is input, the precision is obtained through the parameter input, and if the parameter related to the precision is not input, the precision adopts a default value.
5. The simulation test method of claim 1, wherein the timing information includes a setup time and/or a hold time,
the first delay difference represents that the effective edge of the clock signal is delayed from the time when the input data appears when the set-up time of the timing information is tested;
the first delay difference represents a time for which the input data is held after the occurrence of a valid edge of the clock signal when testing a holding time of the timing information.
6. The simulation test method of claim 1, wherein the dynamically adjusting the first delay difference according to the changed adjustment step comprises:
Changing the adjustment step length to be one half of the original one, and adjusting the first delay difference to be t n+1 ＝t n +step+tp＝(t n +t n-1 ) 2+tp, where t n Representing the first delay difference, t, at the nth simulation n-1 A first delay difference representing the n-1 th simulation, tp representing the accuracy;
the step of dynamically adjusting the first delay difference according to a set adjustment step length comprises the step of adjusting the first delay difference to t n+1 ＝t n Step, wherein step represents a preset adjustment step, t n The first delay difference at the nth simulation is shown.
7. A simulation test circuit of a timing cell, comprising:
an output unit providing a clock signal and input data to the timing unit, the input data having a first delay difference from the clock signal;
a second delay difference obtaining unit, configured to obtain output data of the timing unit, and obtain a second delay difference between the output data and the clock signal;
the judging and adjusting unit is configured to obtain output data of the time sequence unit, judge whether the output data accords with a first expectation, change an adjusting step length if the output data does not accord with the first expectation, dynamically adjust the first delay time difference according to the changed adjusting step length to obtain a new clock signal and input data, start the next simulation, judge whether the second delay time difference accords with a second expectation if the output data accords with the first expectation, dynamically adjust the first delay time difference according to the set adjusting step length if the second delay time difference does not accord with the second expectation, obtain the new clock signal and input data, and start the next simulation; if the second delay difference accords with the second expectation, judging whether the adjustment step length accords with a third expectation or not, if the adjustment step length does not accord with the third expectation, changing the adjustment step length, dynamically adjusting the first delay difference according to the changed adjustment step length to obtain a new clock signal and input data, starting the next simulation, and if the adjustment step length accords with the third expectation, obtaining the time sequence information of the time sequence unit according to the first delay difference of the input data and the clock signal at the moment.
8. The simulation test circuit of claim 7, wherein the judging and adjusting unit comprises:
the first judging unit is connected with the time sequence unit and is used for judging whether the output data reaches an expected value in a preset time after the effective edge of the clock signal appears, if the output data reaches the expected value in the preset time after the effective edge of the clock signal appears, the output data accords with a first expected, otherwise, the output data does not accord with the first expected;
the second judging unit is connected with the first judging unit and is used for judging whether the acquired second delay difference is equal to a preset multiple reference delay difference or not when the output data accords with a first expectation, if the second delay difference is greater than or equal to the preset multiple reference delay difference, the second delay difference accords with the second expectation, otherwise, the second delay difference does not accord with the second expectation, wherein the reference delay difference is the second delay difference acquired by the first simulation;
the third judging unit is connected with the second judging unit and is used for acquiring precision, judging whether the adjustment step length is equal to the precision or not when the second delay difference accords with the second expectation, if so, the adjustment step length accords with a third expectation, otherwise, the adjustment step length does not accord with the third expectation;
The adjusting unit is connected with the first judging unit, the second judging unit, the third judging unit and the output unit and is used for adjusting the first delay difference according to the judging results of the first judging unit, the second judging unit, the third judging unit and the output unit and providing the first delay difference to the output unit until the adjusting step length accords with a third expectation.
9. According to claim 8The simulation test circuit, wherein the adjustment unit changes the adjustment step length to be one half of the original one when receiving the output data which does not meet the first expectation and the adjustment step length which does not meet the third expectation, and adjusts the first delay difference to be t according to the changed adjustment step length n+1 ＝t n +step+tp＝(t n +t n-1 ) 2+tp, where t n Representing the first delay difference, t, at the nth simulation n-1 A first delay difference representing the n-1 th simulation, tp representing the accuracy;
when the second delay difference is received to be not in accordance with the second expected value, the first delay difference is adjusted to be t n+1 ＝t n Step, wherein step represents a preset adjustment step, t n The first delay difference at the nth simulation is shown.
10. The simulation test circuit of claim 7, wherein the timing information of the timing unit includes a setup time and/or a hold time, the first delay difference indicating that a valid edge of the clock signal is delayed from a time at which the input data occurs when the setup time of the timing information is tested; the first delay difference represents a time for which the input data is held after the occurrence of a valid edge of the clock signal when testing a holding time of the timing information.
11. The simulation test circuit of claim 7, further comprising:
the EDA graphical interface is connected with the judging and adjusting unit and used for receiving and displaying the first delay difference;
and the storage module is used for receiving and storing the first delay difference and the second delay difference.
12. The simulation test circuit of claim 7, wherein,
the output unit, the second delay difference obtaining unit and the judging and adjusting unit need to receive a plurality of parameters for initialization before the test starts so as to adapt to different time sequence units.
CN202311309032.5A 2023-10-10 2023-10-10 Simulation test circuit of time sequence unit and simulation test method thereof Pending CN117408222A (en)

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