CN117406563A - Method for detecting position offset of alignment mark and method for processing semiconductor - Google Patents

Method for detecting position offset of alignment mark and method for processing semiconductor Download PDF

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Publication number
CN117406563A
CN117406563A CN202311627041.9A CN202311627041A CN117406563A CN 117406563 A CN117406563 A CN 117406563A CN 202311627041 A CN202311627041 A CN 202311627041A CN 117406563 A CN117406563 A CN 117406563A
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alignment mark
wafer
target
offset
position offset
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杨皓宇
白金宝
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Shenzhen Shengweixu Technology Co ltd
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Shenzhen Shengweixu Technology Co ltd
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Priority to CN202311627041.9A priority Critical patent/CN117406563A/en
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/708—Construction of apparatus, e.g. environment aspects, hygiene aspects or materials
    • G03F7/7085—Detection arrangement, e.g. detectors of apparatus alignment possibly mounted on wafers, exposure dose, photo-cleaning flux, stray light, thermal load

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Environmental & Geological Engineering (AREA)
  • Epidemiology (AREA)
  • Public Health (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

The method obtains warp information of a wafer after front-layer photoetching of the wafer is completed, calculates the position offset of a target alignment mark based on the warp information of the wafer, and achieves accurate positioning of the position information of the target alignment mark. The position offset can be used in the subsequent process, specifically, the alignment mark position of the wafer layer is compensated based on the position offset when the wafer layer is subjected to photoetching treatment, so that the alignment error is reduced. In addition, the original photoetching process flow is not required to be changed, and materials are not increased and changed.

Description

Method for detecting position offset of alignment mark and method for processing semiconductor
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method and apparatus for detecting a position offset of an overlay alignment mark, an electronic device, a storage medium, and a method for processing a semiconductor.
Background
In semiconductor development and mass production, OVL (Overlay error) has been under supervision as an important index in lithography.
OVL refers to the amount of positional offset between two adjacent layers of patterns on a wafer. The wafer is manufactured by stacking a plurality of layers of circuits, an alignment mark is arranged on the layer of the wafer, and the photoetching process is performed by searching the alignment mark for exposure, so that the patterns of two adjacent layers of the wafer are aligned. However, in the whole wafer process, the warpage degree of the wafer is inconsistent in each stage, which causes the alignment mark position on the wafer to change along with the warpage of the wafer, and the exposure accuracy is affected due to the fact that the exposure machine cannot accurately identify the actual alignment mark information of the wafer in real time, and finally the OVL becomes worse.
Disclosure of Invention
In order to solve the above problems, the present application provides a method, an apparatus, an electronic device, a storage medium, and a method for processing a semiconductor for detecting a positional deviation of an overlay alignment mark.
According to an aspect of the embodiments of the present application, a method for detecting a position offset of an overlay alignment mark is disclosed, where the method for detecting a position offset of an overlay alignment mark includes:
After the front layer photoetching of the wafer is completed, obtaining the warping information of the wafer;
calculating the position offset of a target alignment mark based on the warp information of the wafer, wherein the target alignment mark is an alignment mark formed on the front layer of the wafer or an alignment mark expected to be formed on the current layer of the wafer;
and outputting the position offset.
In some embodiments, the calculating the position offset of the target overlay alignment mark based on the warp information of the wafer includes:
acquiring a base line position of a target alignment mark;
and calculating the position offset of the target alignment mark based on the warp information of the wafer and the baseline position of the target alignment mark.
In some embodiments, the warp information of the wafer includes a critical position and a plurality of sample point positions between warp and non-warp positions of the wafer, wherein the plurality of sample points are distributed along a radial pitch of the wafer and between the critical position and an edge position of the wafer;
the calculating the position offset of the target overlay alignment mark based on the warp information of the wafer and the baseline position of the target overlay alignment mark includes:
Performing curve fitting based on the critical position and the plurality of sampling points to obtain a corresponding curve function;
constructing an arc length expression based on the curve function;
and obtaining the position offset of the target alignment mark based on the distance between the critical position and the baseline position of the target alignment mark and the arc length expression, wherein the target alignment mark is an alignment mark formed on the front layer of the wafer.
In some embodiments, the constructing an arc length expression based on the curve function includes:
taking the distance between the critical position and the central position of the wafer as an integral lower limit, taking the actual distance between the target alignment mark and the central position of the wafer after warping as an integral upper limit, and constructing an arc length integral formula based on the curve function;
the obtaining the position offset of the target overlay alignment mark based on the distance between the critical position and the baseline position of the target overlay alignment mark and the arc length expression includes:
setting the distance between the critical position and the baseline position of the target alignment mark as an arc length integral value;
And obtaining the position offset of the target alignment mark based on the arc length integral value and the arc length integral formula.
In some embodiments, the obtaining the position offset of the target overlay alignment mark based on the arc length integral value and the arc length integral formula includes:
acquiring an actual distance between the target alignment mark and the center position of the wafer under the warping information based on the arc length integral value and the arc length integral formula;
substituting the actual distance into the curve function to obtain the actual position of the target alignment mark under the warping information;
and obtaining a displacement vector based on the actual position and the baseline position, and taking the displacement vector as the position offset of the target alignment mark.
In some embodiments, the number of sampling points of the plurality of sampling points is at least three, and distances between adjacent sampling points in the plurality of sampling points are equal.
In some embodiments, the calculating the position offset of the target overlay alignment mark based on the warp information of the wafer and the baseline position of the target overlay alignment mark includes:
based on the baseline position and the deformation angle of the wafer, obtaining the position offset of the target alignment mark; the target alignment mark is an alignment mark expected to be formed on the wafer layer.
In some embodiments, the warp information of the wafer includes a deformation height of the wafer; the obtaining the position offset of the target overlay alignment mark based on the baseline position and the deformation angle of the wafer includes:
acquiring a horizontal distance between the baseline position and the central position of the wafer;
and obtaining the position offset of the target alignment mark based on the baseline position, the deformation height and the horizontal distance.
In some embodiments, the obtaining the position offset of the target overlay alignment mark based on the baseline position, the deformation height, and the horizontal distance includes:
based on the relation) Obtaining the position offset of the target alignment mark in the first direction in the horizontal direction, wherein X represents the position offset in the first direction, tx represents the position coordinate in the first direction, h represents the deformation height, and R represents the horizontal distance;
based on the relation) And obtaining the position offset of the target alignment mark in a second direction in the horizontal direction, wherein Y represents the position offset in the second direction, ty represents the position coordinate in the second direction, h represents the deformation height, and R represents the horizontal distance.
According to an aspect of an embodiment of the present application, a device for detecting a position offset of an alignment mark is disclosed, where the device for detecting a position offset of an alignment mark includes a warp obtaining module, an offset calculating module, and an offset output module, where the warp obtaining module is configured to obtain warp information of a wafer after front-layer lithography of the wafer is completed; the offset calculating module is used for calculating the position offset of a target alignment mark based on the warp information of the wafer, wherein the target alignment mark is an alignment mark formed on the front layer of the wafer or an alignment mark expected to be formed on the current layer of the wafer; the offset output module is used for outputting the position offset.
According to an aspect of an embodiment of the present application, an electronic device is disclosed, which includes one or more processors and a memory for storing one or more computer programs, which when executed by the one or more processors, cause the processors to implement the method for detecting a position offset of an overlay alignment mark as described above.
According to an aspect of the embodiments of the present application, a computer-readable storage medium storing computer-readable instructions that, when executed by a processor of a computer, cause the computer to perform the position offset detection method of the overlay alignment marks as described above is disclosed.
The technical scheme provided by the embodiment of the application at least comprises the following beneficial effects:
according to the scheme disclosed by the application, after the front-layer photoetching of the wafer is completed, the warp information of the wafer is obtained, and the position offset of the target alignment mark is calculated based on the warp information of the wafer, so that the position information of the target alignment mark is accurately positioned. The position offset can be used in the subsequent process, specifically, the alignment mark position of the wafer layer is compensated based on the position offset when the wafer layer is subjected to photoetching treatment, so that the alignment error is reduced. In addition, the original photoetching process flow is not required to be changed, and materials are not increased and changed.
According to an aspect of an embodiment of the present application, a method for processing a semiconductor is disclosed, including:
Carrying out photoetching treatment on the front layer of the wafer;
executing the position offset detection method of the alignment mark;
and carrying out photoetching treatment on the wafer layer based on the position offset output by the position offset detection method.
In some embodiments, when the position offset detection method is performed, the obtaining warp information of the wafer includes:
obtaining warp information of a plurality of position points in the wafer, wherein the position points are distributed at circumferential and/or radial intervals of the wafer, and each position point is associated with one target alignment mark;
when the position offset detection method is executed, acquiring the base line positions of the target alignment marks associated with the plurality of position points; and obtaining the position offset of the target alignment mark associated with the position point based on the warp information of each position point and the baseline position of the target alignment mark associated with the position point.
According to the scheme disclosed by the application, after photoetching of the front layer of the wafer is completed, before photoetching treatment is carried out on the front layer of the wafer, the warping information of the wafer is obtained, the position offset of the target alignment mark is calculated based on the warping information of the wafer, photoetching treatment is carried out on the front layer of the wafer based on the position offset, specifically, the position of the alignment mark of the front layer of the wafer is compensated based on the position offset, the position offset of the alignment mark caused by warping of the wafer can be compensated, so that the alignment mark of the front layer of the wafer and the alignment mark of the front layer of the wafer are accurately aligned, and the alignment error is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
FIG. 1 shows the alignment of an overlay alignment mark and an OVL profile for an ideal case;
FIG. 2 is a graph showing wafer warpage at various stages of a wafer processing;
FIG. 3 shows the alignment of the overlay alignment mark with warpage and the OVL profile;
FIG. 4 is a flowchart of a method for detecting a position offset of an overlay alignment mark according to an embodiment of the present application;
FIG. 5 is a flowchart showing a position offset calculation step according to an embodiment of the present application;
FIG. 6 is a schematic diagram showing a position offset amount calculation step according to an embodiment of the present application;
FIG. 7 shows a flowchart of a two-position offset amount calculation step in an embodiment of the present application;
FIG. 8 shows a schematic diagram of a two-position offset calculation step in an embodiment of the present application;
FIG. 9 is a block diagram showing the constitution of a position deviation amount detecting device of the alignment mark for alignment according to an embodiment of the present application;
FIG. 10 shows a block diagram of the components of an electronic device according to an embodiment of the present application;
FIG. 11 illustrates a block diagram of a computer system architecture for implementing some embodiments of the present application;
FIG. 12 is a flow chart illustrating a method of processing a semiconductor according to one embodiment of the present application;
fig. 13 shows a process schematic of a method for processing a semiconductor according to an embodiment of the present application.
The reference numerals are explained as follows:
101. a wafer; 1011. a sector area; 102. the front layer is sleeved with an alignment mark; 103. when the layers are overlapped, an alignment mark is formed; 104. the target is aligned with the alignment mark; 900. a position offset detecting device for overlaying the alignment mark; 901. a warp obtaining module; 902. an offset calculation module; 903. an offset output module; 1000. an electronic device; 1001. a processor; 1002. a memory; 1100. a computer system; 1101. a CPU; 1102. a ROM; 1103. a RAM; 1104. a bus; 1105. an I/O interface; 1106. an input section; 1107. an output section; 1108. a storage section; 1109. a communication section; 1110. a driver; 1111. removable media.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art.
In the description of the present application, it should be understood that the terms "center," "front," "rear," "left," "right," "vertical," "horizontal," and the like indicate an orientation or a positional relationship based on that shown in the drawings, and are merely for convenience of description and to simplify the description, but do not indicate or imply that the apparatus or element in question must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may include one or more features, either explicitly or implicitly. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present application. One skilled in the relevant art will recognize, however, that the aspects of the application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.
The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
The wafer is manufactured by stacking a plurality of layers of circuits, an alignment mark is arranged on the layer of the wafer, and the photoetching process is performed by searching the alignment mark for exposure, so that the patterns of two adjacent layers of the wafer are aligned. In general, when the wafer 101 is subjected to a photolithography process according to a set reference position without Warpage (warp) or with minimal Warpage, the photolithography apparatus performs a photolithography process on each of the wafer-level alignment marks 103 on the wafer-level with respect to each of the front-level alignment marks 102 on the wafer-front level, as shown in fig. 1 (a). In this case, the OVL profile at each position on the wafer is shown in fig. 1 (b), where the length of the arrow indicates the magnitude of OVL, and as can be seen from fig. 1 (b), the magnitude of OVL at each position on the wafer is almost equal and OVL is smaller.
However, in an actual wafer process, the warpage of each Stage (Stage) wafer is not uniform due to the influence of the film stack and pattern, and as shown in fig. 2, the warpage of the wafer (Degree) varies from FEOL (Front-end-of-line) to MOL (Middle-of-line) to BEOL (Back-end-of-line).
However, the position of the front layer alignment mark 102 of the front layer of the wafer varies with the warpage of the wafer 101, and if the warpage of the wafer 101 is not considered in the photolithography process of the wafer-level, the wafer-level alignment mark 103 may not be aligned with the front layer alignment mark 102 of the front layer of the wafer, as shown in fig. 3 (a). In this case, the OVL profile at each position on the wafer is shown in fig. 3 (b), in which the length of the arrow indicates the magnitude of the OVL, and as is clear from fig. 3 (b), the OVL at each position on the wafer gradually increases, that is, the OVL gradually becomes worse, in the radial direction of the wafer, because the warpage near the edge position of the wafer is more serious than the warpage near the center position of the wafer. Corresponding to (b) of fig. 3, a more visual OVL profile is shown in (c) of fig. 3.
When OVL is large, it affects the lithography process window margin, and WAT (Wafer Acceptance Test, wafer acceptability test) parameter drift, such as resistance drift, voltage, current drift, etc., occurs; when OVL is larger, chips made from the wafer may not work properly, resulting in yield loss, which may lead to increased costs. In addition, with further improvement of the product in the semiconductor field on miniaturization, functional integration and requirement of large-capacity storage space, the graphic miniaturization promotes the increase of structural units on the effective area, so that the OVL process window of the key layer is seriously reduced. For this reason, it is necessary to control the overlay error to a small value.
However, in the prior art, only the overlay error is generally measured, and when the overlay error is too large, the wafer process is stopped or the manufactured wafer is scrapped, so that the overlay error cannot be accurately controlled to be smaller in the wafer process according to the OVL process window. Therefore, the method for detecting the position offset of the alignment mark can accurately position the position information of the alignment mark under the condition that the original photoetching process flow is not changed and materials are not added or changed, so that the accurate position information of the alignment mark is further provided for the photoetching equipment, and finally, the method for detecting the position offset of the alignment mark for reducing the alignment error is realized.
The following describes a detailed description of a method for detecting a position offset of an overlay alignment mark provided in the present application with reference to a specific embodiment.
Fig. 4 is a flowchart of a method for detecting a position offset of an overlay alignment mark according to an embodiment of the present application, and referring to fig. 4, the method for detecting a position offset of an overlay alignment mark at least includes a warp information obtaining step, a position offset calculating step, a position offset outputting step, and the like, which correspond to the following steps S110 to S130, respectively, and are described in detail as follows:
In step S110, after the front-layer lithography is completed, warp information of the wafer is acquired.
The warp information of the wafer may be data that directly characterizes the warp condition of the wafer, for example, deformation angle information of the wafer, deformation height information of the wafer, and the like. Wherein the deformation angle refers to an angle θ between a vertical line of a tangent line at a position corresponding to the target alignment mark and a normal line of a flat surface of the wafer, as shown in fig. 8, where L 1 Representing a tangent line of a position corresponding to the target alignment mark, F 1 Represents a tangent line L 1 Vertical line F of (2) 2 Representing the normal of the wafer flat surface; the included angle theta is also equal to the included angle between the tangent line of the position corresponding to the target alignment mark and the horizontal straight line in the wafer plane, L 2 Representing the horizontal straight line. The deformation height refers to the tilting height of the wafer at the position corresponding to the target overlay alignment mark, and is shown as h in fig. 8.
The wafer warpage information may also be data indirectly indicative of the wafer warpage, e.g., critical position between the wafer warpage and non-warpage positions, such as Q shown in FIG. 6 (a) 0 Points, e.g. between the critical position and the edge position of the wafer, such as Q shown in FIG. 6 (a) 1 Point to Q n And (5) a dot.
In step S120, a positional offset of the target overlay alignment mark is calculated based on the warp information of the wafer.
The target alignment mark may be an alignment mark formed on the front layer of the wafer, or an alignment mark formed on the front layer of the wafer.
In one embodiment, in step S120, the position offset of the target overlay alignment mark is calculated in combination with the baseline position of the target overlay alignment mark. It will be appreciated that the Baseline position (Baseline position) is the position information according to which the lithographic apparatus performs the lithographic process, and in the conventional art, the positional offset of the target alignment mark is not considered, and the lithographic apparatus performs the lithographic process directly according to the Baseline position when performing the lithographic process.
In detail, the step S120 includes: firstly, acquiring a base line position of a target alignment mark; and calculating the position offset of the target alignment mark based on the warp information of the wafer and the baseline position of the target alignment mark.
The warp information of the wafer may be warp information corresponding to a position point associated with the target alignment mark, or may include warp information corresponding to a position point associated with the target alignment mark and warp information corresponding to other position points on the wafer. In step S120, the positional offset of the target overlay alignment mark is calculated based on the warp information corresponding to the position point associated with the target overlay alignment mark and the baseline position of the target overlay alignment mark.
In one embodiment, the warp information of the wafer includes a critical position between the warp position and the non-warp position of the wafer and a plurality of sampling point positions, wherein the plurality of sampling points are distributed along a radial pitch of the wafer and between the critical position and an edge position of the wafer. Referring to fig. 5, in this embodiment, step S120 includes the following steps S210 to S230, which are described in detail below:
in step S210, curve fitting is performed based on the critical position and the plurality of sampling points to obtain a corresponding curve function.
The plurality of sampling points may be at least two sampling points, and at this time, curve fitting is performed by three position points, namely, two sampling points and a critical position. In order to improve the accuracy of the curve fitting result, more sampling points, for example, six sampling points, eight sampling points, ten sampling points or more, can be selected under the condition of considering both the data operand and the curve fitting efficiency.
In order to improve accuracy of the fitting result, the plurality of sampling points are uniformly distributed along the radial direction of the wafer, and in this embodiment, the number of sampling points of the plurality of sampling points is more than three, for example, ten, and distances between adjacent sampling points in the plurality of sampling points are equal.
In detail, the curve fitting may be performed based on the critical position and the plurality of sampling point positions, by using a Least square method (Least square) to fit the curve by minimizing the sum of Squares of errors from the data points to the fitted curve, by using spline interpolation (Spline Interpolation), by creating a smooth curve between the data points, by using polynomial regression (Polynomial Regression), or the like, and will not be described here.
In one embodiment, as shown in FIG. 6 (a), the plurality of sampling points is Q 1 Point to Q n Point where n is greater than 2, critical position Q 0 The coordinates of the point are (r, a, z) based on the critical position Q 0 Point, multiple sampling points Q 1 Point to Q n And performing curve fitting on the point positions to obtain a curve function z (x).
In step S220, an arc length expression is constructed based on the curve function.
In one embodiment, step S220 is specifically: taking the distance between the critical position and the central position of the wafer as an integral lower limit, taking the actual distance between the target alignment mark after warping and the central position of the wafer as an integral upper limit, and constructing an arc length integral formula based on a curve function, wherein the constructed arc length integral formula is as follows:
Wherein R represents the lower integral limit, i.e. the distance between the critical position and the center position O point of the wafer, and R' represents the upper integral limit, i.e. the target alignment mark after warpageThe actual distance from the center O point of the wafer, z' 2 (r) represents the square of the derivative of z (r), i.e. deriving and calculating the square of the curve function z (x) obtained in step S210, i.e. z' 2 (r), dr represents the derivative of r,as a integrand, s' represents the integral value of the arc length, i.e. r corresponds to the position Q 0 The curve length from point (R, a, z) to point (R ', a, z') at position P 'corresponding to R'.
In step S230, a position offset of the target overlay alignment mark is obtained based on the distance between the critical position and the baseline position of the target overlay alignment mark and the arc length expression.
The target alignment mark is an alignment mark formed on the front layer of the wafer.
In one embodiment, step S230 includes: setting the distance between the critical position and the baseline position of the target alignment mark as an arc length integral value; and obtaining the position offset of the target alignment mark based on the arc length integral value and the arc length integral formula.
As described above, the baseline position of the target alignment mark is the position information according to which the lithographic apparatus performs the lithographic process, and in the case where no wafer warpage occurs, the baseline position is the actual position of the target alignment mark, as indicated by the P point (R, a, z) in fig. 6 (a).
Before and after wafer warpage, the same position point is equidistant from the critical position, i.e., critical position Q 0 The distance of point (R, a, z) from the baseline position Ppoint (R, a, z) is from the critical position Q 0 The distance from the point (R, a, z) to the point (R ', a, z ') at the actual position P ' is equal, so that the critical position Q 0 The distance s of the point (R, a, z) to the baseline position P point (R, a, z) is equal to s ' in the arc length integration formula, i.e. satisfying the expression s ' =s=r-R, and R ' can be obtained by combining the expression and the arc length integration formula.
In the embodiment, the distance between the actual position of the target alignment mark after the warpage and the center position of the wafer can be obtained by constructing an arc length integral formula and based on the fact that the arc length is unchanged before and after the warpage, so that the actual position of the target alignment mark after the warpage is further obtained, data calculation is simple, and efficiency is high.
In an embodiment, based on an arc length integral value and an arc length integral formula, obtaining an actual distance between a target alignment mark and a center position O point of a wafer under warp information; substituting the actual distance into a curve function to obtain an actual position P ' point (R ', a, z ') of the target alignment mark under the warping information; obtaining displacement vectors based on actual and baseline positions As a positional offset of the target overlay alignment mark.
By the method, the three-dimensional position offset can be obtained, and the position information of the target alignment mark in the three-dimensional space can be accurately positioned. For the obtained position offsetData processing can be performed subsequently, and the position offset is calculatedAnd performing dimension reduction processing, decomposing the dimension reduction processing into a horizontal offset and a vertical offset, and performing position compensation on the horizontal offset when performing photoetching processing on the wafer layer by using photoetching equipment. When exposure is carried out, a focusing system of the lithography equipment is kept in a region exposed on the surface of a wafer for focusing, and after the offset in the vertical direction is obtained, the focusing position of a light matrix of the lithography equipment can be adjusted through the lens, so that the problem of defocusing caused by deformation in the z direction is solved.
In the foregoing embodiment, Q 0 Coordinates (R, a, z) corresponding to points, coordinates (R, a, z) corresponding to points P, coordinates (R ', a, z ') corresponding to points P ' wherein a in the coordinates (R ', a, z ') represents the angle of the sector corresponding to the arc length S, as shown in fig. 6 (b), the wafer 101 has 360 degrees, and the sector 1011 corresponding to 0 ° to 5 ° is obtained by cutting itThe amount of positional offset of the target overlay alignment mark 104 in (a) is 5 °. Where z represents the coordinate in the vertical direction.
In an embodiment, the position offset of the target overlay alignment mark is obtained based on the baseline position of the target overlay alignment mark and the deformation angle of the wafer. The target alignment mark is an alignment mark expected to be formed on the wafer layer.
The base line position of the alignment mark is formed on the wafer current layer in a predicted mode, and the deformation angle of the wafer is combined, so that the position offset of the base line position of the target alignment mark relative to the correct position under the warping information is obtained, and the calculation mode of the position offset is simple and easy to realize.
In an embodiment, the deformation angle is represented by the deformation height and the horizontal distance between the baseline position of the target alignment mark and the center position of the wafer, the deformation angle is not required to be detected, the deformation height and the horizontal distance are simpler to obtain, and the calculation process of the position offset can be simplified. Referring to fig. 7, in this embodiment, step S120 includes the following steps S310 to S320, which are described in detail below:
in step S310, a horizontal distance between the baseline position of the target overlay alignment mark and the center position of the wafer is obtained.
As shown in fig. 8, the horizontal distance between the base line position of the target overlay alignment mark and the center position of the wafer, that is, the distance R between the position coordinate Tx of the base line position of the target overlay alignment mark in the first direction and the position coordinate Tox of the center position O point of the wafer in the first direction. Wherein the first direction is the x-axis direction.
In step S320, the position offset of the target overlay alignment mark is obtained based on the baseline position, the deformation height, and the horizontal distance of the target overlay alignment mark.
In one embodiment, the relation is based on) Obtaining a first direction of the target alignment mark in the horizontal directionIs used for the position offset of the lens. Wherein X represents the position offset of the target alignment mark in the first direction in the horizontal direction, tx represents the position coordinate of the base line position of the target alignment mark in the first direction, h represents the deformation height, and R represents the horizontal distance between the base line position of the target alignment mark and the center position of the wafer.
Based on the relation) The position offset of the target overlay alignment mark in the second direction in the horizontal direction is obtained. Wherein Y represents the position offset of the target alignment mark in the second direction in the horizontal direction, ty represents the position coordinate of the base line position of the target alignment mark in the second direction, h represents the deformation height, and R represents the horizontal distance between the base line position of the target alignment mark and the center position of the wafer. Wherein the second direction is the y-axis direction.
The position offset X and Y of the target alignment mark in the horizontal direction are obtained in the mode, the calculation of the position offset is simple, and the accurate positioning of the position information of the target alignment mark in the horizontal direction is realized.
In step S130, the positional offset is output.
That is, the positional deviation calculated in step S120 is output to a target object, such as a lithographic apparatus or other apparatus other than the lithographic apparatus.
In summary, according to the scheme disclosed by the application, after the front layer photoetching of the wafer is completed, the warp information of the wafer is obtained, and the position offset of the target alignment mark is calculated based on the warp information of the wafer, so that the position information of the target alignment mark is accurately positioned. The position offset can be used in the subsequent process, specifically, the alignment mark position of the wafer layer is compensated based on the position offset when the wafer layer is subjected to photoetching treatment, so that the alignment error is reduced. In addition, the original photoetching process flow is not required to be changed, and materials are not increased and changed.
Next, referring to fig. 9, the present embodiment provides a device 900 for detecting a position offset of an alignment mark, where the device 900 mainly includes a warp obtaining module 901, an offset calculating module 902, and an offset outputting module 903.
The warp obtaining module 901 is configured to obtain warp information of a wafer after the front-layer lithography of the wafer is completed.
The offset calculating module 902 is configured to calculate, based on warp information of the wafer, a position offset of a target alignment mark, where the target alignment mark is an alignment mark formed on a front layer of the wafer or an alignment mark expected to be formed on a current layer of the wafer.
In one embodiment, the offset calculation module 902 is configured to: acquiring a base line position of a target alignment mark; and calculating the position offset of the target alignment mark based on the warp information of the wafer and the baseline position of the target alignment mark.
In one embodiment, the warp information of the wafer includes a critical position and a plurality of sampling point positions between the warp position and the non-warp position of the wafer, wherein the plurality of sampling points are distributed along the radial distance of the wafer and between the critical position and the edge position of the wafer; the offset calculation module 902 is configured to: performing curve fitting based on the critical position and the plurality of sampling points to obtain a corresponding curve function; constructing an arc length expression based on the curve function; and obtaining the position offset of the target alignment mark based on the distance between the critical position and the baseline position and the arc length expression of the target alignment mark, wherein the target alignment mark is an alignment mark formed on the front layer of the wafer.
In one embodiment, the offset calculation module 902 is configured to: taking the distance between the critical position and the central position of the wafer as an integral lower limit, taking the actual distance between the target alignment mark after warping and the central position of the wafer as an integral upper limit, and constructing an arc length integral formula based on a curve function; setting the distance between the critical position and the baseline position of the target alignment mark as an arc length integral value; and obtaining the position offset of the target alignment mark based on the arc length integral value and the arc length integral formula.
In one embodiment, the offset calculation module 902 is configured to: based on the arc length integral value and the arc length integral formula, obtaining the actual distance between the target alignment mark and the center position of the wafer under the warping information; substituting the actual distance into a curve function to obtain the actual position of the target alignment mark under the warping information; and obtaining a displacement vector based on the actual position and the baseline position as a position offset of the target alignment mark.
In an embodiment, the number of sampling points of the plurality of sampling points is at least three, and distances between adjacent sampling points in the plurality of sampling points are equal.
In one embodiment, the offset calculation module 902 is configured to: based on the base line position and the deformation angle of the wafer, obtaining the position offset of the target alignment mark; the target alignment mark is an alignment mark expected to be formed on the wafer layer.
In one embodiment, the warp information of the wafer includes a deformation height of the wafer; the offset calculation module 902 is configured to: acquiring a horizontal distance between a base line position and a center position of a wafer; and obtaining the position offset of the target alignment mark based on the baseline position, the deformation height and the horizontal distance.
In one embodiment, the offset calculation module 902 is configured to: based on the relation ) And obtaining the position offset of the target alignment mark in the first direction in the horizontal direction, wherein X represents the position offset of the target alignment mark in the first direction in the horizontal direction, tx represents the position coordinate of the base line position of the target alignment mark in the first direction, h represents the deformation height, and R represents the horizontal distance between the base line position of the target alignment mark and the central position of the wafer.
Based on the relation) The position offset of the target overlay alignment mark in the second direction in the horizontal direction is obtained. Wherein Y represents the position offset of the target alignment mark in the second direction in the horizontal direction, ty represents the position coordinate of the base line position of the target alignment mark in the second direction, h represents the deformation height, and R represents the horizontal distance between the base line position of the target alignment mark and the center position of the wafer.
The offset output module 903 is configured to output the position offset calculated by the offset calculation module 902.
The implementation process of the functions and actions of each module in the alignment mark alignment position offset detection apparatus 900 is specifically described in the implementation process of the corresponding steps in the alignment mark alignment position offset detection method, and will not be described in detail herein.
Referring to fig. 10, the present embodiment provides an electronic device 1000, where the electronic device 1000 includes one or more processors 1001 and a memory 1002, and the memory 1002 is configured to store one or more programs, and when the one or more programs are executed by the one or more processors 1001, cause the electronic device 1000 to implement a method for detecting a position offset of an overlay alignment mark according to the present application.
The electronic device 1000 may be a lithographic device or other devices than a lithographic device.
FIG. 11 illustrates a block diagram of a computer system used to implement some embodiments of the present application, it being noted that the computer system illustrated in FIG. 11 is merely an example and should not be taken as limiting the functionality and scope of use of embodiments of the present application.
As shown in fig. 11, the computer system 1100 includes a CPU (Central Processing Unit ) 1101 that can perform various appropriate actions and processes, such as performing the positional deviation amount detection method of the alignment mark in the above-described embodiment, according to a program stored in a ROM (Read-Only Memory) 1102 or a program loaded from a storage section 1108 into a RAM (Random Access Memory ) 1103. In the RAM 1103, various programs and data required for system operation are also stored. The CPU 1101, ROM 1102, and RAM 1103 are connected to each other by a bus 1104. An I/O (Input/Output) interface 1105 is also connected to bus 1104.
The following components are connected to the I/O interface 1105: an input section 1106 including a keyboard, a mouse, and the like; an output portion 1107 including a CRT (Cathode Ray Tube), an LCD (Liquid Crystal Display ), and the like, a speaker, and the like; a storage section 1108 including a hard disk or the like; and a communication section 1109 including a network interface card such as a LAN (Local Area Network ) card, a modem, or the like. The communication section 1109 performs communication processing via a network such as the internet. The drive 1110 is also connected to the I/O interface 1105 as needed. Removable media 1111, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like, is installed as needed in drive 1110, so that a computer program read therefrom is installed as needed in storage section 1108.
In particular, according to embodiments of the present application, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present application include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising a computer program for performing all or part of the steps shown in the flowcharts of the misalignment amount detection method for the overlay alignment. In such an embodiment, the computer program can be downloaded and installed from a network via the communication portion 1109, and/or installed from the removable media 1111. When executed by a Central Processing Unit (CPU) 1101, performs the various functions defined in the system of the present application.
It should be noted that, the computer readable medium shown in the embodiments of the present application may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-Only Memory (ROM), an erasable programmable read-Only Memory (Erasable Programmable Read Only Memory, EPROM), flash Memory, an optical fiber, a portable compact disc read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present application, however, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with a computer-readable computer program embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. A computer program embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the foregoing.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. Where each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units involved in the embodiments of the present application may be implemented by means of software, or may be implemented by means of hardware, and the described units may also be provided in a processor. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.
As another aspect, the present application also provides a computer-readable medium that may be contained in the electronic device described in the above embodiment; or may exist alone without being incorporated into the electronic device. The computer-readable medium carries one or more programs which, when executed by one of the electronic devices, cause the electronic device to implement the methods of the above-described embodiments.
It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functions of two or more modules or units described above may be embodied in one module or unit, in accordance with embodiments of the present application. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.
From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present application may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a usb disk, a mobile hard disk, etc.) or on a network, and includes several instructions to cause a computing device (may be a personal computer, a server, a touch terminal, or a network device, etc.) to perform the method according to the embodiments of the present application.
Next, referring to fig. 12, the present embodiment provides a method for processing a semiconductor, which at least includes a wafer front-layer lithography step, a position offset detection step, a wafer layer lithography step, and the like, and corresponds to the following steps S410 to S430, respectively, and is described in detail below:
in step S410, a photolithography process is performed on the wafer front layer.
The wafer front layer refers to a layer which is subjected to photoetching before the wafer front layer refers to a layer which is subjected to photoetching next.
In step S420, the foregoing method for detecting the position offset of the overlay alignment mark is performed to obtain the position offset of the target overlay alignment mark.
The specific implementation of step S420 may refer to the foregoing description, and the description will not be repeated here.
The position offset of the target alignment mark may be calculated by using the embodiment shown in fig. 5, or the position offset of the target alignment mark may be calculated by using the embodiment shown in fig. 7. In detail, when the layer composition of the wafer is relatively simple and the warpage is slight, the embodiment shown in fig. 7 is adopted to calculate the position offset of the target alignment mark, and only the two-dimensional position offset is obtained at this time, so that the calculation process is simpler; under the conditions that the layer composition of the wafer is complex and the warping is serious, the embodiment shown in fig. 5 is adopted to calculate the position offset of the target alignment mark, and at this time, the three-dimensional position offset can be obtained, which is beneficial to controlling the alignment error to be smaller.
In an embodiment, in order to reduce the overlay error as much as possible, when the method for detecting the position offset is performed, the position offset of a plurality of target overlay alignment marks is detected, where the plurality of target overlay alignment marks respectively correspond to different position points of the wafer. In this embodiment, when warp information of a wafer is acquired, warp information of a plurality of position points in the wafer is acquired, and each position point is associated with a target alignment mark. The plurality of position points may be distributed along the circumferential pitch of the wafer, may be distributed along the radial pitch of the wafer, and may be distributed along the circumferential and radial pitches of the wafer, that is, the plurality of position points include a plurality of position points distributed along the circumferential pitch of the wafer and a plurality of position points distributed along the radial pitch of the wafer. In this embodiment, a baseline position of a target overlay alignment mark associated with a plurality of position points is acquired; and obtaining the position offset of the target alignment mark associated with the position point based on the warp information of each position point and the baseline position of the target alignment mark associated with the position point.
When the plurality of position points are distributed along the circumferential spacing of the wafer, the position offset of the target alignment mark associated with the different position points in the circumferential direction of the wafer can be obtained, when the plurality of position points are distributed along the radial spacing of the wafer, the position offset of the target alignment mark associated with the different position points in the radial direction of the wafer can be obtained, when the plurality of position points are distributed along the circumferential direction and the radial spacing of the wafer, the position offset of the target alignment mark associated with the different position points in the circumferential direction of the wafer can be obtained, and the position offset of the target alignment mark associated with the different position points in the radial direction of the wafer can be obtained.
It should be noted that, the target alignment mark associated with the location point may be that the location point corresponds to the target alignment mark in position, or the location point is close to the target alignment mark in position, for example, the location point associated with the location point is a location point where one or some of the wafer parts corresponding to the target alignment mark is close to the location corresponding to the target alignment mark. The warpage conditions of different parts of the wafer in the circumferential direction and the radial direction are often different, and the position information of more alignment marks is accurately positioned by acquiring the warpage information of a plurality of position points distributed in the circumferential direction and/or the radial direction of the wafer and acquiring the position offset of the target alignment marks associated with each position point, so that photoetching treatment is accurately carried out in the subsequent process, and the alignment error is reduced.
Of course, in other embodiments, warp information of only one position point in the wafer may be obtained, in which case, only the position offset of the target alignment mark associated with the one position point is obtained, and the subsequent photolithography processing step only compensates for the position of the target alignment mark associated with the one position point.
In step S430, a photolithography process is performed on the wafer layer based on the positional offset output in step S420.
The position offset output in step S420 may be directly output to the lithography apparatus, where the lithography apparatus performs the lithography process on the target alignment mark corresponding to the wafer layer directly based on the position offset output in step S420, that is, compensates the baseline position of the target alignment mark corresponding to the wafer layer based on the position offset, for example, adjusts the baseline position of the target alignment mark to the right by d1 when the position of the target alignment mark is offset to the left by d1 in the first direction, obtains the compensated position, and performs the lithography process according to the compensated position; for another example, when the position of a target alignment mark is shifted forward by d2 in the second direction, the baseline position of the target alignment mark is adjusted backward by d2 to obtain a compensated position, and then photolithography is performed according to the compensated position.
The position offset output in step S420 may also be a compensation for the baseline position of the target overlay alignment mark according to the position offset, so as to obtain a compensated position vector diagram, and then output the compensated position vector diagram to the lithography apparatus, where the lithography apparatus may directly use the position vector diagram to perform lithography processing.
The wafer front layer may be a first layer, a second layer, a third layer, or the like. In one embodiment, as shown in fig. 13, after each layer of the wafer is subjected to the photolithography process, the warp information of the wafer is obtained, and when the warp of the wafer exceeds the requirement, the subsequent processing steps are terminated, so as to avoid meaningless processing steps and improve the utilization rate of the photolithography equipment. Before performing the photolithography process, step S420 is performed using the acquired warp information of the wafer to obtain the position offset of the target alignment mark, and the position compensation is performed during the photolithography process.
The step S420 may be performed for a plurality of layers of the wafer and may be performed for position compensation when performing photolithography processing, or the step S420 may be performed only for a critical layer of the wafer and may be performed for position compensation when performing photolithography processing.
According to the scheme disclosed by the application, after photoetching of the front layer of the wafer is completed, before photoetching treatment is carried out on the front layer of the wafer, the warping information of the wafer is obtained, the position offset of the target alignment mark is calculated based on the warping information of the wafer, photoetching treatment is carried out on the front layer of the wafer based on the position offset, specifically, the position of the alignment mark of the front layer of the wafer is compensated based on the position offset, the position offset of the alignment mark caused by warping of the wafer can be compensated, so that the alignment mark of the front layer of the wafer and the alignment mark of the front layer of the wafer are accurately aligned, and the alignment error is reduced. The method can be applied to the processing of series semiconductors such as Dram (Dynamic Random Access Memory ), SRAM (Static Random Access Memory, static random access memory), 3D NAND (flash memory), logic IC (Logic integrated circuit) and the like.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

Claims (14)

1. The method for detecting the position offset of the alignment mark is characterized by comprising the following steps:
after the front layer photoetching of the wafer is completed, obtaining the warping information of the wafer;
calculating the position offset of a target alignment mark based on the warp information of the wafer, wherein the target alignment mark is an alignment mark formed on the front layer of the wafer or an alignment mark expected to be formed on the current layer of the wafer;
and outputting the position offset.
2. The method for detecting a positional deviation of an overlay alignment mark according to claim 1, wherein calculating a positional deviation of a target overlay alignment mark based on warp information of the wafer comprises:
Acquiring a base line position of a target alignment mark;
and calculating the position offset of the target alignment mark based on the warp information of the wafer and the baseline position of the target alignment mark.
3. The method according to claim 2, wherein the warp information of the wafer includes a critical position and a plurality of sampling point positions between a warp position and a non-warp position of the wafer, wherein the plurality of sampling points are distributed along a radial pitch of the wafer and between the critical position and an edge position of the wafer;
the calculating the position offset of the target overlay alignment mark based on the warp information of the wafer and the baseline position of the target overlay alignment mark includes:
performing curve fitting based on the critical position and the plurality of sampling points to obtain a corresponding curve function;
constructing an arc length expression based on the curve function;
and obtaining the position offset of the target alignment mark based on the distance between the critical position and the baseline position of the target alignment mark and the arc length expression, wherein the target alignment mark is an alignment mark formed on the front layer of the wafer.
4. The method for detecting a positional deviation of an overlay alignment mark according to claim 3,
the constructing an arc length expression based on the curve function includes:
taking the distance between the critical position and the central position of the wafer as an integral lower limit, taking the actual distance between the target alignment mark and the central position of the wafer after warping as an integral upper limit, and constructing an arc length integral formula based on the curve function;
the obtaining the position offset of the target overlay alignment mark based on the distance between the critical position and the baseline position of the target overlay alignment mark and the arc length expression includes:
setting the distance between the critical position and the baseline position of the target alignment mark as an arc length integral value;
and obtaining the position offset of the target alignment mark based on the arc length integral value and the arc length integral formula.
5. The method for detecting a positional deviation of an overlay alignment mark according to claim 4, wherein the obtaining the positional deviation of the target overlay alignment mark based on the arc length integral value and the arc length integral formula comprises:
Acquiring an actual distance between the target alignment mark and the center position of the wafer under the warping information based on the arc length integral value and the arc length integral formula;
substituting the actual distance into the curve function to obtain the actual position of the target alignment mark under the warping information;
and obtaining a displacement vector based on the actual position and the baseline position, and taking the displacement vector as the position offset of the target alignment mark.
6. The method for detecting a position offset of an overlay alignment mark according to claim 3, wherein the number of sampling points of the plurality of sampling points is at least three, and distances between adjacent sampling points of the plurality of sampling points are equal.
7. The method for detecting a positional deviation of an overlay alignment mark according to claim 2, wherein the calculating a positional deviation of the target overlay alignment mark based on warp information of the wafer and a baseline position of the target overlay alignment mark comprises:
based on the baseline position and the deformation angle of the wafer, obtaining the position offset of the target alignment mark; the target alignment mark is an alignment mark expected to be formed on the wafer layer.
8. The method for detecting a positional deviation of an overlay alignment mark according to claim 7, wherein the warp information of the wafer includes a deformation height of the wafer; the obtaining the position offset of the target overlay alignment mark based on the baseline position and the deformation angle of the wafer includes:
acquiring a horizontal distance between the baseline position and the central position of the wafer;
and obtaining the position offset of the target alignment mark based on the baseline position, the deformation height and the horizontal distance.
9. The method for detecting a positional deviation of an overlay alignment mark according to claim 8, wherein the obtaining the positional deviation of the target overlay alignment mark based on the baseline position, the deformation height, and the horizontal distance comprises:
based on the relationObtaining a position offset of the target overlay alignment mark in a first direction in a horizontal direction, wherein X represents the position offset in the first direction, and Tx represents the position sitting in the first directionA mark, h represents the deformation height, and R represents the horizontal distance;
based on the relation And obtaining the position offset of the target alignment mark in a second direction in the horizontal direction, wherein Y represents the position offset in the second direction, ty represents the position coordinate in the second direction, h represents the deformation height, and R represents the horizontal distance.
10. The utility model provides a position offset detection device of alignment mark is carved to cover which characterized in that includes:
the warp obtaining module is used for obtaining warp information of the wafer after photoetching of the front layer of the wafer is completed;
the offset calculating module is used for calculating the position offset of a target alignment mark based on the warp information of the wafer, wherein the target alignment mark is an alignment mark formed on the front layer of the wafer or an alignment mark expected to be formed on the current layer of the wafer;
and the offset output module is used for outputting the position offset.
11. An electronic device, comprising:
one or more processors;
a memory for storing one or more computer programs that, when executed by the one or more processors, cause the processors to implement the method of detecting a positional offset of an overlay alignment as recited in any one of claims 1 to 9.
12. A computer-readable storage medium storing computer-readable instructions that, when executed by a processor of a computer, cause the computer to perform the method of detecting the positional offset of the overlay alignment marks according to any one of claims 1 to 9.
13. A method of processing a semiconductor, comprising:
carrying out photoetching treatment on the front layer of the wafer;
performing the positional deviation amount detection method of the overlay alignment mark according to any one of claims 1 to 9;
and carrying out photoetching treatment on the wafer layer based on the position offset output by the position offset detection method.
14. The method of manufacturing a semiconductor device according to claim 13, wherein,
when the position offset detection method is executed, the obtaining warp information of the wafer includes:
obtaining warp information of a plurality of position points in the wafer, wherein the position points are distributed at circumferential and/or radial intervals of the wafer, and each position point is associated with one target alignment mark;
when the position offset detection method is executed, acquiring the base line positions of the target alignment marks associated with the plurality of position points; and obtaining the position offset of the target alignment mark associated with the position point based on the warp information of each position point and the baseline position of the target alignment mark associated with the position point.
CN202311627041.9A 2023-11-29 2023-11-29 Method for detecting position offset of alignment mark and method for processing semiconductor Pending CN117406563A (en)

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