CN117395533A

CN117395533A - Pixel array, control method thereof and image sensor

Info

Publication number: CN117395533A
Application number: CN202210753430.5A
Authority: CN
Inventors: 郭同辉; 石文杰; 邵泽旭
Original assignee: SmartSens Technology Shanghai Co Ltd
Current assignee: SmartSens Technology Shanghai Co Ltd
Priority date: 2022-06-29
Filing date: 2022-06-29
Publication date: 2024-01-12

Abstract

In the pixel array, a first photosensitive module and a second photosensitive module both comprise photosensitive elements and transmission transistors, the transmission transistors of the first photosensitive module and the transmission transistor of the second photosensitive module are arranged oppositely, and a source follower transistor is positioned between the transmission transistor of the first photosensitive module and the transmission transistor of the second photosensitive module, so that the quantity of parasitic capacitance can be effectively reduced compared with the quantity of transistors of other pixel sharing structures; the floating diffusion active region comprises a first floating diffusion active region and a second floating diffusion active region which are connected with each other, and the first floating diffusion active region and the second floating diffusion active region are respectively positioned at two sides of the source follower transistor, so that parasitic capacitance between the floating diffusion active region and a metal connecting wire of the grid electrode of the source follower transistor is reduced. Therefore, interference of conversion gain of pixels of the image sensor is reduced, signal noise is effectively reduced, and image quality acquired by the image sensor is improved.

Description

Pixel array, control method thereof and image sensor

Technical Field

The application relates to the technical field of image sensors, in particular to a pixel array, a control method thereof and an image sensor.

Background

Image sensors have been widely used in digital cameras, mobile phones, medical devices, automobiles, and other applications. Particularly, the rapid development of CMOS (complementary metal oxide semiconductor) image sensor technology makes people have higher demands on the output image quality of the image sensor.

The image sensor comprises a photosensitive pixel array, and the photosensitive pixel array is used for collecting image array optical signal information so as to be converted into image array electric signal data for terminal use. In an image sensor pixel array, the layout of transistor devices may be different between pixels, for example, pixels laid out in a sharing structure manner, including a plurality of pixel sharing structures, the purpose of which is to reduce the number of transistors in the pixels, so as to increase the area occupation ratio of photodiodes in the pixels, and further improve the photosensitive efficiency of the pixels.

Since the conversion gain of an image sensor pixel is inversely related to the parasitic capacitance of the floating diffusion active region. In a multi-pixel sharing structure, the magnitude of the parasitic capacitance is generally determined by two aspects: one is from the parasitic capacitance present between the pixel transistor and the floating diffusion active region, and the other is from the parasitic capacitance between the floating diffusion active region and the metal wiring inside the pixel array. In the existing multi-pixel sharing structure, larger parasitic capacitances exist between the pixel transistor and the floating diffusion active region, and between the floating diffusion active region and the metal wiring inside the pixel array, so that the conversion gain of the pixel of the image sensor is affected.

Disclosure of Invention

In order to overcome at least the above-mentioned shortcomings in the prior art, an object of the present application is to provide a pixel array, a control method thereof, and an image sensor.

In a first aspect, an embodiment of the present application provides a pixel array, where the pixel array includes a plurality of shared pixel units arranged in an array along a row direction or a column direction, and any one of the shared pixel units includes two photosensitive modules, a reset module, a source follower transistor, and a floating diffusion active region, where:

the two photosensitive modules comprise a first photosensitive module and a second photosensitive module, the first photosensitive module and the second photosensitive module both comprise photosensitive elements and transmission transistors positioned at corners of the photosensitive elements, the transmission transistors of the first photosensitive module and the transmission transistors of the second photosensitive module are arranged oppositely, and the first photosensitive module and the second photosensitive module are both used for converting external optical signals into electric signals;

the first floating diffusion active region and the second floating diffusion active region are connected with each other, the first light sensing module and the second light sensing module are respectively connected with the gate end of the source follower transistor through the first floating diffusion active region and the second floating diffusion active region, and the first floating diffusion active region and the second floating diffusion active region are respectively positioned at two sides of the source follower transistor in the row direction or the column direction;

The source follower transistor is positioned between the transmission transistor of the first photosensitive module and the transmission transistor of the second photosensitive module and is used for amplifying and outputting an electric signal entering the floating diffusion active region from the photosensitive element;

the reset module is connected to one side of the source follower transistor in the row direction or the column direction and is arranged close to the photosensitive module, and is used for resetting the voltage of the floating diffusion active region according to a reset control signal.

In one possible implementation, the reset module includes a reset transistor, wherein: the drain terminal of the reset transistor is simultaneously connected with the first floating diffusion active region and the second floating diffusion active region and is connected with the gate terminal of the source follower transistor, the source terminal of the reset transistor is connected with a power supply voltage signal, and the control terminal of the reset transistor is connected with the reset control signal.

In one possible implementation manner, the pixel array includes a plurality of first metal wire groups, where the first metal wire groups correspond to a plurality of the shared pixel units in any row direction, and the first metal wire groups include first metal wires, second metal wires, and third metal wires that are parallel to each other along the row direction, and in any of the shared pixel units: the first metal wire is connected with the control end of the transmission transistor of the first photosensitive module and is used for providing a transmission control signal for the transmission transistor of the first photosensitive module; the second metal wire is connected with the control end of the reset transistor and is used for providing a reset control signal for the reset transistor; the third metal wire is connected with the control end of the transmission transistor of the second photosensitive module and is used for providing a transmission control signal for the transmission transistor of the second photosensitive module.

In one possible implementation, the first metal trace and/or the third metal trace is located on a side of the photosensitive element remote from the transfer transistor.

In one possible implementation manner, the pixel array includes a plurality of second metal wire groups, where the second metal wire groups correspond to a plurality of the shared pixel units in any column direction, and the second metal wire groups include a fourth metal wire, a fifth metal wire, and a sixth metal wire that are parallel to each other along the column direction, and in any of the shared pixel units: the fourth metal wire is connected with the drain end of the source following transistor and is used for providing a power supply voltage signal for the source following transistor; the fifth metal wire is connected with the source end of the source following transistor and is used for transmitting the electric signal amplified and output by the source following transistor; the sixth metal wire is connected with the drain end of the reset transistor and is used for providing a power supply voltage signal for the reset transistor.

In one possible implementation, in the pixel array, the reset module is connected to one side of the source follower transistor in the column direction and is disposed near the photosensitive module.

In one possible implementation, the fourth metal trace and the sixth metal trace share the same metal trace.

In one possible implementation, the fifth metal wire is located at a side of the second photosensitive module close to the first photosensitive module, and is disposed close to the fourth metal wire.

In one possible implementation, the fifth metal trace is located on a side of the second photosensitive module away from the first photosensitive module.

In one possible implementation manner, the shared pixel unit further includes a selection transistor disposed on one side of the row direction or the column direction of the source follower transistor, and a center line of the selection transistor and the source follower transistor is perpendicular to a center line of the reset module and the source follower transistor; the drain of the selection transistor is connected with the source of the source following transistor and is used for addressing and reading signals transmitted by the shared pixel units.

In a possible implementation manner, the first metal wire group further includes a seventh metal wire, and the seventh metal wire is located between the second metal wire and the third metal wire and is connected to the control end of the selection transistor, so as to provide a selection control signal for the selection transistor.

In one possible implementation manner, the row where the first photosensitive module in the shared pixel unit is located is denoted as an mth row, and the first metal wire is respectively connected to a control end of a transfer transistor of the first photosensitive module of the mth row shared pixel unit along the column direction and a control end of a transfer transistor of the second photosensitive module of the mth-1 row shared pixel unit along the column direction, where m is a positive integer greater than 1.

In one possible implementation manner, the row where the first photosensitive module in the shared pixel unit is located is denoted as an mth row, and the third metal wire is connected to the control end of the transfer transistor of the second photosensitive module of the mth row in the column direction and the control end of the transfer transistor of the first photosensitive module of the m+1th row in the column direction, where m is a positive integer greater than or equal to 1.

In one possible implementation manner, two adjacent shared pixel units are stacked in a staggered manner along a row direction, and the first photosensitive modules of the two adjacent shared pixel units are located in the same row.

In one possible implementation, in the shared pixel unit, the second photosensitive module is located at an angle of 120 ° to 140 ° in a clockwise direction of the first photosensitive module.

In a second aspect, an embodiment of the present application further provides a method for controlling a pixel array, where image information is collected for each row of pixels in a unit frame timing sequence of the pixel array by adopting a rolling exposure manner, and a row of a first photosensitive module in the shared pixel unit is denoted as an mth row, where the method includes:

conducting second metal wires corresponding to the m-th row sharing pixel units and second metal wires corresponding to the m-1 th row sharing pixel units, and respectively carrying out first resetting operation on the photosensitive elements of the first photosensitive modules in the m-th row sharing pixel units and the photosensitive elements of the second photosensitive modules in the m-1 th row sharing pixel units through sixth metal wires corresponding to the m-th row sharing pixel units and sixth metal wires corresponding to the m-1 th row sharing pixel units so as to remove charges in the photosensitive elements of the first photosensitive modules in the m-th row sharing pixel units and the photosensitive elements of the second photosensitive modules in the m-1 th row sharing pixel units; conducting a first metal wiring corresponding to the m-th row sharing pixel unit, and exposing a photosensitive element of a second photosensitive module in the m-1-th row sharing pixel unit and a photosensitive element of a first photosensitive module in the m-th row sharing pixel unit respectively; conducting a second metal wire corresponding to the m-th row sharing pixel unit and a second metal wire corresponding to the m+1-th row sharing pixel unit, and respectively carrying out a first resetting operation on a photosensitive element of a second photosensitive module in the m-th row sharing pixel unit and a photosensitive element of a first photosensitive module in the m+1-th row sharing pixel unit through a sixth metal wire corresponding to the m-th row sharing pixel unit and a sixth metal wire corresponding to the m+1-th row sharing pixel unit so as to clear charges in the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit and the photosensitive element of the first photosensitive module in the m+1-th row sharing pixel unit; conducting a third metal wire corresponding to the m-th row sharing pixel unit, and exposing the photosensitive elements of the second photosensitive module in the m-th row sharing pixel unit and the first photosensitive module in the m+1th row sharing pixel unit; conducting a second metal wire corresponding to the m-th row sharing pixel unit and a second metal wire corresponding to the m-1 th row sharing pixel unit, and respectively carrying out a second reset operation on a photosensitive element of a first photosensitive module in the m-th row sharing pixel unit and a photosensitive element of a second photosensitive module in the m-1 th row sharing pixel unit through a sixth metal wire corresponding to the m-th row sharing pixel unit and a sixth metal wire corresponding to the m-1 th row sharing pixel unit so as to clear charges in a first floating diffusion active region and a second floating diffusion active region in the m-th row sharing pixel unit and charges in a first floating diffusion active region and a second floating diffusion active region in the m-1 th row sharing pixel unit; reading reset signals of the photosensitive element of the first photosensitive module in the m-th row sharing pixel unit and the photosensitive element of the second photosensitive module in the m-1 th row sharing pixel unit; ending exposure to the photosensitive element of the first photosensitive module in the m-th row sharing pixel unit and the photosensitive element of the second photosensitive module in the m-1-th row sharing pixel unit, and transferring the charge in the photosensitive element of the first photosensitive module in the m-th row sharing pixel unit and the charge in the photosensitive element of the second photosensitive module in the m-1-th row sharing pixel unit to the first floating diffusion active area and the second floating diffusion active area respectively corresponding to the m-th row sharing pixel unit and the m-1-th row sharing pixel unit respectively; reading initial photoelectric signals of a photosensitive element of a first photosensitive module in the m-th row sharing pixel unit and a photosensitive element of a second photosensitive module in the m-1 th row sharing pixel unit; conducting a second metal wire corresponding to the m-th row sharing pixel unit and a second metal wire corresponding to the m+1-th row sharing pixel unit, and respectively carrying out a second reset operation on a photosensitive element of a second photosensitive module in the m-th row sharing pixel unit and a photosensitive element of a first photosensitive module in the m+1-th row sharing pixel unit through a sixth metal wire corresponding to the m-th row sharing pixel unit and a sixth metal wire corresponding to the m+1-th row sharing pixel unit so as to clear charges in a first floating diffusion active region and charges in a second floating diffusion active region in the m-th row sharing pixel unit and charges in a first floating diffusion active region and a second floating diffusion active region in the m+1-th row sharing pixel unit; reading reset signals of the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit and the photosensitive element of the first photosensitive module in the m+1th row sharing pixel unit; ending exposure to the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit and the photosensitive element of the first photosensitive module in the m+1th row sharing pixel unit, and transferring the charge in the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit and the charge in the photosensitive element of the first photosensitive module in the m+1th row sharing pixel unit to the first floating diffusion active area and the second floating diffusion active area respectively corresponding to the m-th row sharing pixel unit and the m+1th row sharing pixel unit respectively; and reading initial photoelectric signals of the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit and the photosensitive element of the first photosensitive module in the m+1th row sharing pixel unit.

In a third aspect, an embodiment of the present application further provides another method for controlling a pixel array, where image information is collected for each row of pixels in a unit frame timing sequence of the pixel array by adopting a rolling exposure manner, and a row of a first photosensitive module in the shared pixel unit is denoted as an mth row, where the control method includes: turning on a second metal wire corresponding to an mth row of shared pixel units, and performing a first resetting operation on a photosensitive element of a first photosensitive module in the mth row of shared pixel units through a sixth metal wire corresponding to the mth row of shared pixel units so as to remove charges in the photosensitive element of the first photosensitive module in the mth row of shared pixel units; conducting a first metal wire corresponding to the m-th row sharing pixel unit, and exposing a photosensitive element of a first photosensitive module in the m-th row sharing pixel unit; conducting a second metal wire corresponding to the m-th row sharing pixel unit, and performing a first resetting operation on a photosensitive element of a second photosensitive module in the m-th row sharing pixel unit through a sixth metal wire corresponding to the m-th row sharing pixel unit so as to remove charges in the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit; conducting a third metal wire corresponding to the m-th row sharing pixel unit, and exposing a photosensitive element of a second photosensitive module in the m-th row sharing pixel unit; conducting a second metal wire corresponding to the m-th row sharing pixel unit, and performing a second resetting operation on a photosensitive element of a first photosensitive module in the m-th row sharing pixel unit through a sixth metal wire corresponding to the m-th row sharing pixel unit so as to remove charges in a first floating diffusion active region and charges in a second floating diffusion active region in the m-th row sharing pixel unit; reading a reset signal of a photosensitive element of a first photosensitive module in the m-th row shared pixel unit; ending exposure of the photosensitive element of the first photosensitive module in the m-th row sharing pixel unit, and transferring charges in the photosensitive element of the first photosensitive module in the m-th row sharing pixel unit to the first floating diffusion active area corresponding to the m-th row sharing pixel unit; reading an initial photoelectric signal of a photosensitive element of a first photosensitive module in the m-th row shared pixel unit; conducting a second metal wire corresponding to the m-th row sharing pixel unit, and performing a second resetting operation on a photosensitive element of a second photosensitive module in the m-th row sharing pixel unit through a sixth metal wire corresponding to the m-th row sharing pixel unit so as to remove charges in a first floating diffusion active region and charges in a second floating diffusion active region in the m-th row sharing pixel unit; reading a reset signal of a photosensitive element of a second photosensitive module in the m-th row shared pixel unit; ending exposure of the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit, and transferring charges in the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit to the second floating diffusion active area corresponding to the m-th row sharing pixel unit; and reading an initial photoelectric signal of a photosensitive element of a second photosensitive module in the m-th row sharing pixel unit.

In one possible implementation manner, the control method further includes: and turning on a seventh metal wiring corresponding to the m-th row of shared pixel units to turn on a selection transistor, wherein the selection transistor addresses and reads signals transmitted by the shared pixel units and outputs the signals through the fifth metal wiring.

In a possible implementation manner, all the photosensitive modules in the mth row are denoted as mth row pixels, where an expression of the photoelectric signal collected by the mth row pixels is: sig < m, y > = R < m, y > -S < m, y >, wherein Sig < m, y > is a photoelectric signal collected by the pixels in the m-th row, R < m, y > is a reset signal read out from the pixels in the m-th row, S < m, y > is an initial photoelectric signal read out from the pixels in the m-th row, and y is a column position where the pixels are located; the expression of the photoelectric signals collected by the m+1th row pixels is as follows: sig < m+1, y > = R < m+1, y > -S < m+1, y >, wherein Sig < m+1, y > is a photoelectric signal collected by the pixel in the m-th row, R < m+1, y > is a reset signal read out from the pixel in the m-th row, S < m+1, y > is an initial photoelectric signal read out from the pixel in the m-th row, and y is a column position where the pixel is located.

In a fourth aspect, embodiments of the present application further provide an image sensor, where the image sensor includes the foregoing pixel array.

Based on any one of the above aspects, the pixel array, the control method thereof and the image sensor provided by the embodiments of the present application have the beneficial effects that: on the one hand, the first photosensitive module and the second photosensitive module comprise photosensitive elements and transmission transistors, the transmission transistors of the first photosensitive module and the second photosensitive module are arranged oppositely, and the source follower transistor is positioned between the transmission transistor of the first photosensitive module and the transmission transistor of the second photosensitive module, so that the quantity of parasitic capacitance can be effectively reduced compared with the quantity of transistors of other pixel sharing structures; on the other hand, the floating diffusion active region comprises a first floating diffusion active region and a second floating diffusion active region which are connected with each other, the first floating diffusion active region and the second floating diffusion active region are respectively positioned at two sides of the source follower transistor, the metal connecting wire of the floating diffusion active region and the grid electrode of the source follower transistor is shorter, and parasitic capacitance between the floating diffusion active region and the metal connecting wire of the grid electrode of the source follower transistor can be reduced. Therefore, interference of conversion gain of pixels of the image sensor is reduced, signal noise is effectively reduced, and image quality acquired by the image sensor is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following description will briefly explain the drawings required for the embodiments, it being understood that the following drawings illustrate only some embodiments of the present application and are therefore not to be considered limiting of the scope, and that other related drawings may be obtained according to these drawings without the inventive effort of a person skilled in the art.

Fig. 1 is a schematic circuit diagram of a shared pixel unit in a pixel array provided in the present application;

fig. 2 is a schematic diagram of a shared pixel unit in a pixel array according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a pixel array according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of a shared pixel unit in a pixel array according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of a pixel array according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a shared pixel unit in a pixel array according to an embodiment of the present disclosure;

fig. 7 is a schematic diagram of a pixel array according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a shared pixel unit in a pixel array according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram of a pixel array according to an embodiment of the present disclosure;

Fig. 10 is a schematic diagram of a control method of a pixel array according to an embodiment of the present application;

fig. 11 is a schematic diagram of a control method of a pixel array according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it should be understood that the accompanying drawings in the present application are only for the purpose of illustration and description, and are not intended to limit the protection scope of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. A flowchart, as used in this application, illustrates operations implemented according to some embodiments of the present application. It should be understood that the operations of the flow diagrams may be implemented out of order and that steps without logical context may be performed in reverse order or concurrently. Moreover, one or more other operations may be added to the flow diagrams and one or more operations may be removed from the flow diagrams as directed by those skilled in the art.

As mentioned in the background art, in order to solve the technical problem that in the multi-pixel sharing structure in the prior art, larger parasitic capacitance exists between the pixel transistor and the floating diffusion active region and between the floating diffusion active region and the metal wiring inside the pixel array, so as to affect the conversion gain of the pixel of the image sensor, the application provides a pixel array. The pixel array is specifically explained and described below:

Fig. 1 is a schematic circuit diagram of a shared pixel unit in a pixel array provided in the present application, referring to fig. 1, the pixel array includes a plurality of shared pixel units arranged in an array along a row direction or a column direction, any one of the shared pixel units includes two photosensitive modules, a reset module, a source follower transistor, and a floating diffusion active region, wherein:

the two photosensitive modules comprise a first photosensitive module and a second photosensitive module, the first photosensitive module and the second photosensitive module both comprise photosensitive elements and transmission transistors positioned at corners of the photosensitive elements, the transmission transistors of the first photosensitive module and the transmission transistors of the second photosensitive module are oppositely arranged, and the first photosensitive module and the second photosensitive module are both used for converting external light signals into electric signals.

The first photosensitive module includes a photosensitive element 101 and a transfer transistor 103, and the second photosensitive module includes a photosensitive element 102 and a transfer transistor 104. In this application, the photosensitive element 101 is connected to the first end of the transmission transistor 103, the photosensitive element 102 is connected to the first end of the transmission transistor 104, and in terms of layout, the transmission transistor 103 is opposite to the transmission transistor 104, but in terms of circuit connection, the transmission transistor 103 and the transmission transistor 104 respectively receive corresponding transmission signals through the gates thereof, so that the electric signals received and converted by the photosensitive element 101 and the photosensitive element 102 are respectively led into the inside of the pixel and read out.

The first floating diffusion active region and the second floating diffusion active region are connected with the gate end of the source follower transistor respectively through the first floating diffusion active region and the second floating diffusion active region, and the first floating diffusion active region and the second floating diffusion active region are respectively positioned at two sides of the source follower transistor in the row direction or the column direction.

The floating diffusion active region FD may be divided into two parts, namely, a first floating diffusion active region and a second floating diffusion active region, and the first photosensitive module and the second photosensitive module are connected to the gate terminal of the source follower transistor 106 through the first floating diffusion active region and the second floating diffusion active region, respectively, in other words, the photosensitive element 101 and the photosensitive element 102 are connected to the first floating diffusion active region and the second floating diffusion active region through the transfer transistor 103 and the transfer transistor 104, respectively, that is, the second terminal of the transfer transistor 103 and the second terminal of the transfer transistor 104 are connected to the first floating diffusion active region and the second floating diffusion active region, respectively, so that the electric signals received and converted by the photosensitive element 101 and the photosensitive element 102 are led to the gate terminal of the source follower transistor 106. In terms of layout design, the first floating diffusion active region and the second floating diffusion active region are located on both sides of the source follower transistor 106 in the row direction or the column direction, i.e., in the horizontal direction and the vertical direction in the plane, respectively.

The source follower transistor is located between the transfer transistor of the first photosensitive module and the transfer transistor of the second photosensitive module for amplifying an electric signal output from the photosensitive element into the floating diffusion active region.

In terms of layout design, the source follower transistor 106 is located between the transfer transistor 103 and the transfer transistor 104; however, in the circuit connection, the first terminal of the source follower transistor 106, that is, the drain is connected to the power voltage signal VDD, the gate terminal of the source follower transistor 106 is connected to the second terminals of the pass transistor 103 and the pass transistor 104 through the first floating diffusion active region and the second floating diffusion active region, respectively, the source follower transistor 106 is typically used for amplifying and outputting the electric signal from the photosensitive element into the floating diffusion active region, and the output source is typically the first terminal of the source follower transistor 106, that is, the source is located; in some embodiments, a selection transistor 107 for addressing and reading signals transmitted by the photosensitive elements 101 and 102 may also be connected to the source, i.e., the second end, of the source follower transistor 106, and the selection transistor 107 is typically disposed on one side of the source follower transistor 106 in the row direction or the column direction, i.e., the horizontal direction or the vertical direction in the plane.

The reset module is connected to the source follower transistor 106 in a row direction or a column direction, that is, in one side in a horizontal direction or a vertical direction in a plane, and is disposed close to the first photosensitive module or the second photosensitive module, specifically, the reset module is disposed close to the first photosensitive element 101 or the second photosensitive element 102, and is configured to reset the voltage of the floating diffusion active region according to the reset control signal.

The reset module includes a reset transistor 105, a first end, i.e. a drain, of the reset transistor 105 is connected to the first floating diffusion active region and the second floating diffusion active region and is connected to a gate of the source follower transistor 106, a second end, i.e. a source, of the reset transistor 105 is connected to the power supply voltage signal VDD, and a control end, i.e. a gate, of the reset transistor 105 is connected to the reset control signal.

On the one hand, the first photosensitive module comprises a photosensitive element 101 and a transmission transistor 103, the second photosensitive module comprises a photosensitive element 102 and a transmission transistor 104, the transmission transistor 103 and the transmission transistor 104 are oppositely arranged, and a source follower transistor 106 is positioned between the transmission transistor 103 and the transmission transistor 104, so that compared with the transistors of other pixel sharing structures, the number of the transistors is smaller, for example, at least three photosensitive modules are needed in a three-pixel sharing structure, at least four photosensitive modules are needed in a four-pixel sharing structure, at least six photosensitive modules and two source follower transistors are needed in a six-pixel sharing structure, and so on, the number of parasitic capacitances can be effectively reduced by reducing the number of the transistors; on the other hand, the floating diffusion active region FD includes a first floating diffusion active region and a second floating diffusion active region which are connected with each other, and the first floating diffusion active region and the second floating diffusion active region are respectively located at two sides of the source follower transistor 106, and the metal connecting line between the floating diffusion active region FD and the gate of the source follower transistor 106 is shorter, so that parasitic capacitance between the floating diffusion active region FD and the metal connecting line of the gate of the source follower transistor 106 can be reduced. Therefore, interference of conversion gain of pixels of the image sensor is reduced, signal noise is effectively reduced, and image quality acquired by the image sensor is improved.

Optionally, in the shared pixel unit, the second photosensitive module is located at an angle of 120 ° to 140 ° in a clockwise direction of the first photosensitive module.

Further, the pixel array includes a plurality of first metal wire groups, the first metal wire groups correspond to a plurality of shared pixel units in any row direction, the first metal wire groups include first metal wires TX1, second metal wires RST and third metal wires TX2 which are parallel to each other along the row direction, and in any shared pixel unit: the first metal wire TX1 is connected to the control terminal of the transmission transistor 103, and the transmission transistor 103 provides a transmission control signal; the second metal wire RST is connected to the control end of the reset transistor 105 and is used for providing a reset control signal for the reset transistor 105; the third metal trace TX2 is connected to the control terminal of the pass transistor 104, and is used for providing a pass control signal to the pass transistor 104. The pixel array comprises a plurality of second metal wire groups, the second metal wire groups correspond to a plurality of shared pixel units in any column direction, the second metal wire groups comprise fourth metal wires VDD, fifth metal wires S1& S2 and sixth metal wires VDD which are mutually parallel along the column direction, and the second metal wire groups are arranged in any shared pixel unit: the fourth metal wire VDD is connected to the drain terminal of the source follower transistor 106 and is used for providing a power voltage signal for the source follower transistor 106; fifth metal wirings S1& S2 are connected to the source terminal of source follower transistor 106, and are used for transmitting the electric signal amplified and output by source follower transistor 106; the sixth metal wiring VDD is connected to the drain terminal of the reset transistor 105, and is used for providing a power voltage signal to the reset transistor 105.

In the scheme that the source terminal of the source follower transistor 106 is connected to the select transistor 107, since the control terminal of the select transistor 107 needs to be addressed and output by a separate select signal, the pixel array provided in this application further includes a seventh metal trace RS, where the seventh metal trace RS is located between the second metal trace RST and the third metal trace TX2 and the seventh metal trace RS is connected to the control terminal of the select transistor 107, for providing the select control signal to the select transistor 107. For illustrations and detailed descriptions of the first and second metal trace sets, reference is also made to various embodiments of pixel arrays and corresponding figures referred to hereinafter with respect to this application.

Example 1

As shown in fig. 2 and 3, the pixel array includes a plurality of shared pixel units, any one of the shared pixel units includes a first photosensitive module, a second photosensitive module, a reset module, a source follower transistor, and a floating diffusion active region, wherein:

the first photosensitive module includes a photosensitive element 101 and a transfer transistor 103, and the second photosensitive module includes a photosensitive element 102 and a transfer transistor 104. It is understood that the photosensitive element mentioned in the present application may be any one of a photodiode, a grating or a photoconductor, and as a preferred embodiment, the photosensitive element is a photodiode. As shown in fig. 2, the transfer transistor 103 is disposed opposite to the transfer transistor 104, and the transfer transistor 103 and the transfer transistor 104 respectively receive corresponding transfer signals through gates thereof to respectively guide the electric signals received and converted by the photosensitive element 101 and the photosensitive element 102 into the inside of the pixel and read out.

The floating diffusion active region FD may be divided into two parts, namely a first floating diffusion active region and a second floating diffusion active region, and the photosensitive element 101 and the photosensitive element 102 are connected with the first floating diffusion active region and the second floating diffusion active region through the transmission transistor 103 and the transmission transistor 104, respectively, so that the electric signals received and converted by the photosensitive element 101 and the photosensitive element 102 are led to the gate terminal of the source follower transistor 106. The first floating diffusion active region and the second floating diffusion active region are located on both sides of the source follower transistor 106, respectively, in the row direction, i.e., in the horizontal direction in the plane.

The source follower transistor 106 is located between the transfer transistor 103 and the transfer transistor 104, which corresponds to the same plane in which the region where the photosensitive element 101 is located is a row region and the region where the photosensitive element 102 is located is a column region, the photosensitive element 101 being at the upper left corner of the source follower transistor 106 and the photosensitive element 102 being at the lower right corner of the source follower transistor 106.

The reset module is connected to a side of the source follower transistor 106, which is close to the second photosensitive element 102 in the row direction, and specifically, the reset module is arranged close to the second photosensitive element 102 in the row direction of the source follower transistor 106.

In this embodiment, within any shared pixel unit: the first metal wire TX1 is connected to the control terminal of the transmission transistor 103, and the transmission transistor 103 provides a transmission control signal; the second metal wire RST is connected to the control end of the reset transistor 105 and is used for providing a reset control signal for the reset transistor 105; the third metal wire TX2 is connected to the control terminal of the pass transistor 104, and is configured to provide a pass control signal for the pass transistor 104; the fourth metal wire VDD is connected to the drain terminal of the source follower transistor 106 and is used for providing a power voltage signal for the source follower transistor 106; fifth metal wirings S1& S2 are connected to the source terminal of source follower transistor 106, and are used for transmitting the electric signal amplified and output by source follower transistor 106; the sixth metal wiring VDD is connected to the drain terminal of the reset transistor 105, and is used for providing a power voltage signal for the reset transistor 105; in this embodiment, the fifth metal wires S1& S2 are located on the side of the second photosensitive module close to the first photosensitive module, specifically, the fifth metal wires S1& S2 are located on the side of the second photosensitive element 102 close to the first photosensitive element 101, and the fifth metal wires S1& S2 are located close to the fourth metal wires VDD, so that the layout of wires inside the shared pixel unit is more compact than the first to third embodiments, and the pixel array is smaller, so that the number of dots per inch (DotsPerInch) of the shared pixel unit is increased.

At least one of the first metal trace TX1 and the third metal trace TX2 is located at a side of the photosensitive element away from the transfer transistor. Referring to fig. 2, the projection of the first metal trace TX1 in the row direction passes through the projection of the transfer transistor 103 in the row direction, and the second metal trace TX2 is located at a side of the photosensitive element 102 away from the transfer transistor 104. Indeed, in some embodiments, the first metal trace TX1 may also be located on a side of the photosensitive element 101 away from the transfer transistor 103, which is configured to address the problem of larger parasitic capacitance caused by overlapping or closer distance between the metal traces and the photosensitive element or the transfer transistor.

As an alternative embodiment, on one side in the column direction of the source follower transistor 106, a selection transistor 107 for addressing and reading out signals transmitted by the photosensitive element 101 and the photosensitive element 102 is connected, and the selection transistor 107 is provided close to the photosensitive element 102, and since the selection transistor 107 is provided on one side in the column direction of the source follower transistor 106, that is, in the vertical direction, in this embodiment, referring to fig. 2 or 3, in the shared pixel unit, the center line of the selection transistor 107 and the source follower transistor 106 is perpendicular to the center line of the reset transistor 105 and the source follower transistor 105.

In the above embodiment, since the control terminal of the selection transistor 107 needs to be addressed and output by a separate selection signal, the pixel array provided in this embodiment may further include a seventh metal trace RS, where the seventh metal trace RS is located between the second metal trace RST and the third metal trace TX2 and the seventh metal trace RS is connected to the selection transistor 107, for providing the selection control signal to the selection transistor 107.

In this embodiment, referring to fig. 3, two adjacent shared pixel units are stacked in a staggered manner along the column direction, and the first photosensitive modules of the two adjacent shared pixel units are located in the same column. In other words, in the column direction, the photosensitive element 101 of the previous shared pixel unit is on one side of the photosensitive element 101 of the next shared pixel unit, the photosensitive element 102 of the previous shared pixel unit is on one side of the photosensitive element 102 of the next shared pixel unit, and the photosensitive element 102 of the previous shared pixel unit is disposed in the same row as the photosensitive element 101 of the next shared pixel unit. Further, as described above, in any one of the shared pixel units, the photosensitive element 101 and the photosensitive element 102 have a connection relationship, and therefore, adjacent two shared pixel units are in a staggered stack state in the column direction.

Further, the first photosensitive module in the shared pixel unit is marked as an mth row, the first metal wiring TX1 is respectively connected with the control end of the transmission transistor 103 of the mth row shared pixel unit along the column direction and the control end of the transmission transistor 104 of the mth-1 row shared pixel unit along the column direction, and m is a positive integer greater than 1; the third metal trace TX2 is connected to the control terminal of the transfer transistor 104 of the m-th row of the shared pixel units in the column direction and the control terminal of the transfer transistor 103 of the m+1th row of the shared pixel units in the column direction, respectively, where m is a positive integer greater than or equal to 1. In other words, the transmission transistor 104 of the former shared pixel unit shares one metal trace with the transmission transistor 103 of the latter shared pixel unit, and it is also understood that this metal trace may be the first metal trace TX1 or the third metal trace TX2, and the sharing of the metal traces avoids that there is redundancy in the metal traces in the pixel array, so that there is a large parasitic capacitance between the overlapping traces due to the close distance between the two traces.

Example two

As shown in fig. 4 and fig. 5, the pixel array includes a plurality of shared pixel units, any one of the shared pixel units includes a first photosensitive module, a second photosensitive module, a reset module, a source follower transistor and a floating diffusion active region, the shared pixel unit structure disclosed in the second embodiment is the same as the shared pixel unit structure disclosed in the first embodiment, and the arrangement sequence of each metal wire in any one of the shared pixel units is the same. The difference is that:

In the present embodiment, in the first metal trace TX1 and the third metal trace TX2, both of the metal traces are located at a side of the photosensitive element away from the transmission transistor. Referring to fig. 4, the first metal trace TX1 is located at a side of the photosensitive element 101 away from the transmission transistor 103, and the second metal trace TX2 is located at a side of the photosensitive element 102 away from the transmission transistor 104. The purpose of this arrangement is to cope with the problem of larger parasitic capacitance due to overlapping of metals or closer distance by increasing the distance between the metal wiring and the photosensitive element or the transfer transistor on the basis of the scheme disclosed in the first embodiment.

In addition, referring to fig. 5, two adjacent shared pixel units are stacked in a staggered manner along the row direction, and the first photosensitive modules of the two adjacent shared pixel units are located in the same row. In other words, in the row direction, the photosensitive element 101 of the previous shared pixel unit is on one side of the photosensitive element 101 of the next shared pixel unit, the photosensitive element 102 of the previous shared pixel unit is on one side of the photosensitive element 102 of the next shared pixel unit, and the photosensitive element 102 of the previous shared pixel unit is arranged in the same column as the photosensitive element 101 of the next shared pixel unit. Further, as described above, in any one of the shared pixel units, the photosensitive element 101 and the photosensitive element 102 have a connection relationship, and therefore, in the row direction, two adjacent shared pixel units are in a staggered stack state.

In addition, since the first photosensitive modules of all the shared pixel units are located in the same row and the second photosensitive modules of all the shared pixel units are located in the same row in the row direction, any first metal wire TX1 has a connection relationship with the transmission transistors 103 of all the shared pixel units of the corresponding row, any third metal wire TX2 has a connection relationship with the transmission transistors 104 of all the shared pixel units of the corresponding row, the problem of sharing the metal wires of the photosensitive modules of different rows is solved, and the design that one metal wire is adopted for the photosensitive modules of the same row is still maintained, so that the increase of parasitic capacitance between the metal wires can be avoided on the premise of arranging the shared pixel units in the row direction.

Example III

As shown in fig. 6 and 7, the pixel array includes a plurality of shared pixel units, any one of the shared pixel units includes a first photosensitive module and a second photosensitive module, a reset module, a source follower transistor and a floating diffusion active region, wherein:

as in the previous embodiment, the first photosensitive module includes the photosensitive element 101 and the transfer transistor 103, and the second photosensitive module includes the photosensitive element 102 and the transfer transistor 104. It is understood that the photosensitive element mentioned in the present application may be any one of a photodiode, a grating or a photoconductor, and as a preferred embodiment, the photosensitive element is a photodiode. As shown in fig. 6, the transfer transistor 103 is disposed opposite to the transfer transistor 104, and the transfer transistor 103 and the transfer transistor 104 respectively receive corresponding transfer signals through gates thereof to respectively guide the electric signals received and converted by the photosensitive element 101 and the photosensitive element 102 into the inside of the pixel and read out.

The floating diffusion active region FD may be divided into two parts, namely a first floating diffusion active region and a second floating diffusion active region, and the photosensitive element 101 and the photosensitive element 102 are connected with the first floating diffusion active region and the second floating diffusion active region through the transmission transistor 103 and the transmission transistor 104, respectively, so that the electric signals received and converted by the photosensitive element 101 and the photosensitive element 102 are led to the gate terminal of the source follower transistor 106. The first floating diffusion active region and the second floating diffusion active region are located on both sides of the source follower transistor 106, respectively, in the column direction, i.e., in the vertical direction in the plane.

The reset module is connected to one side of the source follower transistor 106 in the column direction near the first photosensitive element 101, and specifically, the reset module is arranged in the row direction of the source follower transistor 106 near the first photosensitive element 101.

In this embodiment, within any shared pixel unit: the first metal wire TX1 is connected to the control terminal of the transmission transistor 103, and the transmission transistor 103 provides a transmission control signal; the second metal wire RST is connected to the control end of the reset transistor 105 and is used for providing a reset control signal for the reset transistor 105; the third metal wire TX2 is connected to the control terminal of the pass transistor 104, and is configured to provide a pass control signal for the pass transistor 104; the fourth metal wire VDD is connected to the drain terminal of the source follower transistor 106 and is used for providing a power voltage signal for the source follower transistor 106; fifth metal wirings S1& S2 are connected to the source terminal of source follower transistor 106, and are used for transmitting the electric signal amplified and output by source follower transistor 106; the sixth metal wiring VDD is connected to the drain terminal of the reset transistor 105, and is used for providing a power voltage signal to the reset transistor 105.

In this embodiment, the fourth metal wire VDD and the sixth metal wire VDD share the same metal wire, as shown in fig. 6, since the reset transistor 105 and the source follower transistor 106 are arranged in the column direction, there is enough space for accommodating the vertical metal wires in the vertical region between the first photosensitive module and the second photosensitive module, and at the same time, since the fourth metal wire VDD and the sixth metal wire VDD share the same metal wire, in the pixel array, the actual number of metal wires is less than that disclosed in the first embodiment and the second embodiment, so that the parasitic capacitance existing between the metal wires can be further reduced.

In this embodiment, the fifth metal wires S1& S2 may be located on a side of the second photosensitive module away from the first photosensitive module, specifically on a side of the second photosensitive element 102 away from the second transmission transistor 104, so that parasitic capacitance may exist between the fifth metal wires S1& S2 and the transistors or other vertical metal wires inside the shared pixel unit.

In the present embodiment, in the first metal trace TX1 and the third metal trace TX2, both of the metal traces are located at a side of the photosensitive element away from the transmission transistor. Referring to fig. 5, the first metal trace TX1 is located at a side of the photosensitive element 101 away from the transmission transistor 103, and the second metal trace TX2 is located at a side of the photosensitive element 102 away from the transmission transistor 104. The purpose of this arrangement is to cope with the problem of larger parasitic capacitance due to overlapping of metals or closer distance by increasing the distance between the metal wiring and the photosensitive element or the transfer transistor on the basis of the scheme disclosed in the first embodiment.

As an alternative embodiment, on one side of the row direction of the source follower transistor 106, a select transistor 107 for addressing and reading out signals transmitted by the photosensitive element 101 and the photosensitive element 102 is connected, and since the select transistor 107 is disposed on one side of the row direction of the source follower transistor 106, that is, the horizontal direction, and the select transistor 107 is disposed close to the photosensitive element 102, in this embodiment, referring to fig. 6 or fig. 7, in the shared pixel unit, the center line of the select transistor 107 and the source follower transistor 106 is perpendicular to the center line of the reset transistor 105 and the source follower transistor 105.

In this embodiment, referring to fig. 7, two adjacent shared pixel units are stacked in a staggered manner along the column direction, and the first photosensitive modules of the two adjacent shared pixel units are located in the same column. In other words, in the column direction, the photosensitive element 101 of the previous shared pixel unit is on one side of the photosensitive element 101 of the next shared pixel unit, the photosensitive element 102 of the previous shared pixel unit is on one side of the photosensitive element 102 of the next shared pixel unit, and the photosensitive element 102 of the previous shared pixel unit is disposed in the same row as the photosensitive element 101 of the next shared pixel unit. Further, as described above, in any one of the shared pixel units, the photosensitive element 101 and the photosensitive element 102 have a connection relationship, and therefore, adjacent two shared pixel units are in a staggered stack state in the column direction.

Further, the first photosensitive module in the shared pixel unit is marked as an mth row, the first metal wiring TX1 is respectively connected with the control end of the transmission transistor 103 of the mth row shared pixel unit along the column direction and the control end of the transmission transistor 104 of the mth-1 row shared pixel unit along the column direction, and m is a positive integer greater than 1; the third metal trace TX2 is connected to the control terminal of the transfer transistor 104 of the m-th row of the shared pixel units in the column direction and the control terminal of the transfer transistor 103 of the m+1th row of the shared pixel units in the column direction, respectively, where m is a positive integer greater than or equal to 1. In other words, the transmission transistor 104 of the former shared pixel unit shares a metal wire with the transmission transistor 103 of the latter shared pixel unit, and it is also understood that the metal wire may be the first metal wire TX1 or the third metal wire TX2.

Example IV

As shown in fig. 8 and fig. 9, the pixel array includes a plurality of shared pixel units, any one of the shared pixel units includes a first photosensitive module, a second photosensitive module, a reset module, a source follower transistor, and a floating diffusion active region, the shared pixel unit structure disclosed in the fourth embodiment is the same as the shared pixel unit structure disclosed in the third embodiment, and the arrangement sequence of each metal wire in any one of the shared pixel units is the same. The difference is that:

In this embodiment, referring to fig. 8, the fifth metal traces S1 and S2 are located on one side of the second photosensitive module close to the first photosensitive module and close to the fourth metal trace VDD, so that the layout of the traces in the shared pixel unit is more compact than those in the first to third embodiments, and the pixel array is further reduced in size and increased in number of dots per inch (DotsPerInch) of the shared pixel unit.

In addition, referring to fig. 9, two adjacent shared pixel units are stacked in a staggered manner along the row direction, and the first photosensitive modules of the two adjacent shared pixel units are located in the same row. In other words, in the row direction, the photosensitive element 101 of the previous shared pixel unit is on one side of the photosensitive element 101 of the next shared pixel unit, the photosensitive element 102 of the previous shared pixel unit is on one side of the photosensitive element 102 of the next shared pixel unit, and the photosensitive element 102 of the previous shared pixel unit is arranged in the same column as the photosensitive element 101 of the next shared pixel unit. Further, as described above, in any one of the shared pixel units, the photosensitive element 101 and the photosensitive element 102 have a connection relationship, and therefore, in the row direction, two adjacent shared pixel units are in a staggered stack state.

Example five

In order to solve the technical problem that in the multi-pixel sharing structure in the prior art, larger parasitic capacitance exists between a pixel transistor and a floating diffusion active region and between the floating diffusion active region and a metal wiring inside a pixel array so as to influence the conversion gain of the pixel of the image sensor, based on the pixel array, the embodiment provides a control method of the pixel array.

Referring to fig. 10, as a possible implementation manner, the pixel array in the first embodiment and the third embodiment corresponds to the first embodiment, and the present embodiment discloses a control method of the pixel array, where the control method collects image information of each row of pixels in a rolling exposure (rolling method) manner within a unit frame time sequence of the pixel array, and in general, the unit frame is a frame, and the present embodiment marks a row of a first photosensitive module in a shared pixel unit as an m-th row, and referring to fig. 3 and fig. 7, the control method includes:

Turning on a second metal wire RST < m > corresponding to the m-th row sharing pixel unit and a second metal wire RST < m-1> corresponding to the m-1 th row sharing pixel unit, and respectively performing a first reset operation on the photosensitive element 101 in the m-th row sharing pixel unit and the photosensitive element 102 in the m-1 th row sharing pixel unit through a sixth metal wire VDD corresponding to the m-th row sharing pixel unit and a sixth metal wire VDD corresponding to the m-1 th row sharing pixel unit so as to clear charges in the photosensitive element 101 in the m-th row sharing pixel unit and the photosensitive element 102 in the m-1 th row sharing pixel unit;

turning on a first metal wiring TX1 corresponding to the m-th row of shared pixel units, and exposing the photosensitive element 102 in the m-1-th row of shared pixel units and the photosensitive element 101 in the m-th row of shared pixel units respectively corresponding to TX < m > in fig. 10;

turning on a second metal wire RST < m > corresponding to the mth row sharing pixel unit and a second metal wire RST < m+1> corresponding to the mth+1th row sharing pixel unit, and respectively performing a first reset operation on the photosensitive element 102 in the mth row sharing pixel unit and the photosensitive element 101 in the mth+1th row sharing pixel unit through a sixth metal wire VDD corresponding to the mth row sharing pixel unit and a sixth metal wire VDD corresponding to the mth+1th row sharing pixel unit so as to remove charges in the photosensitive element 102 in the mth row sharing pixel unit and the photosensitive element 101 in the mth+1th row sharing pixel unit;

Turning on a third metal wire TX2 corresponding to the m-th row sharing pixel unit, exposing a photosensitive element 102 in the m-th row sharing pixel unit and a photosensitive element 101 in the m+1-th row sharing pixel unit corresponding to TX < m+1> in FIG. 10;

conducting a second metal wire RST < m > corresponding to the m-th row sharing pixel unit and a second metal wire RST < m-1> corresponding to the m-1 th row sharing pixel unit, and respectively carrying out a second reset operation on the photosensitive element 101 in the m-th row sharing pixel unit and the photosensitive element 102 of the m-1 th row sharing pixel unit through a sixth metal wire VDD corresponding to the m-th row sharing pixel unit and a sixth metal wire VDD corresponding to the m-1 th row sharing pixel unit so as to clear charges in the first floating diffusion active region and the second floating diffusion active region in the m-th row sharing pixel unit and charges in the first floating diffusion active region and the second floating diffusion active region in the m-1 th row sharing pixel unit;

reading reset signals of the photosensitive element 101 in the m-th row sharing pixel unit and the photosensitive element 102 in the m-1 th row sharing pixel unit;

ending exposure to the photosensitive element 101 in the m-th row sharing pixel unit and the photosensitive element 102 in the m-1 th row sharing pixel unit, and transferring the charges in the photosensitive element 101 in the m-th row sharing pixel unit and the charges in the photosensitive element 102 in the m-1 th row sharing pixel unit to a first floating diffusion active region and a second floating diffusion active region respectively corresponding to the m-th row sharing pixel unit and the m-1 th row sharing pixel unit respectively;

Reading initial photoelectric signals of the photosensitive element 101 in the m-th row sharing pixel unit and the photosensitive element 102 in the m-1 th row sharing pixel unit;

conducting a second metal wire RST < m > corresponding to the m-th row sharing pixel unit and a second metal wire RST < m+1> corresponding to the m+1-th row sharing pixel unit, and respectively carrying out a second reset operation on the photosensitive element 102 in the m-th row sharing pixel unit and the photosensitive element 102 in the m+1-th row sharing pixel unit through a sixth metal wire VDD corresponding to the m-th row sharing pixel unit and a sixth metal wire VDD corresponding to the m+1-th row sharing pixel unit so as to clear charges in the first floating diffusion active region and the second floating diffusion active region in the m-th row sharing pixel unit and charges in the first floating diffusion active region and the second floating diffusion active region in the m+1-th row sharing pixel unit;

reading reset signals of the photosensitive element 102 in the m-th row sharing pixel unit and the photosensitive element 101 in the m+1th row sharing pixel unit;

ending exposure of the photosensitive element 102 in the m-th row sharing pixel unit and the photosensitive element 101 in the m+1-th row sharing pixel unit, and transferring the charges in the photosensitive element 102 in the m-th row sharing pixel unit and the charges in the photosensitive element 101 in the m+1-th row sharing pixel unit to a first floating diffusion active region and a second floating diffusion active region respectively corresponding to the m-th row sharing pixel unit and the m+1-th row sharing pixel unit respectively;

The initial photoelectric signals of the photosensitive element 102 in the m-th row sharing pixel unit and the photosensitive element 101 in the m+1th row sharing pixel unit are read.

Referring to fig. 11, as a possible implementation manner, corresponding to the second embodiment and the fourth embodiment, the present embodiment further discloses a control method of a pixel array, where the control method collects image information of each row of pixels in a rolling exposure (rolling exposure) manner in a unit frame time sequence of the pixel array, and in general, the unit frame is a frame, the present embodiment marks a row where a first photosensitive module in a shared pixel unit is located as an m-th row, and fig. 5 and 9, where the control method includes:

turning on a second metal wire RST < m > corresponding to the m-th row sharing pixel unit, and performing a first resetting operation on the photosensitive element 101 in the m-th row sharing pixel unit through a sixth metal wire VDD corresponding to the m-th row sharing pixel unit so as to clear charges in the photosensitive element 101 in the m-th row sharing pixel unit;

turning on a first metal wire TX1 corresponding to the m-th row of shared pixel units, exposing the photosensitive element 101 in the m-th row of shared pixel units corresponding to the first metal wire TX < m > in FIG. 11;

turning on a second metal wire RST < m > corresponding to the m-th row sharing pixel unit, and performing a first resetting operation on the photosensitive element 102 in the m-th row sharing pixel unit through a sixth metal wire VDD corresponding to the m-th row sharing pixel unit so as to clear charges in the photosensitive element 102 in the m-th row sharing pixel unit;

Turning on a third metal wire TX2 corresponding to the m-th row of shared pixel units, and exposing the photosensitive element 102 in the m-th row of shared pixel units corresponding to the third metal wire TX < m+1 >;

turning on a second metal wire RST < m > corresponding to the m-th row sharing pixel unit, and performing a second reset operation on the photosensitive element 101 in the m-th row sharing pixel unit through a sixth metal wire VDD corresponding to the m-th row sharing pixel unit so as to clear charges in the first floating diffusion active region and charges in the second floating diffusion active region in the m-th row sharing pixel unit;

reading a reset signal of the photosensitive element 101 in the m-th row sharing pixel unit;

ending the exposure of the photosensitive element 101 in the m-th row sharing pixel unit, and transferring the charge in the photosensitive element 101 in the m-th row sharing pixel unit to the first floating diffusion active region corresponding to the m-th row sharing pixel unit;

reading an initial photoelectric signal of the photosensitive element 101 in the m-th row sharing pixel unit;

turning on a second metal wire RST < m > corresponding to the m-th row sharing pixel unit, and performing a second resetting operation on the photosensitive element 102 in the m-th row sharing pixel unit through a sixth metal wire VDD corresponding to the m-th row sharing pixel unit so as to clear charges in the first floating diffusion active region and charges in the second floating diffusion active region in the m-th row sharing pixel unit;

Reading a reset signal of the photosensitive element 102 in the m-th row sharing pixel unit;

ending the exposure of the photosensitive element 102 in the m-th row sharing pixel unit, and transferring the charges in the photosensitive element 102 in the m-th row sharing pixel unit to a second floating diffusion active region corresponding to the m-th row sharing pixel unit;

the initial photo signal of the photosensitive element 102 in the m-th row of the shared pixel units is read.

In the above embodiment, the manner of reading is to read out the photoelectric signal transmitted and converted by the photosensitive element 101 or the photosensitive element 102 through the source follower transistor 106.

Optionally, in some embodiments, the pixel array may further include a selection transistor 107 connected to one side of the readout direction of the source follower transistor 106, where the metal trace for selecting an output line according to the selection control signal to transmit and derive the photoelectric signal, and providing the selection control signal to the selection transistor 107 is a seventh trace RS, taking the mth row shared pixel unit as an example, and in the first embodiment or the third embodiment, referring to fig. 3 or fig. 7, the metal trace for providing the selection control signal to the selection transistor 107 in the mth row shared pixel unit is RS < m > in the drawing; in the second or fourth embodiment, referring to fig. 5 or 9, the metal wiring for providing the selection control signal to the selection transistor 107 in the m-th row of the shared pixel unit is also RS < m > in the corresponding diagram.

Therefore, in the control method of the pixel array provided in the present embodiment, the seventh metal wire RS corresponding to the m-th row of the shared pixel units, for example, the seventh metal wire RS < m > in fig. 3, 5, 7 or 9 is turned on to turn on the selection transistor RS, and the selection transistor RS addresses and reads the signal transmitted by the shared pixel units and outputs the signal through the fifth metal wire S1& S2.

According to the control method, all the photosensitive modules in the mth row are marked as the pixels in the mth row, and the expression of the photoelectric signals collected by the pixels in the mth row is known as follows: sig < m, y > = R < m, y > -S < m, y >, sig < m, y > is a photoelectric signal collected by the pixel in the m-th row, R < m, y > is a reset signal read out from the pixel in the m-th row, S < m, y > is an initial photoelectric signal read out from the pixel in the m-th row, and y is the column position where the pixel is located; the expression of the photoelectric signal collected by the m+1th row pixel is: sig < m+1, y > =r < m+1, y > -S < m+1, y >; sig < m+1, y > is the photoelectric signal collected by the pixel in the m-th row, R < m+1, y > is the reset signal read out from the pixel in the m-th row, S < m+1, y > is the initial photoelectric signal read out from the pixel in the m-th row, and y is the column position where the pixel is located.

Example six

The present embodiment provides an image sensor including the pixel array provided in the first to fourth embodiments. The image sensor mentioned in the present embodiment is a CMOS image sensor or a CCD image sensor, and the image sensor mentioned in the present embodiment can be applied to an electronic device, for example: digital cameras, video cameras, computers, portable terminal devices, copiers, and the like.

In summary, the pixel array, the control method thereof and the image sensor provided by the embodiments of the present application have the beneficial effects that: on the one hand, the first photosensitive module and the second photosensitive module comprise photosensitive elements and transmission transistors, the transmission transistors of the first photosensitive module and the second photosensitive module are arranged oppositely, and the source follower transistor is positioned between the transmission transistor of the first photosensitive module and the transmission transistor of the second photosensitive module, so that the quantity of parasitic capacitance can be effectively reduced compared with the quantity of transistors of other pixel sharing structures; on the other hand, the floating diffusion active region comprises a first floating diffusion active region and a second floating diffusion active region which are connected with each other, the first floating diffusion active region and the second floating diffusion active region are respectively positioned at two sides of the source follower transistor, the metal connecting wire of the floating diffusion active region and the grid electrode of the source follower transistor is shorter, and parasitic capacitance between the floating diffusion active region and the metal connecting wire of the grid electrode of the source follower transistor can be reduced. Therefore, interference of conversion gain of pixels of the image sensor is reduced, signal noise is effectively reduced, and image quality acquired by the image sensor is improved.

In addition, the described embodiments are only some, but not all, of the embodiments of the present application. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.

Claims

1. The pixel array is characterized by comprising a plurality of shared pixel units which are arranged in an array along a row direction or a column direction, wherein any shared pixel unit comprises two photosensitive modules, a reset module, a source following transistor and a floating diffusion active region, wherein the two photosensitive modules are arranged in the array along the row direction or the column direction, and the floating diffusion active region comprises a plurality of pixel units which are arranged in the array along the row direction or the column direction, wherein the pixel units which are arranged in the array along the row direction or the column direction, and the row direction is the row direction.

2. The pixel array of claim 1, wherein the reset module comprises a reset transistor, wherein:

the drain terminal of the reset transistor is simultaneously connected with the first floating diffusion active region and the second floating diffusion active region and is connected with the gate terminal of the source follower transistor, the source terminal of the reset transistor is connected with a power supply voltage signal, and the control terminal of the reset transistor is connected with the reset control signal.

3. The pixel array of claim 2, wherein the pixel array comprises a plurality of first metal wire groups, the first metal wire groups corresponding to the plurality of shared pixel units in any row direction, the first metal wire groups comprising first metal wires, second metal wires, and third metal wires parallel to each other in the row direction, within any of the shared pixel units:

The first metal wire is connected with the control end of the transmission transistor of the first photosensitive module and is used for providing a transmission control signal for the transmission transistor of the first photosensitive module;

the second metal wire is connected with the control end of the reset transistor and is used for providing a reset control signal for the reset transistor;

the third metal wire is connected with the control end of the transmission transistor of the second photosensitive module and is used for providing a transmission control signal for the transmission transistor of the second photosensitive module.

4. A pixel array as claimed in claim 3, wherein the first metal trace and/or the third metal trace is located on a side of the photosensitive element remote from the transfer transistor.

5. A pixel array as claimed in claim 3, characterized in that the pixel array comprises a plurality of second metal wire groups corresponding to a number of the shared pixel cells in any column direction, the second metal wire groups comprising fourth, fifth and sixth metal wires parallel to each other in the column direction, within any of the shared pixel cells:

the fourth metal wire is connected with the drain end of the source following transistor and is used for providing a power supply voltage signal for the source following transistor;

The fifth metal wire is connected with the source end of the source following transistor and is used for transmitting the electric signal amplified and output by the source following transistor;

the sixth metal wire is connected with the drain end of the reset transistor and is used for providing a power supply voltage signal for the reset transistor.

6. The pixel array of claim 5, wherein in the pixel array, the reset module connection is disposed on one side of the source follower transistor column direction and is disposed adjacent to the photosensitive module.

7. The pixel array of claim 6, wherein the fourth metal trace and the sixth metal trace share the same metal trace.

8. The pixel array of claim 7, wherein the fifth metal trace is located on a side of the second photosensitive module adjacent to the first photosensitive module and is located adjacent to the fourth metal trace.

9. The pixel array of claim 7, wherein the fifth metal trace is located on a side of the second photosensitive module remote from the first photosensitive module.

10. The pixel array according to any one of claims 8 to 9, wherein the shared pixel unit further comprises a selection transistor disposed on one side of the row direction or the column direction of the source follower transistor, and a center line of the selection transistor and the source follower transistor is perpendicular to a center line of the reset module and the source follower transistor; the drain of the selection transistor is connected with the source of the source following transistor and is used for addressing and reading signals transmitted by the shared pixel units.

11. The pixel array of claim 10, wherein the first set of metal traces further includes a seventh metal trace, the seventh metal trace being located between the second and third metal traces and the seventh metal trace being connected to a control terminal of the select transistor for providing a select control signal to the select transistor.

12. The pixel array of claim 11, wherein two adjacent shared pixel units are stacked in a staggered manner along a column direction, and the first photosensitive modules of two adjacent shared pixel units are located in the same column.

13. The pixel array of claim 12, wherein the first photosensitive module in the shared pixel unit is denoted as an mth row, and the first metal trace is connected to a control terminal of a transfer transistor of the first photosensitive module of the shared pixel unit along the mth row in the column direction and a control terminal of a transfer transistor of the second photosensitive module of the shared pixel unit along the m-1 th row in the column direction, respectively, where m is a positive integer greater than 1.

14. The pixel array of claim 12, wherein the first photosensitive module in the shared pixel unit is denoted as an mth row, and the third metal wiring connects a control terminal of a transfer transistor of the second photosensitive module of the shared pixel unit along the mth row in the column direction and a control terminal of a transfer transistor of the first photosensitive module of the shared pixel unit along the m+1th row in the column direction, respectively, where m is a positive integer greater than or equal to 1.

15. The pixel array of claim 11, wherein two adjacent shared pixel units are stacked in a staggered manner along a row direction, and the first photosensitive modules of two adjacent shared pixel units are located in the same row.

16. The pixel array of any one of claims 1-15, wherein in the shared pixel cell, the second light sensing module is located at an angle of 120 ° to 140 ° clockwise of the first light sensing module.

17. A control method of a pixel array, applied to the pixel array according to any one of claims 1 to 14, wherein image information is collected for each row of pixels in a rolling exposure manner in a unit frame time sequence of the pixel array, and a first photosensitive module in the shared pixel unit is marked as an mth row, and the control method comprises:

conducting second metal wires corresponding to the m-th row sharing pixel units and second metal wires corresponding to the m-1 th row sharing pixel units, and respectively carrying out first resetting operation on the photosensitive elements of the first photosensitive modules in the m-th row sharing pixel units and the photosensitive elements of the second photosensitive modules in the m-1 th row sharing pixel units through sixth metal wires corresponding to the m-th row sharing pixel units and sixth metal wires corresponding to the m-1 th row sharing pixel units so as to remove charges in the photosensitive elements of the first photosensitive modules in the m-th row sharing pixel units and the photosensitive elements of the second photosensitive modules in the m-1 th row sharing pixel units;

Conducting a first metal wiring corresponding to the m-th row sharing pixel unit, and exposing a photosensitive element of a second photosensitive module in the m-1-th row sharing pixel unit and a photosensitive element of a first photosensitive module in the m-th row sharing pixel unit respectively;

conducting a second metal wire corresponding to the m-th row sharing pixel unit and a second metal wire corresponding to the m+1-th row sharing pixel unit, and respectively carrying out a first resetting operation on a photosensitive element of a second photosensitive module in the m-th row sharing pixel unit and a photosensitive element of a first photosensitive module in the m+1-th row sharing pixel unit through a sixth metal wire corresponding to the m-th row sharing pixel unit and a sixth metal wire corresponding to the m+1-th row sharing pixel unit so as to clear charges in the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit and the photosensitive element of the first photosensitive module in the m+1-th row sharing pixel unit;

conducting a third metal wire corresponding to the m-th row sharing pixel unit, and exposing the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit and the photosensitive element of the first photosensitive module in the m+1-th row sharing pixel unit;

Conducting a second metal wire corresponding to the m-th row sharing pixel unit and a second metal wire corresponding to the m-1 th row sharing pixel unit, and respectively carrying out a second reset operation on a photosensitive element of a first photosensitive module in the m-th row sharing pixel unit and a photosensitive element of a second photosensitive module in the m-1 th row sharing pixel unit through a sixth metal wire corresponding to the m-th row sharing pixel unit and a sixth metal wire corresponding to the m-1 th row sharing pixel unit so as to clear charges in a first floating diffusion active region and a second floating diffusion active region in the m-th row sharing pixel unit and charges in a first floating diffusion active region and a second floating diffusion active region in the m-1 th row sharing pixel unit;

reading reset signals of the photosensitive element of the first photosensitive module in the m-th row sharing pixel unit and the photosensitive element of the second photosensitive module in the m-1 th row sharing pixel unit;

ending exposure to the photosensitive element of the first photosensitive module in the m-th row sharing pixel unit and the photosensitive element of the second photosensitive module in the m-1-th row sharing pixel unit, and transferring the charge in the photosensitive element of the first photosensitive module in the m-th row sharing pixel unit and the charge in the photosensitive element of the second photosensitive module in the m-1-th row sharing pixel unit to the first floating diffusion active area and the second floating diffusion active area respectively corresponding to the m-th row sharing pixel unit and the m-1-th row sharing pixel unit respectively;

Reading initial photoelectric signals of a photosensitive element of a first photosensitive module in the m-th row sharing pixel unit and a photosensitive element of a second photosensitive module in the m-1 th row sharing pixel unit;

conducting a second metal wire corresponding to the m-th row sharing pixel unit and a second metal wire corresponding to the m+1-th row sharing pixel unit, and respectively carrying out a second reset operation on a photosensitive element of a second photosensitive module in the m-th row sharing pixel unit and a photosensitive element of a first photosensitive module in the m+1-th row sharing pixel unit through a sixth metal wire corresponding to the m-th row sharing pixel unit and a sixth metal wire corresponding to the m+1-th row sharing pixel unit so as to clear charges in a first floating diffusion active region and charges in a second floating diffusion active region in the m-th row sharing pixel unit and charges in a first floating diffusion active region and a second floating diffusion active region in the m+1-th row sharing pixel unit;

reading reset signals of the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit and the photosensitive element of the first photosensitive module in the m+1th row sharing pixel unit;

ending exposure to the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit and the photosensitive element of the first photosensitive module in the m+1th row sharing pixel unit, and transferring the charge in the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit and the charge in the photosensitive element of the first photosensitive module in the m+1th row sharing pixel unit to the first floating diffusion active area and the second floating diffusion active area respectively corresponding to the m-th row sharing pixel unit and the m+1th row sharing pixel unit respectively;

And reading initial photoelectric signals of the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit and the photosensitive element of the first photosensitive module in the m+1th row sharing pixel unit.

18. A control method of a pixel array, applied to the pixel array according to claim 15, wherein image information is collected for each row of pixels in a rolling exposure manner in a unit frame time sequence of the pixel array, and a row of a first photosensitive module in the shared pixel unit is denoted as an m-th row, the control method comprises:

turning on a second metal wire corresponding to an mth row of shared pixel units, and performing a first resetting operation on a photosensitive element of a first photosensitive module in the mth row of shared pixel units through a sixth metal wire corresponding to the mth row of shared pixel units so as to remove charges in the photosensitive element of the first photosensitive module in the mth row of shared pixel units;

conducting a first metal wire corresponding to the m-th row sharing pixel unit, and exposing a photosensitive element of a first photosensitive module in the m-th row sharing pixel unit;

conducting a second metal wire corresponding to the m-th row sharing pixel unit, and performing a first resetting operation on a photosensitive element of a second photosensitive module in the m-th row sharing pixel unit through a sixth metal wire corresponding to the m-th row sharing pixel unit so as to remove charges in the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit;

Conducting a third metal wire corresponding to the m-th row sharing pixel unit, and exposing a photosensitive element of a second photosensitive module in the m-th row sharing pixel unit;

conducting a second metal wire corresponding to the m-th row sharing pixel unit, and performing a second resetting operation on a photosensitive element of a first photosensitive module in the m-th row sharing pixel unit through a sixth metal wire corresponding to the m-th row sharing pixel unit so as to remove charges in a first floating diffusion active region and charges in a second floating diffusion active region in the m-th row sharing pixel unit;

reading a reset signal of a photosensitive element of a first photosensitive module in the m-th row shared pixel unit;

ending exposure of the photosensitive element of the first photosensitive module in the m-th row sharing pixel unit, and transferring charges in the photosensitive element of the first photosensitive module in the m-th row sharing pixel unit to the first floating diffusion active area corresponding to the m-th row sharing pixel unit;

reading an initial photoelectric signal of a photosensitive element of a first photosensitive module in the m-th row shared pixel unit;

conducting a second metal wire corresponding to the m-th row sharing pixel unit, and performing a second resetting operation on a photosensitive element of a second photosensitive module in the m-th row sharing pixel unit through a sixth metal wire corresponding to the m-th row sharing pixel unit so as to remove charges in a first floating diffusion active region and charges in a second floating diffusion active region in the m-th row sharing pixel unit;

Reading a reset signal of a photosensitive element of a second photosensitive module in the m-th row shared pixel unit;

ending exposure of the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit, and transferring charges in the photosensitive element of the second photosensitive module in the m-th row sharing pixel unit to the second floating diffusion active area corresponding to the m-th row sharing pixel unit;

and reading an initial photoelectric signal of a photosensitive element of a second photosensitive module in the m-th row sharing pixel unit.

19. A control method of a pixel array according to any one of claims 17 to 18, wherein the control method further comprises:

and turning on a seventh metal wiring corresponding to the m-th row of shared pixel units to turn on a selection transistor, wherein the selection transistor addresses and reads signals transmitted by the shared pixel units and outputs the signals through the fifth metal wiring.

20. A method of controlling a pixel array according to any one of claims 17 to 18, wherein all of the light sensing modules of the mth row are denoted as mth row pixels, wherein,

the expression of the photoelectric signals collected by the m-th row of pixels is as follows:

Sig<m,y>＝R<m,y>-S<m,y>，

the Sig < m, y > is a photoelectric signal collected by the pixel in the m-th row, the R < m, y > is a reset signal read out from the pixel in the m-th row, the S < m, y > is an initial photoelectric signal read out from the pixel in the m-th row, and the y is the column position of the pixel;

The expression of the photoelectric signals collected by the m+1th row pixels is as follows:

Sig<m+1,y>＝R<m+1,y>-S<m+1,y>，

the Sig < m+1, y > is a photoelectric signal collected by the pixels in the m-th row, the R < m+1, y > is a reset signal read out from the pixels in the m-th row, the S < m+1, y > is an initial photoelectric signal read out from the pixels in the m-th row, and the y is the column position of the pixels.

21. An image sensor comprising the pixel array of any one of claims 1-16.