CN117394830A - Pulse phase correction method - Google Patents

Pulse phase correction method Download PDF

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Publication number
CN117394830A
CN117394830A CN202311442639.0A CN202311442639A CN117394830A CN 117394830 A CN117394830 A CN 117394830A CN 202311442639 A CN202311442639 A CN 202311442639A CN 117394830 A CN117394830 A CN 117394830A
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square wave
signal
input
wave
voltage
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冯建生
何丹
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Nanjing Steamer Electrical Control Co ltd
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Nanjing Steamer Electrical Control Co ltd
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Priority to CN202311442639.0A priority Critical patent/CN117394830A/en
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01Shaping pulses

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The invention discloses a pulse phase correction method, which relates to the technical field of communication and comprises the steps of receiving two groups of square wave signals from two different grating sensors, wherein the square wave signals are respectively input signals PAI and PBI; converting the input signal PAI into a triangular wave using a square wave-triangular wave converter U1; adjusting the potentiometer RV1 to set the intermediate value of the triangular wave rising section; comparing the triangular wave signal with a set intermediate value by using an operational amplifier A1, and outputting a rectangular wave signal; performing logic operation on a rectangular wave signal and an input signal PBI by using a two-input OR gate U2, and controlling output through a triode Q3; square wave shaping is carried out on the signal after logic operation by using a four-2 input NAND gate U3; two accurate square wave pulse sequences PAO and PBO with 90 degrees phase difference are output. The method can improve the measurement precision by 4 times on the basis of the prior hardware technology by counting the pulse sequence A and identifying the phase of the pulse sequence B.

Description

Pulse phase correction method
Technical Field
The invention relates to the technical field of communication, in particular to a pulse phase correction method.
Background
The incremental rotary encoder applied to the doubly-fed wind generator is used for measuring the steering, the rotating speed and the phase of the rotor of the wind generator. In the existing pulse phase correction technology for incremental rotary encoders, the phase of the pulse signal obtained from the grating sensor tends to be error due to various factors such as spatial position, interference and diffraction of light, sensing of light, and influence of photosensor materials and processes. The error can cause unstable system and performance degradation, the phase error range of the B phase pulse lagging A phase pulse of the existing encoder is generally +/-45 degrees, and the B phase pulse can only be used as a basis for judging the rotor steering and can not be used as a positioning basis of the rotor phase of the doubly-fed wind power generator due to the fact that the error is too large, the positioning accuracy of the rotor is affected, and the control accuracy and energy efficiency of the generator are further affected.
Disclosure of Invention
The present invention has been made in view of the above-described problems associated with the conventional pulse phase correction method.
Therefore, the problem to be solved by the present invention is how to provide a pulse phase correction method.
In order to solve the technical problems, the invention provides the following technical scheme: a pulse phase correction method comprising receiving two sets of square wave signals, an input signal PAI and an input signal PBI, from two different grating sensors; converting the input signal PAI into a triangular wave using a square wave-triangular wave converter U1; adjusting the potentiometer RV1 to set the intermediate value of the triangular wave rising section; comparing the triangular wave signal with a set intermediate value by using an operational amplifier A1, and outputting a rectangular wave signal; performing logic operation on a rectangular wave signal and an input signal PBI by using a two-input OR gate U2, and controlling output through a triode Q3; square wave shaping is carried out on the signal after logic operation by using a four-2 input NAND gate U3; two accurate square wave pulse sequences PAO and PBO with 90 degrees phase difference are output.
As a preferable embodiment of the pulse phase correction method of the present invention, wherein: the rising segment of the triangular wave corresponds to the high level of the square wave, and the falling segment corresponds to the low level of the square wave.
As a preferable embodiment of the pulse phase correction method of the present invention, wherein: the positions at which two sets of square wave signals are received from two different grating sensors are defined as T1 and T5, the position between the square wave-triangle wave converter U1 and the operational amplifier A1 is defined as T2, the position between the operational amplifier A1 and the potentiometer RV1 is defined as T3, the position between the two-input or gate U2 and the four-2 input nand gate U3 is defined as T6, the position between the operational amplifier A1 and the two-input or gate U2 is defined as T4, and the position after the four-2 input nand gate U3 is defined as T7;
the square wave-triangular wave converter U1 adopts ICL8038, the pin 7 is connected with the pin 8, the pin 4 is connected with a positive power supply, the pin 11 is grounded, and the pin 10 is externally connected with a capacitor C1;
when the T1 position is at a high level, the triode Q1 is conducted by a square wave signal at the T1 position through a resistor R9 and a resistor R5, a power supply voltage V enters a pin 4 through the triode Q1 and a resistor RA, a capacitor C1 is charged through a constant current source in the square wave-triangular wave converter U1, the voltages at two ends of the capacitor C1 are linearly increased, and the voltage of a pin 3 is synchronously increased through an internal circuit; if the input square wave signal PAI has a frequency f, the period is 1/f, the T1 high level maintaining time T0 to T1 is 1/2f, and the output voltage of the pin 3 is: :
the highest voltage at time t1 is:=/>
when T1 is at low level, from T1 to the time T2 at the end of the period, the transistor Q2 is turned on by the square wave signal of T1 through the resistor R6 and the resistor R4, the power supply voltage V enters the leg 4 of the square wave-triangle wave converter U1 through the transistor Q2 and the resistor RB, the capacitor C1 is discharged through the internal constant current circuit of the square wave-triangle wave converter U1, the voltages at two ends of the capacitor C1 are linearly reduced, the voltage at the leg 3 of the square wave-triangle wave converter U1 is synchronously reduced through the internal circuit, and if the low level maintaining time of the input square wave signal PAI is also 1/2f, the output voltage of the leg 3 of the square wave-triangle wave converter U1 is:the voltage at the T2 position throughout the cycle is therefore: t2= = ->-Wherein T1 is a digital quantityOnly 0 and 1;
if the PAI signal is a square wave with a duty cycle of 50%RA=RB=RThe above formula can be simplified as: t2=-/>The square wave signal at the T1 position is converted into a triangular wave in a square wave-triangular wave converter U1 with a maximum value of the waveform +.>The lowest value is 0. As a preferable embodiment of the pulse phase correction method of the present invention, wherein: when the T2 position voltage is greater than the T3 position voltage, the T4 position is high, and when the T2 position voltage is less than the T3 position voltage, the T4 position is low.
As a preferable embodiment of the pulse phase correction method of the present invention, wherein: the output of the two-input or gate U2 is controlled by the transistor Q3, and the output of the two-input or gate U2 is shifted only when the rectangular wave signal is at a high level.
As a preferable embodiment of the pulse phase correction method of the present invention, wherein: four-2 input nand gate U3 uses four nand gates, capacitors and resistors to form a monostable flip-flop for squaring.
The invention has the beneficial effects that: the pulse sequence B can be used as a judging basis for the steering of the rotor of the wind driven generator and can also be used for determining the accurate measurement of the phase of the rotor of the wind driven generator; the rising edge of the pulse sequence B is a square wave which precisely lags the rising edge of the pulse sequence A by 90 degrees; by counting the pulse sequence A and identifying the phase of the pulse sequence B, the measurement accuracy can be improved by 4 times on the basis of the prior hardware technology.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a pulse phase correction method in embodiment 1.
Fig. 2 is a waveform diagram related to the pulse phase correction method in embodiment 1.
Fig. 3 is a circuit diagram of a pulse phase correction method in embodiment 1.
Description of the embodiments
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.
Further, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic can be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
Examples
Referring to fig. 1-3, in an embodiment of the present invention, a pulse phase correction method is provided, the pulse phase correction method includes the following steps,
s1, receiving two groups of square wave signals from two different grating sensors, namely an input signal PAI and an input signal PBI, wherein the waveform diagram of the input signal PAI is shown as W1 in FIG. 2, the waveform of the input signal PBI is shown as W5 in FIG. 2, and the waveform of the input signal PBI is shown as W6 in FIG. 2 after the input signal PBI is processed by two input OR gates U2. The phase of the input signal PBI should ideally lag the PAI signal by 90 degrees, but in practice, the input signal PBI is affected by spatial position, interference and diffraction of light, light sensing, and optical sensor materials and processes, and the error is often large, and the error range is usually ±45 degrees.
S2, an input signal PAI is converted into triangular waves by using a square wave-triangular wave converter U1, for convenience of description, positions where two groups of square wave signals are received from two different grating sensors are defined as T1 and T5, a position between the square wave-triangular wave converter U1 and an operational amplifier A1 is defined as T2, a position between the operational amplifier A1 and a potentiometer RV1 is defined as T3, a position between the two-input OR gate U2 and a four-2 input NAND gate U3 is defined as T6, a position between the operational amplifier A1 and the two-input OR gate U2 is defined as T4, and a position after the four-2 input NAND gate U3 is defined as T7.
In this embodiment, the square wave-triangle wave converter U1 adopts ICL8038, the pin 7 is connected with the pin 8, the pin 4 is connected with a positive power supply, the pin 11 is grounded, and the pin 10 is externally connected with a capacitor C1;
when the T1 position is in a high level (namely logic 1), the triode Q1 is conducted by a square wave signal at the T1 position through a resistor R9 and a resistor R5, a power supply voltage V enters a pin 4 through the triode Q1 and a resistor RA, a capacitor C1 is charged through a constant current source in the square wave-triangle wave converter U1, the voltages at two ends of the capacitor C1 are linearly increased, and the voltage of a pin 3 is synchronously increased through an internal circuit; if the input square wave signal PAI has a frequency f, the period is 1/f, the T1 high level maintaining time T0 to T1 is 1/2f, and the output voltage of the pin 3 is: :
the highest voltage at time t1 is:=/>
when T1 is at low level, from T1 to the time T2 at the end of the period, the square wave signal of T1 makes the triode Q2 conducted through the resistor R6 and the resistor R4, the power voltage V enters the foot 4 of the square wave-triangle wave converter U1 through the triode Q2 and the resistor RB, and passes through the internal constant current circuit of the square wave-triangle wave converter U1Discharging the capacitor C1, wherein the voltage at two ends of the capacitor C1 is linearly reduced, the voltage at the pin 3 of the square wave-triangular wave converter U1 is synchronously reduced through an internal circuit, if the low level maintaining time of the input square wave signal PAI is also 1/2f, the output voltage of the pin 3 of the square wave-triangular wave converter U1 is as follows:the voltage at the T2 position throughout the cycle is therefore: t2= = ->-Wherein T1 is a digital number, only 0 and 1;
if the PAI signal is a square wave with a duty cycle of 50%RA=RB=RThe above formula can be simplified as: t2=-/>The square wave signal at the T1 position is converted into a triangular wave in a square wave-triangular wave converter U1 with a maximum value of the waveform +.>The lowest value is 0, the rising segment of the triangular wave corresponds to the high level of the square wave, and the falling segment of the triangular wave corresponds to the low level of the square wave. S3, adjusting the potentiometer RV1 to set the intermediate value of the triangular wave rising section, namely +.>=/>The waveform is as in FIG. 2 and W3;
s4, as shown in the graph W2 of FIG. 2, crossing the intersection of W3 upwards and being located at a position which is 90 degrees behind the rising edge of the waveform of W1, comparing the triangular wave signal with a set intermediate value by using an operational amplifier A1, and outputting a rectangular wave signal, wherein when the voltage at the T2 position is greater than the voltage at the T3 position, the T4 position is at a high level, and when the voltage at the T2 position is less than the voltage at the T3 position, the T4 position is at a low level, and in the graph of FIG. 3, the waveform is as shown in the W4 of FIG. 2, namely: t4= (T2 > T3), where T4 is a digital quantity, only 0 and 1, and it is known that the T4 position waveform lags the T1 position waveform by 1/4 cycle, i.e., 90 °;
s5, performing logic operation on a rectangular wave signal and an input signal PBI (namely, a T4 position signal and a T5 position signal which are precisely delayed by 90 degrees from the rising edge of a PAI waveform after adjustment) by using a two-input OR gate U2, controlling output through a triode Q3, enabling a collector and an emitter of the triode Q3 to be in a conducting state by the T4 position signal through a base of the triode Q3 and a resistor R3 when the T4 position signal is in a high level, enabling an output signal of a foot 3 of the two-input OR gate U2 to be transmitted to a T6 position, enabling the triode Q3 to be in a cutting-off state when the T5 position signal is in a high level and the T4 position signal is in a low level, and enabling the T6 position signal to not be shifted even though the two-input OR gate U2 foot 31 outputs shift, wherein the relations of the T4, the T5 and the T6 position signal and the triode Q3 are shown in the following table:
table 3 T4, T5, T6 position signals and triode Q3 relationship table
Sequence number T4 T5 U2:3 Q3 T6
1 0 0 0 Cut-off 0
2 0 1 1 Cut-off 0
3 1 0 1 Conduction 1
4 1 1 1 Conduction 1
The logic operation formula of the implementation is as follows: t6= (t4+t5) ·t4; when the rising edge of the T5 position signal arrives later than the rising edge of the T4 position signal, the T4 position signal is high, the transistor Q3 is in on state, and a signal can be output to the T6 position, and the waveform is shown as W6 in fig. 2. That is, the rising edge of the T6 position signal is exactly 90 degrees behind the rising edge of the input signal PAI signal, regardless of whether the T5 position signal leads or lags the T4 position signal; the logic relation of the realization is as follows: t6= (t4+t5) ·t4, where the T4, T5, T6 position signals are digital quantities, only 0 and 1.
S6, square wave shaping is carried out on a signal after logic operation (namely T6 position signal) by using a four-2 input NAND gate U3, the model CD4011 selected by U3 is used, in the embodiment, a monostable trigger is formed by using four NAND gates, a capacitor C2 and a resistor R10, after the T6 position signal is input, a square wave form PBO which is lagging by 90 degrees with respect to the waveforms of an input signal PAI and an output signal PAO is obtained, the position is shown as a T7 position in fig. 1, and the waveform is shown as a W7 in fig. 2;
s7, outputting two accurate square wave pulse sequences PAO and PBO (PBO lag PAO) with 90 degrees phase difference.
It should be noted that, in the technology of the present invention, the phase error correction angle not only can be 90 degrees, but also can be any angle from 0 to 180 degrees, and the technology of the present invention can be used for accurately measuring the rotor phase of a new energy double-fed wind driven generator, and can also be used for correcting signal errors caused by the influence of line length, materials and hardware differences or environmental interference of a multi-path communication line, and the phase correction is usually realized by the technologies of iteration method, baseline recognition, data acquisition compression, etc., while the present invention realizes the correction of pulse phase through specific circuit design and logic operation, and is more direct and efficient; in addition, the measurement accuracy is improved by 4 times, and the control accuracy and the energy efficiency of the wind driven generator can be obviously affected.
It should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present invention may be modified or substituted without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered in the scope of the claims of the present invention.

Claims (6)

1. A pulse phase correction method is characterized in that: comprising the steps of (a) a step of,
receiving two sets of square wave signals, namely an input signal PAI and an input signal PBI, from two different grating sensors;
converting the input signal PAI into a triangular wave using a square wave-triangular wave converter U1;
adjusting the potentiometer RV1 to set the intermediate value of the triangular wave rising section;
comparing the triangular wave signal with a set intermediate value by using an operational amplifier A1, and outputting a rectangular wave signal;
performing logic operation on a rectangular wave signal and an input signal PBI by using a two-input OR gate U2, and controlling output through a triode Q3;
square wave shaping is carried out on the signal after logic operation by using a four-2 input NAND gate U3;
two accurate square wave pulse sequences PAO and PBO with 90 degrees phase difference are output.
2. The pulse phase correction method of claim 1, wherein: the rising segment of the triangular wave corresponds to the high level of the square wave, and the falling segment corresponds to the low level of the square wave.
3. The pulse phase correction method of claim 1, wherein: the positions at which two sets of square wave signals are received from two different grating sensors are defined as T1 and T5, the position between the square wave-triangle wave converter U1 and the operational amplifier A1 is defined as T2, the position between the operational amplifier A1 and the potentiometer RV1 is defined as T3, the position between the two-input or gate U2 and the four-2 input nand gate U3 is defined as T6, the position between the operational amplifier A1 and the two-input or gate U2 is defined as T4, and the position after the four-2 input nand gate U3 is defined as T7;
the square wave-triangular wave converter U1 adopts ICL8038, the pin 7 is connected with the pin 8, the pin 4 is connected with a positive power supply, the pin 11 is grounded, and the pin 10 is externally connected with a capacitor C1;
when the T1 position is at a high level, the triode Q1 is conducted by a square wave signal at the T1 position through a resistor R9 and a resistor R5, a power supply voltage V enters a pin 4 through the triode Q1 and a resistor RA, a capacitor C1 is charged through a constant current source in the square wave-triangular wave converter U1, the voltages at two ends of the capacitor C1 are linearly increased, and the voltage of a pin 3 is synchronously increased through an internal circuit; if the input square wave signal PAI has a frequency f, the period is 1/f, the T1 high level maintaining time T0 to T1 is 1/2f, and the output voltage of the pin 3 is:
the highest voltage at time t1 is:=/>
when T1 is at low level, from T1 to the time T2 at the end of the period, the transistor Q2 is turned on by the square wave signal of T1 through the resistor R6 and the resistor R4, the power supply voltage V enters the leg 4 of the square wave-triangle wave converter U1 through the transistor Q2 and the resistor RB, the capacitor C1 is discharged through the internal constant current circuit of the square wave-triangle wave converter U1, the voltages at two ends of the capacitor C1 are linearly reduced, the voltage at the leg 3 of the square wave-triangle wave converter U1 is synchronously reduced through the internal circuit, and if the low level maintaining time of the input square wave signal PAI is also 1/2f, the output voltage of the leg 3 of the square wave-triangle wave converter U1 is:the voltage at the T2 position throughout the cycle is therefore: t2= = ->-Wherein T1 is a digital number, only 0 and 1;
if the PAI signal is a square wave with a duty cycle of 50%RA=RB=RThe above formula can be simplified as: t2=-The square wave signal at the T1 position is converted into a triangular wave in a square wave-triangular wave converter U1 with a maximum value of the waveform +.>The lowest value is 0.
4. The pulse phase correction method of claim 3, wherein: when the T2 position voltage is greater than the T3 position voltage, the T4 position is high, and when the T2 position voltage is less than the T3 position voltage, the T4 position is low.
5. The method of pulse phase correction as defined in claim 4, wherein: the output of the two-input or gate U2 is controlled by the transistor Q3, and the output of the two-input or gate U2 is shifted only when the rectangular wave signal is at a high level.
6. The method of pulse phase correction as defined in claim 5, wherein: four-2 input nand gate U3 uses four nand gates, capacitors and resistors to form a monostable flip-flop for squaring.
CN202311442639.0A 2023-11-01 2023-11-01 Pulse phase correction method Pending CN117394830A (en)

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