CN117394801A - Overshoot-resistant bias circuit, power amplifier circuit structure and radio frequency chip - Google Patents
Overshoot-resistant bias circuit, power amplifier circuit structure and radio frequency chip Download PDFInfo
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- CN117394801A CN117394801A CN202311699147.XA CN202311699147A CN117394801A CN 117394801 A CN117394801 A CN 117394801A CN 202311699147 A CN202311699147 A CN 202311699147A CN 117394801 A CN117394801 A CN 117394801A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/447—Indexing scheme relating to amplifiers the amplifier being protected to temperature influence
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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Abstract
The invention discloses an overshoot-resistant bias circuit, which comprises a clock signal generating circuit, a first voltage source and a second voltage source, wherein the clock signal generating circuit is used for generating a clock signal with a set frequency; the counter circuit is connected with the clock signal generation circuit and used for counting according to set control logic; the digital-to-analog conversion circuit is connected with the counter circuit and is used for converting the digital signals into analog signals, the size of the analog signals is related to the number of the counting results, the counting results are different, and the sizes of the analog signals are different; and the bias circuit is connected with the digital-to-analog conversion circuit, the analog signal is input to the signal input end of the bias circuit, and the bias signal generated by the bias circuit is higher when the analog signal is higher. The invention also relates to a power amplifier circuit structure and a radio frequency chip.
Description
Technical Field
The invention relates to the field of radio frequency communication, in particular to an overshoot-resistant bias circuit, a power amplifier circuit structure and a radio frequency chip.
Background
The radio frequency transceiver system generally comprises a receiver and a transmitter, wherein the receiver receives radio frequency signals, the transmitter transmits signals to be transmitted, and for other small signal amplifiers except for power amplifiers in the receiver and the transmitter, the transistor junction temperature of the small signal amplifier has little difference with the external environment temperature due to lower self power consumption and less heat dissipation. However, for the power amplifier, the power consumption itself is large, and a large part of the power consumption is converted into heat to be accumulated around the transistor, so that the junction temperature of the power amplifier is far higher than the external environment temperature. Therefore, when the receiving and transmitting system is not in the transmitting state, the power amplifier is not enabled, the junction temperature is close to the ambient temperature, and after the receiving and transmitting system is switched to the transmitting state, the receiving and transmitting system is enabled and then heats itself to raise the junction temperature; in a period of time after switching, the junction temperature of the power amplifier is transited from a lower temperature close to the ambient temperature to a higher steady-state temperature; the gain of the amplifier can be reduced along with the rise of temperature, so that the gain of the power amplifier can be changed from high to low after being enabled; the envelope of the transmitted rf signal is thus also affected and an overshoot is generated after switching.
Overshoot of the rf signal envelope increases the risk of self-excitation of the power amplifier and the system settling time is also affected and prolonged.
How to eliminate the overshoot of the envelope of the rf signal is a urgent problem to be solved.
Disclosure of Invention
The invention aims to provide an overshoot-resistant bias circuit, which aims to solve the problem of envelope overshoot of a radio frequency signal.
In a first aspect, embodiments of the present invention disclose an anti-overshoot bias circuit, the circuit comprising:
a clock signal generating circuit for generating a clock signal of a set frequency;
a counter circuit connected with the clock signal generating circuit and used for counting according to set control logic, wherein the control logic comprises: recording the number of rising edges or falling edges of the clock signals, and generating digital signals according to the counting result until the overshoot-resistant bias circuit reaches a stable working state;
the digital-to-analog conversion circuit is connected with the counter circuit and is used for converting the digital signals into analog signals, the size of the analog signals is related to the number of the counting results, the counting results are different, and the sizes of the analog signals are different;
and the bias circuit is connected with the digital-to-analog conversion circuit, the analog signal is input to the signal input end of the bias circuit, and the bias signal generated by the bias circuit is higher when the analog signal is higher.
Optionally, the recording the number of rising edges or falling edges of the clock signal, and generating the digital signal according to the counting result includes: generating a counting result every time the number of rising edges or falling edges of the set clock signal is recorded, and generating a digital signal according to the counting result; or recording the number of rising edges or falling edges of the clock signal every time a set time passes, generating a counting result, and generating a digital signal according to the counting result, wherein the set time is kept unchanged; or the set time is changed according to a set rule.
Optionally, the more the count result, the larger the analog signal.
Optionally, the analog voltage corresponding to the predetermined value enables the bias generated by the bias circuit to be the maximum stable bias voltage; or the analog voltage corresponding to the preset value can enable the bias generated by the bias circuit to be a set value, and the set value is smaller than the maximum stable bias which can be generated by the bias circuit.
Optionally, the clock signal generating circuit multiplexes the clock signal generating circuit in the radio frequency chip where the overshoot-resistant bias circuit is located; or the clock signal generation circuit is independently designed.
Optionally, the period corresponding to the set frequency range is ns level.
Optionally, the bias circuit comprises a voltage bias circuit or a current bias circuit or an adjustable resistance bias or a diode temperature compensated adjustable resistance bias.
Optionally, the anti-overshoot bias circuit is adapted for use in a power amplifier.
Optionally, the analog signal is an analog voltage or an analog current; the bias signal is a bias voltage or bias current.
Optionally, the device further comprises a logic control circuit, wherein the logic control circuit is connected with the counter circuit and is used for generating the setting control logic; the logic control circuit is also connected with the enabling end of the bias circuit and used for controlling the on-off of the bias circuit.
In a second aspect, an embodiment of the present invention discloses a power amplifier circuit structure, which includes a power amplifier, and the overshoot-resistant bias circuit described above, where the overshoot-resistant bias circuit is used to amplify a signal of the power amplifier.
In a third aspect, an embodiment of the present invention discloses a radio frequency chip, where the radio frequency chip includes a radio frequency signal transmitting end, and the radio frequency signal transmitting end has the power amplifier circuit structure described above.
Compared with the prior art, the embodiment of the invention has the following effects:
the invention can lead the bias of the amplifier to slowly rise along with time through the cooperation of the clock generating circuit, the counter circuit and the logic control circuit, can avoid the overshoot phenomenon, can eliminate the overshoot phenomenon of the envelope of the radio frequency signal, reduce the self-excitation risk and quicken the system stability.
Drawings
FIG. 1 is a schematic diagram of a conventional RF envelope overshoot phenomenon;
FIG. 2 is a circuit diagram of an anti-overshoot bias circuit according to an embodiment of the present invention;
FIG. 3 (a) is a diagram of the bias contrast of an anti-overshoot bias circuit with a normal bias circuit according to an embodiment of the present invention;
FIG. 3 (b) is a radio frequency envelope comparison diagram of an anti-overshoot bias circuit and a normal bias circuit according to an embodiment of the present invention;
FIG. 4 (a) is an initial bias waveform diagram of an anti-overshoot bias circuit according to an embodiment of the invention;
FIG. 4 (b) is a bias waveform diagram of an extended bias settling time of an anti-overshoot bias circuit according to an embodiment of the invention;
FIG. 4 (c) is a bias waveform diagram of a reduced bias magnitude of an anti-overshoot bias circuit according to an embodiment of the invention;
fig. 5 is a block diagram of a power amplifier circuit according to an embodiment of the invention;
FIG. 6 (a) is an LDMOS power amplifier circuit implementing logic for an anti-overshoot bias circuit, suitable for use in embodiments of the present invention;
FIG. 6 (b) is a PowerFET power amplifier circuit implementing logic for an anti-overshoot bias circuit suitable for use with embodiments of the present invention;
fig. 6 (c) is an HBT power amplifier circuit implementing logic for an anti-overshoot bias circuit suitable for use in embodiments of the present invention.
Detailed Description
The invention will be further described with reference to specific examples and figures. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. Furthermore, for convenience of description, only some, but not all, structures or processes related to the present invention are shown in the drawings. It should be noted that in the present specification, like reference numerals and letters denote like items in the following drawings.
It will be understood that, although the terms "first," "second," etc. may be used herein to describe various features, these features should not be limited by these terms. These terms are used merely for distinguishing and are not to be construed as indicating or implying relative importance. For example, a first feature may be referred to as a second feature, and similarly a second feature may be referred to as a first feature, without departing from the scope of the example embodiments.
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a conventional rf envelope overshoot phenomenon.
As shown in fig. 1, after the radio frequency system switches the transmitting state, the transmitting end power amplifier is enabled and then heats itself to raise the junction temperature. During a period of time after switching, the junction temperature of the power amplifier transitions from a lower temperature near the ambient temperature to a higher steady state temperature, and the gain of the amplifier decreases with increasing temperature, so that the gain of the power amplifier changes from high to low after being enabled, the transmitted rf signal envelope is affected, and an overshoot is generated after switching, as shown in fig. 1, the convex portion is the overshoot of the rf envelope.
Overshoot of the rf signal envelope increases the risk of self-excitation of the power amplifier, and the settling time of the rf system is also affected and prolonged.
The overshoot resistant bias circuit of the present invention can solve the above-described problems.
Fig. 2 is a circuit diagram of an anti-overshoot bias circuit according to an embodiment of the present invention.
As shown in fig. 2, the overshoot-resistant bias circuit is composed of a clock signal generation circuit 210, a counter circuit 220, a digital-to-analog conversion circuit 230, and a bias circuit 240.
The anti-overshoot bias circuit of the present invention is applicable to a power amplifier, but, without regard to a specific bias circuit form, the bias circuit may include any form of voltage bias circuit or current bias circuit or adjustable resistance bias or diode temperature compensation adjustable resistance bias, and the limitation of the bias form is described only as a specific example in the following description of the embodiment, and the main bias signal is a bias voltage or bias current.
In one embodiment, the clock signal generating circuit 210 is configured to generate a clock signal with a set frequency, and the period corresponding to the set frequency range is ns.
It should be noted that, the clock signal generating circuit multiplexes the clock signal generating circuit in the rf chip where the anti-overshoot bias circuit is located, or the clock signal generating circuit is designed independently, that is, the clock signal generating circuit 210 may multiplex the clock signal generated by the phase-locked loop circuit (PLL) in the rf transceiver system, or may be designed independently according to the requirement of the circuit, which should be understood by those skilled in the art that the form of the clock signal should not be taken as a limitation condition of the present invention.
The logic control circuit 260 is connected to the counter circuit 220 for generating a setting control logic, the logic control circuit 260 is also connected to an enable end of the bias circuit 240 for controlling the bias circuit to be turned on and off, and when the logic control circuit 260 sends out an enable signal, the counter circuit 220 and the bias circuit 240 start to operate.
The counter circuit 220 is connected to the clock signal generation circuit 210, and the counter circuit 220 is configured to count according to a set control logic, the control logic including: the number of rising edges or falling edges of the clock signal is recorded, a digital signal is generated according to the counting result, the digital signal is sent to a digital-to-analog conversion circuit 230 connected with the counter circuit 220, the digital-to-analog conversion circuit 230 is used for converting the digital signal into an analog signal, wherein the analog signal is an analog voltage or an analog current, the size of the analog signal is related to the number of the counting result, the counting result is different, the size of the analog signal is different, the analog signal is sent to a signal input end of a bias circuit 240 connected with the digital-to-analog conversion circuit, the bias signal generated by the bias circuit is higher when the analog signal is higher, and the logic control circuit adjusts the counting result until the overshoot resistance bias circuit reaches a stable working state.
As one embodiment, recording the number of rising or falling edges of the clock signal, generating the digital signal according to the count result includes: and (3) recording the number of rising edges or falling edges of the set clock signals, generating a counting result, and generating a digital signal according to the counting result.
In one example, a clock signal is given out every oscillation of a clock crystal oscillator of the clock signal system, and a predetermined number of clock signals can be set according to actual needs to perform a counting operation. For example, accumulating 4 clock signals generates a digital signal, accumulating 8 clock signals generates a digital signal, and so on, accumulating 16 clock signals generates a digital signal until the bias of the overshoot-resistant bias circuit reaches a predetermined value.
As one embodiment, recording the number of rising or falling edges of the clock signal, generating the digital signal according to the count result includes: the number of rising edges or falling edges of the clock signal is recorded every time the set time passes, a counting result is generated, a digital signal is generated according to the counting result, and the set time is kept unchanged.
In one example, the number of clock signals is recorded every 4 nanoseconds to generate a digital signal until the bias of the anti-overshoot bias circuit reaches a predetermined value.
As one embodiment, recording the number of rising or falling edges of the clock signal, generating the digital signal according to the count result includes: the set time varies according to the set rule.
For example, the counter circuit 220 is responsible for counting the number of the clocks CLK received after the start of enabling, and generates an 8bit digital signal to the digital-to-analog conversion circuit 230 according to the given control logic, and after the digital-to-analog conversion circuit 230 receives the 8bit digital signal, it converts the digital signal into an analog voltage and outputs the analog voltage to the current mirror control module of the bias circuit, and then, the magnitude of the bias current generated by the current mirror can be adjusted by adjusting the analog voltage, so that the bias of the power amplifying circuit is changed.
The bias of the corresponding power amplifying circuit is lower when the number of the counter accumulated clocks CLK is smaller, the bias is gradually increased along with the accumulation of the counter clocks CLK, and the counter output is not changed into a stable working state after reaching a preset value. The analog voltage corresponding to the predetermined value can make the bias voltage generated by the bias circuit 240 be the maximum stable bias voltage, or the analog voltage corresponding to the predetermined value can make the bias voltage generated by the bias circuit 230 be a set value, which is smaller than the maximum stable bias voltage that can be generated by the bias circuit 230.
It should be noted that the circuit implementation described in the embodiments of the present invention is only a specific example, and the bias portion of the actual overshoot-resistant bias circuit is not limited to the current mirror bias circuit as illustrated in the drawings, and other known voltage bias circuits or current bias circuits can use the implementation logic of the overshoot-resistant bias circuit of the present invention.
FIG. 3 (a) is a diagram of the bias contrast of an anti-overshoot bias circuit with a normal bias circuit according to an embodiment of the present invention;
fig. 3 (b) is a radio frequency envelope comparison diagram of an overshoot resistant bias circuit and a normal bias circuit according to an embodiment of the present invention.
As shown in fig. 3 (a) and 3 (b), when the number of clock signals is small, the output digital signal is also small, the bias of the power amplifier 250 after conversion is low, the clock signals accumulated and counted over time are gradually increased, the bias of the power amplifier 250 is gradually increased, after the set time is reached, the count reaches a predetermined value, the output digital signal is not changed any more, and the bias of the power amplifier 250 is at a stable value.
Since the bias of the power amplifier 250 slowly rises over time, the rf signal does not overshoot.
Fig. 4 is a schematic diagram of a logic control circuit for an anti-overshoot bias circuit according to an embodiment of the invention.
The output of the adjust counter circuit 220 controllably adjusts the bias of the different waveforms.
The logic control circuit 260 adjusts the counting mode of the counter circuit 220, and further changes the digital signal output by the counter circuit 220, so as to change the analog voltage generated by the digital-to-analog conversion circuit 230, and further change the waveform of the bias generated by the bias circuit 240.
FIG. 4 (a) is an initial bias waveform diagram of an anti-overshoot bias circuit according to an embodiment of the invention;
FIG. 4 (b) is a bias waveform diagram of an extended bias settling time of an anti-overshoot bias circuit according to an embodiment of the invention;
fig. 4 (c) is a bias waveform diagram of a reduced bias magnitude of an anti-overshoot bias circuit according to an embodiment of the invention.
The counter circuit 220 is configured to count according to control logic set by the logic control circuit 260, where the control logic records the number of rising edges or falling edges of the clock signal that generates the crystal oscillator, and generates a digital signal according to the count result until the bias of the overshoot-resistant bias circuit reaches a predetermined value.
The method specifically comprises the steps that the set time is kept unchanged or is changed according to a set rule.
As shown in fig. 4 (a), in one example, the clock signal period is set to 1ns, the cumulative 10 rising edges count to 1, and the target voltage is reached after counting 8 times, and the counter output is changed once every 10ns, and the bias reaches the target value after 80 ns.
As shown in fig. 4 (a) and 4 (b), when the set-up time period of the bias is adjusted based on the period of the clock signal and the cumulative 20 rising edge counts are set to 1 based on the above example, the bias reaches the target value 160ns later, and the time period for setting up the bias in fig. 4 (b) is prolonged with respect to the initial bias in fig. 4 (a).
Furthermore, the more analog signals the count result is, the greater and vice versa.
As shown in fig. 4 (a) and 4 (c), the offset is adjusted based on the number of rising edges, and the count number of the clock signal is reduced, that is, the count is counted up 4 times, that is, the stop count is set, based on the above example, and the offset in fig. 4 (c) is half the initial offset in fig. 4 (a) with respect to the initial offset in fig. 4 (a).
It should be noted that the example is merely illustrative of voltage adjustment, and in the practical application scenario, the voltage adjustment strategy is not limited to these several adjustment modes and combinations thereof, and more complex voltage adjustment strategies can be implemented by the logic control circuit 260 to meet the practical application requirements.
Fig. 5 is a block diagram of a power amplifier circuit according to an embodiment of the invention.
The power amplifier circuit is composed of a clock signal generating circuit 210, a counter circuit 220, a digital-to-analog conversion circuit 230, a bias circuit 240, a power amplifier 250, and a logic control circuit 260.
The clock signal generation circuit 210 is used to generate a high-frequency periodic clock signal.
The counter circuit 220 receives the generated clock signals, counts the number of received clock signals, and generates a set of digital signals in real time according to the count result to the digital-to-analog conversion circuit 230.
The digital-to-analog conversion circuit 230 converts the digital signal to an analog signal and outputs the analog signal to a bias circuit of the power amplifier 260 for adjusting the bias of the power amplifier.
The logic control circuit 260 may control the enabling of the bias circuit 240 and may also control the counter circuit 220 to adjust the enabling and the operating mode of the counter circuit 220.
Fig. 6 (a) is an LDMOS power amplifier circuit implementing logic for an anti-overshoot bias circuit suitable for use in embodiments of the present invention.
The LDMOS is an asymmetric power MOSFET device, and is mainly used in a circuit application requiring lower on-resistance and higher blocking voltage, as shown in fig. 6 (a), the gate of the LDMOS is connected with a bias circuit, and the bias circuit is used for outputting a bias voltage Vbias to the gate so as to control the on-off state of the LDMOS; a capacitor C1 is arranged between the grid electrode and the input end IN, and a resistor R1 is arranged between a bias circuit outputting bias voltage Vbias and the grid electrode; the source electrode of the LDMOS is grounded; the drain electrode of the LDMOS is connected with a power supply end VDD, an inductor L1 is arranged between the power supply end VDD and the drain electrode, and a capacitor C2 is arranged between the output end OUT and the drain electrode.
Fig. 6 (b) is a PowerFET power amplifier circuit implementing logic for an anti-overshoot bias circuit suitable for use with embodiments of the present invention.
Powerfets, which are devices for power output stages, are capable of outputting large operating currents (a few to tens of amps). As shown in fig. 6 (b), a quarter transmission line and a capacitor C5 are connected in series between the control terminal of the PowerFET power amplifier and ground; one end of the voltage regulator Vreg (Voltage Regulator) is connected with the power supply end VDD, the other end of the voltage regulator is connected with the capacitor C4 and then grounded, and a resistor R3 is connected in series between the other end of the voltage regulator and a quarter transmission line; a variable resistor R2 is connected in series between the voltage regulator and the ground; the source of the PowerFET power amplifier is grounded and the drain is connected to a load to output a signal (not shown).
Fig. 6 (c) is an HBT power amplifier circuit implementing logic for an anti-overshoot bias circuit suitable for use in embodiments of the present invention.
An HBT is a type of bipolar transistor in which the emitter and base regions are formed of different semiconductor materials. As shown IN fig. 6 (c), the HBT power amplifier has a base connected to the input terminal IN, a diode and a resistor R6 connected IN series between the base and ground, and a base connected to the power supply terminal VDD with a variable resistor R7 provided therebetween; a resistor R5 and a capacitor C3 which are connected in parallel are arranged between the emitter of the HBT power amplifier and the ground; the collector of the HBT power amplifier is connected with a power end and an output end, and a resistor R4 is arranged between the power end VDD and the collector in series.
The foregoing embodiments are illustrative of current mirror bias circuits, and are merely provided as a specific example of the anti-overshoot bias circuit of the present invention, and the actual bias portion of the anti-overshoot bias circuit is not limited to current mirror bias circuits, and other known voltage bias circuits or current bias circuits can employ the implementation logic of the anti-overshoot technique of the anti-overshoot bias circuit of the present invention. As shown in fig. 6 (a), 6 (b) and 6 (c), the LDMOS power amplifier circuit of fig. 6 (a), the PowerFET power amplifier circuit of fig. 6 (b) and the HBT power amplifier circuit of fig. 6 (c) are all applicable to the logic for implementing the overshoot resistance technique of the overshoot resistance bias circuit according to the embodiment of the present invention.
Claims (12)
1. An overshoot-resistant bias circuit, comprising:
a clock signal generating circuit for generating a clock signal of a set frequency;
a counter circuit connected with the clock signal generating circuit and used for counting according to set control logic, wherein the control logic comprises: recording the number of rising edges or falling edges of the clock signals, and generating digital signals according to the counting result until the overshoot-resistant bias circuit reaches a stable working state;
the digital-to-analog conversion circuit is connected with the counter circuit and is used for converting the digital signals into analog signals, the size of the analog signals is related to the number of the counting results, the counting results are different, and the sizes of the analog signals are different;
and the bias circuit is connected with the digital-to-analog conversion circuit, the analog signal is input to the signal input end of the bias circuit, and the bias signal generated by the bias circuit is higher when the analog signal is higher.
2. The overshoot resistant bias circuit according to claim 1, wherein the recording the number of rising edges or falling edges of the clock signal, generating the digital signal based on the count result comprises:
generating a counting result every time the number of rising edges or falling edges of the set clock signal is recorded, and generating a digital signal according to the counting result; or alternatively
Recording the number of rising edges or falling edges of a clock signal every time a set time passes, generating a counting result, and generating a digital signal according to the counting result, wherein the set time is kept unchanged; or alternatively
The set time is changed according to a set rule.
3. The overshoot resistant bias circuit according to claim 1, wherein the more the count result is, the larger the analog signal is.
4. The overshoot resistant bias circuit according to claim 1, wherein an analog voltage corresponding to a predetermined value enables a bias generated by said bias circuit to be a maximum stable bias;
or the analog voltage corresponding to the preset value can enable the bias generated by the bias circuit to be a set value, and the set value is smaller than the maximum stable bias which can be generated by the bias circuit.
5. The overshoot resistant bias circuit according to claim 1, wherein the clock signal generating circuit multiplexes the clock signal generating circuits in the radio frequency chip in which the overshoot resistant bias circuit is located; or alternatively
The clock signal generation circuit is independently designed.
6. The overshoot resistant bias circuit according to claim 1, wherein the set frequency range corresponds to a period of ns-level.
7. The overshoot resistant bias circuit according to claim 1, wherein the bias circuit comprises a voltage bias circuit or a current bias circuit or an adjustable resistance bias or a diode temperature compensated adjustable resistance bias.
8. The anti-overshoot bias circuit according to claim 1, wherein the anti-overshoot bias circuit is adapted for use in a power amplifier.
9. The overshoot resistant bias circuit according to claim 1, wherein the analog signal is an analog voltage or an analog current;
the bias signal is a bias voltage or bias current.
10. The overshoot resistant bias circuit according to claim 1, further comprising a logic control circuit connected with said counter circuit for generating said setting control logic;
the logic control circuit is also connected with the enabling end of the bias circuit and used for controlling the on-off of the bias circuit.
11. A power amplifier circuit structure, comprising: a power amplifier, and an anti-overshoot bias circuit as set forth in claim 1 for amplifying a signal of the power amplifier.
12. A radio frequency chip, comprising: a radio frequency signal transmitting terminal having the power amplifier circuit structure as claimed in claim 11.
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| CN202311699147.XA CN117394801A (en) | 2023-12-12 | 2023-12-12 | Overshoot-resistant bias circuit, power amplifier circuit structure and radio frequency chip |
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| CN202311699147.XA CN117394801A (en) | 2023-12-12 | 2023-12-12 | Overshoot-resistant bias circuit, power amplifier circuit structure and radio frequency chip |
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| US20110298540A1 (en) * | 2010-06-04 | 2011-12-08 | Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. | System and method for controlling a power amplifier using a programmable ramp circuit |
| US20190058448A1 (en) * | 2017-08-21 | 2019-02-21 | Infineon Technologies Ag | Method and Device for Providing a Bias Voltage in Transceivers |
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2023
- 2023-12-12 CN CN202311699147.XA patent/CN117394801A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5430410A (en) * | 1993-06-30 | 1995-07-04 | Alcatel N.V. | Amplifier bias control system |
| US20110298540A1 (en) * | 2010-06-04 | 2011-12-08 | Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. | System and method for controlling a power amplifier using a programmable ramp circuit |
| US20190058448A1 (en) * | 2017-08-21 | 2019-02-21 | Infineon Technologies Ag | Method and Device for Providing a Bias Voltage in Transceivers |
| CN109428551A (en) * | 2017-08-21 | 2019-03-05 | 英飞凌科技股份有限公司 | For providing the method and apparatus of bias voltage in a transceiver |
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