CN117394692A - Low-power consumption hybrid dual-output DC-DC converter - Google Patents
Low-power consumption hybrid dual-output DC-DC converter Download PDFInfo
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- CN117394692A CN117394692A CN202311701389.8A CN202311701389A CN117394692A CN 117394692 A CN117394692 A CN 117394692A CN 202311701389 A CN202311701389 A CN 202311701389A CN 117394692 A CN117394692 A CN 117394692A
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- operational amplifier
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- 239000003990 capacitor Substances 0.000 claims abstract description 41
- 238000006243 chemical reaction Methods 0.000 claims abstract description 11
- 230000009977 dual effect Effects 0.000 claims description 6
- 238000007599 discharging Methods 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 230000001105 regulatory effect Effects 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a low-power consumption hybrid dual-output DC-DC converter which comprises a conversion module and is characterized by comprising a signal input end, a seventh resistor, an eighth resistor, a first inductor, a first diode, a second capacitor, a second operational amplifier, a first transistor, a second MOS (metal oxide semiconductor) tube and a first signal output end, wherein the signal input end is used as an input source, one end of the seventh resistor is connected with the signal input end, one end of the eighth resistor is connected with the other end of the seventh resistor, one end of the first inductor is connected between the seventh resistor and the eighth resistor, the anode of the first diode is connected with the other end of the first inductor, one end of the second capacitor is connected with the cathode of the first diode, and a first signal output end is arranged between the first diode and the first capacitor.
Description
Technical Field
The invention relates to the field of converters, in particular to a low-power-consumption hybrid double-output DC-DC converter.
Background
At present, a DC-DC converter mainly plays a role in converting one direct current voltage into another direct current voltage to provide power supply voltage for a lower-level circuit or a load, and announces a number; CN214256137U discloses a low power consumption hybrid dual output DC-DC converter which is isolated from a boost converter by a buck converter and regulated by the boost converter so that when a power is input at a power input terminal, it is dropped and used as a reference voltage to obtain a relatively stable input voltage, but the converter cannot be regulated according to the allowable fluctuation deviation of the power voltage required by a lower circuit or a load and automatically gain the output voltage signal while regulating, and cannot reduce the power consumption in a signal dual output state.
Disclosure of Invention
The invention aims to provide a low-power consumption hybrid double-output DC-DC converter, which comprises a conversion module, wherein the conversion module comprises a signal input end, a seventh resistor, an eighth resistor, a first inductor, a first diode, a second capacitor, a second operational amplifier, a first transistor, a second MOS tube and a first signal output end, wherein the signal input end is an input source, one end of the seventh resistor is connected with the signal input end, one end of the eighth resistor is connected with the other end of the seventh resistor, one end of the first inductor is connected between the seventh resistor and the eighth resistor, the anode of the first diode is connected with the other end of the first inductor, one end of the second capacitor is connected with the cathode of the first diode, a first signal output end is arranged between the first diode and the first capacitor, the output end of the second operational amplifier is connected with the base electrode of the first transistor, the collector electrode of the first transistor is connected with the drain electrode of the second MOS tube, the source of the second MOS tube is connected between the first inductor and the anode of the first diode, and the other end of the eighth resistor, the other end of the second capacitor is connected with the emitter of the first transistor and the ground.
Further, the transformation module further comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first operational amplifier and a first capacitor, one end of the first resistor is connected with the signal input end, one end of the second resistor is connected with the other end of the first resistor, the same-phase end of the first operational amplifier is connected between the first resistor and the second resistor, the output end of the first operational amplifier is connected with the same-phase end of the first operational amplifier through the third resistor, the inverting end of the first operational amplifier is connected with the output end of the first operational amplifier through the fourth resistor, one end of the first capacitor is connected between the fourth resistor and the inverting end of the first operational amplifier, and the other end of the second resistor, the other end of the first capacitor and the grounding end are connected.
Further, the conversion module further comprises a fifth resistor and a sixth resistor, one end of the fifth resistor is connected with the signal input end, one end of the sixth resistor is connected with the other end of the fifth resistor, and the other end of the sixth resistor is connected with the grounding end.
Further, the conversion module further comprises a third operational amplifier, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor and a second signal output end, one end of the ninth resistor is connected between the first diode and the second capacitor, one end of the tenth resistor is connected with the other end of the ninth resistor, one end of the eleventh resistor is connected with the signal input end, one end of the twelfth resistor is connected with the other end of the eleventh resistor, a second signal output end is arranged between the eleventh resistor and the twelfth resistor, the same-phase end of the third operational amplifier is connected between the ninth resistor and the tenth resistor, the opposite end of the third operational amplifier is connected between the eleventh resistor and the twelfth resistor, and the output end of the third operational amplifier is connected with the grid electrode of the second MOS tube.
Further, the conversion module further comprises a thirteenth resistor, one end of the thirteenth resistor is connected with the grid electrode of the second MOS tube, and the other end of the thirteenth resistor is connected with the grounding end.
Further, the eighth resistor, the tenth resistor and the twelfth resistor are potentiometers.
Further, the first capacitance is a tunable capacitance.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, the voltage amplitude output by VOUT1 can be improved by adjusting the gain time limit while the voltage amplitude output by VOUT2 is adjusted, the fluctuation deviation of the voltage signal output by VOUT1 is synchronously adjusted in a mode of adjusting the single gain amplitude, and the voltage amplitude output by VOUT1 is secondarily gained while being adjusted, so that the power consumption is reduced in a state of dual output of the VOUT1 and VOUT2 signals.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly explain the drawings needed in the prior art and the embodiments, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an overall structure provided by the present invention.
Detailed Description
In order that the objects and advantages of the invention will become more readily apparent, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings, it being understood that the following text is only intended to describe one or more specific embodiments of the invention and is not intended to limit the scope of the invention as defined in the appended claims.
Referring to fig. 1, in this embodiment, the signal input terminal Vin is an input power signal, the signal between the first resistor R1 and the second resistor R2 is fed back to the space between the non-inverting terminal of the first operational amplifier U1 and the third resistor R3, the output terminal of the first operational amplifier U1 is connected with the non-inverting terminal of the first operational amplifier U1 through the third resistor R3, the signal of the output terminal of the first operational amplifier U1 is divided by the third resistor R3 and the second resistor R2 to the ground loop, meanwhile, the signal of the output terminal of the first operational amplifier U1 is input to the first capacitor C1 through the fourth resistor R4, the potential of the first capacitor C1 rises, the first operational amplifier U1 is cut off, the signal of the first capacitor C1 is fed back to the output terminal loop of the first operational amplifier U1 through the fourth resistor R4, the signal of the signal input terminal Vin is divided by the seventh resistor R7 and the eighth resistor R8, the fluctuation threshold value of the signal amplitude of the VOUT1 can be changed by adjusting the resistance value of the eighth resistor R8, the larger the resistance value of the eighth resistor R8 is, the larger the fluctuation threshold value is, the smaller the fluctuation peak value of the signal amplitude of the VOUT1 is in a high/low state when the resistance value of the eighth resistor R8 is in a high/low state, the resistance value of the eighth resistor R8 can be set according to the allowable fluctuation threshold value of the voltage amplitude required by a load, a power supply signal is connected to a ground loop through an eleventh resistor R11 and a twelfth resistor R12, the twelfth resistor R12 can be set according to the voltage amplitude required by the load, the resistance value of the twelfth resistor R12 is adjusted to enable the VOUT2 to output the required voltage amplitude, the higher the resistance value of the twelfth resistor R12 is, the signal between the first diode D1 and the second capacitor C2 is connected to the ground loop through a ninth resistor R9 and a tenth resistor R10, the signal between the ninth resistor R9 and the tenth resistor R10 is fed back to the same phase end of the third operational amplifier U3, the tenth resistor R10 can be set according to the voltage amplitude required by the load, the resistance of the tenth resistor R10 is regulated to enable VOUT1 to output the required voltage amplitude, the voltage amplitude output by VOUT1 is higher when the resistance of the tenth resistor R10 is lower, the second operational amplifier U2 is cut off, a signal between the seventh resistor R7 and the eighth resistor R8 is transmitted to a grounding end loop through the first inductor L1, the first diode D1, the ninth resistor R9 and the tenth resistor R10, the potential of the second capacitor C2 is increased, signals between the fifth resistor R5 and the sixth resistor R6 are fed back to the inverting end of the second operational amplifier U2, signals between the fifth resistor R5 and the sixth resistor R6 are reference signals, signals at the output end of the first operational amplifier U1 are fed back to the non-inverting end of the second operational amplifier U2, when the first operational amplifier U1 outputs, when the second operational amplifier U2 outputs, signals are fed back to the base electrode of the first transistor Q1, the base electrode of the first transistor Q1 and the emitter electrode of the first transistor Q1 generate forward bias, the first transistor Q1 is conducted, signals pass through the L1, the source electrode of the second MOS transistor Q2, the drain electrode of the second MOS transistor Q2, the collector electrode of the first transistor Q1 and the emitter electrode of the first transistor Q1 to a grounding end loop, when the second operational amplifier U2 is cut off, the first transistor Q1 is cut off, the current of the first inductor L1 enables the potential of the second capacitor C2 to rise again through the first diode D1, the first diode D1 is anti-reverse, at the moment, the signal amplitude of the second capacitor C2 is higher than the signal amplitude between the seventh resistor R7 and the eighth resistor R8, the signal amplitude between the seventh resistor R7 and the eighth resistor R8 can be changed, the single gain amplitude of the second capacitor C2 signals after a single cycle of the output/cut-off of the second operational amplifier U2 is fed back to the third operational amplifier U3 through adjusting the signal amplitude between the eleventh resistor R11 and the twelfth resistor R12, the signal between the ninth resistor R9 and the tenth resistor R10 is fed back to the in-phase end of the third operational amplifier U3, U3 is output, when the output signal of the output end of the third operational amplifier U3 is fed back to the grid electrode of the second MOS tube Q2 and the source electrode of the second MOS tube Q2 cannot reach the conduction pressure difference, the second MOS tube Q2 is cut off, the potential of the second capacitor C2 is reduced, when the potential reduction of the second capacitor C2 leads the signal amplitude obtained by the in-phase end of the third operational amplifier U3 to be smaller than the signal feedback obtained by the inverting end of the third operational amplifier U3, the potential of the second capacitor C2 is increased again when the third operational amplifier U3 is cut off, the feedback amplitude obtained by the inverting end of the third operational amplifier U3 is adjusted while the output voltage of the VOUT2 is adjusted to change the gain time limit of the second capacitor C2, so that the signal amplitude of VOUT1 obtains the gain, the amplitude of the VOUT2 is higher, the gain time limit is longer, the amplitude of the output voltage of VOUT1 is higher, when the twelfth resistor R12 is adjusted to enable the VOUT2 to obtain the required voltage amplitude and the voltage amplitude of the VOUT1 signal does not reach the required voltage amplitude, the resistance value of the tenth resistor R10 is adjusted downwards to enable the VOUT1 signal amplitude to obtain the secondary gain, the voltage amplitude of the VOUT1 signal is improved again, when the twelfth resistor R12 is adjusted to enable the VOUT2 to obtain the required voltage amplitude and the voltage amplitude of the VOUT1 signal is higher than the required voltage amplitude, the resistance value of the tenth resistor R10 is adjusted upwards to enable the voltage amplitude of the VOUT1 signal to be reduced, the voltage amplitude of the required signal can be obtained by adjusting the twelfth resistor R12 according to the requirement, so that the power consumption is reduced under the double-output state, under the condition that the resistance value of the tenth resistor R10 is unchanged, the lower the signal amplitude between the seventh resistor R7 and the eighth resistor R8 is, the smaller the rising amplitude of the second capacitor C2 potential is when the second operational amplifier U2 is cut off, the lower the peak value of the VOUT1 signal is, the higher the signal amplitude between the seventh resistor R7 and the eighth resistor R8 is, the larger the potential rising amplitude of the second capacitor C2 is when the second operational amplifier U2 is turned off, the higher the fluctuation peak value of the VOUT1 signal is, and the resistance of the eighth resistor R8 is set according to the allowable fluctuation threshold of the voltage amplitude of the required signal, so that the power consumption can be further reduced, and the thirteenth resistor R13 is used for discharging the parasitic capacitance of the gate of the second MOS transistor Q2.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (7)
1. The low-power consumption hybrid dual-output DC-DC converter comprises a conversion module and is characterized by comprising a signal input end, a seventh resistor, an eighth resistor, a first inductor, a first diode, a second capacitor, a second operational amplifier, a first third transistor, a second MOS tube and a first signal output end, wherein the signal input end is an input source, one end of the seventh resistor is connected with the signal input end, one end of the eighth resistor is connected with the other end of the seventh resistor, one end of the first inductor is connected between the seventh resistor and the eighth resistor, the anode of the first diode is connected with the other end of the first inductor, one end of the second capacitor is connected with the cathode of the first diode, a first signal output end is arranged between the first diode and the first capacitor, the output end of the second operational amplifier is connected with the base electrode of the first third diode, the collector of the first third diode is connected with the drain electrode of the second MOS tube, the source of the second MOS tube is connected between the first inductor and the anode of the first diode, the other end of the eighth resistor, the emitter of the second capacitor is connected with the ground, the seventh resistor is connected with the emitter of the seventh resistor, the seventh resistor is connected with the emitter of the eighth resistor, the first diode is connected with the first resistor, the first diode and the first diode is connected with the ground, the signal can be amplified by the first capacitor and the first diode is amplified by the first capacitor, the amplitude signal can be amplified by the first capacitor and the amplitude of the first resistor and the first capacitor is adjusted after the signal amplitude is amplified by the first resistor and the amplitude has the amplitude.
2. The low-power hybrid dual-output DC-DC converter of claim 1, wherein the conversion module further comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first operational amplifier, and a first capacitor, one end of the first resistor is connected to the signal input terminal, one end of the second resistor is connected to the other end of the first resistor, the non-inverting end of the first operational amplifier is connected between the first resistor and the second resistor, the output end of the first operational amplifier is connected to the non-inverting end of the first operational amplifier through the third resistor, the inverting end of the first operational amplifier is connected to the output end of the first operational amplifier through the fourth resistor, one end of the first capacitor is connected between the fourth resistor and the inverting end of the first operational amplifier, the other end of the second resistor, the other end of the first capacitor is connected to the ground terminal, the signal between the first resistor and the second resistor is fed back to the non-inverting end of the first operational amplifier, the non-inverting end of the first operational amplifier is connected to the non-inverting end of the first operational amplifier through the third resistor, the first operational amplifier is connected to the non-inverting end of the first operational amplifier, and the signal is fed back to the first capacitor through the first resistor, and the first capacitor is connected to the ground terminal through the first resistor.
3. The low power consumption hybrid dual output DC-DC converter of claim 2 wherein the conversion module further comprises a fifth resistor and a sixth resistor, wherein one end of the fifth resistor is connected to the signal input terminal, one end of the sixth resistor is connected to the other end of the fifth resistor, the other end of the sixth resistor is connected to the ground terminal, the signal between the fifth resistor and the sixth resistor is fed back to the inverting terminal of the second operational amplifier, and the signal amplitude between the fifth resistor and the sixth resistor is the reference signal.
4. The low-power hybrid dual-output DC-DC converter according to claim 1, wherein the conversion module further comprises a third operational amplifier, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, and a second signal output terminal, one end of the ninth resistor is connected between the first diode and the second capacitor, one end of the tenth resistor is connected with the other end of the ninth resistor, one end of the eleventh resistor is connected with the signal input terminal, one end of the twelfth resistor is connected with the other end of the eleventh resistor, the second signal output terminal is disposed between the eleventh resistor and the twelfth resistor, the same phase end of the third operational amplifier is connected between the ninth resistor and the tenth resistor, the opposite end of the third operational amplifier is connected between the eleventh resistor and the twelfth resistor, the output end of the third operational amplifier is connected with the gate of the second MOS transistor, the twelfth resistor is adjusted to make VOUT2 output a desired voltage amplitude, signals between the ninth resistor and the tenth resistor are fed back to the same phase end of the third operational amplifier, and the feedback amplitude of the third operational amplifier is adjusted at the same time when the inverting terminal of the VOUT2 output voltage is adjusted.
5. The low-power hybrid dual-output DC-DC converter of claim 1, wherein the conversion module further comprises a thirteenth resistor, one end of the thirteenth resistor is connected to the gate of the second MOS transistor, the other end of the thirteenth resistor is connected to the ground, and the thirteenth resistor R13 is used for discharging parasitic capacitance of the gate of the second MOS transistor Q2.
6. The low power hybrid dual output DC-DC converter of claim 4 wherein the eighth resistor, tenth resistor, twelfth resistor are potentiometers.
7. The low power hybrid dual output DC-DC converter of claim 1 wherein the first capacitor is an adjustable capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311701389.8A CN117394692B (en) | 2023-12-12 | 2023-12-12 | Low-power consumption hybrid dual-output DC-DC converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311701389.8A CN117394692B (en) | 2023-12-12 | 2023-12-12 | Low-power consumption hybrid dual-output DC-DC converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117394692A true CN117394692A (en) | 2024-01-12 |
| CN117394692B CN117394692B (en) | 2024-03-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311701389.8A Active CN117394692B (en) | 2023-12-12 | 2023-12-12 | Low-power consumption hybrid dual-output DC-DC converter |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08298771A (en) * | 1995-04-26 | 1996-11-12 | Mitsubishi Electric Corp | Current mode controller dc-dc converter |
| US20130294125A1 (en) * | 2012-05-07 | 2013-11-07 | Fuji Electric Co., Ltd. | Control circuit of power supply system |
| DE102012217732A1 (en) * | 2012-09-28 | 2014-04-03 | Siemens Aktiengesellschaft | Pulsed voltage transformer |
| US20140153293A1 (en) * | 2012-11-30 | 2014-06-05 | Chung-Shan Institute Of Science And Technology | Double-Output Half-Bridge LLC Serial Resonant Converter |
| US20160241145A1 (en) * | 2015-02-16 | 2016-08-18 | Tdk Corporation | Control circuit and switching power supply |
-
2023
- 2023-12-12 CN CN202311701389.8A patent/CN117394692B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08298771A (en) * | 1995-04-26 | 1996-11-12 | Mitsubishi Electric Corp | Current mode controller dc-dc converter |
| US20130294125A1 (en) * | 2012-05-07 | 2013-11-07 | Fuji Electric Co., Ltd. | Control circuit of power supply system |
| DE102012217732A1 (en) * | 2012-09-28 | 2014-04-03 | Siemens Aktiengesellschaft | Pulsed voltage transformer |
| US20140153293A1 (en) * | 2012-11-30 | 2014-06-05 | Chung-Shan Institute Of Science And Technology | Double-Output Half-Bridge LLC Serial Resonant Converter |
| US20160241145A1 (en) * | 2015-02-16 | 2016-08-18 | Tdk Corporation | Control circuit and switching power supply |
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| Publication number | Publication date |
|---|---|
| CN117394692B (en) | 2024-03-08 |
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