CN117393634A - Avalanche diode and preparation method thereof - Google Patents

Abstract

The invention relates to an avalanche diode and a preparation method thereof, wherein the avalanche diode comprises a diode main body region and an isolation region formed at the periphery of the diode main body region, the isolation region comprises a deep trench for forming isolation, the diode main body region comprises a PN junction, a light absorption region formed around the PN junction, and a first carrier collection region formed by carrying out ion implantation on the side wall of the light absorption region adjacent to the deep trench. Compared with the prior art, the invention constructs the hole absorption region with deeper depth and uniform doping by means of side wall ion implantation, has simple process, greatly reduces cost, and can increase PDE, reduce DCR and the like.

Description

Avalanche diode and preparation method thereof

Technical Field

The invention belongs to the technical field of diode devices, and relates to an avalanche diode and a preparation method thereof.

Background

Avalanche diodes include APD, which is an abbreviation for avalanche photodiode (Avalanche Photodiode), and SPAD, which is an abbreviation for single photon avalanche diode (Single Photo Avalanche Diode). The SPAD operates on the principle that when a reverse bias voltage (breakdown voltage V _bd+ Overload voltage V _ex ) When the light absorption region absorbs electrons generated by the light signal, the electrons are subjected to reverse bias voltageAvalanche occurs, thereby rapidly amplifying the optical signal, as shown in fig. 1.

The avalanche diode generally needs higher reverse bias voltage when in operation, so that the adjacent pixels are generally isolated by deep trench isolation (deep trench isolation) to play a role in electrical isolation. Meanwhile, SPAD avalanches may be caused by hole avalanches or electron avalanches. In electron avalanche, the hole absorption region is connected to the anode, and holes are collected. In the case of hole avalanches, the original "hole absorption region" will collect electrons.

The structure of the current SPAD and the manufacturing process flow thereof can be seen in fig. 2, and generally are as follows: ion implantation and annealing are performed on different regions of a silicon substrate or silicon epitaxial surface by definition of different photomasks to form the first conductivity type semiconductor 102 and the second conductivity type semiconductor 103 (the conductivity types of the two semiconductors are opposite), the light absorption region 101, the carrier collection structure, the positive electrode and the negative electrode. And defining the position of the isolation region by photoetching, and obtaining a groove through etching the medium and the silicon substrate. The isolation region 117 is then formed by a thermal oxidation growth of silicon oxide (or deposition of a high dielectric constant material), deposition of polysilicon or metal, etc., to form the avalanche diode structure. Next, one or more layers of the insulating layer are deposited over the first conductivity type semiconductor 102. Through-hole contact is formed in the insulating layer by photolithography and etching, then metal is deposited, and then metal is deposited and etched to complete metal connection.

For the hole-absorbing region, there are generally two approaches in the process: (a) As shown in fig. 3, the device comprises a silicon substrate 100, a well layer 101, a first conductive type semiconductor 102, a second conductive type semiconductor 103, a PN junction positive electrode 104, a PN junction negative electrode 105, a masking layer 108 and the like, and after the front surface is subjected to high-energy ion implantation, a carrier absorption region 110a is formed after multiple times of implantation, and the number of times of implantation in the process is up to ten times; (b) As shown in fig. 4, a boron-containing dielectric 118 is deposited in the trench of the device and diffused into the substrate to form a carrier-absorbing region 110b formed by the deposition diffusion. However, both of these approaches have the following problems: (1) The ion implantation has limited energy and limited corresponding implantation depth, namely the depth of a hole collecting area is limited, the ion concentration distribution is uneven, the implantation times are more, the cost is higher, and when the implantation depth is deeper, the ion implantation is performed by the mode with high energy, so that the lattice damage to the substrate is large; (2) The surface is deposited with Si containing boron, the diffusion rate is slower, the process time is longer and the diffusion distance is limited.

Disclosure of Invention

The invention aims to provide an avalanche diode and a preparation method thereof, which are used for forming doping of a carrier collecting region by carrying out ion implantation on the side wall adjacent to a deep trench, so as to obtain a structure with the depth of the carrier collecting region far higher than that of the prior art, and the avalanche diode has the advantages of simple process, greatly reduced cost, uniform doping, greatly improved light detection efficiency of the device, and Si/SiO (silicon/silicon oxide) simultaneously ₂ The holes at the interface are in an accumulated state, so that dark current at the interface can be reduced, and DCR is reduced.

The aim of the invention can be achieved by the following technical scheme:

according to one of the technical schemes, the avalanche diode comprises a diode main body region and an isolation region formed at the periphery of the diode main body region, wherein the isolation region comprises a deep trench for forming isolation, the diode main body region comprises a PN junction, a light absorption region formed around the PN junction and a first carrier collection region formed by carrying out ion implantation on the side wall of the light absorption region, which is adjacent to the deep trench.

Further, the ion implantation direction obliquely intersects the sidewall adjacent to the deep trench.

Further, the sidewall is ion implanted one or more times.

Further, when the number of ion implantation is plural, the ion types are the same or different when different ion implantation are performed, and the directions are the same or different when different ion implantation are performed.

Further, when the side wall ion implantation is performed, when the deep trench is not etched to the surface dielectric layer region and no shallow trench isolation is provided, the ion implantation concentration of the side wall ion implantation region is different from that of the bottom region of the deep trench.

Further, when the side wall ion implantation is performed, when the deep trench is etched to the surface dielectric layer region or shallow trench isolation is provided, the ion implantation concentration of the surface dielectric layer region or the surface of the shallow trench isolation communicated with the deep trench is different from that of the side wall ion implantation region.

Further, the first carrier-collection region is formed adjacent to a single-sided sidewall or multi-sided sidewalls of the deep trench.

Further, the light absorption region is subjected to front ion implantation treatment, and a front ion implantation region adjacent to the positive electrode of the PN junction is formed.

Further, the diode body region is further provided with a dark current reducing structure, which is a functional doped region formed on the semiconductor doped region surrounding the PN junction cathode, the functional doped region is grounded or connected with the PN junction cathode, and the conductivity type of the functional doped region is opposite to that of the semiconductor doped region surrounding the PN junction cathode.

The second technical scheme of the invention provides a preparation method of the avalanche diode, which comprises the following steps:

forming a diode body region and a deep trench;

and performing ion implantation on the side wall of the light absorption region adjacent to the deep trench to form the first carrier collection region.

Compared with the prior art, the invention has the following advantages:

(1) According to the invention, on the basis of deep trenches obtained by DTI etching, ion implantation is carried out on the sidewalls for multiple times, so that doping of a carrier collecting region is formed. The method can obtain a structure with the depth of the carrier collecting region far higher than that of the traditional process, has uniform doping, and can greatly improve the light detection efficiency of the device.

(2) And the technology of side wall injection is utilized on the basis of obtaining the deep groove by DTI etching, so that the technology is simple, the cost is low, and the implementation is easy.

Drawings

FIG. 1 is a schematic diagram of the working principle of SPAD;

FIG. 2 is a schematic diagram of a prior art SPAD;

FIG. 3 is a schematic diagram of a front side ion implantation process for forming a carrier absorbing structure;

FIG. 4 is a schematic diagram of a process for forming a carrier-absorbing structure by deposition and diffusion;

FIG. 5 is a schematic diagram of a prior art and structure of a proprietary ion implantation process;

FIG. 6 is a schematic diagram of the process and structure before the first ion implantation in the patent;

FIG. 7 is a top view of four different rotation angle sidewall ion implantation processes;

FIG. 8 is a schematic diagram of four different rotation angle sidewall ion implantation processes and structures;

FIG. 9 is a schematic diagram of a trench isolation structure;

FIG. 10 is a schematic diagram of a sidewall ion implantation structure without STI on the front surface;

FIG. 11 is a top view of two different rotation angle sidewall ion implantation processes;

FIG. 12 is a top view of a process of forming an avalanche diode by a primary sidewall ion implantation;

FIG. 13 is a schematic diagram of a structure in which an avalanche diode is formed by a primary sidewall ion implantation;

FIG. 14 is a schematic diagram of a sidewall ion implantation configuration for different types of ions;

FIG. 15 is a schematic diagram showing the structure of the combination of sidewall ion implantation and front side ion implantation to adjust the electric field distribution near the positive electrode;

FIG. 16 is a schematic illustration of an increasing and decreasing dark current sidewall ion implantation structure;

fig. 17 is a schematic diagram before and after sidewall ion implantation (color shade in Si represents concentration);

fig. 18 is a region of boron concentration distribution along the horizontal dashed line direction at the DTI side wall in fig. 17;

fig. 19 is a schematic view before and after front side ion implantation;

fig. 20 is a schematic view of ion implantation angles.

Detailed Description

Several concepts of the present invention are explained below:

1) The single photon avalanche diode (Single Photo Avalanche Diode, SPAD) works by applying a reverse bias voltage (breakdown voltage V) _bd+ Overload voltage V _ex ) When the absorption region absorbs electrons generated by the optical signal, the electrons reach the avalanche region under the action of an electric field, and avalanche is initiated in the avalanche region, so that the optical signal is rapidly amplified. SPAD is essentially a reverse biased PN junction when the bias voltage applied to it is of the magnitude of V _bd On the basis of which an overload voltage V is superimposed _ex This PN junction will then operate in Geiger mode. .

2) After avalanche, the reverse bias voltage of the SPAD needs to be controlled to be reduced below the avalanche breakdown voltage, and the SPAD is recovered from the state 2 to the state 3, so that quenching is realized. Then an overload voltage is applied to reach state 1, effecting a reset of SPAD to receive the following photons (see fig. 1).

In addition, dark current: in addition to avalanche initiation by photoelectrons, carriers generated by thermal effects, tunneling effects, and the like (noise pulses) may also initiate avalanche, generating dark current. The corresponding signal Count is referred to as Dark Count Rate (DCR).

Photon detection efficiency: photon Detection Efficiency (PDE) the average probability that a photon will be able to initiate an avalanche and be detected after entering SPAD.

Crosstalk: cross talk, SPAD avalanche, can produce secondary photon when reaching the SPAD unit of surrounding, will have certain probability to initiate avalanche, causes the erroneous count of corresponding unit, is called Crosstalk.

The present invention will be described in detail below with reference to the drawings and the detailed description. The present embodiment is implemented on the premise of the technical scheme of the present invention, and a detailed embodiment and a specific operation process are given, but the protection scope of the present invention is not limited to the following embodiments.

In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In order to obtain a structure in which the depth of the carrier collecting region is much higher than that of the conventional process, and to improve the light detection efficiency of the device, while reducing the production cost and simplifying the production process, etc., the present invention provides an avalanche diode, which may be seen in fig. 6, etc., comprising a diode body region including a deep trench for forming isolation, and an isolation region formed at the periphery of the diode body region, the diode body region including a PN junction, a light absorbing region formed at the periphery of the PN junction, and a first carrier collecting region formed by ion-implanting the side wall of the light absorbing region adjacent to the deep trench, formed at the periphery of the diode body region.

Other parts of the avalanche diode of the present invention not specifically stated are shown as conventional means in the art.

In some embodiments, referring again to fig. 5, the ion implantation direction obliquely intersects the sidewalls adjacent to the deep trench. In a more specific embodiment, the inclined angle range (taking the silicon substrate as a reference plane) can be defined within 30 °, where the inclined angle (i.e., tilt) is defined as the included angle between the ion implantation direction and the normal of the surface of the silicon substrate, and for example, see fig. 20, etc., the dotted line is the projection of the ion beam on the wafer plane; the triangular notch of the wafer is a groove, so that the position of the wafer can be determined; tilt is the angle between the ion beam and the normal of the wafer plane; rotation is the angle between the projection of the ion beam on the wafer plane and the X-axis. For rotation of the implantation process, for example, 45 ° and 135 ° may be used, so that ions are implanted at a specific angle, and ion implantation of all sidewalls can be completed twice. Of course, the angle here may be other values, such as 60 °, etc., according to the actual needs.

In some embodiments, the sidewall is ion implanted one or more times. For example, referring to fig. 7, for a stereoscopic pixel structure, one injection can only inject a portion of the side of the pixel, thus requiring multiple injections. After four ion implants, it is ensured that each side of the picture element has an ion implant. After ion implantation, the dopant ions must be thermally activated. The thermal activation may be achieved by laser annealing or may be combined with the thermal oxygen growth of the deep trenches in the process path, i.e. a separate thermal activation step is omitted. In addition, referring to fig. 12, for less demanding structures, a partial implant, such as a single side implant, may be used.

In a more specific embodiment, when the number of ion implantations is a plurality of times, the ion types are the same or different when different ion implantations are performed, and the directions are the same or different when different ion implantations are performed. Specifically, different types of ions can be injected to adjust the distribution of an electric field inside the pixel and the structure of carrier collection. For example, referring to fig. 14, the third carrier-doped region 114 having the opposite doping type from the first carrier-collecting region 110 formed by the first sidewall ion implantation may be formed by the second sidewall ion implantation.

In some specific embodiments, when the deep trench is not etched to the surface dielectric layer region and no shallow trench isolation is provided, the bottom region of the deep trench is simultaneously ion implanted (and in a subsequent thermal activation process), and at this time, the ion implantation concentration of the sidewall ion implantation region is different from the concentration of the bottom region of the deep trench. Specifically, if the inclined intersection area of the ion beam of ion implantation and the side wall of the deep trench does not reach the bottom of the deep trench, the bottom is not ion implanted, and under the condition, the concentration of the ion implantation area of the side wall is large; and if the inclined intersection area of the ion beam of the ion implantation and the side wall of the deep trench covers the bottom of the deep trench, the bottom ion implantation concentration is large in the case. In addition, when the deep trench is etched to the surface dielectric layer region or the shallow trench isolation is provided at the time of sidewall ion implantation, for example, referring to fig. 9 and 10, the ion implantation concentration of the surface dielectric layer region or the surface of the shallow trench isolation communicating with the deep trench is different from that of the sidewall ion implantation region, and this portion of the ion implantation region is denoted as an ion implantation region 109 (corresponding to the presence of STI) or an ion implantation region 109a (corresponding to the absence of STI).

In some specific embodiments, the first carrier-collecting region 110 is formed adjacent to a single-sided sidewall or multi-sided sidewalls of the deep trench, so that the pixel structure can be selectively partially or fully implanted as required.

In some embodiments, the light absorbing region is further subjected to a front side ion implantation process, and a front side ion implantation region 115 is formed adjacent to the positive electrode 104 of the PN junction, for adjusting the electric field distribution in the vicinity of the positive electrode, as shown in fig. 15.

In some specific embodiments, the light absorbing region is further provided with a dark current reducing structure 116, which is a functional doped region formed on the first conductivity type semiconductor 102 surrounding the PN junction cathode 105, the functional doped region is grounded or connected to the PN junction cathode 105, and the conductivity type of the functional doped region is opposite to that of the first conductivity type semiconductor 102 surrounding the PN junction cathode 105, as shown in fig. 16.

In addition, the invention also provides a preparation method of the avalanche diode, which comprises the following steps:

forming the deep trench on a light absorption region of a diode body region;

and performing ion implantation on the side wall of the light absorption region adjacent to the deep trench to form the first carrier collection region.

It should be noted that there are two process routes for the existing avalanche diode structure (for the back-illuminated picture element). The first is: and (3) injecting the front surface of the wafer to obtain a diode structure in a back-illuminated process path of the main stream, carrying out metal wiring on the surface, carrying out Cu-Cu bonding, then etching to obtain a deep groove, depositing oxide in the deep groove, and filling metal. The second is: injecting the front surface of the wafer to obtain a diode structure, and then etching to obtain a deep trench; and growing the deep groove by hot oxygen, filling metal, carrying out metal wiring on the surface, and then carrying out Cu-Cu bonding. (part of the process of the second process route can be applied in front-lit picture elements.)

The preparation method is mainly based on the existing preparation process of the avalanche diode structure, deep trenches are obtained based on DTI etching, and ion implantation is carried out on the side walls adjacent to the deep trenches for multiple times, so that doping of partial carrier collecting areas is formed. Whereas the functional areas or elements with respect to the other avalanche diode structures can be performed according to existing processes.

The above embodiments may be implemented alone or in any combination of two or more.

The above embodiments are described in more detail below in connection with exemplary embodiments. It should be noted that the following embodiments are described on the basis of a first backside illuminated process, and correspond to a P-type substrate or P-type epitaxy. If the substrate is an N-type substrate or an N-type epitaxy, the doping types of different areas are opposite, the P type is changed into the N type, and the N type is changed into the P type.

Example 1:

for the avalanche diode and the preparation process thereof provided in this embodiment, referring to fig. 5, before sidewall ion implantation, a diode body region is constructed, and at this time, the diode body region includes a silicon substrate 100, a well layer 101, a first conductivity type semiconductor 102 (which is an N-type doped region), a second conductivity type semiconductor 103 (which is a P-type doped region), a positive electrode 104 of a PN junction, a negative electrode 105 of a PN junction, a shallow trench isolation 105 (STI, typically, silicon oxide, to reduce damage to a sidewall of the substrate caused by ion implantation), a carrier collection structure 107 on a back surface, and a masking layer 108 (which may be a photoresist, or a dielectric layer, such as silicon oxide, silicon nitride, or the like, or a combination of both) for sidewall ion implantation. As can be seen from fig. 5, when the sidewall ion implantation is performed, unlike the conventional front-side ion implantation process, the ion implantation direction is inclined at a certain angle with respect to the silicon substrate, so that the doping depth is deep at a lower ion implantation energy, and the damage of the forward high-energy ion implantation to the substrate is avoided. Meanwhile, the ion implantation times are less, the cost is lower, the process is simple, and the doping ions are uniformly distributed.

The topography after the first sidewall ion implantation can be seen in fig. 6, where a first carrier collection region 110 is formed on the diode body region adjacent to the sidewalls of the deep trench. In addition, it should be noted that, while the sidewall ion implantation forms the first carrier-collecting region 110, the upper portion of the shallow trench isolation 106 is also ion-implanted to form the ion-implanted region 109, and the implantation concentration is higher than that of the sidewall ion-implanted region, where the ion-implanted region 109 and the positive electrode 104 of the PN junction have no definite size relationship in width, and the specific size can be adjusted by the photolithography dimension and the ion implantation energy.

In addition, for the three-dimensional pixel structure, only part of the side faces of the pixel can be implanted by one implantation, so that multiple implantations are needed, as shown in fig. 7, the circle represents a wafer, the square represents the pixel, and after four ion implantations, it is ensured that each side face of the pixel is implanted with ions, and after the ion implantations, the doped ions must be thermally activated. In addition, it should be noted that, for the first process route adopted in this embodiment, laser annealing may be used, and if an avalanche diode is prepared by adopting the second process route, the first process route may be combined with thermal oxygen growth of the deep trench, and in the high-temperature environment of the thermal oxygen growth, the doping ions are activated, so that the step of thermal activation is omitted. At this time, a device structure as shown in fig. 8 is formed.

After the sidewall ion implantation is completed, oxide can be grown and filled in the deep trenches, such that the grown oxide can be deposited using ALD atoms, and it should be noted that for the second process route, silicon oxide can also be grown using thermal oxygen because no metal has been deposited at this time. At this time, the deep trench region may be first deposited with a DTI dielectric layer 111 and then deposited with a metal layer 112 to prevent optical crosstalk, where the DTI dielectric layer 111 is used to isolate the substrate from the metal, as shown in fig. 9.

Example 2:

in comparison with embodiment 1, most of the same except that in this embodiment, STI is not present, as shown in fig. 10, at this time, the ions implanted in the sidewall are directly implanted into the dielectric layer 113 on the surface of the pixel, forming an ion implantation region 109a on the dielectric layer on the surface of the pixel, where the ion doping concentration of the implanted surface dielectric layer is higher than that of the sidewall ion implantation region.

Example 3:

compared to example 1, the vast majority are identical, except in this example: referring to fig. 11, sidewall ion implantation can be accomplished twice by tilting a specific angle, e.g., 45 °, 135 °.

Example 4:

most of the same as in example 1, except that in this example, the requirement for ion implantation is lower because of the lower requirement for device performance, and at this time, as shown in fig. 12, a partial implantation method, for example, ion implantation is performed on only a single side, and the resulting device structure is shown in fig. 13.

Example 5:

in comparison with embodiment 1, most of the same is achieved, except that in this embodiment, the sidewall ion implantation is performed a plurality of times on each side, and the type of the implanted ions is also different, so that, as shown in fig. 14, the device structure obtained in this embodiment forms a doped region 114 having a doping type opposite to that of the first carrier collecting region 110 formed by the first sidewall ion implantation.

Example 6:

most of the same as in embodiment 1, the carrier collection region of the sidewall and the front side ion implantation process are combined to form a front side ion implantation region 115 of the positive electrode adjacent to the PN junction for adjusting the electric field distribution in the vicinity of the positive electrode, as shown in fig. 15, except for the present embodiment.

Example 7:

in comparison with embodiment 1, the structure is largely the same except that in this embodiment, a dark current reducing structure is added to SPAD, as shown in fig. 16, specifically, a P-type doped region 116 is formed in the middle region of the first conductivity type semiconductor 102, and at this time, the negative electrode 105 of the corresponding PN junction is located beside the P-type doped region 116. The P-doped region 116 is grounded or connected to a negative electrode, which can act as a collection region for holes, reducing dark current on the substrate surface and in high field areas.

When the SPAD avalanche is caused by the hole avalanche, the doping types of the first conductivity type semiconductor 102 and the second conductivity type semiconductor 103 are opposite to the above, that is, when the first conductivity type semiconductor 102 is a P-type doped region and the second conductivity type semiconductor 103 is an N-type doped region, the P-type doped region 116 is correspondingly adjusted to be an N-type doped region, and the polarities and positions of the positive electrode and the negative electrode of the PN junction are correspondingly adjusted,

example 8:

based on the structure of example 1, this example selects a boron concentration of 1×10 ¹⁴ cm ^-3 A DTI (i.e., deep trench) is made in Si of (1X 10) and then sidewall ion implantation is performed ¹⁵ cm ^-2 The boron implantation angle rotation=90°, tilt=5°, resulting in the structure shown in fig. 17, wherein the left graph is before ion implantation and the right graph is after ion implantation, and it can be seen from the graph that the DTI bottom is also ion implanted, forming a depth of 8um at an ion implantation energy of 500keV, which is far from that achieved by front ion implantation. And meanwhile, the carrier collecting structure on the side surface of the whole device can be formed by four times of injection. In the simulation of front side ion implantation, as shown in fig. 19, the implantation times are up to 17, and the highest implantation energy of front side ion implantation is 7MeV (14 times of sidewall implantation), so that high energy implantation can increase substrate lattice damage, reduce device performance, and simultaneously present a great challenge for blocking the ion beam by the masking layer and photoresist.

Fig. 18 shows the boron concentration profile of the DTI sidewall device along the dashed line after the above process, and it can be seen that, overall, the boron doping concentration gradually decreases from the sidewall to the inside of the device after annealing.

The previous description of the embodiments is provided to facilitate a person of ordinary skill in the art in order to make and use the present invention. It will be apparent to those skilled in the art that various modifications can be readily made to these embodiments and the generic principles described herein may be applied to other embodiments without the use of the inventive faculty. Therefore, the present invention is not limited to the above-described embodiments, and those skilled in the art, based on the present disclosure, should make improvements and modifications without departing from the scope of the present invention.

Claims (10)

1. An avalanche diode comprising a diode body region and an isolation region formed at the periphery of the diode body region, the isolation region comprising a deep trench for forming isolation, the diode body region comprising a PN junction, a light absorbing region formed around the PN junction, and a first carrier collection region formed by ion implanting a sidewall of the light absorbing region adjacent to the deep trench.

2. The avalanche diode according to claim 1 wherein the ion implantation direction obliquely intersects the sidewall adjacent to said deep trench.

3. The avalanche diode according to claim 1 wherein said sidewall is ion implanted one or more times.

4. The avalanche diode according to claim 3, wherein when the number of ion implantation is plural, ion types are the same or different at different ion implantation times, and directions are the same or different at different ion implantation times.

5. The avalanche diode according to claim 1, wherein when the deep trench is not etched to the surface dielectric layer region and no shallow trench isolation is provided, the ion implantation concentration of the sidewall ion implantation region is different from the concentration of the bottom region of the deep trench.

6. The avalanche diode according to claim 1, wherein when the side wall ion implantation is performed, when the deep trench is etched to the surface dielectric layer region or the shallow trench isolation is provided, the ion implantation concentration of the surface dielectric layer region or the surface of the shallow trench isolation communicating with the deep trench is different from the ion implantation concentration of the side wall ion implantation region.

7. The avalanche diode according to claim 1, wherein said first carrier collection region is formed on a single side wall or multiple side walls adjacent to said deep trench.

8. The avalanche diode according to claim 1, wherein said light absorbing region is further subjected to a front side ion implantation process and forms a front side ion implantation region adjacent to a positive pole of said PN junction.

9. The avalanche diode according to claim 1, wherein said diode body region is further provided with a dark current reducing structure which is a functional doped region formed on a semiconductor doped region surrounding said PN junction cathode, said functional doped region being grounded or connected to said PN junction cathode and having a conductivity type opposite to that of said semiconductor doped region surrounding said PN junction cathode.

10. The method of manufacturing an avalanche diode according to any one of claims 1 to 9, comprising:

forming a diode body region and a deep trench;

and performing ion implantation on the side wall of the light absorption region adjacent to the deep trench to form the first carrier collection region.