CN117393565A - Semiconductor device and method of forming the same - Google Patents

Abstract

The device comprises: a stack of semiconductor nanostructures; a gate structure surrounding the semiconductor nanostructure, the gate structure extending in a first direction; source/drain regions adjoining the gate structure and the stack in a second direction transverse to the first direction; a contact structure on the source/drain region; a backside conductive trace located under the stack, the backside conductive trace extending in a second direction; a first via extending vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure adjacent to the first via in the second direction. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Semiconductor device and method of forming the same

Technical Field

Embodiments of the present application relate to semiconductor devices and methods of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such scaled down processes generally provide benefits by improving production efficiency and reducing associated costs. This shrinking also increases the complexity of processing and manufacturing ICs.

Disclosure of Invention

Some embodiments of the present application provide a semiconductor device including: a stack of semiconductor nanostructures; a gate structure surrounding the semiconductor nanostructure, the gate structure extending in a first direction; source/drain regions adjoining the gate structure and the stack in a second direction transverse to the first direction; a contact structure located on the source/drain region; a backside conductive trace located under the stack, the backside conductive trace extending in the second direction; a first via extending vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure adjacent to the first via in the second direction.

Further embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a vertical stack of nanostructure channels over a substrate; forming source/drain regions adjacent to the nanostructure channel; forming a gate structure surrounding the nanostructure channel and extending in a first direction across the nanostructure channel; forming a first opening extending through the gate structure; forming a gate isolation structure in the first opening; forming a second opening adjacent to the gate isolation structure in the second direction; forming a first through hole in the second opening; forming a contact structure in contact with the first via structure and the source/drain region; and forming a backside conductive trace in contact with the first via.

Still further embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a vertical stack of nanostructure channels over a substrate; forming source/drain regions adjacent to the nanostructure channel; forming a gate structure surrounding the nanostructure channel; forming a first via adjacent to the gate structure and a second via adjacent to the gate structure, the first via and the second via being located on opposite sides of the gate structure; forming a contact structure having an underside in contact with the source/drain regions and the first via; and forming respective backside conductive members in contact with the first and second vias.

Drawings

The various aspects of the embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A to 1C are schematic perspective views of portions of an IC device according to an embodiment of the present disclosure.

Fig. 2A-11 are views of an IC device at various stages of manufacture in accordance with aspects of an embodiment of the present disclosure.

Fig. 12-29 are views of various embodiments of an IC device at various stages of forming a via, in accordance with various embodiments.

Fig. 30A to 30F are schematic perspective views of an IC device according to various embodiments.

Fig. 31A-31F are schematic cross-sectional side views of vias according to various embodiments.

Fig. 32 is a flowchart illustrating a method of fabricating a semiconductor device according to aspects of an embodiment of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure embodiments. These are, of course, merely examples and are not intended to limit the disclosed embodiments. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, embodiments of the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as "under …," "under …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Embodiments of the present disclosure relate generally to semiconductor devices, and more particularly to Field Effect Transistors (FETs), such as planar FETs, three-dimensional fin-line FETs (finfets), or nanostructured devices. Examples of nanostructure devices include full Gate (GAA) devices, nanoflake FETs (NSFETs), nanowire FETs (NWFETs), and the like. In prior art nodes, as Integrated Circuit (IC) devices shrink, routing signal lines and power lines (or rails) at the front side of the substrate becomes increasingly challenging. As scaling down, the spacing for the interconnects decreases, thereby increasing the difficulty of power rail design. For example, the power rails may be narrower to increase the spacing of the signal lines, which increases resistance and reduces power efficiency.

The embodiments disclosed herein provide power from the back side of the IC device, which improves front side signal routing flexibility and allows for the formation of wired power rails, which reduces resistance and increases power efficiency. Embodiments include vias that enable backside power delivery and improve front side signal routing spacing. In some embodiments, power Vias (PV) and Signal Vias (SV) are designed to electrically connect source/drain contacts (or "MD") to corresponding traces of a backside metal layer, such as the lowest backside metal layer (or "BM 0"), other backside interconnect features, such as conductive traces and vias, may be stacked on higher backside metal layers (e.g., BM1, BM2, BM3, BM 4) to provide routing of power lines, signal lines, or both on the backside of the IC device.

Embodiments disclosed herein provide a method of manufacturing a power via. In some embodiments, the via is formed from the front side by depositing conductive material of the via in an opening formed prior to forming the source/drain contacts. In some embodiments, the openings are formed from the backside, and then the vias are formed from the backside by depositing a conductive material in the openings. In some embodiments, a first opening is formed from the front side, a dielectric plug is formed in the first opening, a second opening is formed from the back side by removing the dielectric plug, and a via is formed by depositing a conductive material in the second opening from the back side.

Fig. 1A, 1B illustrate portions of an IC device 10 according to various embodiments. Fig. 1A is a schematic perspective view of a front side up-oriented portion of an IC device 10 according to various embodiments. Fig. 1B is a schematic perspective view of a portion of the back side of IC device 10 oriented upward in accordance with various embodiments.

In fig. 1A, the nanostructure device 20 is located at a region where the nanostructure channel 22 has a gate structure 200 wrapped around it, and is adjacent to the source/drain regions 82 on either side. Source/drain regions may refer to either source or drain, either individually or collectively depending on the context. Nanostructure device 20 may include an n-type transistor, a p-type transistor, or both. The IC unit including nanostructure device 20 may include other integrated devices such as integrated capacitors, integrated resistors, integrated inductors, integrated diodes, and the like.

Vias 250, 254 are located in IC device 10. The via 254 may be a power via 254 and may electrically connect one or more of the source/drain regions 82 at the front side of the IC device 10 with a power line 380 at the back side of the IC device 10. For example, source/drain regions 82 may be in contact with source/drain contacts 120, source/drain contacts 120 are in contact with power via 254, and power via 254 is in contact with power line 380. Additional source/drain regions 82 may be coupled to power via 254 by front side power line 280, as shown in fig. 1A. The inclusion of power line 380 and front side power line 280 facilitates reducing resistance, increasing current, and increasing speed.

The vias 250 may be signal vias 250 and may electrically connect one or more of the source/drain regions 82 at the front side of the IC device 10 with signal pads or signal lines 250E at the back side of the IC device 10. For example, the source/drain regions 82 may contact the source/drain contacts 120, the source/drain contacts 120 contact the signal vias 250, and the signal vias 250 contact the signal pads 250E. In some embodiments, the source/drain contacts 120 may be in electrical contact with the signal vias 250 through optional connection traces 450, as shown in dashed lines in fig. 1A. The connection trace 450 may be disposed in the same metal layer as the front side power line 280 is disposed in. The signal vias 250 are advantageous in many respects, including larger areas at the back side of the IC device 10 for transmitting signals, elimination or reduction of complex routing, and increased speed. The signal vias 250 may be particularly advantageous for "line-dominated cells" that transmit signals over relatively long distances. Instead of connecting up on the front side of IC device 10, this involves reducing the wiring complexity by connecting to complex wiring that passes through many metal layers (e.g., 8 or more metal layers) to signal vias 250. Other cells (such as "gate-dominated cells") may be routed on the front side of IC device 10 without being connected to signal vias 250 because the signal paths included therein may be relatively short. IC device 10 may include gate-dominated cells, line-dominated cells, or a combination thereof.

In some embodiments, the vias 250, 254 are or include one or more of W, ru, co, cu, mo, etc. The vias 250, 254 may include one or more glue layers, which may be TaN, tiN, or the like. In some embodiments, the glue layer is omitted such that the metallic material of the vias 250, 254 is in direct contact with their adjacent components. The glue layer may be disposed on and along the sidewalls of the metal material of the vias 250, 254.

The height of the vias 250, 254 (e.g., in the Z-axis direction) may be in the range of about 60nm to about 180nm, which may be selected by a Chemical Mechanical Polishing (CMP) operation on the front side and a wafer thinning operation on the back side.

The length of power via 254 (e.g., in the X-axis direction) may be a multiple of the minimum gate pitch (CPP) of IC device 10. A multiple of the minimum gate pitch (CPP) may refer to the number of gate structures 200 traversed by the power vias 254. CPP may be, for example, 20 nanometers (nm), 16nm, 10nm, 7nm, 5nm, 3nm, 2nm, 1.4nm, 1nm, or another suitable dimension. In some embodiments, the length of power via 254 is in the range of about 0.5CPP to about 24 CPP. The width of the power supply via 254 (e.g., in the Y-axis direction) may be in the range of about 10nm to about 40 nm.

Signal vias 250 are disposed within the IC unit and facilitate providing a low resistance signal path for transmitting signals from the front side of IC device 10 to the back side of IC device 10. The length of the signal via 250 may be in the range of about 1CPP to about 10 CPP. The width of the signal via 250 may be in the range of about 10nm to about 150 nm.

Fig. 1C shows a schematic cross-sectional side view of a portion of an IC device 10 fabricated in accordance with an embodiment of the present disclosure, wherein IC device 10 includes a nanostructure device 20, such as nanostructure devices 20A, 20B, 20C. In some embodiments, nanostructure device 20 may be an n-type FET (NFET), a p-type FET (PFET), or both. Integrated circuit devices such as IC device 10 typically include transistors having different threshold voltages based on their function in the IC device. For example, input/output (IO) transistors typically have the highest threshold voltage because IO transistors require high current handling. The core logic transistors typically have the lowest threshold voltage to achieve higher switching speeds at lower operating powers. The third threshold voltage between the threshold voltage of the IO transistor and the threshold voltage of the core logic transistor may also be used for some other functional transistor, such as a Static Random Access Memory (SRAM) transistor. Some circuit blocks within IC device 10, such as one or more of IC units 100A-100C, may include two or more NFETs and/or PFETs of two or more different threshold voltages.

The cross-sectional view of IC device 10 in fig. 1C is taken along the X-Z plane, where the X direction is the horizontal direction and the Z direction is the vertical direction. Nanostructure device 20A is described in detail as an illustrative example. The nanostructure devices 20B, 20C may be similar or identical in all or most respects to the nanostructure device 20A.

The nanostructure device 20A includes channels 22A1, 22B1, 22C1 (alternatively referred to as "nanostructure 22" or "channel 22") over optional fin structures 32. In some embodiments, fin structure 32 is removed along with substrate 110 during backside processing (see, e.g., fig. 28).

The channel 22 is laterally adjacent to the source/drain regions 82 and is covered and surrounded (or "surrounded") by the gate structure 200. The gate structure 200 controls the flow of current through the channel 22 based on the voltage applied at the gate structure 200 and at the source/drain regions 82. The threshold voltage is the voltage (e.g., gate-to-source voltage or source-to-gate voltage) below which a negligible current flows through the channel 22, while above which a significant current (e.g., several orders of magnitude greater current) flows through the channel 22. Voltages at or above the threshold voltage establish a conductive path in channel 22. Threshold voltage adjustment may be implemented during fabrication of various transistors (e.g., IO transistors, core logic transistors, and SRAM transistors), for example, during fabrication of gate structure 200.

In some embodiments, fin structure 32 comprises silicon. In some embodiments, nanostructure device 20 is an NFET and its source/drain regions 82 comprise silicon-phosphorus (SiP). In some embodiments, nanostructure device 20 is a PFET and its source/drain regions 82 comprise silicon germanium (SiGe). In some embodiments, NFETs and PFETs include source/drain regions 82 of the same material with different doping levels to achieve the operating characteristics of the NFETs or PFETs. In some embodiments, the source/drain regions 82 comprise one or more of SiGeB, siP, siAs, siGe or another suitable semiconductor material. In some embodiments, the source/drain regions 82 have a width (e.g., in the Y-axis direction) in the range of about 0.5nm to about 100nm (see fig. 1B). In some embodiments, the height (e.g., in the Z-axis direction) of the source/drain regions 82 is in the range of about 0.1nm to about 100 nm. The height of the source/drain regions 82 may be measured from the interface between the respective source/drain regions 82 and the fin 32 on which the respective source/drain regions 82 are disposed to the top of the source/drain regions 82. In some embodiments, a bottom isolation layer 84 is disposed between the source/drain regions 82 and the underlying fin structure 32. The bottom isolation layer 84 may be a layer of dielectric material including an organic dielectric or an inorganic dielectric, such as a low-k dielectric or a high-k dielectric.

Channel 22 comprises a semiconductor material, such as silicon or a silicon compound, such as silicon germanium or the like. The channels 22 are nanostructures (e.g., having dimensions in the range of a few nanometers) and may also each have an elongated shape and extend in the X-direction. In some embodiments, the channel 22 has a Nanowire (NW) shape, a Nanoplatelet (NS) shape, a Nanotube (NT) shape, or other suitable nanoscale shape. The cross-sectional profile of the channel 22 (e.g., in the Y-Z plane) may be rectangular, circular, square, annular, oval, hexagonal, or a combination thereof.

In some embodiments, the lengths of the channels 22 (e.g., measured in the X-axis direction) may be different from one another, for example due to tapering during an etching process that forms the fin structures 32. In some embodiments, the length of channel 22A1 may be less than the length of channel 22B1, and the length of channel 22B1 may be less than the length of channel 22C 1. The channels 22 may not have a uniform thickness, for example, due to a channel trimming process for expanding the spacing between the channels 22 (e.g., measured in the Z-direction) to increase the manufacturing process window for forming the gate structure 200. For example, a middle portion of each of the channels 22 may be thinner than both ends of each of the channels 22. Such shapes may be collectively referred to as "dog bone" shapes.

In some embodiments, the spacing between channels 22 (e.g., between channel 22B1 and channel 22A1 or channel 22C 1) is in the range of about 8 nanometers (nm) to about 12 nm. In some embodiments, the thickness of each of the channels 22 (e.g., measured in the Z-direction) is in the range of about 5nm to about 8nm. In some embodiments, the width of each of the channels 22 (e.g., measured in the Y direction perpendicular to the X-Z plane, not shown in fig. 1C) is at least about 8nm.

The gate structures 200 are disposed over the channels 22 and between the channels 22, respectively. In some embodiments, threshold voltage adjustment is achieved by driving at least one specific dopant into one or more high-k gate dielectric layers 610 of gate structure 200. In some embodiments, threshold voltage adjustment is alternatively or further achieved by adding one or more barrier layers (also referred to as "work function barrier layers") in the work function metal layer between the high-k gate dielectric layer 610 and the metal core layer 290.

A first Interface Layer (IL) 210, which may be an oxide of the material of the channel 22, is disposed on the exposed regions of the channel 22 and the top surface of the fin 32 (when present). The first IL layer 210 promotes adhesion of the gate dielectric layer 610 to the channel 22. In some embodiments, the first IL layer 210 has a thickness of about 5 angstroms (a) to about 50 angstroms (a). In some embodiments, the first IL layer 210 has a thickness of about 10A. The first IL layer 210 having too thin a thickness may exhibit voids or insufficient adhesion. The too thick first IL layer 210 consumes gate fill windows, which is related to threshold voltage adjustment and resistance as described above.

In some embodiments, gate dielectric layer 610 comprises a high-k gate dielectric material, which may refer to a dielectric material having a high dielectric constant greater than that of silicon oxide (k≡3.9). ExampleThe high-k dielectric material comprises HfO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO ₂ 、Ta ₂ O ₅ 、LaO _x 、AlO _x Or a combination thereof. In some embodiments, the gate dielectric layer 610 includes a dopant at a concentration that achieves threshold voltage adjustment, such as from La ₂ O ₃ 、MgO、Y ₂ O ₃ 、TiO ₂ 、Al ₂ O ₃ 、Nb ₂ O ₅ Or from B ₂ O ₃ Driven boron ions.

The gate structure 200 may include one or more work function metal layers, such as an N-type work function metal layer, an in-situ capping layer, and an oxygen barrier layer. The gate structure 200 also includes a metal core layer 290. Work function metal layers may be included in the metal core layer 290. The metal core layer 290 may comprise a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. Between the channels 22, the metal core layer 290 is circumferentially surrounded (in cross-section) by a gate dielectric layer 610.

Referring to fig. 1C, the distance D1 (e.g., in the X-axis direction) between adjacent stacks of nanostructures 22 may be in the range of about 0.5nm to about 100 nm.

The nanostructure device 20A also includes gate spacers 41 and internal spacers 74 disposed on sidewalls of the gate dielectric layer 610. An inner spacer 74 is also disposed between channels 22A1-22C 1. The gate spacers 41 and the inner spacers 74 may comprise a dielectric material, for example a low-k material such as SiOCN, siON, siN, SICN, siO or SiOC.

Nanostructure device 20A includes an interlayer dielectric (ILD) 130 and an Etch Stop Layer (ESL) 131.ILD 130 and ESL 131 provide electrical isolation between the various components of nanostructure device 20, for example between gate structure 200 and source/drain contact 120.

The nanostructure device 20A is electrically connected to (e.g., in physical contact with) a source/drain contact 120 disposed over the source/drain region 82. The source/drain contacts 120 may comprise a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, taN, tiN, or combinations thereof. The source/drain contacts 120 may be laterally surrounded by a barrier layer (not shown), such as SiN or TiN, which helps prevent or reduce diffusion of material from the source/drain contacts 120 or into the source/drain contacts 120. Silicide layer 118 may also be formed between source/drain regions 82 and source/drain contacts 120 to reduce the source/drain contact resistance. The silicide layer 118 may comprise a metal silicide material, such as cobalt silicide in some embodiments, or TiSi in some other embodiments. The height of the source/drain contacts 120 (e.g., in the Z-axis direction) may be in the range of about 3nm to about 150 nm. The source/drain contacts 120 may extend through the first ILD 140 and the first ESL 141 and through the ILD 130 and the etch stop layer 131.

An optional conductive cap layer 204 may be disposed on an upper surface of the gate structure 200. The conductive cover layer 204 may include one or more of the conductive materials described above for the metal core layer 290. The gate via 184 may be in contact with the gate structure 200, or alternatively in contact with the conductive cap layer 204, and may include one or more of the conductive materials described above for the metal core layer 290. The first ESL 141 may be located above the conductive cap layer 204 and in contact with the conductive cap layer 204. The second ILD 150 and the second ESL 151 may be disposed on the first ILD 140. The gate via 184 may extend through the second ILD 150, the second ESL 151, the first ILD 140, and the first ESL 141. Source/drain vias 183 may extend through the second ILD 150 and the second ESL 151 to contact the source/drain contacts 120.

The third ILD 160 may be located on the second ILD 150. An optional third ESL may be present between the third ILD 160 and the second ILD 150 and is not shown for simplicity. The front side power line 280 may be disposed in the third ILD 160 and may contact one or more of the source/drain vias 183, one or more of the gate vias 184, or both.

In some embodiments, ILD 130, first ILD 140, second ILD 150, and third ILD 160 may comprise one or more of silicon dioxide, carbon doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated Silicate Glass (FSG), porous dielectric material, and the like. The ESL 131, the second ESL 141, and the third ESL 151 may be formed of silicon nitride, silicon carbonitride, or the like.

Fig. 32 illustrates a flow diagram of a method 1000 for forming an IC device or portion thereof from a workpiece in accordance with one or more aspects of an embodiment of the disclosure. Method 1000 is merely an example and is not intended to limit the disclosed embodiments to what is explicitly shown in method 1000. Additional steps may be provided before, during, and after method 1000, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the methods. For example, the vias 250, 254 may be formed from the front side (e.g., before the source/drain contacts 120 are formed) or from the back side (e.g., after the source/drain contacts 120 are formed). For simplicity, not all steps are described in detail herein. The method 1000 is described below in connection with partial cross-sectional views (shown in fig. 2A-11 and 12-29) of a workpiece at various stages of manufacture in accordance with an embodiment of the method 1000. For the avoidance of doubt, throughout all of the drawings, the X-direction is perpendicular to the Y-direction, and the Z-direction is perpendicular to the X-direction and the Y-direction. It should be noted that because the workpiece may be fabricated as a semiconductor device, the workpiece may be referred to as a semiconductor device, depending on the context.

Fig. 2A-11 are schematic perspective and cross-sectional side views of intermediate stages in the fabrication of a nanostructure device that includes a channel 22, source/drain regions 82, and a gate structure 200, in accordance with some embodiments. Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A show perspective views. Fig. 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B illustrate reference sections B-B' (gate cuts) shown in fig. 2A, 3A, and 4A. Fig. 4C, 5C, 6C, 7C, 8C, 9C, 10C, and 11 illustrate reference cross-sections C-C' (channel/fin cut) shown in fig. 4A.

In fig. 2A and 2B, a substrate 110 is provided. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with a p-type dopant or an n-type dopant) or undoped. The semiconductor material of the substrate 110 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof. Other substrates may be used, such as single layer substrates, multi-layer substrates, or gradient substrates.

Further, in fig. 2A and 2B, a multi-layer stack 25 or "lattice" is formed over the substrate 110 of alternating layers of first semiconductor layers 21A-21C (collectively first semiconductor layers 21) and second semiconductor layers 23. In some embodiments, the first semiconductor layer 21 may be formed of a first semiconductor material suitable for an n-type nano-FET, such as silicon, silicon carbide, etc., and the second semiconductor layer 23 may be formed of a second semiconductor material suitable for a p-type nano-FET, such as silicon germanium, etc. Each of the layers of the multi-layer stack 25 may be epitaxially grown using a process such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), vapor Phase Epitaxy (VPE), molecular Beam Epitaxy (MBE), or the like.

Three layers of each of the first semiconductor layer 21 and the second semiconductor layer 23 are shown. In some embodiments, the multi-layer stack 25 may include one or two of each of the first semiconductor layer 21 and the second semiconductor layer 23 or four or more of each. For example, the IC device 10 shown in fig. 1A-1C includes stacks of nanostructured channels 22, each stack having three channels 22. Although the multilayer stack 25 is shown as including the second semiconductor layer 23 as the bottommost layer, in some embodiments, the bottommost layer of the multilayer stack 25 may be the first semiconductor layer 21.

Due to the high etch selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material may be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby allowing the first semiconductor layer 21 to be patterned to form the channel region 22 of the nano-FET. In some embodiments, the first semiconductor layer 21 is removed and the second semiconductor layer 23 is patterned to form the channel region 22. The high etch selectivity allows the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, thereby allowing the second semiconductor layer 23 to be patterned to form the channel region 22 of the nano-FET.

In fig. 3A and 3B, a fin or "fin structure" 32 is formed in a substrate 110 and nanostructures 22, 24 are formed in a multi-layer stack 25, corresponding to operation 1100 of fig. 32. In some embodiments, the nanostructures 22, 24 and fins 32 may be formed by etching trenches in the multilayer stack 25 and the substrate 110. The etching may be any acceptable etching process, such as Reactive Ion Etching (RIE), neutral Beam Etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. The first nanostructures 22A-22D (hereinafter also referred to as "channels") are formed by the first semiconductor layer 21, and the second nanostructures 24 are formed by the second semiconductor layer 23. The distance CD1 between adjacent fins 32 and nanostructures 22, 24 may be from about 18nm to about 100nm, although other distances CD1 less than 18nm or greater than 100nm are also embodiments contemplated herein.

The fins 32 and nanostructures 22, 24 may be patterned by any suitable method. For example, one or more photolithographic processes (including double patterning or multiple patterning processes) may be used to form the fins 32 and the nanostructures 22, 24. Typically, double patterning or multiple patterning processes combine photolithography and self-aligned processes, allowing for a pitch smaller than that obtainable using a single, direct photolithography process. As an example of a multiple patterning process, a sacrificial layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and then the remaining spacers may be used to pattern the fins 32.

Fig. 3A and 3B illustrate fins 32 having tapered sidewalls such that the width of each of the fins 32 and/or nanostructures 22, 24 continuously increases in a direction toward the substrate 110. In such embodiments, each of the nanostructures 22, 24 may have a different width and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered) such that the width of the fin 32 and the nanostructures 22, 24 are substantially similar, and each of the nanostructures 22, 24 is rectangular in shape.

In fig. 3A and 3B, isolation regions 36 are formed adjacent to fin 32 after forming the trenches, and isolation regions 36 may be Shallow Trench Isolation (STI) regions. Isolation region 36 may be formed by depositing an insulating material over substrate 110, fins 32, and nanostructures 22, 24, and between adjacent fins 32 and nanostructures 22, 24. The insulating material may be an oxide such as silicon oxide, nitride, or the like, or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. In some embodiments, a liner (not separately shown) may first be formed along the surfaces of the substrate 110, fin 32, and nanostructures 22, 24. Thereafter, a filler or core material, such as those discussed above, may be formed over the liner.

The insulating material is subjected to a removal process, such as a Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, or the like, to remove excess insulating material over the nanostructures 22, 24. After the removal process is complete, the top surfaces of the nanostructures 22, 24 may be exposed and level with the insulating material.

The insulating material is then recessed to form isolation regions 36. After recessing, the nanostructures 22, 24 and upper portions of the fins 32 may protrude from between adjacent isolation regions 36. The isolation region 36 may have a planar (as shown), convex, concave, or a combination thereof top surface. In some embodiments, isolation region 36 is recessed by an acceptable etching process, such as oxide removal using, for example, dilute hydrofluoric acid (dHF), which is selective to the insulating material and leaves fin 32 and nanostructures 22, 24 substantially unchanged.

Fig. 2A-3B illustrate one embodiment (e.g., post etch) of forming fins 32 and nanostructures 22, 24. In some embodiments, the fins 32 and/or nanostructures 22, 24 are epitaxially grown in trenches in the dielectric layer (e.g., a "pre-etch" process). The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material.

Furthermore, in fig. 3A and 3B, suitable wells (not separately shown) may be formed in fin 32, nanostructures 22, 24, and/or isolation region 36. Using the mask, an n-type impurity implantation may be performed in the p-type region of the substrate 110, and a p-type impurity implantation may be performed in the n-type region of the substrate 110. Exemplary n-type impurities may include phosphorus, arsenic, antimony, and the like. Exemplary p-type impurities may include boron, boron fluoride, indium, and the like. An anneal may be performed after implantation to repair the implant damage and activate the p-type and/or n-type impurities. In some embodiments, in-situ doping during epitaxial growth of the fin 32 and the nanostructures 22, 24 may avoid separate implants, but in-situ doping and implant doping may be used together.

In fig. 4A-4C, a dummy or sacrificial gate structure 40 is formed over fin 32 and/or nanostructures 22, 24. A dummy or sacrificial gate layer 45 is formed over the fins 32 and/or nanostructures 22, 24. The dummy gate layer 45 may be made of a material having a high etching selectivity with respect to the isolation region 36. The dummy gate layer 45 may be a conductive, semiconductive, or nonconductive material, and may be or include one or more of amorphous silicon, polysilicon (poly-silicon), poly-silicon-germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. Dummy gate layer 45 may be deposited by Physical Vapor Deposition (PVD), CVD, sputter deposition, or other technique for depositing the selected material. A mask layer 47, which may include, for example, silicon nitride, silicon oxynitride, or the like, is formed over the dummy gate layer 45. In some embodiments, a gate dielectric layer (not shown for simplicity) is formed between dummy gate layer 45 and fin 32 and/or nanostructures 22, 24.

A spacer layer 41 is formed over the sidewalls of the dummy gate layer 45 and the mask layer 47. According to some embodiments, the spacer layer 41 is made of an insulating material, such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon carbonitride oxide, or the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. Spacer layer 41 may be formed by depositing a layer of spacer material (not shown) over mask layer 47 and dummy gate layer 45. According to some embodiments, portions of the spacer material layer between the dummy gate structures 40 are removed using an anisotropic etching process.

In fig. 5A-5C, an etching process is performed to etch the protruding fins 32 and/or portions of the nanostructures 22, 24 not covered by the dummy gate structure 40, resulting in the illustrated structure. The recess may be anisotropic such that the portions of fin 32 directly underneath dummy gate structure 40 and spacer layer 41 are protected and not etched. According to some embodiments, the top surface of recessed fin 32 may be substantially coplanar with the top surface of isolation region 36, as shown. According to some other embodiments, the top surface of recessed fin 32 may be lower than the top surface of isolation region 36.

Fig. 6A to 6C and fig. 7A to 7C illustrate the formation of the inner spacer 74. A selective etching process is performed to recess the end portions of the nanostructures 24 exposed by the openings in the spacer layer 41 without substantially attacking the nanostructures 22. After the selective etching process, grooves 64 are formed in the nanostructures 24 where the removed end portions were located. The resulting structure is shown in fig. 6A-6C.

Next, an inner spacer layer is formed to fill the recesses 64 in the nanostructures 22 formed by the previous selective etching process. The internal spacer layer may be a suitable dielectric material such as silicon carbonitride (SICN), silicon oxynitride (SiOCN), or the like, formed by a suitable deposition method such as PVD, CVD, ALD, or the like. An etching process, such as an anisotropic etching process, is performed to remove portions of the inner spacer layer that are disposed outside the grooves in the nanostructures 24. The remaining portion of the inner spacer layer (e.g., the portion disposed inside the recess 64 in the nanostructure 24) forms the inner spacer 74. The resulting structure is shown in fig. 7A-7C.

Fig. 8A-8C illustrate the formation of a bottom spacer 84 and source/drain regions 82, corresponding to operation 1200 of fig. 32. A bottom isolation layer 84 is formed on the bottom surface of the S/D trench. The formation of the bottom isolation layer 84 may include various processes. Referring to fig. 8C, first, an isolation layer is deposited over the dummy gate structure 40, along the sidewalls of the gate spacers 41, and in the S/D trenches. In some embodiments, the isolation layer comprises a dielectric having a different selectivity than the gate spacer 41A material. For example, the isolation layer comprises a material such as SiO, siN, alumina (Al ₂ O ₃ ) Isolation material, other isolation material, or a combination thereof. The isolation layer may be deposited by CVD, PVD, ALD, other suitable processes, or a combination thereof. The isolation layer has a thickness in the range of about 1nm to about 10nm above the bottom surface of the S/D trench (e.g., the exposed surface of fin structure 32 in the S/D trench), such that the isolation layer is thin enough to leave sufficient spacing for future formed S/D features and thick enough to ensure isolation function above the recessed fin portions in the S/D regions. Too thin an isolation layer may cause the bottom isolation layer 84 to crack during a later etching process, thereby allowing the S/D components to epitaxially grow from the fin structure 32 and causing a significant amount of leakage between the S/D components and the fin structure 32.

In the illustrated embodiment, the source/drain regions 82 are epitaxially grown from an epitaxial material. When a bottom spacer 84 is present, the source/drain regions 82 may be epitaxially grown outward from the sidewalls of the channels 22 and may merge in the lateral spacing between the channels 22 in the S/D trenches. In some embodiments, the source/drain regions 82 exert stress in the respective channels 22A-22C, thereby improving performance. The source/drain regions 82 are formed such that each dummy gate structure 40 is disposed between a respective adjacent pair of source/drain regions 82. In some embodiments, spacer layer 41 separates source/drain regions 82 from dummy gate layer 45 by an appropriate lateral distance to prevent electrical bridging to the subsequently formed gates of the resulting device.

Source/drain regions 82 may comprise any acceptable material, such as a material suitable for n-type or p-type devices. In some embodiments, for n-type devices, the source/drain regions 82 comprise a material that imparts a tensile strain in the channel region, such as silicon, SIC, SICP, siP, siAs, and the like. According to some embodiments, when forming a p-type device, the source/drain regions 82 comprise a material that imparts a compressive strain in the channel region, such as SiGe, siGeB, ge, geSn and the like. The source/drain regions 82 may have surfaces protruding from the corresponding surfaces of the fins, and may have facets. In some embodiments, adjacent source/drain regions 82 may merge to form a single source/drain region 82 adjacent to two adjacent fins 32.

The source/drain regions 82 may be implanted with dopants followed by annealing. The source/drain regions may have a thickness of about 10 ¹⁹ cm ^-3 About 10 ²¹ cm ^-3 The impurity concentration between them. The n-type and/or p-type impurities for source/drain regions 82 may be any of the impurities previously discussed. In some embodiments, the source/drain regions 82 are doped in-situ during growth. Then, a Contact Etch Stop Layer (CESL) and an interlayer dielectric (ILD) (not shown in fig. 8C for simplicity) may be formed overlying the dummy gate structure 40 and the source/drain regions 82 (see fig. 11).

Fig. 9A-9C illustrate the release of fin channels 22A-22C by removing nanostructure 24, mask layer 47, and dummy gate layer 45, which corresponds to step 1500 of fig. 11. A planarization process, such as CMP, is performed to level the top surfaces of the dummy gate layer 45 and the gate spacer layer 41. The planarization process may also remove mask layer 47 (see fig. 8A) on dummy gate layer 45 and portions of gate spacer layer 41 along sidewalls of mask layer 47. Thus, the top surface of the dummy gate layer 45 is exposed.

Next, the dummy gate layer 45 is removed in an etching process, thereby forming a recess 92. In some embodiments, the dummy gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reaction gas that selectively etches the dummy gate layer 45 without etching the spacer layer 41. When the dummy gate layer 45 is etched, the dummy gate dielectric (when present) may serve as an etch stop layer. Then, after removing the dummy gate layer 45, the dummy gate dielectric may be removed.

The nanostructures 24 are removed to release the nanostructures 22. After removal of the nanostructures 24, the nanostructures 22 form a plurality of nanoplatelets that extend horizontally (e.g., parallel to the major upper surface of the substrate 110). The nanoplates may be collectively referred to as channels 22 of the formed nanostructure device 20.

In some embodiments, the nanostructures 24 are removed by a selective etching process using an etchant that is selective to the material of the nanostructures 24, thereby forming a baseThe nanostructures 24 are removed without substantially eroding the nanostructures 22. In some embodiments, the etching process is an isotropic etching process using an etching gas and optionally a carrier gas, wherein the etching gas comprises F ₂ And HF, and the carrier gas may be an inert gas such as Ar, he, N ₂ Combinations thereof, and the like.

In some embodiments, the nanostructures 24 are removed and the nanostructures 22 are patterned to form channel regions of PFETs and NFETs. However, in some embodiments, the nanostructures 24 may be removed and the nanostructures 22 may be patterned to form channel regions of the nanostructure device 20 (which is an NFET), and the nanostructures 22 may be removed and the nanostructures 24 may be patterned to form channel regions of the nanostructure device 20 (which is a PFET). In some embodiments, the nanostructures 22 may be removed and the nanostructures 24 may be patterned to form channel regions of the nanostructure device 20 (which is an NFET), and the nanostructures 24 may be removed and the nanostructures 22 may be patterned to form channel regions of the nanostructure device 20 (which is a PFET). In some embodiments, the nanostructures 22 may be removed and the nanostructures 24 may be patterned to form channel regions of PFETs and NFETs.

In some embodiments, the nanoplatelets 22 of the nanostructure device 20 are remodelled (e.g., thinned) by a further etching process to improve the gate fill window. Remodeling may be performed by an isotropic etching process selective for the nanoplatelets 22. After remodeling, the nanoplatelets 22 may take on a dog bone shape, wherein a middle portion of the nanoplatelets 22 is thinner than a peripheral portion of the nanoplatelets 22 along the X-direction.

Next, in fig. 10A to 10C, a gate structure 200 is formed, corresponding to operation 1300 of fig. 32. Each gate structure 200 may include a first IL layer 210, a high-k dielectric layer 610, and a metal core layer 290. After depositing the material of gate structure 200, a removal operation, such as CMP, may be performed to remove excess material of gate structure 200 that is located over ILD 130. The resulting structure is shown in fig. 11 and 12.

Fig. 12-29 are diagrams of various embodiments of an IC device at various stages of forming vias for backside power and signal routing, according to various embodiments.

Fig. 12-19D are diagrams of forming a power via 254 and a signal via 250 according to various embodiments.

Fig. 12 is a schematic perspective view of an IC device formed as described above with reference to fig. 2A through 11. The IC device in operation shown in fig. 12 may include a substrate 110 having fins 32 thereon, the fins 32 extending in a first direction (e.g., X-axis direction), being arranged in a second direction (e.g., Y-axis direction) transverse to the first direction, and having vertical stacks 26 of nanostructure channels 22 thereon. The gate structure 200 extends in the second direction, is arranged in the first direction, and covers and wraps the channel 22. Source/drain regions 82 adjoin channel 22 on either side in the first direction. The fins 32 are isolated from each other by isolation regions 36 arranged along the second direction. Source/drain regions 82 are each located over a respective fin 32 and are optionally isolated from the respective fin by a bottom isolation layer 84. The source/drain regions 82 are isolated from each other in a second direction by ILD 130 and ESL 131. The gate structure 200 is isolated from each other in a first direction by the ILD 130 and the ESL 131. To form an IC cell that performs an electrical function, such as a Static Random Access Memory (SRAM) cell that stores digital data, the gate structure 200 may be "diced" to form openings, and isolation structures may be formed in the openings. In some embodiments, the vias 250, 254 may be formed between and/or in isolation structures, as will be described in more detail with reference to fig. 13-19D.

In fig. 13, after forming gate structure 200, a first mask layer 300A is formed over ILD 130 and gate structure 200, which may include forming one or more mask layers. In some embodiments, the first mask layer 300A is or includes a hard mask layer and one or more of a photoresist layer, an anti-reflective coating layer, and the like. The first mask layer 300A may include a dielectric material such as nitride, for example, siN, SICN, siOC, siOCN, etc. An opening 37 corresponding to the power supply via 254 is formed in a portion of the first mask layer 300A exposed by the photolithography operation. The opening 37 may correspond to a gate isolation region in which the gate isolation structure 99 will be formed in a later operation. The opening 37 may have a width in the Y-axis direction in the range of about 30nm to about 180 nm. Below about 30nm, residues may remain in the openings 310A due to insufficient spacing to adequately cut the underlying structure. The formation of the opening 310A is described below with reference to fig. 14A to 14C.

In fig. 14A-14C, the portion of IC device 10 exposed by opening 37 in first mask layer 300A is then etched through first mask layer 300A to form an opening or "first opening" 310A. One or more suitable etching operations may be performed to form opening 310A by removing the material of ILD 130, gate structure 200, isolation region 36, and substrate 110. The opening 310A may extend through the ILD 130, the gate structure 200, and the isolation region 36, and may fall on the substrate 110, as shown in fig. 14A. In some embodiments, as shown in fig. 14B, the formation of openings 310A stops at a point prior to exposing substrate 110 such that openings 310A extend into isolation regions 36, but do not penetrate isolation regions 36. In the embodiment shown in fig. 14B, the thickness of the horizontal portion of isolation region 36 in the bottom of opening 310A may be in the range of about 1nm to about 30 nm. In some embodiments, as shown in fig. 14C, the opening 310A extends into the substrate 110, for example, when the etching operation does not stop when the substrate 110 is exposed, but for a selected time after the substrate 110 is exposed. Distance H310A shown in fig. 14C is the extension of opening 310A beyond the lower surface of isolation region 36 and/or beyond the upper surface of substrate 110. In some embodiments, the distance H310A may be in the range of about 1nm to about 30 nm. The embodiment of fig. 14B may be advantageous in reducing the aspect ratio (e.g., width/height) of the first opening 310A, which may improve the process window for depositing the dielectric material of the gate isolation structure 99 in subsequent operations.

In fig. 15, a gate isolation structure 99 is formed in the opening 310A, corresponding to operation 1400 of fig. 32. The gate isolation structure 99 may include a liner layer 99L and a core layer 99C. In some embodiments, liner layer 99L is or includes nitride and may be the same material as that of first mask layer 300A. In some embodiments, liner layer 99L is SiN. Liner layer 99L is deposited as a conformal layer over the exposed areas of the IC device in first opening 310A and over first mask layer 300A. The core layer 99C may be or include an oxide, such as silicon oxide. The liner layer 99L is located between the core layer 99C and adjacent components of the IC device and facilitates blocking oxide diffusion to the adjacent components. In some embodiments, liner layer 99L is in contact with core layer 99C. After the liner layer 99L and the core layer 99C are formed, excess material of the liner layer 99L and the core layer 99C located above the first mask layer 300A may be removed by a removal operation such as CMP. The regions 250A, 254A shown in broken lines in fig. 15 correspond to regions where the through holes 250, 254 will be formed in the subsequent operation, respectively.

In fig. 16, an optional second mask layer 300B is formed over the first mask layer 300A and the gate isolation structure 99, and then patterned to form openings or "second openings" 310B and openings or "third openings" 310C, the second openings 310B and the third openings 310C exposing portions of the IC device where vias 254, 250 will be formed in subsequent operations. The second opening 310B and the third opening 310C may extend through the first mask layer 300A by one or more suitable etching operations. The second mask layer 300B may include one or more photoresist layers, anti-reflective coating layers, hard mask layers, and the like. In some embodiments, the second mask layer 300B is not formed, and the openings 310B, 310C are formed by directly patterning the first mask layer 300A. When the remaining thickness of the first mask layer 300A is insufficient after the gate isolation structure 99 is formed, it may be advantageous to include the second mask layer 300B. In some embodiments, the second mask layer 300B is or includes the same material as the first mask layer 300A. In some embodiments, the second opening 310B is substantially aligned with the gate isolation structure 99. In some embodiments, the second opening 310B has substantially the same width as the gate isolation structure 99 in the Y-axis direction. In some embodiments, the second opening 310B partially overlaps the gate isolation structure 99 and exposes the gate isolation structure 99. The second opening 310B may be disposed at a boundary region between adjacent IC units. The third opening 310C may be provided in one of the IC units, for example, in a middle or central region thereof. The second opening 310B and the third opening 310C may each have a width in the Y-axis direction in a range of about 30nm to about 180 nm. A width of greater than about 30nm is advantageous to provide sufficient spacing for the conductive material filling the vias 250, 254 in subsequent operations.

In fig. 17A-17C, the second opening 310B and the third opening 310C extend by etching the exposed portion of the IC device through the second mask layer 300B. In some embodiments, the exposed portions are etched by one or more anisotropic etching operations. As shown in fig. 17A, the second opening 310B and the third opening 310C may extend through the isolation region 36 until the substrate 110 is exposed and may fall on the substrate 110. As shown in fig. 17B, the second and third openings 310B and 310C may extend partially into the isolation regions 36 without exposing the substrate 110, such that horizontal portions of the respective isolation regions 36 remain in the second and third openings 310B and 310C. The horizontal portion may have a thickness in the range of about 1nm to about 30nm in the Z-axis direction. As shown in fig. 17C, the second opening 310B and the third opening 310C may extend through the isolation region 36 and partially into the substrate 110, for example, when the etching operation is continued after the substrate 110 is exposed. The second opening 310B and the third opening 310C may extend to a depth H310B beyond the upper surface of the substrate 110 and/or beyond the lower surface of the isolation region 36, the depth H310B being in the range of about 1nm to about 30 nm. The embodiment of fig. 17B may be advantageous in reducing the aspect ratio (e.g., width/height) of the second opening 310B and the third opening 310C, which may improve the process window for depositing the conductive material of the vias 250, 254 in subsequent operations.

It should be appreciated that although not seen in fig. 17A-17C, the fins 32 on either side of the third opening 310C may have a jog (see fig. 28) to increase the spacing for accommodating the vias 250. In this way, the etch that forms the third opening 310C has less chance to etch into the adjacent source/drain region 82, which is advantageous in reducing defects.

In fig. 18A to 18C, the material of the through holes 250, 254 is deposited in the second opening 310B and the third opening 310C formed by the process described with reference to fig. 17A to 17C, corresponding to operations 1500 and 1600 of fig. 32. Operations 1500 and 1600 are performed concurrently. The material of the vias 250, 254 may be deposited by one or more PVD, CVD, ALD, sputtering or other suitable deposition operations. In some embodiments, the liner layers 250L, 254L are deposited, followed by the core layers 250C, 254C. The liner layers 250L, 254L may be deposited in the same operation and may comprise the same material, which may be a nitride dielectric such as SiN, SICN, or the like. The liner layers 250L, 254L facilitate isolating the core layers 250C, 254C from adjacent components of the IC device. In some embodiments, the spacer layers 250L, 254L have a thickness in the range of about 5nm to about 20 nm. The core layers 250C, 254C may be deposited in the same operation and may comprise the same material, which may be a conductive material, such as TiN, W, ru, mo, co, etc. After depositing the material of the vias 250, 254 in the second opening 310B and the third opening 310C, one or more removal operations, such as CMP, may be performed to remove the second mask layer 300B. The removal operation may expose the gate isolation structure 99. As shown in fig. 18B, one or more seams or voids may be formed in the core layers 250C, 254C. A seam 254S of one of the through holes 254 is shown in fig. 18B. Similar seams may be present in the through-hole 250, even though not specifically shown. As shown in fig. 18C, the vias 250, 254 may include optional barrier layers 250L2, 254L2 formed prior to the core layers 250C, 254C. The barrier layers 250L2, 254L2 may comprise the same material, which may be a conductive material, such as Ti, ta, tiN, taN, etc.

In fig. 19A to 19D, after forming the through holes 250, 254, the through holes 250, 254 may be recessed to form openings 250R, 254R. Recessing the vias 250, 254 may include recessing the core layers 250C, 254C and the optional barrier layers 250L2, 254L2 (when present) by one or more suitable etching operations that are selective to the material of the core layers 250C, 254C and/or the optional barrier layers 250L2, 254L2 without substantially attacking the material of the gate isolation structure 99, the first mask layer 300A, and the optional liner layers 250L, 254L (when present). Recessing the core layers 250C, 254C below the level of the top surface of the gate structure 200 facilitates protecting the core layers 250C, 254C during a subsequent etching process that forms openings 420R (see fig. 20) for the isolation structures 420, which isolation structures 420 may be referred to as continuous polysilicon or "CPODE"420 (see fig. 22A-22B) over the oxide diffusion edges.

Fig. 19C, 19D show dimensions H254R, H R1, H254R2, H254R3 of the groove 254R, and a description will be given with reference thereto. The recess 250R may have the same or very similar dimensions as the dimensions H254R, H254R1, H254R2, H254R 3. As shown in fig. 19D, the dimension H254R is the total depth of the grooves, for example, the distance between the upper surface of the core layer 254C and the upper surface of the first mask layer 300A. The dimension H254R1 is the distance between the upper surface of the core layer 254C and the upper surface of the gate structure 200. The dimension H254R1 may be in the range of about 10nm to about 20 nm. A dimension H254R1 of greater than about 10nm is advantageous to protect the core layers 250C, 254C from exposure during the etching process used to form the CPODE 420. The dimensions H254R2 and H254R3 are the distance between the upper surface of the core layer 254C and the upper surface of the source/drain region 82 and the distance between the upper surface of the core layer 254C and the upper surface of the uppermost channel 22, respectively. It is beneficial for the dimensions H254R2, H254R3 to be greater than about 1nm so that the CMP operation used to expose the gate structure 200 and vias 250, 254 after forming the CPODE 420 does not expose the source/drain regions 82 and leaves portions of the gate structure 200 above the uppermost channel 22. In some embodiments, the dimensions H254R2, H254R3 are greater than about 1nm, about 2nm, about 5nm, about 10nm, or another suitable dimension.

Fig. 20-23 are schematic plan views of forming a CPODE 420 according to various embodiments. CPODE 420 may be incorporated with one or more transistors in a standard cell layout and facilitate higher density and smaller corner variations, such as mobility variations caused by process variations for cells placed at different locations on the same die or for dies placed at different locations on the same wafer. Corner variations are the result of non-uniformities in the fabrication process, which results in devices with varying performance characteristics. In some embodiments, CPODE 420 is not formed.

In fig. 20, a third mask layer 300C is formed on the first mask layer 300A, the gate isolation structure 99, and the vias 250, 254. The third mask layer 300C extends into the recesses 250R, 254R, which facilitates protecting the vias 250, 254 when the third mask layer 300C is etched to form the openings 420R. The third mask layer 300C may be or include a hard mask layer such as a dielectric nitride, e.g., siN, SICN, etc. In some embodiments, the third mask layer 300C is the same material as the first mask layer 300A.

After forming the third mask layer 300C, an opening 420R is formed by patterning the third mask layer 300C and etching through the first mask layer 300A and the underlying structure exposed by the third mask layer 300C, as shown in fig. 20. In some embodiments, the opening 420R is first formed to a depth that exposes the gate structure 200. During etching to form opening 420R, the exposed portions of gate isolation structure 99 may be recessed as shown. Because of the presence of the third mask layer 300C over the vias 250, 254, the etching operation stops well before the core layers 250C, 254C are exposed, as shown.

In fig. 21, after exposing gate structure 200, opening 420R is extended downward by one or more subsequent etching operations that remove material of gate structure 200, channel 22, fin structure 32, and optional isolation region 36 without substantially attacking the material of third mask layer 300C. In some embodiments, a first etching operation is performed to remove exposed portions of the gate structure 200. The first etching operation may be a wet etching operation. In some embodiments, a second etching operation is performed after the first operation to remove exposed portions of the channel 22 and fin structure 32 until the isolation region 36 is exposed. The second etching operation may be a dry etching operation.

In fig. 22A, 22B, 23, after the opening 420R is extended, the isolation structure 420 is formed in the opening 420R. CPODE 420 may be or include a low-k dielectric material, such as SiO, siN, siCN, siON, siOCN, etc., which may be deposited by a suitable deposition operation, such as PVD, CVD, ALD, etc. The dielectric material of CPODE 420 may be different or the same as the dielectric material of gate isolation structure 99. After forming the CPODE 420, CMP may be performed to remove the third mask 300C and the first mask 300A, thereby exposing the via holes 250, 254 and the gate structure 200, as shown in fig. 22A. In some embodiments, the second etching operation described with reference to fig. 21 removes fin structure 32 to a depth slightly below the top surface of isolation region 36. In such an embodiment, the resulting structure after forming CPODE 420 is shown in fig. 22B. That is, the CPODE 420 inherits the shape of the opening 420R and may extend partially below the top surface of the isolation region 36, as shown. Fig. 23 is a schematic plan view of an IC device including a CPODE 420 in another view.

Fig. 24A-26 are schematic perspective and cross-sectional side views illustrating the formation of front side electrical interconnect components according to various embodiments.

In fig. 24A, a first ESL 141 and a first ILD 140 are formed on the upper surface of the structure shown in fig. 23. The first ESL 141 may be deposited as a conformal thin layer on the upper surfaces of the gate structure 200, the vias 250, 254, the gate isolation structure 99, the ILD 130, the ESL 131, the CPODE 420, and the sidewall spacers 41. After forming the first ESL 141, the first ILD 140 may be formed on the first ESL 141. The first ESL 141 and the first ILD 140 may each be formed by a suitable deposition process, such as one or more of PVD, CVD, ALD, etc.

Thereafter, the first ILD 140 is patterned to form openings in which the source/drain contacts 120 and the first via layer 250A are formed. In some embodiments, various photoresist photolithography and etching processes may be performed on the first ILD 140 to form the opening. For example, a patterned photoresist mask is formed over the first ILD 140. Subsequently, one or more etching processes are performed using the patterned photoresist mask to remove the exposed portions of the first ILD 140. The etching process may be stopped on the first ESL 141. Thereafter, a subsequent etching process may be performed to penetrate the first ESL 141 and expose the upper surfaces of the vias 250, 254 and ILD 130. After exposing the upper surface of ILD 130, a further etching process may be performed to remove the exposed portion of ILD 130 to expose etch stop layer 131. A further etch process may then be performed to remove the etch stop layer 131, thereby exposing the source/drain regions 82.

As shown in fig. 24B, the etching process described above may form at least one single opening exposing source/drain regions 82 and adjacent power vias 254. Other openings may expose only the source/drain regions 82, such as the right side source/drain regions 82 adjacent to the gate isolation regions 99. The etching process may also form an opening exposing the upper surface of the signal via 250, as shown in fig. 24B, 24C.

Source/drain contacts 120 may then be formed in the openings over source/drain regions 82 and optionally over power vias 254. The first via layer 250A is formed in an opening above the signal via 250. In some embodiments, the first via layer 250A has a width in the Y-axis direction that is less than the width of the signal via 250, which is advantageous in avoiding bridging between the first via layer 250A and the adjacent gate structure 200.

The formation of the source/drain contacts 120 and the first via layer 250A may include one or more deposition processes. In some embodiments, isolation layer 122 is formed in the opening prior to forming source/drain contacts 120 and first via layer 250A. For example, isolation layer 122 may be deposited as a thin, conformal layer over sidewalls of first ILD 140 and ILD 130. A suitable etching operation may then be performed to remove the portion of isolation layer 122 that overlies source/drain regions 82 so as to expose source/drain regions 82. After forming isolation layer 122, one or more barrier layers (not shown), such as TiN layers, may be deposited that adhere well to the material of source/drain contacts 120 and first via layer 250A, as well as to the material of first ILD 140 and ILD 130. The silicide layer 118 may be formed by an annealing operation that causes the materials of the source/drain regions 82 and the barrier layer to form a silicide at the interface therebetween, such as cobalt silicide in some embodiments, or TiSi or TiSiN in some other embodiments. The source/drain contacts 120 may comprise a conductive core material that may be formed by depositing a conductive material, such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof, over the source/drain regions 82, the silicide layer 118, the barrier layer, or combinations thereof. A CMP operation may be performed after depositing the source/drain contacts 120 and the first via layer 250A to remove excess material of the source/drain contacts 120 and the first via layer 250A from over the first ILD 140.

In fig. 25, a second ESL 151 and a second ILD 150 are formed over the first ILD 140, source/drain contacts 120, and first via layer 250A. The second ESL 151 may be deposited as a conformal thin layer on the upper surfaces of the first ILD 140, the source/drain contacts 120, and the first via layer 250A. After forming the second ESL 151, the second ILD 150 may be formed on the second ESL 151. The second ESL 151 and the second ILD 150 may each be formed by a suitable deposition process, such as one or more of PVD, CVD, ALD, etc.

Thereafter, the second ILD 150 is patterned to form openings in which the source/drain contacts 120 and the first via layer 250A are formed. In some embodiments, various photoresist photolithography and etching processes may be performed on the second ILD 150 to form the opening. For example, a patterned photoresist mask is formed over the second ILD 150. Subsequently, one or more etching processes are performed using the patterned photoresist mask to remove the exposed portions of the second ILD 150. The etching process may be stopped on the second ESL 151. Thereafter, a subsequent etching process may be performed to penetrate the second ESL 151 and expose the source/drain contacts 120 and the upper surfaces of the first via layer 250A.

After forming the opening exposing the source/drain contact 120 and the first via layer 250A, a source/drain Via (VD) 183, an extended source/drain Via (VDR) 183R, and a second via layer 250B are formed in the opening. The source/drain Via (VD) 183, the extended source/drain Via (VDR) 183R, and the second via layer 250B may be formed by depositing a conductive material in the opening. The conductive material may be or include W, ru, co, cu, mo, etc., and may be deposited by a suitable process, such as PVD, CVD, ALD, etc. In some embodiments, the source/drain Via (VD) 183, the extended source/drain Via (VDR) 183R, and the second via layer 250B are the same material as the source/drain contact 120 and the first via layer 250A. The second via layer 250B may also be referred to as an extended source/drain via 250B. In some embodiments, the gate via 184 is formed in the same deposition process as the source/drain via 183, the extended source/drain via 183R, and the second via layer 250B. For example, the locations where gate via 184 may be located are shown in dashed lines in fig. 25.

In fig. 26, a metallization layer is formed for the front-side interconnect structure 108 (see fig. 1C), which may be referred to as a back-end-of-line (BEOL) interconnect structure 108. The metallization layer may include a third ILD 160 and conductive features disposed therein. The conductive features may include front side power lines 280, third via layers 250C, and other local interconnect traces 282. In some embodiments, a third ESL is present between the third ILD 160 and the second ILD 150. The third ILD 160 may be patterned by a process similar to that used to pattern the first ILD 140 and/or the second ILD 150, thereby forming openings in which conductive features are formed. The conductive members may be or include W, ru, co, cu, mo, etc., and may be formed by a suitable process, such as PVD, CVD, ALD, etc. Additional metallization layers may be formed on top of the metallization layers shown in fig. 26 in a similar manner. The BEOL interconnect structure 108 at the front side of the IC device may include at least two metallization layers, such as eight, ten, or more metallization layers similar to those shown in fig. 26.

Fig. 27-29 are schematic perspective and cross-sectional side views illustrating the formation of front side electrical interconnect components in accordance with various embodiments.

In fig. 27, the IC device may be flipped so that the bottom side of the substrate 110 is exposed for processing. In some embodiments, carrier 800 is attached to the front side of the IC device as shown. For simplicity of illustration, the view of carrier 800 is omitted in the subsequent figures. Carrier 800 may be attached to the top surface (or "front side") of the device by a release layer (not shown). Carrier 800 may include glass, ceramic, bulk silicon, etc., while the release layer may include a Die Attach Film (DAF), dielectric material, etc. After attaching the carrier 800, the orientation of the device is flipped (e.g., such that the carrier 800 is disposed under the device), and the substrate 110 is removed.

In fig. 28, the substrate 110 may be removed, exposing the bottom sides 250U, 254U of the vias 250, 254. In some embodiments, a planarization process (e.g., CMP, grinding, etc.) may be applied to remove the substrate 110. In some embodiments, fin 32 is removed in a planarization process. In some embodiments, the planarization process stops on an etch stop layer (omitted from the figures), which may be formed prior to the operations shown in fig. 2A, 2B. The etch stop layer (when present) may be in contact with the bottom surface of isolation region 36. After removing the material underlying the etch stop layer, the etch stop layer may be removed by a suitable etching process, such as an isotropic etch that removes the material of the etch stop layer without substantially attacking the material of the underlying layers mentioned. Alternatively, the substrate 110 may be removed by grinding, etching, or the like.

In some embodiments, fin structure 32 remains in the IC device after substrate 110 is removed. In some embodiments, removing the substrate 110 includes removing the fin structure 32. When fin structure 32 is removed, a backside dielectric layer may then be formed to isolate (e.g., electrically and physically isolate) subsequently formed conductive features from gate structure 200.

In some embodiments, the remaining height of fin structure 32 in the Z-axis direction is in the range of about 20nm to about 35 nm. The remaining height above 20nm is advantageous for isolating the backside conductive features from the gate structure 200. The remaining height below 35nm is advantageous in reducing the resistance of the vias 250, 254.

As shown in the view of fig. 28, fin structures 32 on either side of signal via 250 may have narrower portions adjacent to signal via 250 (e.g., due to a jog), which increases the available space for accommodating signal via 250 and facilitates reducing the formation of defects in adjacent source/drain regions 82 during etching of third opening 310C in which signal via 250 is formed. The narrower portion of the fin structure 32 may have a width in the Y-axis direction that is greater than about half the width of the remaining portion of the fin structure 32.

In fig. 29, after removal of the substrate 110, a backside metallization layer is formed on the backside of the structure of fig. 28, corresponding to operations 1700 and 1800 of fig. 32. Operations 1700 and 1800 are performed simultaneously. The backside metallization layer may include a backside ILD 360 and one or more conductive features disposed therein. The conductive features may include a backside power rail 380 (operation 1700) and a backside via layer 250E (operation 1800). In some embodiments, backside ESL 361 is formed prior to forming backside ILD 360 such that backside ESL 361 is located between backside ILD 360 and fin structure 32 and isolation region 36. The backside power rail 380 and backside via layer 250E may be referred to as a "backside conductive feature".

The backside ESL 361 and backside ILD 360 may be formed by one or more deposition operations, such as PVD, CVD, ALD, etc. Openings may be formed in the backside ILD 360 by one or more photolithographic operations, including one or more etching operations to remove exposed portions of the backside ILD 360. The etching operation may be terminated on the backside ESL 361 (when present) and then a subsequent etching operation may be performed to penetrate the backside ESL 361 and expose the power vias 254 and the signal vias 250. Backside power rails 380 may be formed in some of the openings and backside via layer 250E may be formed in another of the openings over signal vias 250. An additional backside metallization layer similar to that shown in fig. 26 may be formed on the backside metallization layer shown in fig. 29. For example, the IC device may include two or more (e.g., four, five, six, or more) backside metallization layers, including the backside metallization layers shown in fig. 29. After the backside metallization is formed, carrier 800 may be removed.

Fig. 30A to 30F are schematic perspective views of respective layers of the IC device 10 according to respective embodiments. Fig. 30A shows the device layer including front end of line (FEOL) components, with middle of line (MEOL) and BEOL interconnect structures omitted from the view. Fig. 30A shows an IC unit 100, the IC unit 100 being defined by a power supply via 254 and a CPODE 420 and comprising six transistors with a signal via 250 in between. Figure 30B shows a first MEOL layer on a device layer. Figure 30C shows a second MEOL layer on top of the first MEOL layer. Figure 30D shows the first BEOL layer on the second MEOL layer. Fig. 30E shows the device layer with its back side facing upward. Figure 30F shows a first backside BEOL layer on the device layer.

Fig. 31A-31F are schematic cross-sectional side views of vias 250, 254 according to various embodiments.

Fig. 31A shows a power via 254 in accordance with various embodiments. Fig. 31B shows a signal via 250 in accordance with various embodiments. As can be seen in fig. 31A, 31B, each of the power vias 254 and signal vias 250 are part of a respective stack that includes a front side power line 280 or third via layer 250C in a first BEOL layer ("M0"), extended source/drain vias 183, 250B in a second MEOL layer ("VDR"), source/drain contacts 120 or second via layer 250A in a first MEOL layer ("MD"), power vias 254 or signal vias 250 in a device layer ("super via"), and back side power rail 380 or back side via layer 250E in a first back side BEOL layer ("BM 0"). Accordingly, the power supply via 254 and the signal via 250 may be formed in the same manufacturing process without using a complicated process to form the power supply via 254 and the signal via 250, respectively.

The dimension or height H1 is shown in fig. 31A, 31B and is the height of the vias 250, 254, which may be in the range of about 60nm to about 180 nm. Due to the front side CMP and backside wafer thinning, the heights H1 of the vias 250, 254 may be the same as each other, as described with reference to fig. 22A, 22B, and 28.

Fig. 31A, 31B show seams 250S, 254S in the through holes 250, 254. In some embodiments, the seams or voids 250S, 254S have a width in the range of about 1nm to about 5 nm. In some embodiments, no seams or voids 250S, 254S are present, for example, when a bottom-up metal growth process is performed to form vias 250, 254.

The through holes 250, 254 may be formed with tapered sidewalls as shown in fig. 31A, 31B. The through-hole 254 may be formed to have a taper angle 754 ranging from about 85 degrees to about 90 degrees. The through hole 250 may be formed to have a taper angle 750 in a range of about 85 degrees to about 90 degrees. In some embodiments, taper angle 750 is different from taper angle 754. For example, taper angle 750 may be greater than taper angle 754, e.g., because the aspect ratio of signal via 250 is less than the aspect ratio of power via 254.

In some embodiments, the vias 250, 254 have an inverted cone profile, for example in the Y-Z plane. In the above description of fig. 2A to 29, the openings for forming the vias 250, 254 are etched from the front side of the IC device 10 so that the vias 250, 254 have a tapered profile in the Y-Z plane, the tapered profile narrowing gradually with increasing proximity to the backside conductive member 380. In some embodiments, the openings for forming vias 250, 254 may be etched from the backside of IC device 10 such that vias 250, 254 have a profile in the Y-Z plane that gradually widens as the proximity to backside conductive feature 380 increases. For example, the openings 310B, 310C may be filled with one or more dielectric plugs prior to forming the source/drain contacts 120, source/drain vias 183, and front side power rail 280. Then, in the backside process, thinning the substrate 110 may expose the dielectric plug. The dielectric plugs may then be removed to reopen the openings 310B, 310C, and vias 250, 254 may be formed in the reopened openings 310B, 310C. In such an embodiment, when the openings 310B, 310C are reopened by a suitable etching process, the openings 310B, 310C may have a profile that narrows as the source/drain contacts 120 and/or the first via layer 250A are approached. Vias 250, 254 may take the shape and contour of openings 310B, 310C and may have a contour that narrows toward source/drain contacts 120 and/or first via layer 250A.

Fig. 31C shows source/drain regions 82 that may be in electrical communication with signal vias 250. In some embodiments, the source/drain contact 120 is located on the source/drain region 82, the source/drain via 183 is located on the source/drain contact 120, and the frontside trace 280 is located on the source/drain via 183. The front side trace 280 is located in the same metal layer as the third via layer 250C, the third via layer 250C being electrically connected to the signal via 250 through the first via 250A and the second via layer 250B. In some embodiments, the front side trace 280 is in contact with the third via layer 250C. In some embodiments, the front side trace 280 may be in electrical contact with the third via layer 250C via one or more conductive features in the metal layer over the front side trace 280 and the third via layer 250C.

Fig. 31D-31F show the structural relationship between the first MEOL layer MD and the conductive features in either via 250 or via 254. The description is given with respect to the power supply via 254, but may be similarly applied to the signal via 250. Fig. 31D shows a source-to-drain structure in which source region 82 is coupled to via 254 by source/drain contact 120 in contact with source region 82 and via 254. Fig. 31E shows a source-to-source structure in which a first source region 82 is coupled to a via 254 and a second source region 82 by source/drain contacts 120. Fig. 31F shows a drain-to-drain structure in which the first drain 82 and the second drain 82 are physically and electrically isolated from the via 254. For example, the drain contact 120 located over the first drain 82 and the second drain 82 is isolated from the via 254. It should be appreciated that fig. 31D-31F illustrate embodiments related to possible scenarios in circuit layout. Fig. 31D shows that only one side of the cell (e.g., the source side) has power requirements, while the other side does not. Fig. 31E shows that both sides have such a requirement. Fig. 31F shows that some cells have no power requirements in the Y-Z plane view, and may have power requirements on other Y-Z plane areas not shown herein, for example.

Embodiments may provide advantages. Vias 250, 254 provide flexibility in front side signal and power routing by enabling signal and power lines to be disposed on the back side of device 10. Forming the power lines on the back side of the device 10 allows for wider power lines, which reduces resistance and increases power efficiency. Vias 250, 254 may be formed from the front side of the device or the back side of the device. The use of the vias 250, 254 can reduce resistance and increase speed while also simplifying the routing of power and signal lines.

According to at least one embodiment, a device includes: a stack of semiconductor nanostructures; a gate structure surrounding the semiconductor nanostructure, the gate structure extending in a first direction; source/drain regions adjoining the gate structure and the stack in a second direction transverse to the first direction; a contact structure on the source/drain region; a backside conductive trace located under the stack, the backside conductive trace extending in a second direction; a first via extending vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure adjacent to the first via in the second direction.

According to at least one embodiment, a method comprises: forming a vertical stack of nanostructure channels over a substrate; forming source/drain regions adjacent the nanostructure channel; forming a gate structure surrounding the nanostructure channel and extending across the nanostructure channel in a first direction; forming a first opening extending through the gate structure; forming a gate isolation structure in the first opening; forming a second opening adjacent to the gate isolation structure in a second direction; forming a first through hole in the second opening; forming a contact structure in contact with the first via structure and the source/drain region; and forming a backside conductive trace in contact with the first via.

According to at least one embodiment, a method comprises: forming a vertical stack of nanostructure channels over a substrate; forming source/drain regions adjacent the nanostructure channel; forming a gate structure surrounding the nanostructure channel; forming a first via adjacent the gate structure and a second via adjacent the gate structure, the first via and the second via being located on opposite sides of the gate structure; forming a contact structure having an underside in contact with the source/drain regions and the first via; and forming respective backside conductive members in contact with the first and second vias.

Some embodiments of the present application provide a semiconductor device including: a stack of semiconductor nanostructures; a gate structure surrounding the semiconductor nanostructure, the gate structure extending in a first direction; source/drain regions adjoining the gate structure and the stack in a second direction transverse to the first direction; a contact structure located on the source/drain region; a backside conductive trace located under the stack, the backside conductive trace extending in the second direction; a first via extending vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure adjacent to the first via in the second direction. In some embodiments, the semiconductor device further comprises: a second through hole offset in the first direction with respect to the first through hole; a second gate isolation structure adjacent to the second via in the second direction. In some embodiments, the semiconductor device further comprises: and a third through hole located between the first through hole and the second through hole in the first direction. In some embodiments, the semiconductor device further comprises: a first isolation structure extending in the first direction; and a second isolation structure extending in the first direction and offset relative to the first isolation structure along the second direction; wherein the third through hole is located between the first isolation structure and the second isolation structure. In some embodiments, the semiconductor device further comprises: a second source/drain region located on an opposite side of the first via from the source/drain region; and a second contact structure in contact with the second source/drain region and the first via. In some embodiments, the via has a tapered profile that narrows with increasing proximity to the backside conductive trace. In some embodiments, the via has a width that increases with increasing proximity to the backside dielectric layer.

Further embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a vertical stack of nanostructure channels over a substrate; forming source/drain regions adjacent to the nanostructure channel; forming a gate structure surrounding the nanostructure channel and extending in a first direction across the nanostructure channel; forming a first opening extending through the gate structure; forming a gate isolation structure in the first opening; forming a second opening adjacent to the gate isolation structure in the second direction; forming a first through hole in the second opening; forming a contact structure in contact with the first via structure and the source/drain region; and forming a backside conductive trace in contact with the first via. In some embodiments, the method further comprises: forming a second via hole offset in the first direction with respect to the first via hole; and forming a second backside conductive trace in contact with the second via. In some embodiments, the first via and the second via are formed simultaneously in a first process. In some embodiments, the first process comprises: a conductive material is deposited in the second opening and in a third opening offset relative to the second opening in the first direction. In some embodiments, the first process comprises: a dielectric liner layer is formed in the second opening and the third opening prior to the depositing of the conductive material. In some embodiments, the method further comprises: forming a second source/drain region during the forming of the source/drain region; and forming a second contact structure in contact with the first via structure and the second source/drain region; wherein the second source/drain region is located on an opposite side of the first via structure from the source/drain region.

Still further embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a vertical stack of nanostructure channels over a substrate; forming source/drain regions adjacent to the nanostructure channel; forming a gate structure surrounding the nanostructure channel; forming a first via adjacent to the gate structure and a second via adjacent to the gate structure, the first via and the second via being located on opposite sides of the gate structure; forming a contact structure having an underside in contact with the source/drain regions and the first via; and forming respective backside conductive members in contact with the first and second vias. In some embodiments, the method further comprises: exposing the first and second vias by removing the substrate; forming a backside dielectric layer in contact with the first via and the second via; and exposing the first and second vias by forming first and second openings in the backside dielectric layer; wherein the forming of the respective backside conductive members includes depositing a conductive material in the first opening and the second opening. In some embodiments, the first and second vias have the same height. In some embodiments, the method further comprises: forming source/drain vias over the contact structures; and forming a front-side conductive member on the first via hole. In some embodiments, removing the substrate removes fin structures located under the vertical stack of nanostructure channels. In some embodiments, the method further comprises: forming a bottom isolation layer on the fin structure under the nanostructure channel; wherein the forming source/drain regions includes epitaxially growing the source/drain regions on the nanostructure channel, and the source/drain regions are isolated from the fin structure by the bottom isolation layer. In some embodiments, the method further comprises: exposing the first and second vias and the fin structure by removing the substrate; wherein after removing the substrate, the fin structure has a height in a range of 20 nanometers to 35 nanometers.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A semiconductor device, comprising:

a stack of semiconductor nanostructures;

a gate structure surrounding the semiconductor nanostructure, the gate structure extending in a first direction;

source/drain regions adjoining the gate structure and the stack in a second direction transverse to the first direction;

a contact structure located on the source/drain region;

a backside conductive trace located under the stack, the backside conductive trace extending in the second direction;

a first via extending vertically from the contact structure to a top surface of the backside dielectric layer; and

A gate isolation structure adjacent to the first via in the second direction.

2. The semiconductor device of claim 1, further comprising:

a second through hole offset in the first direction with respect to the first through hole;

a second gate isolation structure adjacent to the second via in the second direction.

3. The semiconductor device of claim 2, further comprising:

and a third through hole located between the first through hole and the second through hole in the first direction.

4. The semiconductor device according to claim 3, further comprising:

a first isolation structure extending in the first direction; and

a second isolation structure extending in the first direction and offset relative to the first isolation structure along the second direction;

wherein the third through hole is located between the first isolation structure and the second isolation structure.

5. The semiconductor device of claim 1, further comprising:

a second source/drain region located on an opposite side of the first via from the source/drain region; and

And a second contact structure in contact with the second source/drain region and the first via.

6. The semiconductor device of claim 1, wherein the via has a tapered profile that narrows with increasing proximity to the backside conductive trace.

7. The semiconductor device of claim 1, wherein the via has a width that increases with increasing proximity to the backside dielectric layer.

8. A method of forming a semiconductor device, comprising:

forming a vertical stack of nanostructure channels over a substrate;

forming source/drain regions adjacent to the nanostructure channel;

forming a gate structure surrounding the nanostructure channel and extending in a first direction across the nanostructure channel;

forming a first opening extending through the gate structure;

forming a gate isolation structure in the first opening;

forming a second opening adjacent to the gate isolation structure in the second direction;

forming a first through hole in the second opening;

forming a contact structure in contact with the first via structure and the source/drain region; and

a backside conductive trace is formed in contact with the first via.

9. The method of claim 8, further comprising:

forming a second via hole offset in the first direction with respect to the first via hole; and

a second backside conductive trace is formed in contact with the second via.

10. A method of forming a semiconductor device, comprising:

forming a vertical stack of nanostructure channels over a substrate;

forming source/drain regions adjacent to the nanostructure channel;

forming a gate structure surrounding the nanostructure channel;

forming a first via adjacent to the gate structure and a second via adjacent to the gate structure, the first via and the second via being located on opposite sides of the gate structure;

forming a contact structure having an underside in contact with the source/drain regions and the first via; and

respective backside conductive members are formed in contact with the first and second vias.