CN116525676A

CN116525676A - Semiconductor device and method of forming the same

Info

Publication number: CN116525676A
Application number: CN202310207934.1A
Authority: CN
Inventors: 范韵如; 苏焕杰; 谌俊元; 庄正吉; 王志豪
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-04-04
Filing date: 2023-03-07
Publication date: 2023-08-01

Abstract

The device includes a stack of semiconductor nanostructures, a gate structure surrounding the semiconductor nanostructures, source/drain regions adjacent to the gate structure and the stack, a contact structure located on the source/drain regions, a backside dielectric layer located below the stack, and a via structure extending from the contact structure to a top surface of the backside dielectric layer. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Semiconductor device and method of forming the same

Technical Field

Embodiments of the present application relate to semiconductor devices and methods of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such scaled down processes generally provide benefits by improving production efficiency and reducing associated costs. This shrinking also increases the complexity of processing and manufacturing ICs.

Disclosure of Invention

Some embodiments of the present application provide a device comprising: a stack of semiconductor nanostructures; a gate structure surrounding the semiconductor nanostructure; source/drain regions adjacent to the gate structure and the stack; a contact structure located on the source/drain region; a backside dielectric layer located under the stack; and a via structure extending from the contact structure to a top surface of the backside dielectric layer.

Further embodiments of the present application provide a method comprising: forming a nanostructure channel vertical stack over a substrate; forming source/drain regions adjacent to the nanostructure channel; forming a gate structure surrounding the nanostructure channel; forming a via structure adjacent to and laterally isolated from the source/drain regions; forming a contact structure in contact with the via structure and the source/drain regions; and forming a backside interconnect structure in contact with the via structure.

Still other embodiments of the present application provide a method comprising: forming a nanostructure channel vertical stack over a substrate; forming source/drain regions adjacent to the nanostructure channel; forming a gate structure surrounding the nanostructure channel; forming a gate isolation structure isolating portions of the gate structure from each other; forming a contact structure having an underside in contact with the source/drain regions and the gate isolation structure; exposing the gate isolation structure by removing the substrate; forming an opening in the gate isolation structure, the opening exposing the underside of the contact structure; and forming a via structure in the opening, the via structure being in contact with the contact structure.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A to 1H are schematic plan, perspective, and cross-sectional side views of a portion of an IC device according to an embodiment of the present invention.

Fig. 2A-10D are diagrams of various embodiments of an IC device at various stages of fabrication, in accordance with various aspects of the invention.

Fig. 11A-11J are diagrams of various embodiments of an IC device at various stages of forming a front-side via for backside power delivery, in accordance with various embodiments.

Fig. 12A-12I are diagrams of various embodiments of an IC device at various stages of forming a front-side via for backside power delivery, in accordance with various embodiments.

Fig. 13A-13G are diagrams of various embodiments of an IC device at various stages of forming a front-side via for backside power delivery, in accordance with various embodiments.

Fig. 14 to 16 are flowcharts illustrating methods of manufacturing a semiconductor device according to aspects of the present invention.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as "under …," "under …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The present invention relates generally to semiconductor devices and more particularly to Field Effect Transistors (FETs), such as planar FETs, three-dimensional fin line FETs (finfets), or nanostructured devices. Examples of nanostructure devices include full Gate (GAA) devices, nanoflake FETs (NSFETs), nanowire FETs (NWFETs), and the like. In prior art nodes, as Integrated Circuit (IC) devices shrink, routing signal lines and power lines (or rails) at the front side of the substrate becomes increasingly challenging. As scaling down, the spacing for the interconnects decreases, increasing the difficulty of power rail design. For example, the power rails may be narrowed to increase the spacing for the signal lines, which increases resistance and reduces power efficiency.

Embodiments disclosed herein provide power from the back side of an IC device, which increases the flexibility of front side signal routing and allows wired power rail formation, which reduces resistance and increases power efficiency. Embodiments include front side power vias that enable backside power delivery and improve front side signal routing spacing. In some embodiments, power Vias (PV) are located at cell boundaries (e.g., between memory cells, logic cells, etc.), and are designed to electrically connect source/drain contacts (or "MD") to a backside metal layer, such as the lowest backside metal layer (or "BM 0"). Other backside interconnect features, such as conductive traces and vias, may be stacked on the higher backside metal layers (e.g., BM1, BM2, BM3, BM 4) to provide routing of power lines, signal lines, or both on the backside of the IC device.

Embodiments disclosed herein provide a method of manufacturing a power via. In some embodiments, the power vias are formed from the front side by depositing conductive material of the power vias in openings formed prior to forming the source/drain contacts. In some embodiments, the openings are formed from the backside, and then the power vias are formed from the backside by depositing a conductive material. In some embodiments, a first opening is formed from the front side, a dielectric plug is formed in the first opening, a second opening is formed from the back side by removing the dielectric plug, and a power via is formed by depositing a conductive material in the second opening from the back side.

Fig. 1A to 1G illustrate portions of IC devices 10, 10A, 10B according to various embodiments. Fig. 1A is a schematic plan view of a portion of an IC device 10 according to various embodiments. Fig. 1B to 1E are schematic perspective views of portions of the IC devices 10, 10A, 10B. Fig. 1F and 1G are schematic cross-sectional side views of a nanostructure device 20 and a boundary region 20BR of an IC device 10, 10A, 10B.

In fig. 1A, IC units 100A, 100B, 100C are arranged with a boundary region 100BR between them. IC unit 100A is separated from IC unit 100B by boundary region 100BR, and IC unit 100B is separated from IC unit 100C by boundary region 100BR. The nanostructure device 20 is positioned at a region of the gate structure 200 adjacent to the source/drain regions 82 on either side. Source/drain regions may refer to either source or drain, either individually or collectively depending on the context.

As shown in fig. 1A, each of IC units 100A-100C may include four nanostructure devices 20. In some embodiments, IC units 100A-100C may include fewer than four nanostructure devices 20 or more than four nanostructure devices 20. Nanostructure device 20 may include an n-type transistor, a p-type transistor, or both. The IC units 100A-100C may include other integrated devices such as integrated capacitors, integrated resistors, integrated inductors, integrated diodes, and the like.

A power via 150 (or via structure 150) is positioned in the IC device 10. The power vias 150 may electrically connect one or more of the source/drain regions 82 at the front side of the IC device 10 with a power rail 250 (see fig. 1F and 1G) at the back side of the IC device 10. For example, the source/drain regions 82 may be in contact with the source/drain contacts 120 (or the contact structures 120; see fig. 1B), the source/drain contacts 120 are in contact with the power vias 150, the power vias 150 are in contact with the backside conductive members 180, and the backside conductive members 180 are in contact with the power rails 250 either directly or through the backside vias 240 (see fig. 1F and 1G). The source/drain regions 82 may be separated from the power via 150, the back side conductive feature 180, the back side via 240, and the power rail 250 by isolation regions 36 (see fig. 1B), first back side dielectric layer 160, and second back side dielectric layer 160A (see fig. 1F and 1G). In some embodiments, as shown in FIG. 1A, power vias 150 are positioned in the boundary region 100BR, rather than in the IC units 100A-100C.

In some embodiments, the power vias 150 are or include one or more of W, ru, co, cu, mo, etc. The power via 150 includes a glue layer, which may be TaN, tiN, etc. In some embodiments, the glue layer is omitted so that the metallic material of the power vias 150 is in direct contact with their surrounding components, such as the fourth isolation layer 140 (see fig. 1B), the source/drain contacts 120, the first isolation layer 122, and the second isolation layer 124. The glue layer may be formed on and along the sidewalls of the metal material of the power supply via 150.

The height of the power vias 150 (e.g., in the Z-axis direction) may be in the range of about 10nm to about 150 nm. In some embodiments, when the source/drain contacts 120 have a height of greater than about 150nm, the power vias 150 may have a height of greater than about 150 nm. When the power via 150 is shorter than about 10nm, the resistance of the power via 150 may be too high.

The width of the power supply via 150 (e.g., in the Y-axis direction) may be in the range of about 50nm to about 85 nm. Widths greater than about 85nm may make the cell size (e.g., in the X-Y plane) too large. A width narrower than about 50nm may result in leakage current at the boundary region 100BR between cells. In some embodiments, the power vias 150 have a tapered profile, for example, in the Y-Z plane. In fig. 1B and 1E, the power via 150 may have a profile in the Y-Z plane that gradually narrows as it gets closer to the backside conductive member 180, corresponding to an embodiment in which an opening for forming the power via 150 is etched from the front side of the IC device 10. In fig. 1D, fig. 1D corresponds to an embodiment in which an opening for forming the power supply via 150 is etched from the back side of the IC device 10, the power supply via 150 may have a profile that gradually widens as it gets closer to the back side conductive member 180 in the Y-Z plane. In some embodiments, the taper angle of the power supply via 150 may be in the range of about 80 degrees to 90 degrees (e.g., vertical). A taper angle of less than about 80 degrees may make the contact area between the power supply via 150 and the source/drain contact 120 or the backside metal feature 180 too small, thereby increasing the resistance to a level that degrades circuit performance or malfunctions.

In some embodiments, as shown in fig. 1B, the fourth isolation layer 140 is positioned along the sidewalls of the power via 150 between the power via 150 and the source/drain regions 82. In fig. 1B, the fourth isolation layer 140 is partially positioned between the power via 150 and the source/drain contacts 120 such that one or more of the source/drain contacts 120 contact the power via 150. In some embodiments, the fourth isolation layer 140 is or includes one or more of SiC, laO, alO, alON, zrO, hfO, siN, si, znO, zrN, zrAlO, tiO, taO, YO, taCN, zrSi, siOCN, siOC, siCN, hfSi, laO or SiO.

As described with reference to fig. 1A, the power supply via 150 may be positioned at the boundary region 100BR between the IC units 100A, 100B, 100C. As shown in fig. 1B, the spacing W1 (e.g., in the Y-axis direction) between adjacent source/drain regions 82 within an IC cell (e.g., IC cell 100A) may be in the range of about 10nm to about 50 nm. As also shown in fig. 1B, the contact width W2 (e.g., in the Y-axis direction) between the source/drain contacts 120 and the power supply via 150 may be in the range of about 10nm to about 85 nm. In some embodiments, the source/drain contacts 120 are in contact with the entire upper surface of the power via 150 (e.g., the source/drain contacts 120 fall completely over the power via 150). In some embodiments, the source/drain contacts 120 are in contact with portions of the upper surface of the power via 150 that are less than the entire upper surface of the power via 150 (e.g., the source/drain contacts 120 partially fall on the power via 150). In the vertical direction (e.g., the Z-axis direction), the contact between the source/drain contacts 120 and the power vias 150 may be in the range of about 3nm to about 100 nm. In some embodiments, the upper surface of the fourth isolation layer 140 in contact with the sidewalls of the power supply via 150 is located at a level from about 0nm (e.g., coplanar) to about 99nm lower than the upper surface of the power supply via 150. In some embodiments, the length of the power supply via 150 (e.g., in the X-axis direction) may be equal to or greater than one cell pitch (e.g., the length of the IC unit 100A in the X-axis direction). When the width and height of the contact area between the power supply via 150 and the source/drain contact 120 are smaller than the dimensions given above, the contact resistance therebetween may be too large, resulting in degradation or malfunction of the circuit performance.

Fig. 1F shows a schematic cross-sectional side view of a portion of an IC device 10 fabricated in accordance with an embodiment of the invention, wherein IC device 10 includes a nanostructure device 20. In some embodiments, nanostructure device 20 may be an n-type FET (NFET) or a p-type FET (PFET). Integrated circuit devices such as IC device 10 typically include transistors having different threshold voltages based on their function in the IC device. For example, input/output (IO) transistors typically have the highest threshold voltage because IO transistors require high current processing. The core logic transistors typically have the lowest threshold voltage to achieve higher switching speeds at lower operating power supplies. The third threshold voltage between the threshold voltage of the IO transistor and the threshold voltage of the core logic transistor may also be used for some other functional transistor, such as a Static Random Access Memory (SRAM) transistor. Some circuit blocks within IC device 10, such as one or more of IC units 100A-100C, may include two or more NFETs and/or PFETs of two or more different threshold voltages.

The cross-sectional view of IC device 10 in fig. 1F is taken along the X-Z plane, where the X direction is the horizontal direction and the Z direction is the vertical direction. The nanostructure device 20 includes channels 22A-22D (alternatively referred to as "nanostructures 22" or "channels 22") located over an optional fin structure 32 (see fig. 1B). In some embodiments, fin structure 32 is removed along with substrate 110 (see fig. 2A) during backside processing.

The channels 22A-22D are laterally adjacent to the source/drain regions 82 and are covered and surrounded by the gate structure 200. The gate structure 200 controls the flow of current through the channels 22A-22D based on the voltage applied at the gate structure 200 and at the source/drain regions 82. The threshold voltage is the voltage below which a negligible current flows through the channel 22 (e.g., a gate-to-source voltage or a source-to-gate voltage), and above which a significant current (e.g., an order of magnitude more current) flows through the channel 22. Voltages at or above the threshold voltage establish a conductive path in the channels 22A-22D. Threshold voltage adjustment may be implemented during fabrication of individual transistors, such as IO transistors, core logic transistors, and SRAM transistors, for example, during fabrication of gate structure 200.

In some embodiments, fin structure 32 comprises silicon. In some embodiments, nanostructure device 20 is an NFET and its source/drain regions 82 comprise silicon-phosphorus (SiP). In some embodiments, nanostructure device 20 is a PFET and its source/drain regions 82 comprise silicon germanium (SiGe). In some embodiments, NFETs and PFETs include source/drain regions 82 of the same material at different doping levels to achieve the operating characteristics of the NFETs or PFETs. In some embodiments, the source/drain regions 82 comprise one or more of SiGeB, siP, siAs, siGe or another suitable semiconductor material. In some embodiments, the source/drain regions 82 have a width (e.g., in the Y-axis direction) in the range of about 0.5nm to about 100nm (see fig. 1B). In some embodiments, the extension H1 of the source/drain region 82 above the level of the interface between the source/drain region 82 and the fourth isolation layer 140 (see fig. 1B) is in the range of about 0.1nm to about 50 nm. In some embodiments, the height (e.g., in the Z-axis direction) of the source/drain regions 82 is in the range of about 0.1nm to about 100 nm. The height of the source/drain regions 82 may be measured from the interface between the respective source/drain region 82 and the fin 32 on which it is disposed to the top of the source/drain region 82.

The channels 22A-22D each comprise a semiconductor material, for example silicon or a silicon compound, such as silicon germanium or the like. The channels 22A-22D are nanostructures (e.g., having dimensions in the range of a few nanometers) and may also each have an elongated shape and extend in the X-direction. In some embodiments, channels 22A-22D each have a Nanowire (NW) shape, a Nanoplatelet (NS) shape, a Nanotube (NT) shape, or other suitable nanoscale shape. The cross-sectional profile of channels 22A-22D may be rectangular, circular, square, annular, oval, hexagonal, or a combination thereof.

In some embodiments, the lengths of the channels 22A-22D (e.g., measured in the X-axis direction) may be different from one another, for example, due to tapering during the fin etching process. In some embodiments, the length of channel 22A may be less than the length of channel 22B, the length of channel 22B may be less than the length of channel 22C, and the length of channel 22C may be less than the length of channel 22D. The channels 22A-22D may not have a uniform thickness, for example, due to a channel trimming process for expanding the spacing between the channels 22A-22D (e.g., measured in the Z-direction) to increase the gate structure manufacturing process window. For example, the middle portion of each of channels 22A-22D may be thinner than the ends of each of channels 22A-22D. Such shapes may be collectively referred to as "dog bone" shapes.

In some embodiments, the spacing between channels 22A-22D (e.g., between channel 22B and channel 22A or channel 22C) is in a range between about 8 nanometers (nm) and about 12 nm. In some embodiments, the thickness (e.g., measured in the Z direction) of each of the channels 22A-22D is in a range between about 5nm and about 8nm. In some embodiments, the width of each of the channels 22A-22D (e.g., measured in the Y direction, not shown in FIG. 1F, orthogonal to the X-Z plane) is at least about 8nm.

Gate structure 200 is disposed over and between channels 22A-22D, respectively. In some embodiments, threshold voltage adjustment is achieved by driving at least one specific dopant into the first high-k gate dielectric layer 222 of the gate structure 200. In some embodiments, threshold voltage adjustment is alternatively or further achieved by adding one or more barrier layers 700 (also referred to as "work function barrier layers") in the work function metal layer between the second high-k gate dielectric layer 230 and the metal core layer 290.

A first Interface Layer (IL) 210, which may be an oxide of the material of trenches 22A-22D, is disposed on the exposed areas of trenches 22A-22D and the top surface of fin 32 (when present). The first IL layer 210 promotes adhesion of the first gate dielectric layer 222 to the channels 22A-22D. In some embodiments, the first IL layer 210 has a thickness of about 5 angstroms (a) to about 50 angstroms (a). In some embodiments, the first IL layer 210 has a thickness of about 10A. The first IL layer 210 having a too thin thickness may exhibit voids or insufficient adhesion. Too thick of the first IL layer 210 consumes gate fill windows, which is related to threshold voltage adjustment and resistance as described above.

The first gate dielectric layer 222 and the second gate dielectric layer 230 are collectively referred to as a "gate dielectric layer" or gate dielectric structure 600. In some embodiments, the gate dielectric layers 222, 230 comprise a high-k gate dielectric material, which may refer to a dielectric material having a high dielectric constant greater than that of silicon oxide (k≡3.9). Exemplary high-k dielectric materials include HfO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2、Ta ₂ O ₅ 、LaO _x 、AlO _x Or a combination thereof. In some embodiments, the first gate dielectric layer 222 has a thickness of about 5A to about 50A, and the first gate dielectric layer 222 may be similar to or slightly thinner than the first IL layer 210. In some embodiments, the first gate dielectric layers 222 each have a thickness of about 9A. In some embodiments, the second gate dielectric layer 230 has a thickness of about 5A to about 50A and is substantially thinner than the first gate dielectric layer 222. In some embodiments, the second gate dielectric layer 230 has a thickness of about 6A, and the second gate dielectric layer 230 is about two-thirds of the first gate dielectric layer 222.

In some embodiments, the first gate dielectric layer 222 may also be included in the real worldDopants at concentrations now adjusted for threshold voltage, e.g. from La ₂ O ₃ 、MgO、Y ₂ O ₃ 、TiO ₂ 、Al ₂ O ₃ 、Nb ₂ O ₅ Metal ions driven into high-k gate dielectric or from B ₂ O ₃ The driven boron ions and the first gate dielectric layer 220 is substantially free of dopants. As one example, for N-type transistor devices, a higher concentration of lanthanum ions reduces the threshold voltage relative to a layer with a lower concentration or no lanthanum ions, and vice versa for P-type devices. In some embodiments, the first gate dielectric layer 222 of some transistor devices (e.g., IO transistors) is also free of dopants present in some other transistor devices (e.g., N-type core logic transistors or P-type IO transistors). In an N-type IO transistor, for example, a relatively high threshold voltage is desired so that the IO transistor high-k dielectric layer is preferably free of lanthanum ions, which would otherwise reduce the threshold voltage. The second gate dielectric layer 230 is substantially free of dopants present in the first gate dielectric layer 222. The second gate dielectric layer 230 reduces gate leakage.

The gate structure 200 includes one or more work function metal layers, collectively referred to as a first work function metal layer 900. In the nanostructure device 20, which in most embodiments is an NFET, the first work function metal layer 900 may include at least an N-type work function metal layer, an in-situ capping layer, and an oxygen barrier layer. In some embodiments, the first work function metal layer 900 includes more or less layers than those described. In the nanostructure device 20, which is a PFET, the first work function metal layer 900 is substantially the same as the work function metal layer for an NFET, and the gate structure 200 may further include an additional second work function layer 700, the second work function layer 700 typically including one or more barrier layers comprising a metal nitride, such as TiN, WN, moN, taN, and the like. Each of the one or more barrier layers may have a thickness in a range from about 5A to about 20A. The inclusion of one or more barrier layers provides additional threshold voltage adjustment flexibility. Typically, each additional barrier layer increases the threshold voltage.

The gate structure 200 also includes a metal core layer 290. The metal core layer 290 may comprise a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. Between the channels 22A-22D, the metal core layer 290 is circumferentially surrounded (in cross-section) by one or more work function metal layers 900, and further circumferentially surrounded by a work function barrier layer 700 in the gate structure 200, which work function barrier layer 700 is then circumferentially surrounded by the gate dielectric layer 600 (see fig. 14). In the portion of gate structure 200 positioned over channel 22A furthest from fin 32, metal core 290 is positioned over one or more work function metal layers 900. One or more work function metal layers 900 encapsulate the metal core 290. The gate dielectric layer 600 also encapsulates the one or more work function metal layers 900 and further encapsulates the work function barrier layer 700. The gate structure 200 may also include a glue layer formed between the one or more work function layers 900 and the metal core layer 290 to increase adhesion. For simplicity, the glue layer is not specifically shown in fig. 1F.

Referring to fig. 1B, a distance D1 (e.g., in the X-axis direction) between adjacent stacks of nanostructures 22 may be in the range of about 0.5nm to about 100 nm.

Referring to fig. 1F, nanostructure device 20 also includes gate spacers 41 and internal spacers 74 disposed on sidewalls of first gate dielectric layer 222. An inner spacer 74 is also disposed between channels 22A-22D. The gate spacers 41 and the inner spacers 74 may comprise a dielectric material, for example a low-k material such as SiOCN, siON, siN, siCN, siO or SiOC.

The nanostructure device 20 also includes source/drain contacts 120 formed over the source/drain regions 82. The source/drain contacts 120 may comprise a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, taN, tiN, or combinations thereof. The source/drain contacts 120 may be surrounded by a barrier layer (not shown), such as SiN or TiN, which helps prevent or reduce diffusion of material from the source/drain contacts 120 or into the source/drain contacts 120. Silicide layer 118 may also be formed between source/drain regions 82 and source/drain contacts 120 to reduce the source/drain contact resistance. The silicide layer 118 may comprise a metal silicide material, such as cobalt silicide in some embodiments, or TiSi in some other embodiments. The height of the source/drain contacts 120 (e.g., in the Z-axis direction) may be in the range of about 3nm to about 150 nm.

The nanostructure device 20 also includes an interlayer dielectric (ILD) 130.ILD 130 provides electrical isolation between the various components of nanostructure device 20 discussed above, for example between gate structure 200 and source/drain contacts 120.

In some embodiments, the first isolation layer 122 is disposed on sidewalls of the ILD 130 between the ILD 130 and the source/drain contacts 120. The first barrier layer 122 may be or include one or more of SiC, laO, alO, alON, zrO, hfO, siN, si, znO, zrN, zrAlO, tiO, taO, YO, taCN, zrSi, siOCN, siOC, siCN, hfSi, laO, siO.

In some embodiments, a second isolation layer 124 is disposed over ILD 130 and gate structure 200. The second barrier layer 124 may be or include one or more of SiC, laO, alO, alON, zrO, hfO, siN, si, znO, zrN, zrAlO, tiO, taO, YO, taCN, zrSi, siOCN, siOC, siCN, hfSi, laO, siO.

In some embodiments, the third barrier layer 134 is disposed on the second barrier layer 124 and may be or include one or more of SiC, laO, alO, alON, zrO, hfO, siN, si, znO, zrN, zrAlO, tiO, taO, YO, taCN, zrSi, siOCN, siOC, siCN, hfSi, laO, siO.

The source/drain contacts 120 may extend through the second isolation layer 124 and the third isolation layer 134. The upper surfaces of the source/drain contacts 120 and the third isolation layer 134 may be coplanar or substantially coplanar.

Fig. 14-16 illustrate flow diagrams of methods 1000, 2000, 3000 for forming an IC device or portion thereof from a workpiece, in accordance with one or more aspects of the present invention. The methods 1000, 2000, 3000 are merely examples and are not intended to limit the present disclosure to what is explicitly shown in the methods 1000, 2000, 3000. Additional steps may be provided before, during, and after the methods 1000, 2000, 3000, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the methods. For simplicity, not all steps are described in detail herein. The methods 1000, 2000, 3000 are described below in connection with partial cross-sectional views (shown in fig. 2A, 2B, 3A, 3B, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A-10D, 11A-11J, 12A-12I, and 13A-13G) of a workpiece at various stages of manufacture according to embodiments of the methods 1000, 2000, 3000. For the avoidance of doubt, throughout the drawings, the X-direction is perpendicular to the Y-direction and the Z-direction is perpendicular to the X-direction and the Y-direction. It should be noted that since the workpiece can be manufactured as a semiconductor device, the workpiece can be referred to as a semiconductor device as the context requires.

Fig. 2A-10C are perspective and cross-sectional views of intermediate stages in the fabrication of a nano-FET including a channel 22, source/drain regions 82, and a gate structure 200, in accordance with some embodiments. Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A show perspective views. Fig. 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B illustrate reference sections B-B' (gate cuts) shown in fig. 2A, 3A, and 4A. Fig. 4C, 5C, 6C, 7C, 8C, 9C, and 10C illustrate reference cross-sections C-C' (channel/fin cut) shown in fig. 4A.

In fig. 2A and 2B, a substrate 110 is provided. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with a p-type dopant or an n-type dopant) or undoped. The semiconductor material of the substrate 110 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof. Other substrates may be used, such as single layer, multi-layer or gradient substrates.

Further in fig. 2A and 2B, a multi-layer stack 25 or "lattice" is formed over the substrate 110 of alternating layers of first semiconductor layers 21A-21C (collectively referred to as first semiconductor layers 21) and second semiconductor layers 23A-23C (collectively referred to as second semiconductor layers 23). In some embodiments, the first semiconductor layer 21 may be formed of a first semiconductor material suitable for an n-type nano-FET, such as silicon, silicon carbide, etc., and the second semiconductor layer 23 may be formed of a second semiconductor material suitable for a p-type nano-FET, such as silicon germanium, etc. Each of the layers of the multi-layer stack 25 may be epitaxially grown using a process such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), vapor Phase Epitaxy (VPE), molecular Beam Epitaxy (MBE), or the like.

Three layers of each of the first semiconductor layer 21 and the second semiconductor layer 23 are shown. In some embodiments, the multi-layer stack 25 may include one or two of each of the first semiconductor layer 21 and the second semiconductor layer 23 or four or more of each. For example, the IC devices 10, 10A, 10B shown in fig. 1A-1E include stacks of nanostructured channels 22 each having four channels 22. Although the multilayer stack 25 is shown as including the second semiconductor layer 23C as the bottommost layer, in some embodiments, the bottommost layer of the multilayer stack 25 may be the first semiconductor layer 21.

Due to the high etch selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material may be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby allowing the first semiconductor layer 21 to be patterned to form a channel region of the nano-FET. In some embodiments, the first semiconductor layer 21 is removed and the second semiconductor layer 23 is patterned to form a channel region. The high etch selectivity allows the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, thereby allowing the second semiconductor layer 23 to be patterned to form the channel region of the nano-FET.

In fig. 3A and 3B, fins 32 are formed in the substrate 110 and nanostructures 22, 24 are formed in the multi-layer stack 25, corresponding to operations 1100, 2100, 3100 of fig. 14-16. In some embodiments, the nanostructures 22, 24 and fins 32 may be formed by etching trenches in the multilayer stack 25 and the substrate 110. The etching may be any acceptable etching process, such as Reactive Ion Etching (RIE), neutral Beam Etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. The first nanostructures 22A-22C (hereinafter also referred to as "channels") are formed by the first semiconductor layer 21, and the second nanostructures 24A-24C are formed by the second semiconductor layer 23. The distance CD1 between adjacent fins 32 and nanostructures 22, 24 may be from about 18nm to about 100nm.

The fins 32 and nanostructures 22, 24 may be patterned by any suitable method. For example, one or more photolithographic processes including double patterning or multiple patterning processes may be used to form the fins 32 and the nanostructures 22, 24. Typically, double patterning or multiple patterning processes combine photolithography and self-aligned processes, allowing for a pitch smaller than that obtainable using a single, direct photolithography process. As an example of a multiple patterning process, a sacrificial layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed beside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and then the remaining spacers may be used to pattern the fins 32.

Fig. 3A and 3B illustrate fins 32 having tapered sidewalls such that the width of each of the fins 32 and/or nanostructures 22, 24 continuously increases in a direction toward the substrate 110. In such embodiments, each of the nanostructures 22, 24 may have a different width and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered) such that the width of the fin 32 and the nanostructures 22, 24 are substantially similar, and each of the nanostructures 22, 24 is rectangular in shape.

In fig. 3A and 3B, isolation regions 36, which may be Shallow Trench Isolation (STI) regions, are formed adjacent to fin 32. Isolation region 36 may be formed by depositing an insulating material over substrate 110, fins 32, and nanostructures 22, 24, and between adjacent fins 32 and nanostructures 22, 24. The insulating material may be an oxide such as silicon oxide, nitride, or the like, or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. In some embodiments, a liner (not separately shown) may first be formed along the surfaces of the substrate 110, fin 32, and nanostructures 22, 24. Thereafter, a filler material or core material, such as those discussed above, may be formed over the liner.

The insulating material is subjected to a removal process, such as a Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, or the like, to remove excess insulating material over the nanostructures 22, 24. After the removal process is complete, the top surfaces of the nanostructures 22, 24 may be exposed and level with the insulating material.

The insulating material is then recessed to form isolation regions 36. After recessing, the nanostructures 22, 24 and upper portions of the fins 32 may protrude from between adjacent isolation regions 36. The isolation region 36 may have a planar (as shown), convex, concave, or a combination thereof top surface. In some embodiments, isolation region 36 is recessed by an acceptable etching process, such as oxide removal using, for example, dilute hydrofluoric acid (dHF), which is selective to the insulating material and leaves fin 32 and nanostructures 22, 24 substantially unchanged.

Fig. 2A-3B illustrate one embodiment (e.g., post etch) of forming fins 32 and nanostructures 22, 24. In some embodiments, the fins 32 and/or nanostructures 22, 24 are epitaxially grown (e.g., etched first) in trenches in the dielectric layer. The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material.

Further in fig. 3A and 3B, suitable wells (not separately shown) may be formed in fin 32, nanostructures 22, 24, and/or isolation region 36. Using the mask, an n-type impurity implantation may be performed in the p-type region of the substrate 110, and a p-type impurity implantation may be performed in the n-type region of the substrate 110. Exemplary n-type impurities may include phosphorus, arsenic, antimony, and the like. Exemplary p-type impurities may include boron, boron fluoride, indium, and the like. An anneal may be performed after implantation to repair the implant damage and activate the p-type and/or n-type impurities. In some embodiments, in situ doping during epitaxial growth of the fin 32 and nanostructures 22, 24 may avoid separate implants, but in situ and implant doping may be used together.

In fig. 4A-4C, a dummy or sacrificial gate structure 40 is formed over fin 32 and/or nanostructures 22, 24. A dummy or sacrificial gate layer 45 is formed over the fins 32 and/or nanostructures 22, 24. The dummy gate layer 45 may be made of a material having a high etching selectivity with respect to the isolation region 36. The dummy gate layer 45 may be a conductive, semiconductive, or nonconductive material, and may be or include one or more of amorphous silicon, polysilicon (poly-silicon), poly-silicon-germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. Dummy gate layer 45 may be deposited by Physical Vapor Deposition (PVD), CVD, sputter deposition, or other technique for depositing the selected material. A mask layer 47, which may include, for example, silicon nitride, silicon oxynitride, or the like, is formed over the dummy gate layer 45. In some embodiments, a gate dielectric layer (not shown for simplicity) is formed before the dummy gate layer 45 and the dummy gate layer 45 between the fins 32 and/or nanostructures 22, 24.

A spacer layer 41 is formed over the sidewalls of the dummy gate layer 45 and the mask layer 47. According to some embodiments, the spacer layer 41 is made of an insulating material, such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon carbonitride oxide, or the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. Spacer layer 41 may be formed by depositing a layer of spacer material (not shown) over mask layer 47 and dummy gate layer 45. According to some embodiments, portions of the spacer material layer between the dummy gate structures 40 are removed using an anisotropic etching process.

In fig. 5A-5C, an etching process is performed to etch the protruding fins 32 and/or portions of the nanostructures 22, 24 not covered by the dummy gate structure 40, resulting in the illustrated structure. The recess may be anisotropic so as to protect and not etch portions of fin 32 directly underneath dummy gate structure 40 and spacer layer 41. According to some embodiments, the top surface of recessed fin 32 may be substantially coplanar with the top surface of isolation region 36, as shown. According to some other embodiments, the top surface of recessed fin 32 may be lower than the top surface of isolation region 36.

Fig. 6A to 6C and fig. 7A to 7C illustrate the formation of the inner spacer 74. A selective etching process is performed to recess the end portions of the nanostructures 24 exposed by the openings in the spacer layer 41 without substantially attacking the nanostructures 22. After the selective etching process, grooves 64 are formed in the nanostructures 24 where the removed end portions were located. The resulting structure is shown in fig. 6A-6C.

Next, an inner spacer layer is formed to fill the recesses 64 in the nanostructures 22 formed by the previous selective etching process. The internal spacer layer may be a suitable dielectric material such as silicon carbonitride (SiCN), silicon oxynitride (SiOCN), or the like, formed by a suitable deposition method such as PVD, CVD, ALD. An etching process, such as an anisotropic etching process, is performed to remove portions of the inner spacer layer that are disposed outside the grooves in the nanostructures 24. The remaining portion of the inner spacer layer (e.g., the portion disposed within the recess 64 in the nanostructure 24) forms the inner spacer 74. The resulting structure is shown in fig. 7A-7C.

Fig. 8A-8C illustrate the formation of source/drain regions 82, corresponding to operations 1200, 2200, 3200 of fig. 14-16. In the illustrated embodiment, the source/drain regions 82 are epitaxially grown from an epitaxial material. In some embodiments, the source/drain regions 82 exert stress in the respective channels 22A-22C, thereby improving performance. The source/drain regions 82 are formed such that each dummy gate structure 40 is disposed between a respective adjacent pair of source/drain regions 82. In some embodiments, spacer layer 41 separates source/drain regions 82 from dummy gate layer 45 by an appropriate lateral distance to prevent electrical bridging to the subsequently formed gates of the resulting device.

Source/drain regions 82 may comprise any acceptable material, such as a material suitable for n-type or p-type devices. In some embodiments, for n-type devices, the source/drain regions 82 comprise a material that imparts a tensile strain in the channel region, such as silicon, siC, siCP, siP, siAs, and the like. According to some embodiments, when forming a p-type device, the source/drain regions 82 comprise a material that imparts a compressive strain in the channel region, such as SiGe, siGeB, ge, geSn and the like. The source/drain regions 82 may have surfaces protruding from the corresponding surfaces of the fins and may have facets. In some embodiments, adjacent source/drain regions 82 may merge to form a single source/drain region 82 adjacent to two adjacent fins 32.

The source/drain regions 82 may be implanted with dopants followed by annealing. The source/drain regions may have a thickness of about 10 ¹⁹ cm ^-3 About 10 ²¹ cm ^-3 The impurity concentration between them. The N-type and/or p-type impurities for source/drain regions 82 may be any of the impurities previously discussed. In some embodiments, the source/drain regions 82 are doped in-situ during growth. A Contact Etch Stop Layer (CESL) and an interlayer dielectric (ILD) may then be formed overlying the dummy gate structure 40 and the source/drain regions 82, not shown for simplicity.

Fig. 9A-9C illustrate the release of fin channels 22A-22C by removing nanostructures 24A-24C, mask layer 47, and dummy gate layer 45, which corresponds to step 1500 of fig. 14. A planarization process, such as CMP, is performed to level the top surfaces of the dummy gate layer 45 and the gate spacer layer 41. The planarization process may also remove mask layer 47 (see fig. 8A) on dummy gate layer 45 and portions of gate spacer layer 41 along sidewalls of mask layer 47. Thus, the top surface of the dummy gate layer 45 is exposed.

Next, the dummy gate layer 45 is removed in an etching process, thereby forming a recess 92. In some embodiments, the dummy gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reaction gas that selectively etches the dummy gate layer 45 without etching the spacer layer 41. The dummy gate dielectric (when present) may serve as an etch stop layer when etching the dummy gate layer 45. The dummy gate dielectric may then be removed after the dummy gate layer 45 is removed.

The nanostructures 24 are removed to release the nanostructures 22. After removal of the nanostructures 24, the nanostructures 22 form a plurality of nanoplatelets extending horizontally (e.g., parallel to the major upper surface of the substrate 110). The nanoplates may be collectively referred to as channels 22 of the formed nanostructure device 20.

In some embodiments, the nanostructures 24 are removed by a selective etching process using an etchant that is selective to the material of the nanostructures 24, thereby removing the nanoparticles without substantially eroding the nanostructures 22A rice structure 24. In some embodiments, the etching process is an isotropic etching process using an etching gas and optionally a carrier gas, wherein the etching gas comprises F ₂ And HF, and the carrier gas may be an inert gas such as Ar, he, N ₂ Combinations thereof, and the like.

In some embodiments, the nanostructures 24 are removed and the nanostructures 22 are patterned to form channel regions of PFETs and NFETs. However, in some embodiments, the nanostructures 24 may be removed and the nanostructures 22 may be patterned to form channel regions of the nanostructure device 20 that is an NFET, and the nanostructures 22 may be removed and the nanostructures 24 may be patterned to form channel regions of the nanostructure device 20 that is a PFET. In some embodiments, the nanostructures 22 may be removed and the nanostructures 24 may be patterned to form channel regions of the nanostructure device 20 that is an NFET, and the nanostructures 24 may be removed and the nanostructures 22 may be patterned to form channel regions of the nanostructure device 20 that is a PFET. In some embodiments, the nanostructures 22 may be removed and the nanostructures 24 may be patterned to form channel regions of PFETs and NFETs.

In some embodiments, the nanoplatelets 22 of the nanostructure device 20 are remodelled (e.g., thinned) by a further etching process to improve the gate fill window. Remodeling may be performed by an isotropic etching process selective for the nanoplatelets 22. After remodeling, the nanoplatelets 22 may exhibit a dog bone shape, wherein a middle portion of the nanoplatelets 22 is thinner than a peripheral portion of the nanoplatelets 22 along the X-direction.

Next, in fig. 10A to 10D, a gate structure 200 is formed, corresponding to operations 1300, 2300, 3300 of fig. 14 to 16. Each gate structure 200 may include a first IL layer 210, a first gate dielectric layer 222, a second gate dielectric layer 230, a second IL layer 240, a first work function metal layer 900, and a gate core layer 290. In some embodiments, the replacement gate 200 includes a second work function layer 700. After depositing the material of gate structure 200, a removal operation, such as CMP, may be performed to remove excess material of gate structure 200 that is located over ILD 130. The resulting structure is shown in fig. 10D.

Fig. 11A-11J are diagrams of various embodiments of an IC device at various stages of forming a front-side via for backside power delivery, in accordance with various embodiments. Fig. 12A-12I are diagrams of various embodiments of an IC device at various stages of forming a front-side via for backside power delivery, in accordance with various embodiments. Fig. 13A-13G are diagrams of various embodiments of an IC device at various stages of forming a front-side via for backside power delivery, in accordance with various embodiments.

In fig. 11A, after forming the gate structure 200, a first mask layer 300 is formed over the ILD 130 and the gate structure 200, followed by one or more second mask layers 320A, 320B formed over the first mask layer 300. In some embodiments, the first mask layer 300 is a hard mask layer and the second mask layer 320A, 320B includes one or more of a photoresist layer, an anti-reflective coating layer, and the like. Portions of the first mask layer 300 are exposed by patterning the second mask layers 320A, 320B. These portions extend in a first direction (e.g., an X-axis direction) that is transverse to the direction of the extension of the gate structure 200. These portions are arranged in a second direction (e.g., Y-axis direction).

In fig. 11B, openings 37, 37A are formed in portions of the first mask layer 300 exposed by the second mask layers 320A, 320B. In some embodiments, the openings 37, 37A include a cell boundary opening 37 and a cell interior opening 37A. The portions of the IC device 10 exposed by the openings 37, 37A in the first mask layer 300 are then etched through the first mask layer 300 to extend the openings 37, 37A to the substrate 110, as shown. Openings 37, 37A may extend through ILD 130, gate structure 200, and isolation region 36, and may extend partially into substrate 110. One or more suitable etching operations may be performed to extend the openings 37, 37A by removing the material of the ILD 130, gate structure 200, isolation region 36, and substrate 110.

In fig. 11C, a fourth isolation layer 140 and a dielectric plug layer 142 are formed in the openings 37, 37A by one or more deposition operations, corresponding to operations 1400, 2400, 3400 of fig. 14-16. The fourth isolation layer 140 may be formed as a conformal layer of the first dielectric material by a first deposition operation such as PVD, CVD, ALD. After forming the isolation layer 140, the dielectric plug layer 142 is formed of a second dielectric material different from the first dielectric material by a second deposition operation such as PVD, CVD, ALD. Dielectric plug layer 142 may be or include the same material as ILD 130. In some embodiments, the fourth isolation layer 140 and the dielectric plug layer 142 are formed by depositing different materials of SiC, laO, alO, alON, zrO, hfO, siN, si, znO, zrN, zrAlO, tiO, taO, YO, taCN, zrSi, siOCN, siOC, siCN, hfSi, laO and SiO. The fourth isolation layer 140 and the dielectric plug layer 142 may be collectively referred to as a gate isolation structure.

The operations shown in fig. 11A-11C may be collectively referred to as a gate structure isolation process (or "cut metal gate process") and may be used to isolate the IC cells from each other and to isolate the nanostructure devices 20 in each of the IC cells from each other.

In fig. 11D, third mask layers 400A, 400B are formed over isolation layer 140 and dielectric plug layer 142, and then patterned to form openings exposing portions of isolation layer 140 and dielectric plug layer 142. The third mask layer 400A, 400B may include one or more photoresist layers, anti-reflective coating layers, hard mask layers, and the like.

In fig. 11E, openings 38 are formed by etching the exposed portions of isolation layer 140 and dielectric plug layer 142 through openings in third mask layers 400A, 400B, corresponding to operation 1500 of fig. 14 and operation 3500 of fig. 16. In some embodiments, the exposed portions are etched by one or more anisotropic etching operations. For example, a first anisotropic etching operation may be performed to remove material of the dielectric plug layer 142 exposed by the openings in the third mask layer 400A, 400B. A second anisotropic etching operation may then be performed to remove (e.g., break down) material of the isolation layer 140 in contact with the substrate 110 so as to expose the substrate 110. In a second anisotropic etching operation, the material at the top of the isolation layer 140 exposed by the openings in the third mask layer 400A, 400B may be recessed, as shown.

In fig. 11F, the material of the power via 150 is deposited in the opening 38 formed by the process described with reference to fig. 11E, corresponding to operation 1600 of fig. 14. The material of the power vias 150 may be deposited by PVD, CVD, ALD, sputtering, or other suitable deposition operations. After depositing the material of the power via 150 in the opening 38, one or more removal operations, such as CMP, may be performed to remove the third mask layers 400A, 400B and the portions of the fourth isolation layer 140 and the dielectric plug layer 142 that overlie the gate structure 200. The removal operation may recess the gate structure, ILD 130, and power via 150 to a level below that shown in fig. 11E.

In fig. 11G, after recessing the structure 10 shown in fig. 11F and planarizing the structure 10 shown in fig. 11F, a hard mask structure 500 may be formed over the gate structure 200, ILD 130, and power supply via 150. In some embodiments, the hard mask structure 500 includes a second isolation layer 124 and a bottom hard mask layer 500A. The hard mask structure 500 may be a multi-layer structure including two or more hard mask layers. For example, as shown in fig. 11G, the hard mask structure 500 includes three hard mask layers located on the bottom hard mask layer 500A.

In fig. 11H, after forming the hard mask structure 500, the hard mask structure 500 is patterned, forming the openings 39. The exposed portions of the second isolation layer 124 and ILD 130 over the source/drain regions 82 are etched through the openings 39. In some embodiments, portions of the fourth isolation layer 140 are removed such that the fourth isolation layer 140 is recessed at the top of the power via 150, exposing portions of one or more sidewalls of the power via 150, as shown. Recessing the fourth isolation layer 140 increases the contact between the power via 150 and the source/drain contact 120 formed in a later operation.

In fig. 11I, source/drain contacts 120 are formed in openings formed by the etching operation described with reference to fig. 11H, corresponding to operation 1700 of fig. 14. In some embodiments, a first isolation layer 122 is formed in the opening prior to forming the source/drain contacts 120. For example, the first isolation layer 122 may be deposited as a thin, conformal layer over sidewalls of the ILD 130. Then, a suitable etching operation may be performed to remove the portion of the first isolation layer 122 located above the source/drain regions 82 so as to expose the source/drain regions 82. After forming the first isolation layer 122, the material of the source/drain contacts 120 may be deposited on the source/drain regions 82 and in contact with the first isolation layer 122. The material of the source/drain contacts 120 may include a glue layer and a conductive core layer. In some embodiments, silicide layer 118 is formed at the interface of source/drain contact 120 and source/drain region 82 (see fig. 1F). A CMP operation may be performed after depositing the source/drain contacts 120 to remove excess material of the source/drain contacts 120 from over the bottom hard mask layer 500A and recess the bottom hard mask layer 500A and the source/drain contacts 120. The bottom hard mask layer 500A may be the first isolation layer 134 after recessing and is so labeled in fig. 11I.

In fig. 11J, after forming the source/drain contacts 120, a backside conductive member 180 is formed, corresponding to operation 1800 of fig. 14. The formation of the backside conductive member 180 may include a plurality of removal and deposition operations. For example, the substrate 110 may be removed by CMP, grinding, or both. After the substrate 110 is removed, the power vias 150 may be exposed. A first backside dielectric layer 160 is formed on isolation region 36, fin 32 (when present), and the bottom surface of power via 150 by a suitable deposition operation. After forming the first backside dielectric layer 160, the backside dielectric layer 160 may be patterned to form openings in which the backside conductive members 180 are deposited.

In some embodiments, the front-side interconnect structure may be formed prior to removing the substrate 110. In some embodiments, the front-side interconnect structure is formed after the back-side interconnect structure is formed. The front-side interconnect structure may include one or more additional dielectric layers (e.g., inter-metal dielectric layers or "IMD" layers) and one or more additional conductive features (e.g., conductive traces, conductive vias, or both) embedded therein.

The operation shown in fig. 11A to 11J is for forming the power supply via 150 from the front side of the IC device 10. In some embodiments, the operations shown in fig. 11A-11J may also be used to form a gate contact (not shown) on the gate structure 200 that contacts the gate structure 200.

In fig. 12A, a removal operation, such as CMP, is performed on the structure shown in fig. 11C, and then a hard mask structure 520 is formed over the resulting structure. For example, after depositing fourth isolation layer 140 and dielectric plug layer 142, a removal operation may be performed to remove excess material of fourth isolation layer 140 and dielectric plug layer 142 that is located over gate structure 200 and ILD 130, which exposes the top surfaces of gate structure 200 and ILD 130. A hard mask structure 520 is then formed over the gate structure 200, ILD 130, fourth isolation layer 140, and dielectric plug layer 142. The hard mask structure 520 may be similar to the hard mask structure 500 described with reference to fig. 11G and includes the second isolation layer 124, a bottom hard mask layer 520A, and one or more additional mask layers located above the bottom hard mask layer 520A. The bottom hard mask layer 520A may be similar or identical to the bottom hard mask layer 500A.

In fig. 12B, after forming the hard mask structure 520, the hard mask structure 520 is patterned, forming the opening 39. The exposed portions of the second isolation layer 124 and ILD 130 over the source/drain regions 82 are etched through the openings 39. In some embodiments, portions of the fourth isolation layer 140 are removed such that the fourth isolation layer 140 is recessed at a top portion of the dielectric plug layer 142, exposing portions of one or more sidewalls of the dielectric plug layer 142, as shown. Recessing the fourth isolation layer 140 increases the contact between the power supply via 150 and the source/drain contact 120, both formed in a respective later operation.

In fig. 12C, source/drain contacts 120 are formed in openings formed by the etching operation described with reference to fig. 12B, corresponding to operation 2500 of fig. 15. In some embodiments, the first isolation layer 122 is formed in the opening prior to forming the source/drain contacts 120. For example, the first isolation layer 122 may be deposited as a thin, conformal layer over sidewalls of the ILD 130, the fourth isolation layer 140, the etch stop layer 131, and the bottom hard mask layer 520A. Then, a suitable etching operation may be performed to remove the portion of the first isolation layer 122 located above the source/drain regions 82 so as to expose the source/drain regions 82. After forming the first isolation layer 122, the material of the source/drain contacts 120 may be deposited on the source/drain regions 82 and in contact with the first isolation layer 122. The material of the source/drain contacts 120 may include a glue layer and a conductive core layer. In some embodiments, silicide layer 118 is formed at the interface of source/drain contact 120 and source/drain region 82 (see fig. 1F). A CMP operation may be performed after depositing the source/drain contacts 120 to remove excess material of the source/drain contacts 120 from over the bottom hard mask layer 520A and recess the bottom hard mask layer 520A and the source/drain contacts 120. The bottom hard mask layer 520A may be the first isolation layer 134 after recessing and is so labeled in fig. 12C.

In fig. 12D, after source/drain contacts 120 are formed, device 10A is flipped over and substrate 110 is removed. Carrier 80 may be attached to the top surface (or "front side") of device 10A by a release layer (not shown). Carrier 80 may comprise glass, ceramic, bulk silicon, etc., while the release layer may comprise a Die Attach Film (DAF), dielectric material, etc. After attaching carrier 80, the orientation of device 10A is flipped (e.g., such that carrier 80 is disposed under device 10A), and substrate 110 is removed. In some embodiments, a planarization process (e.g., CMP, grinding, etc.) may be applied to remove the substrate 110 and expose the fin 32, isolation region 36, fourth isolation layer 140, and dielectric plug layer 142. In some embodiments, fin 32 is removed in a planarization process. In some embodiments, the planarization process stops on an etch stop layer (omitted from the views in the figures) that may be formed prior to the operations shown in fig. 2A, 2B. The etch stop layer (when present) may be in contact with the bottom surfaces of the isolation region 36, the dielectric plug layer 142, and the fourth isolation layer 140. After removing the material underlying the etch stop layer, the etch stop layer may be removed by a suitable etching process, such as an isotropic etch that removes the material of the etch stop layer without substantially attacking the material of the underlying layers mentioned.

In fig. 12E, after removing the substrate 110 and optionally the fin 32, one or more masking layers 440, 420A, 420B are formed on the back side of the device 10A. Masking layers 440, 420A, 420B may include one or more photoresist layers, hard mask layers, antireflective coating layers, etc., and may be patterned to form openings 79 exposing dielectric plug layer 142. In some embodiments, opening 79 exposes fourth isolation layer 140 and isolation region 36.

In fig. 12F, after masking layers 440, 420A, 420B are formed and patterned (which forms openings 79), exposed portions of device 10A are etched through openings 79, forming openings 79E, corresponding to operation 2600 of fig. 15. The etching operation removes portions of the dielectric plug layer 142 that overlie the source/drain contacts 120, exposing the respective undersides of the source/drain contacts 120. In some embodiments, the etching operation is an anisotropic etch using an etchant that is selective to the material of dielectric plug layer 142. Because the etching operation is performed from the backside of device 10A, opening 79E may have a narrower tapered profile closer to source/drain contact 120. The taper angle of the opening 79E may be in the range of about 80 degrees to 90 degrees (e.g., perpendicular).

In fig. 12G, after forming the opening 79E, the power supply via 150 is formed by depositing the material of the power supply via 150 in the opening 79E, corresponding to operation 2700 of fig. 15. In some embodiments, a glue layer is deposited in opening 79E prior to depositing the material of power via 150. For example, the glue layer may comprise TiN, taN, or other suitable material. The power vias 150 may be entirely or partially located on the respective source/drain contacts 120 as shown. For example, the power vias 150 may be located on the source/drain contacts 120 and on the remaining portions of the dielectric plug layer 142 exposed by the openings 79E. After depositing the material of the power vias 150, a planarization operation, such as CMP, may be performed to remove excess material of the power vias 150, and optionally excess material of the glue layer on the backside of the device 10A. After the planarization operation, the power supply via 150 may include an overhang portion 150V on the fourth isolation layer 140.

In fig. 12H, after forming the power supply via 150, a first backside dielectric layer 160 may be formed on the backside of the device 10A, and one or more backside conductive members 180 may be formed in the first backside dielectric layer 160, corresponding to operation 2800 of fig. 15. In some embodiments, the first backside dielectric layer 160 is formed by a suitable deposition operation, such as PVD, CVD, ALD. After depositing the first back side dielectric layer 160, an opening may be formed in the first back side dielectric layer 160, and the material of the back side conductive feature 180 may be formed in the opening in the back side dielectric layer 160. The opening exposes the underside of the power via 150 such that the backside conductive member 180 is electrically connected to (e.g., in contact with) the power via 150. In some embodiments, after forming the backside conductive feature 180, additional backside dielectric layers and backside conductive features (e.g., power rails/lines 250; see fig. 1G) may be formed on the backside dielectric layer 160 and the backside conductive feature 180. The additional backside dielectric layer and backside conductive features may be collectively referred to as a backside interconnect structure.

In fig. 12I, carrier 80 may be removed and device 10A may be flipped to produce the structure shown in fig. 12I. In some embodiments, the front-side interconnect structure may be formed prior to removing the substrate 110. In some embodiments, the front-side interconnect structure is formed after the back-side interconnect structure is formed. The front-side interconnect structure may include one or more additional dielectric layers (e.g., inter-metal dielectric or "IMD" layers) and one or more additional conductive features (e.g., conductive traces, conductive vias, or both) embedded therein.

Fig. 13A-13G are views of various embodiments of IC device 10B at various stages of forming front-side via 150 for back-side power delivery, in accordance with various embodiments.

In fig. 13A, a deposition operation, such as PVD, CVD, ALD, etc., is performed on the structure shown in fig. 11E to form a dielectric structure 190 instead of forming a power via 150, corresponding to operation 3600 of fig. 16. After depositing the material of dielectric structure 190, a suitable removal operation, such as CMP, is performed to remove the material of fourth isolation layer 140, dielectric plug layer 142, dielectric structure 190, and expose gate structure 200 and ILD 130. In some embodiments, the gate structure 200 is recessed by a removal operation. The material of the dielectric structure 190 is different from those of the fourth isolation layer 140 and the dielectric plug layer 142, for example, has different etching selectivity from those of the fourth isolation layer 140 and the dielectric plug layer 142.

In fig. 13B, a hard mask structure 540 is formed over the gate structure 200, ILD 130, fourth isolation layer 140, and dielectric plug layer 142. The hard mask structure 540 may be similar to the hard mask structure 500 described with reference to fig. 11G and includes the second isolation layer 124, the bottom hard mask layer 540A, and one or more additional mask layers located above the bottom hard mask layer 540A. The bottom hard mask layer 540A may be similar or identical to the bottom hard mask layer 500A.

In fig. 13C, after forming the hard mask structure 540, the hard mask structure 540 may be patterned to form openings. The exposed portions of the second isolation layer 124 and ILD 130 over the source/drain regions 82 are etched through the openings. In some embodiments, portions of the fourth isolation layer 140 are removed such that the fourth isolation layer 140 is recessed at a top portion of the dielectric structure 190, exposing portions of one or more sidewalls of the dielectric structure 190, as shown. Recessing the fourth isolation layer 140 increases the contact between the power via 150 and the source/drain contact 120.

Further in fig. 13C, source/drain contacts 120 are formed in the openings, corresponding to operation 3700 of fig. 16. In some embodiments, the first isolation layer 122 is formed in the opening prior to forming the source/drain contacts 120. For example, the first isolation layer 122 may be deposited as a thin, conformal layer over sidewalls of the ILD 130, the fourth isolation layer 140, the etch stop layer 131, and the bottom hard mask layer 540A. Then, a suitable etching operation may be performed to remove the portion of the first isolation layer 122 located above the source/drain regions 82 so as to expose the source/drain regions 82. After forming the first isolation layer 122, the material of the source/drain contacts 120 may be deposited on the source/drain regions 82 and in contact with the first isolation layer 122. The material of the source/drain contacts 120 may include a glue layer and a conductive core layer. In some embodiments, silicide layer 118 is formed at the interface of source/drain contact 120 and source/drain region 82 (see fig. 1F). A CMP operation may be performed after depositing the source/drain contacts 120 to remove excess material of the source/drain contacts 120 from over the bottom hard mask layer 540A and recess the bottom hard mask layer 540A and the source/drain contacts 120. The bottom hard mask layer 540A may be the first isolation layer 134 after recessing and is so labeled in fig. 13C.

In fig. 13D, device 10B is flipped over, substrate 110 is removed, and masking layer 620 is formed over the back side of device 10B. The masking layer 620, which may be a hard mask layer, is patterned and openings 89 are formed in the areas of the device 10B exposed by the masking layer 620. The opening 89 may be formed by an etching operation that removes material of the dielectric structure 190 without substantially attacking the material of the fourth isolation layer 140 and the dielectric plug layer 142. In some embodiments, the etching operation is or includes isotropic etching or anisotropic etching. After the etching operation, the underside of the source/drain contacts 120 are exposed. The opening 89 may have a tapered profile such that the width of the opening 89 (e.g., in the Y-axis direction) is narrower closer to the source/drain contact 120 and wider closer to the backside of the device 10B.

In fig. 13E, when the device 10B is flipped, after forming the opening 89, a power via 150 is formed in the opening 89 by one or more deposition operations, corresponding to operation 3800 of fig. 16. In some embodiments, a glue layer is formed in the openings 89 on the sidewalls of the fourth isolation layer 140, the source/drain contacts 120, and the dielectric plug layer 142. The material of the power vias 150 is deposited in the openings 89 by a suitable deposition operation, such as PVD, CVD, ALD, sputtering, etc. After depositing the material of the power via 150, a suitable removal operation, such as CMP, may be performed to remove excess material of the power via 150 and optionally the glue layer from over the isolation region 36, fin 32, fourth isolation layer 140, and dielectric plug layer 142. The power supply through hole 150 takes the shape of the opening 89, and thus may have a tapered profile as described with reference to fig. 13D.

In fig. 13F, after forming the power supply via 150, a first backside dielectric layer 160 may be formed on the backside of the device 10B, and one or more backside conductive members 180 may be formed in the first backside dielectric layer 160, corresponding to operation 3900 of fig. 16. In some embodiments, the first backside dielectric layer 160 is formed by a suitable deposition operation, such as PVD, CVD, ALD. After depositing the first back side dielectric layer 160, an opening may be formed in the first back side dielectric layer 160, and the material of the back side conductive feature 180 may be formed in the opening in the back side dielectric layer 160. The opening exposes the underside of the power via 150 such that the backside conductive member 180 is electrically connected to (e.g., in contact with) the power via 150. In some embodiments, after forming the backside conductive feature 180, additional backside dielectric layers and backside conductive features (e.g., power rails/lines 250; see fig. 1G) may be formed on the backside dielectric layer 160 and the backside conductive feature 180. The additional backside dielectric layer and backside conductive features may be collectively referred to as a backside interconnect structure.

In fig. 13G, carrier 80 may be removed and device 10B may be flipped, resulting in the structure shown in fig. 13G. In some embodiments, the front-side interconnect structure may be formed prior to removing the substrate 110. In some embodiments, the front-side interconnect structure is formed after the back-side interconnect structure is formed. The front-side interconnect structure may include one or more additional dielectric layers (e.g., inter-metal dielectric or "IMD" layers) and one or more additional conductive features (e.g., conductive traces, conductive vias, or both) embedded therein.

Embodiments may provide advantages. The power vias 150 provide front side signal routing flexibility by enabling power lines to be provided on the back sides of the devices 10, 10A, 10B. Forming the power lines on the back side of the devices 10, 10A, 10B allows for wider power lines, which reduces resistance and increases power efficiency. The power vias 150 may be formed by replacement gate isolation structures, which may be implemented from the front side of the device, the back side of the device, or both.

In accordance with at least one embodiment, a device includes a stack of semiconductor nanostructures, a gate structure surrounding the semiconductor nanostructures, source/drain regions adjoining the gate structure and the stack, a contact structure located on the source/drain regions, a backside dielectric layer located below the stack, and a via structure extending from the contact structure to a top surface of the backside dielectric layer.

According to at least one embodiment, a method comprises: forming a nanostructure channel vertical stack over a substrate; forming source/drain regions adjacent the nanostructure channel; forming a gate structure surrounding the nanostructure channel; forming a via structure adjacent to and laterally isolated from the source/drain regions; forming a contact structure in contact with the via structure and the source/drain regions; and forming a backside interconnect structure in contact with the via structure.

According to at least one embodiment, a method comprises: forming a nanostructure channel vertical stack over a substrate; forming source/drain regions adjacent the nanostructure channel; forming a gate structure surrounding the nanostructure channel; forming a gate isolation structure isolating portions of the gate structure from each other; forming a contact structure having an underside in contact with the source/drain regions and the gate isolation structure; exposing the gate isolation structure by removing the substrate; forming an opening in the gate isolation structure, the opening exposing the underside of the contact structure; and forming a via structure in the opening, the via structure being in contact with the contact structure.

Some embodiments of the present application provide a device comprising: a stack of semiconductor nanostructures; a gate structure surrounding the semiconductor nanostructure; source/drain regions adjacent to the gate structure and the stack; a contact structure located on the source/drain region; a backside dielectric layer located under the stack; and a via structure extending from the contact structure to a top surface of the backside dielectric layer. In some embodiments, a first portion of an upper surface of the via structure is in contact with the contact structure and a second portion of the upper surface is in contact with the isolation layer. In some embodiments, the entire upper surface of the via structure is in contact with the contact structure. In some embodiments, portions of the sidewalls of the via structures are in contact with the contact structures. In some embodiments, the via structure is laterally separated from the source/drain regions by an isolation layer. In some embodiments, the device further comprises: a semiconductor fin is located between the stack and the backside dielectric layer. In some embodiments, the via structure has a width that increases as it approaches the backside dielectric layer.

Further embodiments of the present application provide a method comprising: forming a nanostructure channel vertical stack over a substrate; forming source/drain regions adjacent to the nanostructure channel; forming a gate structure surrounding the nanostructure channel; forming a via structure adjacent to and laterally isolated from the source/drain regions; forming a contact structure in contact with the via structure and the source/drain regions; and forming a backside interconnect structure in contact with the via structure. In some embodiments, the forming the via structure includes: forming a first opening for removing part of the gate structure; forming a dielectric plug in the first opening; forming a second opening exposing the substrate by removing at least a portion of the dielectric plug; and forming the through hole structure in the second opening. In some embodiments, the forming a dielectric plug includes: forming an isolation layer in the first opening; and forming a dielectric plug layer on the isolation layer. In some embodiments, a top portion of the isolation layer is recessed when the second opening is formed. In some embodiments, the forming the via structure includes: forming an intermediate device structure by forming a dielectric layer in the second opening; exposing the substrate by flipping the intermediate device structure; exposing a bottom side of the dielectric layer by removing the substrate; opening the second opening by removing the dielectric layer, the second opening exposing the contact structure; and forming the via structure by depositing a material of the via structure in the second opening while flipping the intermediate device structure. In some embodiments, the method further comprises: and forming a backside power line in electrical contact with the via structure.

Still other embodiments of the present application provide a method comprising: forming a nanostructure channel vertical stack over a substrate; forming source/drain regions adjacent to the nanostructure channel; forming a gate structure surrounding the nanostructure channel; forming a gate isolation structure isolating portions of the gate structure from each other; forming a contact structure having an underside in contact with the source/drain regions and the gate isolation structure; exposing the gate isolation structure by removing the substrate; forming an opening in the gate isolation structure, the opening exposing the underside of the contact structure; and forming a via structure in the opening, the via structure being in contact with the contact structure. In some embodiments, the method further comprises: forming a backside dielectric layer in contact with the via structure; exposing the via structure by forming a second opening in the backside dielectric layer; and forming a backside conductive member in the second opening. In some embodiments, the method further comprises: a power line is formed in electrical connection with the backside conductive member. In some embodiments, the method further comprises: forming a second source/drain region adjacent the nanostructure channel opposite the source/drain region; and forming a signal line electrically connected to the second source/drain region, the signal line being located on a front side of the second source/drain region and being vertically separated from the second source/drain region by a front side dielectric layer. In some embodiments, removing the substrate removes semiconductor fins located under the nanostructure channel vertical stack. In some embodiments, forming an opening in the gate isolation structure includes removing a portion of a dielectric plug layer of the gate isolation structure that is located below the contact structure. In some embodiments, forming an opening in the gate isolation structure further comprises removing a portion of an isolation layer of the gate isolation structure that is in contact with the contact structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising:

a stack of semiconductor nanostructures;

a gate structure surrounding the semiconductor nanostructure;

source/drain regions adjacent to the gate structure and the stack;

a contact structure located on the source/drain region;

a backside dielectric layer located under the stack; and

a via structure extends from the contact structure to a top surface of the backside dielectric layer.

2. The semiconductor device of claim 1, wherein a first portion of an upper surface of the via structure is in contact with the contact structure and a second portion of the upper surface is in contact with the isolation layer.

3. The semiconductor device of claim 1, wherein the entire upper surface of the via structure is in contact with the contact structure.

4. The semiconductor device of claim 1, wherein a portion of a sidewall of the via structure is in contact with the contact structure.

5. The semiconductor device of claim 4, wherein the via structure is laterally separated from the source/drain regions by an isolation layer.

6. The semiconductor device of claim 1, further comprising: a semiconductor fin is located between the stack and the backside dielectric layer.

7. The semiconductor device of claim 1, wherein the via structure has a width that increases as it approaches the backside dielectric layer.

8. A method of forming a semiconductor device, comprising:

forming a nanostructure channel vertical stack over a substrate;

forming source/drain regions adjacent to the nanostructure channel;

forming a gate structure surrounding the nanostructure channel;

forming a via structure adjacent to and laterally isolated from the source/drain regions;

forming a contact structure in contact with the via structure and the source/drain regions; and

And forming a backside interconnection structure in contact with the through hole structure.

9. The method of claim 8, wherein the forming a via structure comprises:

forming a first opening for removing part of the gate structure;

forming a dielectric plug in the first opening;

forming a second opening exposing the substrate by removing at least a portion of the dielectric plug; and

and forming the through hole structure in the second opening.

10. A method of forming a semiconductor device, comprising:

forming a nanostructure channel vertical stack over a substrate;

forming source/drain regions adjacent to the nanostructure channel;

forming a gate structure surrounding the nanostructure channel;

forming a gate isolation structure isolating portions of the gate structure from each other;

forming a contact structure having an underside in contact with the source/drain regions and the gate isolation structure;

exposing the gate isolation structure by removing the substrate;

forming an opening in the gate isolation structure, the opening exposing the underside of the contact structure; and

a via structure is formed in the opening, the via structure being in contact with the contact structure.