CN117393556A - Single-particle transient layout reinforcement method based on source isolation in nano CMOS (complementary metal oxide semiconductor) process - Google Patents
Single-particle transient layout reinforcement method based on source isolation in nano CMOS (complementary metal oxide semiconductor) process Download PDFInfo
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Abstract
The invention discloses a single-particle transient layout reinforcement method based on source isolation in a nano CMOS process, which comprises the following steps: step 1: finding a PMOS tube connected with a power supply in a layout structure of a standard unit; step 2: if the layout of the standard unit only contains one PMOS tube, adding a new PMOS tube P1 above the layout of the PMOS tube; step 3: if the layout of the standard unit comprises two or more PMOS tubes, the PMOS tubes connected with the power supply are isolated from other PMOS tubes by a shallow trench isolation technology. The layout design method provided by the invention can be used for reinforcing any combination logic layout structure. For a complex combined logic circuit layout structure, the aim of resisting the single event transient effect can be achieved by isolating a PMOS tube connected with a power supply from other PMOS tubes through STI and then connecting the isolated PMOS source and drain electrodes through a first layer of metal.
Description
Technical Field
The invention relates to the technical field of layout design, in particular to a single-particle transient layout reinforcement method based on source isolation in a nano CMOS process.
Background
In space there are a large number of energetic particles (protons, electrons, heavy ions, etc.). After the integrated circuit is bombarded with these energetic particles, a Single Event Transient (SET) occurs and has a significant negative impact on the normal operation of the integrated circuit. For example, when a SET pulse propagates to a memory cell, if the corresponding timing constraint of the memory cell is satisfied, the SET pulse is latched by the memory cell and converted to a Single Event Upset (SEU). The higher the Linear Energy Transfer (LET) value of a single particle bombarded integrated circuit, the greater the width of the SET pulse generated, and the greater the threat to the proper operation of the integrated circuit. Integrated circuits used in the aviation and aerospace fields are threatened by single-event transients, so that the integrated circuits work unstably and even generate fatal errors, and therefore, development of an advanced layout design method for resisting the single-event transients is particularly important in the integrated circuits.
Standard units such as an inverter, a NAND gate, a NOR gate and the like are basic units forming an integrated circuit, and the single event transient resistance of the standard units directly determines the single event transient resistance of the integrated circuit. Therefore, the single-event transient resistance capability of the integrated circuit can be improved by researching the single-event transient resistance layout design method of the standard unit. A layout design method for reducing the SET pulse width is proposed by Amsan et al on IEEE Transactions on Nuclear Science (institute of Electrical and electronics Engineers), "Design techniques to reduce SET pulse widths in deep-submicron combinational logic" (design technique for reducing the SET pulse width in combinational logic cells under ultra-deep submicron technology) (volume 54, pages 2060-2064, 12 th month of 2007). The method achieves the purpose of reducing charges generated by a single particle bombardment circuit by adding a guard band around the sensitive transistor. The method uses the inverter layout structure in the standard unit as an illustration of the working mechanism of the layout design method. The traditional inverter layout structure consists of a PMOS tube and an NMOS tube, wherein the source electrode of the PMOS tube is connected with a power supply, the source electrode of the NMOS tube is connected with the ground, the grid electrode of the PMOS tube is connected with the grid electrode of the NMOS tube to serve as the input end of the inverter, and the drain electrode of the PMOS tube is connected with the drain electrode of the NMOS tube to serve as the output end of the inverter. The layout design method for adding the guard ring is to surround the PMOS tube by an active region to form a guard ring on the basis of the traditional inverter layout structure, and connect the guard ring with a power supply. The method has the advantage that the contact area between the N well of the PMOS tube and the power supply is increased. When the particles vertically bombard the PMOS tube, the particles bombard to generate electron-hole pairs in the N well, wherein electrons can be quickly absorbed by a power supply, so that the single-particle transient pulse width increase caused by the collapse of the N well barrier can be relieved. The shortcomings of adding a protection ring layout design method are pointed out by "Effect of Multiple-Transistor Charge Collection on Single-Event Transient Pulse Widths" (influence of multi-transistor charge collection on single event transient pulse width) (11 rd edition 3, volume 11, page 400-405) published by Ahlbin et al in IEEE Transactions on Device and Material Reliability (IEEE device and Material reliability Congress). When particles bombard the drain electrode of the PMOS tube according to a certain angle, the source electrode of the PMOS tube is also affected by the particle bombardment, so that the bipolar effect of the PMOS tube is enhanced, and the SET pulse width generated by the layout structure of the added guard ring is larger than that of the conventional inverter layout structure. In addition, as the process dimension is reduced to 90nm and below, the distance between the source electrode and the drain electrode of each MOS transistor is correspondingly reduced, and the source electrode is also affected by particle bombardment. Therefore, when the process size is reduced to 90nm or below, the layout design method for increasing the protection ring has too large area cost, and the reinforcing effect on the SET can be reduced. A layout design method for suppressing SET based on the pulse cut-off principle is proposed in "Layout Technique for Single-Event Transient Mitigation via Pulse Quenching" (layout technology for alleviating single event transient by pulse cut-off method) published by nichas m.atkinson et al in IEEE Transaction on Nuclear Science (IEEE journal of nuclear science) (volume 58, pages 885-890 of 6 th month of 2011), and the working mechanism of the layout design method is illustrated by taking the or gate layout structure as an example. The traditional OR gate layout structure consists of three PMOS tubes P1, P2, P3 and three NMOS tubes N1, N2, N3. Sources of P1 and P3 tubes in the POMS tube are connected with a power supply, and sources of N1, N2 and N3 tubes in the NMOS tube are connected with ground. The drains of the N1 and N2 pipes are respectively connected with the drain of the P2 pipe and the grid of the P3 pipe. The grid electrode of the P1 pipe and the grid electrode of the N1 pipe are connected to be used as an input end, the grid electrode of the P2 pipe and the grid electrode of the N2 pipe are connected to be used as another input end, the grid electrode of the P3 pipe and the grid electrode of the N3 pipe are connected to be used as input ends of the inverter, and the drain electrode of the P3 pipe and the drain electrode of the N3 pipe are connected to be used as output ends. Compared with the traditional OR gate, the gate layout structure adopting the pulse cutting method is additionally provided with a PMOS tube P4 and an NMOS tube N4 at the left side of the layout, the source electrode of the P4 tube is connected with a power supply, and the source electrode of the N4 tube is connected with the ground. The gate of the P4 pipe is connected with the gate of the N4 pipe and with the drain of the P2 pipe. The drain electrode of the P4 pipe is connected with the drain electrode of the N4 pipe and is connected with the drain electrodes of the P3 pipe and the N3 pipe as output ends. The advantage of this structure is that when the particles bombard the P1 tube, a single transient pulse is generated at the drain of the P2 tube, which would flip the inverter formed by the P3 tube and the N3 tube, however, the drain of the P3 tube is also affected by the particle bombardment due to the charge sharing effect, and a bipolar effect is generated in the P3 tube. This effect counteracts the flipping due to the single event transient pulse. When the particles bombard the drain electrode of the P2 tube, the newly added P4 tube exists at the left side of the P2 tube, and the bipolar effect generated by the particle bombardment in the P4 tube can offset the overturn caused by the single-particle transient pulse, so the structure can relieve the SET effect caused by the particle bombardment on the OR gate circuit. The layout design method has the defects that the method is only suitable for some special logic circuits, and the area cost is increased due to the fact that one PMOS tube and one NMOS tube are added in the method. The layout design method through the pulse cut-off method needs to meet two basic conditions, firstly, the logic circuit needs to be a circuit with an inversion function, and secondly, an inverter unit needs to be arranged near the logic unit bombarded by particles so as to generate charge sharing to relieve the pulse generated by a single-particle transient, so that the application range of the method is limited, and the method can only be applied to some special logic circuits.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a single-particle transient layout reinforcement method based on source isolation in a nano CMOS process, so as to solve the problems in the background technology.
In order to achieve the above purpose, the present invention provides the following technical solutions: a single-particle transient layout reinforcement method based on source isolation in a nano CMOS process comprises the following steps:
step 1: finding a PMOS tube connected with a power supply in a layout structure of a standard unit;
step 2: if the layout of the standard unit only contains one PMOS tube, adding a new PMOS tube P1 above the layout of the PMOS tube; the width W of the P1 pipe is the same as that of the original PMOS pipe;
step 3: if the layout of the standard unit comprises two or more PMOS tubes, the PMOS tubes connected with the power supply are isolated from other PMOS tubes through a shallow trench isolation technology, the space between the PMOS tubes connected with the power supply and the other PMOS tubes meets the minimum space required by the layout design rule, and the connection relation between the PMOS tubes is kept unchanged.
Preferably, in the step B, the P1 pipe is isolated from the original PMOS pipe by a shallow trench isolation technology, the distance between the P1 pipe and the original PMOS pipe meets the minimum distance required by the layout design rule, and finally, the source electrode of the P1 pipe is connected with the power supply, the gate electrode of the P1 pipe is connected with the gate electrode of the original PMOS pipe, and the drain electrode of the P1 pipe is connected with the source electrode of the original PMOS pipe.
Preferably, in the step B, when the input is high level, the output is low level, the newly added PMOS transistor and the original PMOS transistor are turned off, and at this time, when a single particle bombards the drain electrode of the original PMOS transistor, electron-hole pairs are generated at the drain electrode of the original PMOS transistor, wherein the holes drift to the output end due to the action of the electric field and change the output from low level to high level, so as to generate a single-particle transient pulse.
Preferably, the inverter layout structure comprises an N well 6, an N well contact 7, a first PMOS tube 8 with a width W P A second PMOS tube 9 with width W P A first NMOS tube 10 having a width W N The substrate contact 11 is formed by connecting the grid electrode G of the first PMOS tube and the grid electrode G of the second PMOS tube as the input of the inverter, connecting the drain electrode D of the second PMOS tube and the drain electrode D of the first NMOS tube as the output of the inverter, and connecting the source electrode S of the first NMOS tube and the ground.
Preferably, the two-input NOR gate layout structure comprises an N well 17, an N well contact 18, a first PMOS tube 19 with a width W P A second PMOS tube 20 having a width W P A first NMOS tube and a second NMOS tube 21 having a width W N The source electrode S of the first PMOS tube is connected with a power supply, the drain electrode D of the first PMOS tube is isolated from the source electrode S of the second PMOS tube through STI, the drain electrode D of the first PMOS tube is connected with the source electrode S of the second PMOS tube through a first layer of metal, the drain electrode D of the second PMOS tube is connected with the drain electrode D1 of the first NMOS tube and is connected with the drain electrode D2 of the second NMOS tube to serve as an output end of a two-input NOR gate, the source electrodes S of the first NMOS tube and the second NMOS tube are connected with the ground, and the grid electrode G1 of the first PMOS tube is connected with the grid electrode G1 of the first NMOS tubeThe pole G1 is connected as a first input end, and the grid G2 of the second PMOS tube is connected with the grid G2 of the second NMOS tube as a second input end.
Compared with the prior art, the invention has the beneficial effects that: the layout design method provided by the invention damages the structure of the parasitic transistor in the PMOS tube, reduces the quantity of holes injected into the PMOS tube by the power supply, and reduces the maintenance time of single-event transient pulses, thereby obviously reducing the pulse width generated by single-event bombardment and relieving the influence of the single-event transient effect on the circuit; in addition, the layout design method provided by the invention can be used for reinforcing any combination logic layout structure. For a complex combined logic circuit layout structure, the aim of resisting the single event transient effect can be fulfilled only by isolating a PMOS tube connected with a power supply from other PMOS tubes through STI and then connecting the isolated PMOS source and drain electrodes through a first layer of metal, so the layout design method provided by the invention is not limited for the layout structure required to be reinforced.
Drawings
FIG. 1 is an inverter layout structure designed using the layout design method proposed by the present invention;
FIG. 2 is a layout structure of a typical inverter;
FIG. 3 is a typical two-input NOR gate layout structure;
FIG. 4 is a diagram of a two-input NOR gate layout designed using the layout design method of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-4, the present invention provides a technical solution: a single-particle transient layout reinforcement method based on source isolation in a nano CMOS process comprises the following steps:
step 1: finding a PMOS tube connected with a power supply in a layout structure of a standard unit;
step 2: if the layout of the standard unit only contains one PMOS tube, adding a new PMOS tube P1 above the layout of the PMOS tube; the width W of the P1 pipe is the same as that of the original PMOS pipe;
step 3: if the layout of the standard unit comprises two or more PMOS tubes, the PMOS tubes connected with the power supply are isolated from other PMOS tubes through a shallow trench isolation technology, the space between the PMOS tubes connected with the power supply and the other PMOS tubes meets the minimum space required by the layout design rule, and the connection relation between the PMOS tubes is kept unchanged.
In the step B, the P1 pipe and the original PMOS pipe are isolated by a shallow trench isolation technology, the distance between the P1 pipe and the original PMOS pipe meets the minimum distance required by the layout design rule, the source electrode of the P1 pipe is finally connected with a power supply, the grid electrode of the P1 pipe is connected with the grid electrode of the original PMOS pipe, and the drain electrode of the P1 pipe is connected with the source electrode of the original PMOS pipe.
In addition, in the step B, when the input is at a high level, the output is at a low level, the newly added PMOS tube and the original PMOS tube are cut off, at the moment, when single particles bombard the drain electrode of the original PMOS tube, electron hole pairs are generated at the drain electrode of the original PMOS tube, wherein holes drift to the output end due to the action of an electric field and change the output from the low level to the high level, single-particle transient pulses are generated, electrons cannot diffuse to the source electrode of the newly added PMOS tube due to the blocking action of STI between the original PMOS tube and the newly added PMOS tube, so that almost no holes are injected into the original PMSO tube by a power supply connected with the source electrode of the newly added PMOS tube, parasitic bipolar amplification effect is weakened, the single-particle transient pulse maintaining time is reduced, and the pulse width is correspondingly reduced.
In step C, the working process of the anti-single event transient effect is the same. Electrons can not diffuse to the sources of other PMOS tubes due to the blocking effect of STI between the PMOS tube connected with the power supply and other PMOS tubes, so that few holes are injected into other PMSO tubes by the power supply, parasitic bipolar amplification effect is weakened, single-event transient pulse maintaining time is shortened, and pulse width is correspondingly reduced.
The inverter layout structure designed by the layout design method provided by the invention comprises an N well 6, an N well contact 7 and a first PMOS tube 8, wherein the width of the first PMOS tube is W P A second PMOS tube 9 with width W P A first NMOS tube 10 having a width W N The substrate contact 11 is formed by connecting the grid electrode G of the first PMOS tube and the grid electrode G of the second PMOS tube as the input of the inverter, connecting the drain electrode D of the second PMOS tube and the drain electrode D of the first NMOS tube as the output of the inverter, and connecting the source electrode S of the first NMOS tube and the ground.
Fig. 2 is a layout structure of a typical inverter. The layout structure of the typical inverter comprises an N well 1, an N well contact 2, a first PMOS tube 3, and a width W P A first NMOS tube 4 with width W N And a substrate contact 5. The source electrode S of the first PMOS tube is connected with a power supply, the grid electrode G of the first PMOS tube is connected with the grid electrode G of the first NMOS tube, the drain electrode D of the first PMOS tube is connected with the drain electrode D of the first NMOS tube, and the source electrode S of the first NMOS tube is connected with ground.
Fig. 3 is a typical two-input nor gate layout structure. The layout structure of the typical inverter comprises an N well 12, an N well contact 13, a first PMOS tube and a second PMOS tube 14 which are in series connection, and a width W P A first NMOS tube and a second NMOS tube 15 with parallel connection and width W N And a substrate contact 16. The source electrode S of the first PMOS tube is connected with a power supply, and the drain electrode D of the second PMOS tube is connected with the drain electrode D1 of the first NMOS tube and connected with the drain electrode D2 of the second NMOS tube. The grid electrode G1 of the first PMOS tube is connected with the grid electrode G1 of the first NMOS tube. The grid electrode G2 of the second PMOS tube is connected with the grid electrode G2 of the second NMOS tube. The sources S of the first NMOS tube and the second NMOS tube are connected with the ground.
FIG. 4 is a two-input NOR gate layout designed by the layout design method of the present inventionStructure is as follows. The two-input NOR gate layout structure comprises an N well 17, an N well contact 18, a first PMOS tube 19 with the width W P A second PMOS tube 20 having a width W P A first NMOS tube and a second NMOS tube 21 having a width W N The source electrode S of the first PMOS tube is connected with a power supply, the drain electrode D of the first PMOS tube is isolated from the source electrode S of the second PMOS tube through STI, the drain electrode D of the first PMOS tube is connected with the source electrode S of the second PMOS tube through a first layer of metal, the drain electrode D of the second PMOS tube is connected with the drain electrode D1 of the first NMOS tube and is connected with the drain electrode D2 of the second NMOS tube to serve as an output end of a two-input NOR gate, the source electrodes S of the first NMOS tube and the second NMOS tube are connected with the ground, the grid electrode G1 of the first PMOS tube is connected with the grid electrode G1 of the first NMOS tube to serve as a first input end, and the grid electrode G2 of the second PMOS tube is connected with the grid electrode G2 of the second NMOS tube to serve as a second input end.
The area comparison of the designed inverter, the two-input NOR gate layout structure, the typical inverter, the two-input NOR gate layout structure and the inverter and the two-input NOR gate layout structure designed by adding the protection ring mode under the process size of 65nm is shown in the table 1. It can be seen from table 1 that the layout design method provided by the invention is smaller than the layout area of the increased guard ring although the original layout area is increased.
Table 1 comparison of layout areas for three layout design methods
In summary, the layout design method provided by the invention damages the structure of the parasitic transistor in the PMOS tube, reduces the number of holes injected into the PMOS tube by the power supply, and reduces the maintenance time of the single-event transient pulse, thereby obviously reducing the pulse width generated by single-event bombardment and relieving the influence of the single-event transient effect on the circuit; in addition, the layout design method provided by the invention can be used for reinforcing any combination logic layout structure. For a complex combined logic circuit layout structure, the aim of resisting the single event transient effect can be fulfilled only by isolating a PMOS tube connected with a power supply from other PMOS tubes through STI and then connecting the isolated PMOS source and drain electrodes through a first layer of metal, so the layout design method provided by the invention is not limited for the layout structure required to be reinforced.
The circuit, the electronic components and the modules are all in the prior art, and can be completely realized by a person skilled in the art, and needless to say, the protection of the invention does not relate to the improvement of software and a method.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (5)
1. A single-particle transient layout reinforcement method based on source isolation in a nano CMOS process is characterized in that: the method comprises the following steps:
step 1: finding a PMOS tube connected with a power supply in a layout structure of a standard unit;
step 2: if the layout of the standard unit only contains one PMOS tube, adding a new PMOS tube P1 above the layout of the PMOS tube; the width W of the P1 pipe is the same as that of the original PMOS pipe;
step 3: if the layout of the standard unit comprises two or more PMOS tubes, the PMOS tubes connected with the power supply are isolated from other PMOS tubes through a shallow trench isolation technology, the space between the PMOS tubes connected with the power supply and the other PMOS tubes meets the minimum space required by the layout design rule, and the connection relation between the PMOS tubes is kept unchanged.
2. The single-particle transient layout reinforcement method based on source isolation in the nano CMOS process of claim 1, wherein the method is characterized in that: in the step B, the P1 pipe is isolated from the original PMOS pipe by a shallow trench isolation technology, the distance between the P1 pipe and the original PMOS pipe meets the minimum distance required by the layout design rule, the source electrode of the P1 pipe is finally connected with a power supply, the grid electrode of the P1 pipe is connected with the grid electrode of the original PMOS pipe, and the drain electrode of the P1 pipe is connected with the source electrode of the original PMOS pipe.
3. The single-particle transient layout reinforcement method based on source isolation in the nano CMOS process of claim 1, wherein the method is characterized in that: in the step B, when the input is high level, the output is low level, the newly added PMOS tube and the original PMOS tube are cut off, at the moment, when single particles bombard the drain electrode of the original PMOS tube, electron hole pairs are generated at the drain electrode of the original PMOS tube, wherein the holes drift to the output end due to the action of an electric field and the output is changed from low level to high level, and single-particle transient pulses are generated.
4. The single-particle transient layout reinforcement method based on source isolation in the nano CMOS process of claim 1, wherein the method is characterized in that: the inverter layout structure comprises an N well 6, an N well contact 7, a first PMOS tube 8 with a width W P A second PMOS tube 9 with width W P A first NMOS tube 10 having a width W N The source electrode S of the first PMOS tube is connected with a power supply, the drain electrode D of the first PMOS tube is isolated from the source electrode S of the second PMOS tube through STI, the drain electrode D of the first PMOS tube is connected with the source electrode S of the second PMOS tube through a first layer of metal, the grid electrode G of the first PMOS tube and the grid electrode G of the second PMOS tube are connected and used as the input of an inverter, and the drain electrode D of the second PMOS tube is connected with the drain electrode D of the first NMOS tube and used as the input of the inverterAnd outputting, wherein the source electrode S of the first NMOS tube is connected with the ground.
5. The single-particle transient layout reinforcement method based on source isolation in the nano CMOS process of claim 1, wherein the method is characterized in that: the two-input NOR gate layout structure comprises an N well 17, an N well contact 18, a first PMOS tube 19 with the width W P A second PMOS tube 20 having a width W P A first NMOS tube and a second NMOS tube 21 having a width W N The source electrode S of the first PMOS tube is connected with a power supply, the drain electrode D of the first PMOS tube is isolated from the source electrode S of the second PMOS tube through STI, the drain electrode D of the first PMOS tube is connected with the source electrode S of the second PMOS tube through a first layer of metal, the drain electrode D of the second PMOS tube is connected with the drain electrode D1 of the first NMOS tube and is connected with the drain electrode D2 of the second NMOS tube to serve as an output end of a two-input NOR gate, the source electrodes S of the first NMOS tube and the second NMOS tube are connected with the ground, the grid electrode G1 of the first PMOS tube is connected with the grid electrode G1 of the first NMOS tube to serve as a first input end, and the grid electrode G2 of the second PMOS tube is connected with the grid electrode G2 of the second NMOS tube to serve as a second input end.
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