CN110830021A - Single event effect resisting reinforcing circuit of CMOS integrated circuit - Google Patents
Single event effect resisting reinforcing circuit of CMOS integrated circuit Download PDFInfo
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- CN110830021A CN110830021A CN201911242247.3A CN201911242247A CN110830021A CN 110830021 A CN110830021 A CN 110830021A CN 201911242247 A CN201911242247 A CN 201911242247A CN 110830021 A CN110830021 A CN 110830021A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
Abstract
The invention discloses a single event effect resisting reinforcement circuit of a CMOS integrated circuit, and belongs to the technical field of radiation resisting reinforcement of integrated circuits and circuits. The circuit comprises a pull-up network, a pull-down network and a source substrate voltage setting network, wherein the pull-up network, the pull-down network and the source substrate voltage setting network share an input end, the voltage of a power supply port and the voltage of a substrate of the pull-up network are provided by the source substrate voltage setting network, the voltage of a ground port and the voltage of the substrate of the pull-down network are also provided by the source substrate voltage setting network, and the pull-up network and the pull-down network are connected to form an output port. The invention not only can complete the logic function of the common CMOS integrated circuit, but also has the performance of high performance and single event effect resistance.
Description
Technical Field
The invention relates to the technical field of integrated circuits and circuit radiation resistance reinforcement, in particular to a CMOS integrated circuit single event effect resistance reinforcement circuit.
Background
With the rapid development and mutual integration of disciplines such as materials, chemistry, engineering and the like, the minimum size of devices in integrated circuits is continuously breaking through the limit. The integrated circuit is the core of aerospace and electronic products, and with the continuous reduction of the size of the integrated circuit, the power supply voltage is continuously reduced, the thickness of a gate oxide layer reaches several nanometers, the integration level is high, and other technical changes, obvious changes and more serious challenges are brought to the radiation-resistant reinforcement design of the integrated circuit, for example, the influence of the total dose effect on the integrated circuit is very small due to the very thin thickness of the gate oxide layer, the single event effect is obviously aggravated due to the reduction of the power supply voltage, the multiple-bit single event upset aggravated due to the improvement of the integration level, and the radiation-resistant design is updated and has higher requirements.
For CMOS integrated circuits, the region of the integrated circuit most sensitive to incident particles is typically a reverse biased PN junction, the drain electrode of a field effect transistor operating in the off state is reverse biased, and a strong applied voltage exists between the drain region and the substrate. When particles with high energy are incident to the drain region of the cut-off tube, a large number of free electron-hole pairs are generated on the incident track by the action of the particles and materials, and a built-in electric field between the drain region and the substrate is damaged, so that a strong electric field generated by an applied voltage can extend downwards along the incident track to form a funnel-like shape, and the phenomenon is called a funnel effect. Under the funnel effect, a drain region of the semiconductor transistor is approximately conducted with the substrate, and under an applied voltage, most of a large number of electron-hole pairs generated by incident particles are collected by the drain region and the substrate to form transient pulse current. Single event transients can produce erroneous logic signals and cause overall system malfunction.
Disclosure of Invention
In view of this, the present invention provides a single event effect resistant reinforcement circuit for a CMOS integrated circuit, which can improve the single event effect resistance of the circuit.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a CMOS integrated circuit reinforcing circuit for resisting single event effect comprises a pull-up network and a pull-down network; the source-substrate voltage setting network is used for setting the source electrode and the substrate voltage of the transistors in the pull-up network and the pull-down network; the power supply port and the substrate voltage port of the pull-up network, the ground port and the substrate voltage port of the pull-down network are connected to the output end of the source substrate voltage setting network, the pull-up network is connected with the pull-down network, the connection point serves as the output end of the whole reinforcement circuit, and the input ends of the source substrate voltage setting network, the pull-up network and the pull-down network are connected and serve as the input end of the whole reinforcement circuit.
Further, the output voltage of the source-substrate voltage setting network is the same as the voltage of the output end of the whole reinforcing circuit.
Furthermore, the source-side voltage setting network is composed of an upper part and a lower part, wherein the upper part has the same structure as the pull-up network, the lower part has the same structure as the pull-down network, the upper part and the lower part are connected, the connection part forms the output end of the source-side voltage setting network, and meanwhile, the upper part and the lower part share the input end and are connected to the input end of the whole reinforcing circuit.
Furthermore, the source-substrate voltage setting network is composed of an upper part and a lower part, wherein the upper part is a circuit obtained by splitting or combining the PMOS devices in the pull-up network according to the size, the lower part is a circuit obtained by splitting or combining the NMOS devices in the pull-down network according to the size, the upper part and the lower part are connected, the connection part forms the output end of the source-substrate voltage setting network, and meanwhile, the upper part and the lower part share the input end and are connected to the input end of the whole reinforcing circuit.
By adopting the technical scheme, the invention has the following beneficial effects:
1. in the invention, when the input combination enables the output to be at a low level, the source-substrate voltage setting network sets the power input end of the pull-up network and the substrate to be at a low level, and the output is also at a low level, so that the voltage difference between the drain electrode of the transistor of the pull-up network and the substrate is zero, after high-energy particles enter the drain electrode of the transistor of the pull-up network and generate a large number of electron hole pairs, because the voltage difference between the drain electrode of the transistor and the substrate is zero, the electron hole pairs are not greatly collected by the drain electrode under the action of an electric field, and only can absorb a little in the diffusion process of the electron hole pairs, thereby greatly reducing the influence on the voltage of an output node, and greatly improving the performance of the circuit for.
2. In the invention, when the input combination makes the output be high level, the source-substrate voltage setting network sets the grounding end of the pull-down network and the substrate to be high level, and the output is also high level, so that the voltage difference between the drain electrode of the transistor of the pull-down network and the substrate is zero, after high-energy particles are incident to the drain electrode of the transistor of the pull-down network and generate a large number of electron hole pairs, because the voltage difference between the drain electrode of the transistor and the substrate is zero, the electron hole pairs can not be greatly collected by the drain electrode under the action of an electric field, and only can absorb a little in the diffusion process of the electron hole pairs, thereby greatly reducing the influence on the voltage of an output node, and further greatly improving the performance of the circuit for resisting.
3. By using the invention, no matter the output is high level or low level, the voltage difference between the drain electrode of the output end sensitive node and the substrate is zero, and no electric field absorbs electron hole pairs, so that the influence of high-energy particle incidence on the output node level is minimum. The method has a great effect on improving the performance of the circuit against the single event effect.
Drawings
FIG. 1 is a diagram of a circuit for reinforcing the single event effect resistance of a CMOS integrated circuit according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a nand gate reinforcement circuit according to an embodiment of the invention.
FIG. 3 is a comparison graph of single event simulation results for a conventional NAND gate circuit and the circuit of FIG. 2. Wherein, the curve general is the output curve of the ordinary nand gate, and the curve harded is the output curve of the reinforced nand gate in fig. 2.
Detailed Description
To further clarify the objects, technical solutions and advantages of the present invention, the following detailed description of the present invention will be made with reference to the accompanying drawings.
As shown in FIG. 1, the circuit for reinforcing the single event effect resistance of the CMOS integrated circuit comprises a pull-up network, a pull-down network and a source-substrate voltage setting network, wherein the source-substrate voltage setting network is used for setting the voltages of the source electrode and the substrate of a transistor in the pull-up network and the pull-down network, the pull-up network, the pull-down network and the source-substrate voltage setting network share an input end input, the voltage of a power supply port of the pull-up network and the voltage of the substrate are provided by the source-substrate voltage setting network, the voltage of a ground port of the pull-down network and the voltage of the substrate are also provided by the source-substrate voltage setting network, and the pull-up network and the pull-down network are connected to.
In the circuit, the output voltage of a source substrate voltage setting network is the same as the output voltage of the whole reinforcing circuit, and the structures of a pull-up network and a pull-down network are the same as the structures of a standard pull-up network and a standard pull-down network.
In general, the off-state NMOS or the off-state PMOS in the pull-up network and the pull-down network are sensitive to single-event transient effects. The NMOS or PMOS in off state has voltage difference between the source and drain (or drain and body), but no current exists between the source and drain because the device is in off state and no current path exists. When a single particle is incident to an off-state NMOS or PMOS, a current path is formed between a source and a drain or between a drain and a body in the process of generating a single-particle transient effect, and a voltage difference exists between the source and the drain (or between the source and the drain) so that the off-state device can generate current under irradiation.
In the circuit, the source-substrate voltage setting network can eliminate the source-drain voltage difference and the drain voltage difference of the NMOS or the PMOS in an off state, so that the single-particle transient effect can be weakened. In order to eliminate the source-drain voltage difference and the drain-body voltage difference of the sensitive NMOS or PMOS, the source-substrate voltage setting network is used for short-circuiting a VDD port and a substrate voltage port of the pull-up network and a GND port and a substrate voltage port of the pull-down network and is connected to the output end of the source-substrate voltage setting network.
The structure of the source substrate voltage setting network can take many forms. For example, the source substrate voltage setting network may be the same as the pull-up network and the pull-down network. That is, in the circuit configuration of the source substrate voltage setting network, the upper half portion may duplicate a pull-up network, and the lower half portion may duplicate a pull-down network, and then these two duplicate networks are connected to form the output terminal of the source substrate voltage setting network. The pull-up and pull-down networks in the source substrate voltage setting network share an input end and are connected to an input port of the whole reinforcing circuit. The power supply VDD port, GND port and substrate port of the source substrate voltage setting network are normally connected to the VDD and GND power supply lines.
In addition, the upper part and the lower part of the source substrate voltage setting network can also be different from the structures of the pull-up network and the pull-down network. Specifically, in the circuit structure of the source-substrate voltage setting network, the upper half part of the source-substrate voltage setting network can split or combine the PMOS devices in the pull-up network of the reinforcing circuit according to the size, for example, a PMOS transistor with a gate width of 200 μm can be split into two PMOS transistors with a gate width of 100 μm connected in parallel; the lower half of the source substrate voltage setting network can split or combine NMOS devices in the pull-down network of the reinforcing circuit according to the size.
Fig. 2 is a reinforcing circuit of a two-input nand gate reinforced by a source-substrate voltage setting network. The P1 tube and the P2 tube form a pull-up network, the N1 tube and the N2 tube form a pull-down network, and the P3 tube, the P4 tube, the N3 tube and the N4 tube form a source-substrate voltage setting network. When only one of the input signals is low level, the level of the output OUT and the level of the node A are high level at the same time, the substrates of the N1 transistor and the N2 transistor are high level, the voltage difference between the drain of the N1 transistor and the substrate is 0, and when the single-event incidence transistor N1 is arranged on the drain, the influence on the output voltage is reduced to the minimum. When the output OUT is at low level, the node A reduces the voltage of the source and the substrate of the transistors P1 and P2 to low level, which is the same as the output node, thereby reducing the influence of single event effect on the voltage of the output node.
Impact of the source-substrate voltage setting network on circuit performance: the transistors P1, P2 are connected in parallel and "in series" with the parallel transistors P3, P4, but the rising edge rises more slowly than in series; the transistors N1 and N2 are connected in series and then connected in series with the transistors N3 and N4, which are connected in series, similarly, the falling speed of the falling edge is slower than that of the series connection, and the size of the transistors is increased to maintain a certain driving capability.
In the embodiment of fig. 2, the pull-up network and the pull-down network of the circuit are respectively duplicated in the upper half part and the lower half part of the source substrate voltage setting network, and in actual use, the source substrate voltage setting network may also have a structure different from that of the pull-up network and the pull-down network. For example, the P4 transistor of the source-substrate voltage setting network is split into two transistors, where each transistor has a gate width of half of P4. Similar splitting and merging transformations can be performed for the lower half of the source substrate voltage setting network. It should be noted that all the source-substrate voltage setting network structures that can short-circuit the VDD terminal of the pull-up network, the GND terminal of the pull-down network, and the substrate voltage terminals of the two networks are consistent with the core idea of the present invention, and belong to the protection scope of the present invention.
FIG. 3 is a comparison graph of single event simulation results for a conventional NAND gate circuit and the circuit of FIG. 2. Wherein, curve general is the output curve of the ordinary NAND gate, and curve harded is the output curve of the reinforced NAND gate. It can be seen from the figure that at the time of 2ns, the output voltage of the ordinary nand gate has dropped to nearly 0.1V, the output logic has already been seriously inverted, while the output voltage of the reinforced nand gate has dropped by less than 0.4mV, only a glitch is generated in the output, and the logic level inversion of the output node is not changed. When the output is high level, the output logic level of the common NAND gate is already seriously inverted at the moment of 7ns, and the reinforced NAND gate is not inverted.
As is well known to those skilled in the art, a CMOS integrated circuit has a sensitive node in any output condition, when the sensitive node exists, if high-energy particles are incident to the sensitive node, a large number of free electron-hole pairs are generated on an incident track of the sensitive node and acted on materials, a built-in electric field between a drain region and a substrate is damaged, the drain region of a semiconductor transistor and the substrate are approximately conducted, and under the applied voltage, a large number of electron-hole pairs generated by the incident particles are mostly collected by the drain region and the substrate, so that the logic of the output node is wrong. The invention provides a single event effect resistance reinforcing circuit of a CMOS integrated circuit, which can improve the single event effect resistance of the circuit and is an important improvement on the prior art.
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only examples of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (4)
1. A CMOS integrated circuit reinforcing circuit for resisting single event effect comprises a pull-up network and a pull-down network; the method is characterized in that: the source-substrate voltage setting network is used for setting the source electrode and the substrate voltage of the transistors in the pull-up network and the pull-down network; the power supply port and the substrate voltage port of the pull-up network, the ground port and the substrate voltage port of the pull-down network are connected to the output end of the source substrate voltage setting network, the pull-up network is connected with the pull-down network, the connection point serves as the output end of the whole reinforcement circuit, and the input ends of the source substrate voltage setting network, the pull-up network and the pull-down network are connected and serve as the input end of the whole reinforcement circuit.
2. The CMOS integrated circuit single event effect resistant ruggedization circuit of claim 1, wherein: the output voltage of the source-substrate voltage setting network is the same as the voltage of the output end of the whole reinforcing circuit.
3. The CMOS integrated circuit single event effect resistant ruggedization circuit of claim 1, wherein: the source substrate voltage setting network is composed of an upper part and a lower part, wherein the structure of the upper part is the same as that of the pull-up network, the structure of the lower part is the same as that of the pull-down network, the upper part and the lower part are connected, the connection part forms the output end of the source substrate voltage setting network, and meanwhile, the upper part and the lower part share the input end and are connected to the input end of the whole reinforcing circuit.
4. The CMOS integrated circuit single event effect resistant ruggedization circuit of claim 1, wherein: the source substrate voltage setting network is composed of an upper part and a lower part, wherein the upper part is a circuit obtained by splitting or combining PMOS devices in the pull-up network according to sizes, the lower part is a circuit obtained by splitting or combining NMOS devices in the pull-down network according to sizes, the upper part and the lower part are connected, the connection position forms an output end of the source substrate voltage setting network, and meanwhile, the upper part and the lower part share an input end and are connected to the input end of the whole reinforcing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911242247.3A CN110830021A (en) | 2019-12-06 | 2019-12-06 | Single event effect resisting reinforcing circuit of CMOS integrated circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911242247.3A CN110830021A (en) | 2019-12-06 | 2019-12-06 | Single event effect resisting reinforcing circuit of CMOS integrated circuit |
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| Publication Number | Publication Date |
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| CN110830021A true CN110830021A (en) | 2020-02-21 |
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| CN201911242247.3A Pending CN110830021A (en) | 2019-12-06 | 2019-12-06 | Single event effect resisting reinforcing circuit of CMOS integrated circuit |
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