CN117392951B

CN117392951B - Power supply detection circuit, silicon-based display panel and display device

Info

Publication number: CN117392951B
Application number: CN202311654559.1A
Authority: CN
Inventors: 刘炳麟; 吴桐; 张皓东
Original assignee: Shanghai Shiya Technology Co ltd
Current assignee: Shanghai Shiya Technology Co ltd
Priority date: 2023-12-05
Filing date: 2023-12-05
Publication date: 2024-03-19
Anticipated expiration: 2043-12-05
Also published as: CN117392951A

Abstract

The invention discloses a power supply detection circuit, a silicon-based display panel and a display device, wherein the power supply detection circuit comprises: the power supply detection module, the voltage regulation module and the initialization module; the power supply detection module is used for outputting a first control signal to the initialization module when the first power supply and/or the second power supply are/is not powered on normally; the voltage regulating module is used for outputting a power supply signal with larger potential in the first power supply and the second power supply as a first voltage signal to the initializing module, and outputting a power supply signal with the largest potential in the first power supply, the second power supply and the third power supply as a second voltage signal to the initializing module; the initialization module is used for outputting a second voltage signal to the load as a first initialization signal under the control of the first control signal, and outputting a power signal or a ground signal of a negative-pressure power supply electrically connected with the second voltage signal to the load as a second initialization signal. By adopting the technical scheme, the uncontrolled current in the load can be avoided, and the reliability of the power supply detection circuit and the load is improved.

Description

Power supply detection circuit, silicon-based display panel and display device

Technical Field

The present invention relates to the field of circuit technologies, and in particular, to a power supply detection circuit, a silicon-based display panel, and a display device.

Background

The organic light emitting display device has advantages of self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, wide application temperature range, etc., and is known in the industry as the display device with the most development potential nowadays.

In general, signals of different potentials are required in a display device, and the display device includes a level shift circuit that matches the level circuits of different potentials so as to provide signals of different potentials to the display device.

However, the level shifter circuit needs to receive signals of different power supplies, and when part of the power supplies are not powered on or are abnormally powered on, the level shifter circuit is easy to be out of control, and the display device is damaged. Therefore, it is particularly important to perform power supply detection for the display device.

Disclosure of Invention

The invention provides a power supply detection circuit, a silicon-based display panel and a display device, which are used for solving the problems that partial power supply is not electrified or is abnormally electrified and the circuit is out of control.

According to an aspect of the present invention, there is provided a power supply detection circuit including: the power supply detection module, the voltage regulation module and the initialization module;

the power supply detection module is respectively and electrically connected with the first power supply, the second power supply and the initialization module; the power supply detection module is used for outputting a first control signal to the initialization module when the first power supply and/or the second power supply are/is not powered on normally; the power supply detection module is also used for outputting a second control signal to the initialization module when the first power supply and the second power supply are powered on normally;

The voltage regulating module is electrically connected with the first power supply, the second power supply, the third power supply and the initializing module respectively; the voltage regulating module is used for outputting a power supply signal with larger potential in the first power supply and the second power supply as a first voltage signal to the initializing module, and outputting a power supply signal with the largest potential in the first power supply, the second power supply and the third power supply as a second voltage signal to the initializing module;

the initialization module is used for outputting a second voltage signal to the load as a first initialization signal under the control of the first control signal, and outputting a power signal or a ground signal of a negative-pressure power supply electrically connected with the second voltage signal to the load as a second initialization signal; the initialization module is further used for outputting a ground signal to the load as a first initialization signal and outputting a first voltage signal to the load as a second initialization signal under the control of the second control signal.

According to another aspect of the present invention, there is provided a silicon-based display panel including: the display device comprises a silicon-based substrate, a display unit and a power module; the power supply module comprises the power supply detection circuit;

the power module and the display unit are both formed on a silicon-based substrate.

According to still another aspect of the present invention, there is provided a display device including: the silicon-based display panel.

According to the technical scheme, the power supply detection module is used for detecting the electric potentials of the first power supply and the second power supply, outputting a first control signal to the initialization module when any one of the first power supply and the second power supply is not powered on normally, and simultaneously outputting an effective first voltage signal and an effective second voltage signal to the initialization module by the voltage regulation module so that the initialization module outputs a first initialization signal with a higher electric potential and a second initialization signal with a lower electric potential, and a middle circuit of a load electrically connected with the initialization module is controlled to be not operated; when the power supply detection module detects that the first power supply and the second power supply are powered on normally, outputting a second control signal to the initialization module, so that the initialization module outputs a first initialization signal with a lower potential and a second initialization signal with a higher potential, and controlling a load electrically connected with the initialization module to work; therefore, by detecting the potentials of the first power supply and the second power supply in real time, outputting corresponding control signals according to the power-on states of the first power supply and the second power supply and outputting effective first voltage signals and second voltage signals, when any one power supply is not powered on normally, effective first initialization signals and second initialization signals are still output, circuits in a load are controlled to be not operated, and the phenomena that the circuits in the load enter an uncontrollable state, uncontrollable abnormal heavy current occurs, and functional modules in the load are damaged are avoided. The power supply detection circuit provided by the embodiment of the invention protects the load from being damaged easily, and improves the reliability of the power supply detection circuit and the load.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a prior art power detection circuit;

FIG. 2 is a schematic diagram of a positive voltage level shifter circuit;

FIG. 3 is a schematic diagram of a negative voltage level shifter circuit;

fig. 4 is a schematic structural diagram of a power detection circuit according to an embodiment of the present invention;

FIG. 5 is a timing diagram of a power detection circuit corresponding to FIG. 4;

FIG. 6 is a schematic diagram of a power detection circuit according to another embodiment of the present invention;

FIG. 7 is a schematic diagram of a power detection circuit according to another embodiment of the present invention;

FIG. 8 is a schematic diagram of a power detection circuit according to another embodiment of the present invention;

FIG. 9 is a schematic diagram of a power detection circuit according to another embodiment of the present invention;

FIG. 10 is a schematic diagram of a power detection circuit according to another embodiment of the present invention;

FIG. 11 is a schematic diagram of a power detection circuit according to another embodiment of the present invention;

FIG. 12 is a schematic diagram of a power detection circuit according to another embodiment of the present invention;

FIG. 13 is a schematic diagram of a power detection circuit according to another embodiment of the present invention;

FIG. 14 is a schematic diagram of a power detection circuit according to another embodiment of the present invention;

FIG. 15 is a schematic view of a silicon-based display panel according to an embodiment of the present invention;

fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic diagram of a prior art power detection circuit, referring to fig. 1, the power detection circuit 001 includes a power detection module 002, and the power detection module 002 receives a medium voltage power signal vph_1, a reference signal Vref and a ground signal VN, and outputs an enable signal pwr_ready and a disable signal xpwr_ready. The power detection module 002 includes a comparator circuit, and when the potential of the medium voltage power supply signal vph_1 is higher than the potential of the reference signal Vref, the enable signal pwr_ready is 1, and the disable signal xpwr_ready is 0, indicating that the power-up of the medium voltage power supply signal vph_1 is completed. The power supply detection circuit 001 also outputs a first initialization control signal Reset and a second initialization control signal XReset to control an operation state of a circuit electrically connected to the power supply detection circuit 001; the power detection module 002 includes an enable terminal 003 for outputting an enable signal pwr_ready, the enable terminal 003 is electrically connected to two inverters 004 connected in series in sequence, the output terminal of a first inverter 004 electrically connected to the enable terminal 003 outputs a second initialization control signal XReset, and the output terminal of a second inverter 004 electrically connected to the enable terminal 003 through the first inverter outputs a first initialization control signal Reset. The medium voltage power supply signal vph_1 may be a power supply signal of a medium voltage circuit such as an interface circuit.

Fig. 2 is a schematic diagram of a structure of the positive voltage level conversion circuit, referring to fig. 2, the positive voltage level conversion circuit 005 receives a first initialization control signal Reset outputted from the power supply detection circuit 001, and the first initialization control signal Reset can control the on/off state of the enable control tube T01 of the positive voltage level conversion circuit 005, so as to control whether the positive voltage level conversion circuit 005 operates. The positive voltage level conversion circuit 005 is further connected to the low voltage power supply signal vp_l, the high voltage power supply signal vph_2, and the ground signal VN to perform level conversion IN a positive voltage range on the electric signal of the positive voltage input terminal in_1, and the positive voltage output terminal out_1 outputs the converted electric signal.

Fig. 3 is a schematic diagram of a negative voltage level conversion circuit, referring to fig. 3, the negative voltage level conversion circuit 006 receives a second initialization control signal XReset output by the power detection circuit 001, where the second initialization control signal XReset can control the on/off state of the enable control tube T02 of the negative voltage level conversion circuit 006, so as to control whether the negative voltage level conversion circuit 006 works. The negative voltage level conversion circuit 006 further receives the negative voltage power supply signal vp_l, the negative voltage power supply signal vn_l, and the ground signal VN to perform level conversion IN a negative voltage range on the electric signal of the negative voltage input terminal in_2, and the negative voltage output terminal out_2 outputs the converted electric signal.

Referring to fig. 1 and 2, when only the medium voltage power supply signal vph_1 is not successfully powered on or is abnormally powered on, the power supply detection circuit 001 is turned off, the first initialization control signal Reset is 0, the enable control tube T01 in the positive voltage level conversion circuit 005 is disabled, and both the positive voltage power supply signal vp_l and the high voltage power supply signal vph_2 are successfully powered on, so that the positive voltage level conversion circuit 005 has a part of nodes suspended, resulting in abnormal current, the electrical signal output by the positive voltage output terminal out_1 is uncontrollable, and unexpected large current is likely to be caused, and a functional module electrically connected with the positive voltage output terminal out_1 is damaged; when the power-on of the medium voltage power supply signal vph_1 and the power-on of the low voltage power supply signal vp_l are unsuccessful or abnormal, the first initialization control signal Reset is also 0, and the power-on of the high voltage power supply signal vph_2 is successful, which may cause unexpected large current, and damage the functional module electrically connected to the positive voltage output terminal out_1.

Similarly, referring to fig. 1 and 3, when the power supply signal vph_1 is not successfully powered on or is abnormally powered on, the power supply detection circuit 001 is turned off, the first initialization control signal Reset and the second initialization control signal XReset are both 0, the enable control tube T02 of the negative voltage level conversion circuit 006 is turned on, the negative voltage control signal is pulled up to the potential of the power supply signal vp_l, the negative voltage power supply signal vn_l is successfully powered on, and the electric signal output by the negative voltage output terminal out_2 is uncontrollable; when the power-on of the power-on signal vp_l is unsuccessful or abnormal, the second initialization control signal XReset is also 0, the power-on of the negative voltage power-on signal vn_l is successful, the electric signal output by the negative voltage output terminal out_2 is uncontrollable, and an uncontrollable large current may be output, and the functional module electrically connected with the negative voltage output terminal out_2 may be damaged.

As described in the background art, when the low voltage power supply signal vp_l providing the lower potential and the medium voltage power supply signal vph_1 providing the intermediate potential are not successfully powered up or are abnormally powered up, and the high voltage power supply signal vph_2 providing the higher potential and the negative voltage power supply signal vn_l providing the negative voltage in the circuit are successfully powered up, the control signal of the circuit is disabled, so that the circuit cannot communicate with the external system, and the large current inside the circuit is uncontrollable, which is likely to damage the functional module connected with the circuit.

To solve the above technical problem, an embodiment of the present invention provides a power supply detection circuit, including: the power supply detection module, the voltage regulation module and the initialization module; the power supply detection module is respectively and electrically connected with the first power supply, the second power supply, the third power supply and the initialization module; the power supply detection module is used for outputting a first control signal to the initialization module when the first power supply and/or the second power supply are/is not powered on normally; the power supply detection module is also used for outputting a second control signal to the initialization module when the first power supply and the second power supply are powered on normally; the voltage regulating module is electrically connected with the first power supply, the second power supply, the third power supply and the initializing module respectively; the voltage regulating module is used for outputting a power supply signal with larger potential in the first power supply and the second power supply as a first voltage signal to the initializing module, and outputting a power supply signal with the largest potential in the first power supply, the second power supply and the third power supply as a second voltage signal to the initializing module; the initialization module is used for outputting a second voltage signal to the load as a first initialization signal under the control of the first control signal, and outputting a power signal or a ground signal of a negative-pressure power supply electrically connected with the second voltage signal to the load as a second initialization signal; the initialization module is further used for outputting a ground signal to the load as a first initialization signal and outputting a first voltage signal to the load as a second initialization signal under the control of the second control signal.

By adopting the technical scheme, the power supply detection module is used for detecting the electric potentials of the first power supply and the second power supply, outputting a first control signal to the initialization module when any one of the first power supply and the second power supply is not normally electrified, and simultaneously outputting an effective first voltage signal and an effective second voltage signal to the initialization module by the voltage regulation module so that the initialization module outputs a first initialization signal with higher electric potential and a second initialization signal with lower electric potential, and controlling a circuit in a load electrically connected with the initialization module to be inoperative; when the power supply detection module detects that the first power supply and the second power supply are powered on normally, outputting a second control signal to the initialization module, so that the initialization module outputs a first initialization signal with a lower potential and a second initialization signal with a higher potential, and controlling a load electrically connected with the initialization module to work; therefore, by detecting the potentials of the first power supply and the second power supply in real time, outputting corresponding control signals according to the power-on states of the first power supply and the second power supply and outputting effective first voltage signals and second voltage signals, when any one power supply is not powered on normally, effective first initialization signals and second initialization signals are still output, circuits in a load are controlled to be not operated, and the phenomena that the circuits in the load enter an uncontrollable state, uncontrollable abnormal heavy current occurs, and functional modules in the load are damaged are avoided. The power supply detection circuit provided by the embodiment of the invention protects the load from being damaged easily, and improves the reliability of the power supply detection circuit and the load.

The above is the core idea of the invention, and based on the embodiments of the invention, all other embodiments obtained by a person skilled in the art without making any inventive effort are within the scope of the invention. The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.

Fig. 4 is a schematic structural diagram of a power detection circuit according to an embodiment of the present invention. Referring to fig. 4, the power detection circuit 01 includes a power detection module 10, a voltage adjustment module 20, and an initialization module 30. The power detection module 10 is electrically connected to the first power VPL, the second power VPH1, the third power VPH2 and the initialization module 30, respectively, and the power detection module 10 is configured to output a first control signal ctr1 to the initialization module 30 when the first power VPL and/or the second power VPH1 are not normally powered on, and the power detection module 10 is further configured to output a second control signal ctr2 to the initialization module 30 when the first power VPL and the second power VPH1 are both normally powered on. The voltage adjustment module 20 is electrically connected to the first power supply VPL, the second power supply VPH1, the third power supply VPH2, and the initialization module 30, and the voltage adjustment module 20 is configured to output a power supply signal with a larger potential of the first power supply VPL and the second power supply VPH1 as a first voltage signal vp1 to the initialization module 30, and output a power supply signal with a largest potential of the first power supply VPL, the second power supply VPH1, and the third power supply VPH2 as a second voltage signal vp2 to the initialization module 30. The initialization module 30 is configured to output the second voltage signal vp2 as the first initialization signal Reset1 to the load under the control of the first control signal ctr1, and output the negative voltage power supply signal vn_l or the ground signal VN electrically connected thereto as the second initialization signal XReset2 to the load, and the initialization module 30 is further configured to output the ground signal VN as the first initialization signal Reset1 to the load under the control of the second control signal ctr2, and output the first voltage signal vp1 as the second initialization signal XReset2 to the load.

Wherein the load includes, but is not limited to, a low voltage circuit, a medium voltage circuit, and a high voltage circuit, and the load further includes a functional module electrically connected with the circuit, the functional module of the load including a display unit when the load is applied to the silicon-based display panel. The first power supply VPL may be a power supply of a low-voltage circuit such as a digital circuit, and the first power supply VPL may provide a first power supply signal vp_l for a logic determination module in the low-voltage circuit, where the first power supply signal vp_l is a positive voltage signal with a lower potential. The second power supply VPH1 may be a power supply of a medium voltage circuit such as an interface circuit, and the second power supply VPH1 may provide a second power supply signal vph_1 for a switch control module in the medium voltage circuit, where the second power supply signal vph_1 is a positive voltage signal of an intermediate potential. The third power supply VPH2 may be a power supply of a high voltage circuit such as a switching circuit, and the third power supply VPH2 may provide a third power supply signal vph_2 for a low dropout regulator or other structure in the high voltage circuit, where the third power supply signal vph_2 is typically a positive voltage signal with a high potential. The negative voltage power supply VNL is a power supply of the negative voltage circuit, and the negative voltage power supply VNL may provide, for example, a negative voltage power supply signal vn_l, which is typically a negative voltage signal of a lower potential. The ground signal VN is a zero potential signal. The first initialization signal Reset1 of the initialization module 30 is electrically connected to the circuit of the positive power domain in the load and is used for controlling the initialization state of the circuit of the positive power domain; the second initialization signal XReset2 of the initialization module 30 is electrically connected to the circuit of the negative voltage power supply domain in the load for controlling the initialization state of the circuit of the negative voltage power supply domain. The initialization state comprises an inactive state and an active state, wherein the inactive state is a circuit non-conducting state, and the active state is a circuit conducting state.

When the first power supply VPL, the second power supply VPH1, the third power supply VPH2 and the negative voltage power supply VNL are powered on normally, the potential of the negative voltage power supply signal vn_l provided by the negative voltage power supply VNL is smaller than 0, and the potentials of the first power supply signal vp_l provided by the first power supply VPL, the second power supply signal vph_1 provided by the second power supply VPH1 and the third power supply signal vph_2 provided by the third power supply VPH2 are all larger than 0. In general, the potential of the first power supply signal vp_l is smaller than the potential of the second power supply signal vph_1, and the potential of the second power supply signal vph_1 is smaller than the potential of the third power supply signal vph_2. When the power supply is powered on normally, the power supply signal of the power supply rises to the stable range of the power supply, for example, the power supply signal of a 3.3V power supply rises to 3.2V and is stably kept in the range of 3.2V-3.4V, and the power supply can be considered to be powered on normally. Note that, in the embodiment of the present invention, the potentials of the power supply signals provided by the first power supply VPL, the second power supply VPH1, the third power supply VPH2, and the negative voltage power supply VNL are not particularly limited.

It can be understood that when the third power supply VPH2 and/or the negative voltage power supply VNL are not normally powered on, but the first power supply VPL and the second power supply VPH1 are both normally powered on, the first power supply VPL and the second power supply VPH1 are normally powered on to enable the low-voltage circuit and the medium-voltage circuit in the load to be powered on, and the logic judgment, the switch control and other modules in the circuit can still be normally communicated with an external system, namely, the current in the circuit is in a controllable state; the third power supply VPH2 and/or the negative voltage power supply VNL are not normally powered up so that the high voltage circuit and/or the negative voltage circuit in the load circuit are not powered up. At this time, the current in the circuit is in a controllable state, and as the high-voltage circuit and/or the negative-voltage circuit are not electrified, no large current exists in the circuit, and the situation that the abnormal large current is out of control is avoided, the load and the functional module inside the load are not easy to damage. When the third power supply VPH2 and the negative voltage power supply VNL are both normally powered on, but the first power supply VPH1 and/or the second power supply VPH2 are/is not normally powered on, the third power supply VPH2 and the negative voltage power supply VNL are normally powered on to enable a high-voltage circuit and a negative voltage circuit in the load circuit to be powered on, and a large current exists in the circuit; the first power supply VPL and/or the second power supply VPH1 are/is not normally powered on, so that the low-voltage circuit and/or the medium-voltage circuit in the load are/is not powered on, the modules such as logic judgment, switch control and the like in the circuit cannot work normally, and the current in the circuit is in a runaway state, so that uncontrollable large current can be formed, and the functional module electrically connected with the circuit is damaged. When the first power supply VPL, the second power supply VPH1, the third power supply VPH2 and the negative-voltage power supply VNL are not normally powered on, all circuits in the load are in a non-powered state, no current exists in the circuits, and the condition that the load and functional modules inside the load are damaged can not occur. When the first power supply VPL, the second power supply VPH1, the third power supply VPH2 and the negative-pressure power supply VNL are all normally electrified, all circuits in the load are in an electrified state, the logic judgment, the switch control and other modules can be normally communicated with an external system, the currents in the circuits are in a controllable state, and the conditions of damaging the load and the functional modules inside the load are generally avoided. Therefore, to avoid an abnormally large current or a current in the load being in a runaway state, it is at least necessary to detect whether the first power supply VPL and the second power supply VPH1 are normally powered up.

Specifically, the power detection module 10 detects whether the first power supply VPL and the second power supply VPH1 are normally powered on, and when any one of the first power supply VPL and the second power supply VPH1 is not normally powered on, the power detection module 10 outputs a first control signal ctr1 to control the initialization module 30 to output a corresponding first initialization signal Reset1 and a second initialization signal XReset2, so as to control a circuit in the load to enter a non-working state, that is, to control the circuit in the load to be non-conductive, in particular to control the high-voltage circuit to be non-conductive with the third power supply VPH2 and the negative-voltage circuit to be non-conductive with the negative-voltage power supply VNL. Thus, even if the middle and low voltage circuits in the load are not electrified, the modules such as logic judgment, switch control and the like in the circuits cannot work normally, and because the circuits are not conducted, abnormal large current cannot be formed in the circuits, and the current cannot be in a runaway state.

When the first power supply VPL and the second power supply VPH1 are powered on normally, the power supply detection module 10 outputs the second control signal ctr2 to control the initialization module 30 to output the corresponding first initialization signal Reset1 and the second initialization signal XReset2, so as to control the circuits in the load to enter a working state, i.e. to control the circuits in the load to be turned on, especially to control the high-voltage circuit to be turned on with the third power supply VPH2 and the negative-voltage circuit to be turned on with the negative-voltage power supply VNL. At this time, the medium-voltage circuit and the low-voltage circuit in the load are electrified, and the modules such as logic judgment, switch control and the like in the circuit can work normally, and the current in the circuit is in a controllable state.

When any one of the power supplies is not normally powered on, the voltage adjusting module 20 may output the effective first voltage signal vp1 and the second voltage signal vp2, so that the first initializing signal Reset1 and the second initializing signal XReset2 output by the initializing module 30 are both effective signals, and the circuits in the load can be effectively controlled to enter an inactive state, that is, the circuits in the load are controlled to be not conducted, so that the situations that the first initializing signal Reset1 and/or the second initializing signal XReset2 are invalid due to the fact that the power supply is not normally powered on, the circuits are abnormally conducted, and uncontrollable large current occurs in the circuits in the load are avoided.

Fig. 5 is a timing diagram of a power supply detection circuit corresponding to fig. 4, for example. In connection with fig. 4 and 5, the load will be described as including the positive voltage level shift circuit 005 and the negative voltage level shift circuit 006 shown in fig. 2 and 3, the positive voltage level shift circuit 005 receiving the first initialization signal Reset1 output from the initialization module 30, and the negative voltage level shift circuit 006 receiving the second initialization signal XReset2.

In the period t1, the first power supply VPL is not normally powered on, the second power supply VPH1, the third power supply VPH2 and the negative voltage power supply VNL are normally powered on, and the power detection module 10 outputs the first control signal ctr1 to the initialization module 30; the voltage regulation module 20 outputs the second power supply signal vph_1 as the first voltage signal vp1, and the voltage regulation module 20 also outputs the third power supply signal vph_2 as the second voltage signal vp2; the initialization module 30 outputs the second voltage signal vp2 as the first initialization signal Reset1 to the positive voltage level conversion circuit 005, and the initialization module 30 outputs the negative voltage power supply signal vn_l or the ground signal VN as the second initialization signal XReset2 to the negative voltage level conversion circuit 006. The enabling control tube T01 of the positive voltage level conversion circuit 005 receives the first initialization signal Reset1 with higher potential and then is conducted, the positive voltage control signal is pulled down to the ground signal VN, the positive voltage level conversion circuit 005 is controlled to be not operated, and the third power supply VPH2 for providing the third power supply signal VPH_2 is not conducted with the positive voltage output end OUT_1; the enable control tube T02 of the negative voltage level conversion circuit 006 receives the second initialization signal XReset2 with a lower potential and then is turned on, pulls the negative voltage control signal up to the first power signal vp_l, and controls the negative voltage level conversion circuit 006 to be inoperative, and the negative voltage power VNL providing the negative voltage power signal vn_l is not turned on with the negative voltage output terminal out_2. In this way, any floating node and uncontrollable abnormal large current do not occur in the positive voltage level conversion circuit 005 and the negative voltage level conversion circuit 006.

In the period t2, the second power supply VPH1 is not normally powered on, the first power supply VPL, the third power supply VPH2 and the negative voltage power supply VNL are normally powered on, and the power detection module 10 outputs the first control signal ctr1 to the initialization module 30; the voltage regulation module 20 outputs the first power supply signal vp_l as the first voltage signal VP1, and the voltage regulation module 20 outputs the third power supply signal vph_2 as the second voltage signal VP2; the initialization module 30 outputs the second voltage signal vp2 as the first initialization signal Reset1 to the positive voltage level conversion circuit 005, and the initialization module 30 outputs the negative voltage power supply signal vn_l or the ground signal VN as the second initialization signal XReset2 to the negative voltage level conversion circuit 006. The enable control tube T01 of the positive voltage level conversion circuit 005 receives the first initialization signal Reset1 with a higher potential, controls the positive voltage level conversion circuit 005 to be inoperative, and provides the third power supply VPH2 of the third power supply signal vph_2 to be non-conductive to the positive voltage output terminal out_1; the enable control tube T02 of the negative voltage level shift circuit 006 receives the second initialization signal XReset2 with a lower potential, and controls the negative voltage level shift circuit 006 to be inoperative, and the negative voltage power VNL providing the negative voltage power signal vn_l is not conducted with the negative voltage output terminal out_2.

In the period t3, the first power supply VPL, the second power supply VPH1, the third power supply VPH2 and the negative voltage power supply VNL are all powered on normally, and the power detection module 10 outputs the second control signal ctr2 to the initialization module 30; the voltage regulation module 20 outputs the second power supply signal vph_1 as the first voltage signal vp1, and the voltage regulation module 20 outputs the third power supply signal vph_2 of the third power supply VPH2 as the second voltage signal vp2; the initialization module 30 outputs the ground signal VN as the first initialization signal Reset1 to the positive voltage level conversion circuit 005, and the initialization module 30 outputs the first voltage signal vp1 as the second initialization signal XReset2 to the negative voltage level conversion circuit 006. The enabling control tube T01 of the positive voltage level conversion circuit 005 receives a first initialization signal Reset1 with a lower potential, controls the positive voltage level conversion circuit 005 to work, and provides a third power supply VPH2 of a third power supply signal VPH_2 to be conducted with the positive voltage output end OUT_1, wherein as the first power supply VPL and the second power supply VPH1 are powered on normally, the logic judgment, switch control and other modules of the medium-low voltage circuit can be communicated with an external system normally, and the current of the circuit in the load is in a controllable state; the enabling control tube T02 of the negative voltage level conversion circuit 006 receives the second initializing signal XReset2 with higher potential, controls the negative voltage level conversion circuit 006 to work, the negative voltage power VNL providing the negative voltage power signal vn_l is conducted with the negative voltage output terminal out_2, and the logic judgment, the switch control and other modules of the middle and low voltage circuits can be normally communicated with an external system, and the current of the circuit in the load is in a controllable state.

As can be seen from this, when the power is normally powered up in the order of the third power VPH2, the negative voltage power VNL, the second power VPH1, the first power VPL, or the third power VPH2, the second power VPH1, the negative voltage power VNL, the first power VPL, or the second power VPH1, the third power VPH2, the negative voltage power VNL, the first power VPL, the initialization module 30 outputs the first initialization signal Reset1 with a higher potential and the second initialization signal XReset2 with a lower potential before the first power VPL is normally powered up, and the positive voltage level conversion circuit 005 and the negative voltage level conversion circuit 006 do not operate. When the power is normally powered up in the order of the first power VPL, the third power VPH2, the negative voltage power VNL, the second power VPH1, or the first power VPL, the third power VPH2, the second power VPH1, the negative voltage power VNL, or the third power VPH2, the first power VPL, the second power VPH1, the negative voltage power VNL, or the third power VPH2, the negative voltage power VNL, the first power VPL, the second power VPH1, the initialization module 30 outputs the first initialization signal Reset1 of the higher potential and the second initialization signal XReset2 of the lower potential before the second power VPH1 is normally powered up, the positive voltage level conversion circuit 005 and the negative voltage level conversion circuit 006 do not operate.

In this way, when any one of the first power supply VPL and the second power supply VPH1 is not normally powered on, the power detection module 10 outputs the first control signal ctr1 to the initialization module 30, and simultaneously, the voltage adjustment module 20 outputs the effective first voltage signal vp1 and the second voltage signal vp2 to the initialization module 30, so that the initialization module 30 outputs the first initialization signal Reset1 with a higher potential and the second initialization signal XReset2 with a lower potential, and the circuit in the load is controlled to be inoperative, i.e. the circuit in the load is controlled to be non-conductive, so that the current in the circuit is prevented from entering an uncontrollable state, and the circuit system where the load is located is not easily damaged, and the reliability of the power detection circuit and the circuit system is improved.

It should be noted that, when the power detection circuit 01 outputs the first control signal ctr1, the negative voltage power supply signal vn_l plays a role of outputting the second initialization signal XReset2 as a low potential to the load, whether the negative voltage power supply VNL is normally powered up does not affect the operation of the power detection circuit 01, and when the negative voltage power supply VNL is not normally powered up, the negative voltage power supply VNL fails to serve as a zero potential signal, and does not affect the power detection circuit 01 to output the second initialization signal XReset2 as a lower potential to the load, so that the power detection circuit 01 does not need to detect whether the negative voltage power supply VNL is normally powered up.

The third power supply VPH2 plays a role in the power supply detection circuit 01 as the second voltage signal vp2 output to the initialization module 30, and whether the third power supply VPH2 is normally powered on does not affect the operation of the power supply detection circuit 01. When the first power supply VPL and the second power supply VPH1 are both normally powered on and the third power supply VPH2 is not normally powered on, even if the initialization module 30 outputs the first initialization signal Reset1 with a lower potential and the second initialization signal XReset2 with a higher potential, the circuit in the load is controlled to be turned on, and since the third power supply VPH2 for supplying power to the functional module in the load is not normally powered on, no large current exists in the load, and the functional module does not work. However, if the third power supply VPH2 is powered up suddenly and normally at this time, the circuit in the load is turned on, and there may be a large instantaneous current in the circuit, which may damage the load and the functional modules therein, so the power detection module 10 may also detect whether the third power supply VPH2 is powered up normally in order to avoid the above situation.

In an alternative embodiment, the power detection module 10 is further electrically connected to the third power supply VPH2, and the power detection module 10 is configured to output the first control signal ctr1 to the initialization module 30 when any one of the first power supply VPL, the second power supply VPH1 and the third power supply VPH2 is not normally powered on; the power detection module 10 is further configured to output a second control signal ctr2 to the initialization module 30 when the first power VPL, the second power VPH1 and the third power VPH2 are powered up normally.

For example, when the first power supply VPL and the second power supply VPH1 are powered up normally, and the third power supply VPH2 is not powered up normally, the power supply detection module 10 outputs the first control signal ctr1, the voltage adjustment module 20 may also output the effective first voltage signal vp1 and the second voltage signal vp2, at this time, the potential of the first voltage signal vp1 is equal to the potential of the second voltage signal vp2, the initialization module 30 outputs the first initialization signal Reset1 with a higher potential and the second initialization signal XReset2 with a lower potential, so as to control the circuit in the load to enter a non-working state, i.e. control the circuit in the load to be non-conductive, so as to avoid the third power supply VPH2 from being powered up suddenly, and there is a larger instantaneous current to damage the load and the functional module therein. The first power supply VPL, the second power supply VPH1, and the third power supply VPH2 are the same as the above embodiments when only the first power supply VPL is not normally powered up or only the second power supply VPH1 is not normally powered up, and will not be described here again.

When the first power supply VPL is normally powered on and the second power supply VPH1 and the third power supply VPH2 are not normally powered on, or the second power supply VPH1 is normally powered on and the first power supply VPL and the third power supply VPH2 are not normally powered on, the power detection module 10 outputs the first control signal ctr1, the voltage adjustment module 20 outputs the first voltage signal vp1 and the second voltage signal vp2 with equal and valid potentials, the initialization module 30 outputs the first initialization signal Reset1 with a higher potential and the second initialization signal XReset2 with a lower potential, and the circuits in the load are controlled to enter a non-working state.

In addition, when the third power supply VPH2 is normally powered up and the first power supply VPL and the second power supply VPH1 are not normally powered up, the power detection module 10 outputs the first control signal ctr1 to the initialization module 30, the first voltage signal vp1 may be weak, but the voltage adjustment module 20 may still output the effective second voltage signal vp2 to the initialization module 30, and under the control of the first control signal ctr1, the initialization module 30 may still output the second voltage signal vp2 as the first initialization signal Reset1 to the load, and output the negative voltage power supply signal vn_l of the negative voltage power supply VNL or the ground signal VN as the second initialization signal XReset1 to the load. Therefore, as long as any one of the first power supply VPL, the second power supply VPH1 and the third power supply VPH2 is powered on normally, the power supply detection circuit 01 can work normally, that is, when any one or two of the first power supply VPL, the second power supply VPH1 and the third power supply VPH2 are not powered on normally, the power supply detection circuit 01 can output a first initialization signal Reset1 with a higher potential and a second initialization signal XReset2 with a lower potential, and the circuits in the load are controlled to enter a non-working state, so that the current in the load is prevented from being out of control.

In this way, when any power supply of the first power supply VPL, the second power supply VPH1 and the third power supply VPH2 is not normally powered on, the initialization module 30 can output the effective first initialization signal Reset1 and the second initialization signal XReset2, so as to control the circuit in the load to enter a non-working state and avoid the current in the load from entering an uncontrollable state; when the first power supply VPL, the second power supply VPH1 and the third power supply VPH2 are powered on normally, a circuit in the load can enter a working state, and meanwhile, a functional module in the load can also work, so that the condition that the circuit in the load enters the working state when the third power supply VPH2 powered by a circuit system where the load is located is not powered on normally can be avoided, the circuit is conducted, when the third power supply VPH2 is powered on normally suddenly, a large instant current is formed in the circuit to damage the load and the functional module inside the load, and the reliability of the power supply detection circuit 01 and the load can be further improved.

It should be noted that, the positive voltage level conversion circuit 005 and the negative voltage level conversion circuit 006 shown in fig. 2 and fig. 3 are merely exemplary circuit structures according to the embodiments of the present invention, and the first initialization signal Reset1 and the second initialization signal XReset2 output by the power detection circuit 01 according to the embodiments of the present invention may also be provided to other circuit structures to protect functional modules in a load from being damaged, and the structure of the load electrically connected to the initialization module 30 is not specifically limited according to the embodiments of the present invention. In addition, on the premise that the core point of the embodiment of the present invention can be satisfied, the structures of the power detection module 10, the voltage adjustment module 20, and the initialization module 30 of the power detection circuit 01 are not particularly limited. The following describes exemplary structures of each module in the power supply detection circuit 01 according to the embodiment of the present invention with reference to the drawings.

Optionally, fig. 6 is a schematic structural diagram of another power detection circuit according to an embodiment of the present invention. Referring to fig. 6, the power detection module 10 includes a first power detection unit 11, a second power detection unit 12, and a logic unit 13; the first power supply detecting unit 11 is electrically connected with the second power supply VPH1 and the logic unit 13, respectively; the first power detection unit 11 is configured to output a first enable signal Ready1 to the logic unit 13 when the second power VPH1 is not normally powered on, and output a second enable signal Ready2 to the logic unit 13 when the second power VPH1 is normally powered on; the second power supply detecting unit 12 is electrically connected to the first power supply VPL and the logic unit 13, respectively; the second power detection unit 12 is configured to output a third enable signal Ready3 to the logic unit when the first power VPL is not normally powered on, and output a fourth enable signal Ready4 to the logic unit 13 when the first power VPL is normally powered on; the logic unit 13 is configured to output the first control signal ctr1 to the initialization module 30 when receiving the first enable signal Ready1 and the third enable signal Ready3, the first enable signal Ready1 and the fourth enable signal Ready4, or the second enable signal Ready2 and the third enable signal Ready 3; the logic unit 13 is further configured to output the second control signal ctr2 to the initialization module 30 when receiving the second enable signal Ready2 and the fourth enable signal Ready 4.

Specifically, the first power supply detecting unit 11 includes a first enable terminal Ready-MV, the first enable terminal Ready-MV outputs a first enable signal Ready1 with 0 when the second power supply VPH1 is not normally powered on, and the first enable terminal Ready-MV outputs a second enable signal Ready2 with 1 when the second power supply VPH1 is normally powered on; the second power detecting unit 12 includes a second enable terminal Ready-LV, and when the first power VPL is not normally powered on, the second enable terminal Ready-LV outputs a third enable signal Ready3 with a 0, and when the first power VPL is normally powered on, the second enable terminal Ready-LV outputs a fourth enable signal Ready4 with a 1; the logic unit 13 includes a control signal output terminal CTRL, and the control signal output terminal CTRL of the logic unit 13 outputs the first control signal ctr1 or the second control signal ctr2 according to signals output from the first enable terminal Ready-MV and the second enable terminal Ready-LV. The power domain of the logic unit 13 is the first power signal vp_l to the ground signal VN, and only when the logic unit 13 receives the second enable signal Ready2 with 1 and the fourth enable signal Ready4 with 1, the control signal output end CTRL of the logic unit 13 outputs the second control signal ctr2 to the initialization module 30, so that the initialization module 30 outputs the corresponding initialization signal to control the circuits in the load to enter the working state.

It should be noted that, the potentials of the first control signal ctr1 and the second control signal ctr2 may be set according to actual requirements, and the potentials of the first control signal ctr1 and the second control signal ctr2 are not specifically limited in the embodiment of the present invention.

Optionally, fig. 7 is a schematic structural diagram of a power detection circuit according to another embodiment of the present invention. Referring to fig. 7, the initialization module 30 includes a fifth MOS transistor M5, a first initialization unit 31, and a second initialization unit 32; the initialization module 30 further includes a first voltage terminal VP-1 for receiving the first voltage signal VP1, a second voltage terminal VP-2 for receiving the second voltage signal VP2, a signal control terminal CTR-L for receiving the first control signal CTR1 or the second control signal CTR2, a first initialization terminal Reset-1 for outputting the first initialization signal Reset1, and a second initialization terminal Reset-2 for outputting the second initialization signal XReset 2; the second voltage terminal VP-2, the first electrode of the fifth MOS transistor M5, the input control terminal of the first initializing unit 31, and the input control terminal of the second initializing unit 32 are electrically connected to the third node N3; the second electrode of the fifth MOS transistor M5 receives the ground signal VN; the grid electrode of the fifth MOS tube M5 is electrically connected with the signal control end CTR-L; the output end of the first initializing unit 31 is electrically connected with the first initializing end RESET-1; the output terminal of the second initializing unit 32 is electrically connected to the second initializing terminal RESET-2.

Specifically, the signal control terminal CTR-L is electrically connected to the control signal output terminal CTRL of the logic unit 13, where the control signal output terminal CTRL outputs the first control signal CTR1 or the second control signal CTR2 to the gates of the fifth MOS transistor M5 to control the potential of the third node N3, so as to further implement potential control on the input control terminal of the first initialization module 31 and the input control terminal of the second initialization module 32. The first initializing unit 31 receives the second voltage signal vp2 and the ground signal VN as power supply signals, respectively, the second initializing unit 32 receives the first voltage signal vp1 and the negative voltage power supply VNL as power supply signals, respectively, or the second initializing unit 32 receives the first voltage signal vp1 and the ground signal VN as power supply signals, respectively. By controlling the potential of the third node N3, signals of the input control terminal of the first initializing unit 31 and the input control terminal of the second initializing unit 32 may be controlled, thereby controlling the first initializing terminal RESET-1 of the first initializing unit 31 to output the second voltage signal vp2 as the first initializing signal RESET1 and controlling the second initializing terminal RESET-2 of the second initializing unit 32 to output the negative voltage power supply signal vn_l or the ground signal VN as the second initializing signal XReset2, or controlling the first initializing terminal RESET-1 of the first initializing unit 31 to output the ground signal VN as the first initializing signal RESET1 and controlling the second initializing terminal RESET-2 of the second initializing unit 32 to output the first voltage signal vp1 as the second initializing signal XReset2.

Taking the fifth MOS transistor M5 as a P-channel MOS transistor as an example. The first control signal CTR1 is a higher-potential signal, the first control signal CTR1 may be, for example, the first power supply signal vp_l of the first power supply VPL, the second control signal CTR2 is a lower-potential signal, the second control signal CTR2 may be, for example, the ground signal VN, when any power supply of the first power supply VPL and the second power supply VPH1 is not normally powered on, the signal control terminal CTR-L may receive the first control signal CTR1, the fifth MOS transistor M5 is turned off, the potential of the third node N3 is pulled up to the potential of the second voltage signal VP2, at this time, the input control terminal of the first initializing unit 31 receives the higher-potential second voltage signal VP2, outputs the higher-potential second voltage signal VP2 as the first initializing signal Reset1, and the input control terminal of the second initializing unit 32 also receives the higher-potential second voltage signal VP2, but outputs the lower-potential negative-voltage power supply signal vn_l or the ground signal as the second initializing signal VN 2. When all the power supplies are normally powered on, the signal control terminal CTR-L may receive the second control signal CTR2, the fifth MOS transistor M5 is turned on, the potential of the third node N3 is pulled down to the potential of the ground signal VN, at this time, the input control terminal of the first initializing unit 31 receives the ground signal VN with a lower potential, outputs the ground signal VN with a lower potential as the first initializing signal Reset1, and the input control terminal of the second initializing unit 32 also receives the ground signal VN with a lower potential, outputs the first voltage signal vp1 with a higher potential as the second initializing signal XReset2.

Similarly, the first control signal ctr1 may be a signal with a lower potential, and the second control signal ctr2 may be a signal with a higher potential, so that the structures of the first initializing unit 31 and the second initializing unit 32 are not specifically limited in the embodiment of the present invention on the premise that the invention can be satisfied.

It should be noted that fig. 7 is only an exemplary illustration of the embodiment of the present invention, and the fifth MOS transistor M5 in fig. 7 is a P-channel MOS transistor; in the embodiment of the present invention, the fifth MOS transistor M5 may be an N-channel MOS transistor, where the voltage difference between the gate and the source of the N-channel MOS transistor is turned on when the voltage difference between the gate and the source of the P-channel MOS transistor is greater than the threshold voltage (the threshold voltage is greater than 0), and the voltage difference between the gate and the source of the P-channel MOS transistor is turned on when the voltage difference between the gate and the source of the P-channel MOS transistor is less than the threshold voltage (the threshold voltage is less than 0). Meanwhile, the embodiment of the invention does not limit the types of the MOS transistors in other modules of the provided power supply detection circuit 01. For convenience of description, the embodiment of the invention takes the MOS transistors in the power supply detection circuit as P-channel MOS transistors as examples for exemplary description.

In an alternative embodiment, initialization module 30 further includes a first current source IA; the input end of the first current source IA is electrically connected with the second voltage end VP-2; the output of the first current source IA is electrically connected to the third node N3. Therefore, the current of the passage where the fifth MOS tube M5 is located can be limited in a smaller range, which is beneficial to reducing the energy consumption of the power supply detection circuit 01.

Optionally, fig. 8 is a schematic structural diagram of a power detection circuit according to another embodiment of the present invention. Referring to fig. 8, the first initializing unit 31 includes a third inverter 33 and a fourth inverter 34; the input terminal of the third inverter 33 is electrically connected to the third node N3; the output end of the third inverter 33 is electrically connected with the input end of the fourth inverter 34; the output end of the fourth inverter 34 is electrically connected with the first initialization end RESET-1; the first power supply terminal of the third inverter 33 and the first power supply terminal of the fourth inverter 34 are electrically connected to the second voltage terminal VP-2; the second power supply terminal of the third inverter 33 and the second power supply terminal of the fourth inverter 34 each receive the ground signal VN.

Taking the fifth MOS transistor M5 as a P-channel MOS transistor as an example. When the signal control terminal CTR-L receives the first control signal CTR1, the fifth MOS transistor M5 is turned off, and the potential of the third node N3 is at a higher level, that is, the potential of the input control terminal of the first initializing unit 31 is higher, and the first initializing unit 31 can output the second voltage signal VP2 of the second voltage terminal VP-2 as the first initializing signal Reset1; when the signal control terminal CTR-L receives the second control signal CTR2, the fifth MOS transistor M5 is turned on, and the potential of the third node N3 is at a lower level, i.e., the potential of the input control terminal of the first initializing unit 31 is lower, and the first initializing unit 31 can output the ground signal VN as the first initializing signal Reset1.

In an alternative embodiment, the initialization module 30 further includes a third initialization terminal RESET-3; the third initialization end RESET-3 is electrically connected with the output end of the third inverter 33; under the control of the first control signal ctr1, the third initialization terminal RESET-3 of the first initialization unit 31 outputs the ground signal VN as the third initialization signal XReset3; the third initialization terminal RESET-3 of the first initialization unit 31 outputs the second voltage signal vp2 as the third initialization signal XReset3 under the control of the second control signal ctr 2.

The third initializing signal XReset3 is also electrically connected to the circuit of the positive power domain in the load and is used for controlling the initializing state of the circuit of the positive power domain, however, the potential level of the third initializing signal XReset3 is opposite to that of the first initializing signal Reset1, when the third initializing signal XReset3 is at a higher potential, the first initializing signal Reset1 is at a lower potential, and when the third initializing signal XReset3 is at a lower potential, the first initializing signal Reset1 is at a higher potential. Thus, through the third initializing terminal RESET-3, the initializing module 30 can output the third initializing signal XReset3 with the same driving capability and opposite potential level as the first initializing signal RESET1, and can simultaneously control the initializing states of the circuits of the plurality of positive power domains in the load, or simultaneously control the initializing states of different paths in the circuit of one positive power domain in the load, so as to control the circuit of the positive power domain in the load to be non-conductive when the power detecting module 10 outputs the first control signal ctr1, and protect the load and the functional modules therein from being damaged easily.

Optionally, fig. 9 is a schematic structural diagram of a power detection circuit according to another embodiment of the present invention. Referring to fig. 9, the second initializing unit 32 includes a sixth MOS transistor M6, a fifth inverter 35, and a sixth inverter 36; the grid electrode of the sixth MOS tube M6 is electrically connected with the third node N3; the first electrode of the sixth MOS tube M6 is electrically connected with the first voltage end VP-1; the second electrode of the sixth MOS transistor M6 and the input end of the fifth inverter 35 are electrically connected to the fourth node N4; the fourth node N4 is coupled to the negative voltage power supply VNL; the output terminal of the fifth inverter 35 is electrically connected to the input terminal of the sixth inverter 36; the output terminal of the sixth inverter 36 is electrically connected to the second initialization terminal RESET-2; the first power supply terminal of the fifth inverter 35 and the first power supply terminal of the sixth inverter 36 are electrically connected to the first voltage terminal VP-1; the second power supply terminal of the fifth inverter 35 and the second power supply terminal of the sixth inverter 36 are both electrically connected to the negative voltage power supply VNL, or are both grounded.

For example, taking the fifth MOS transistor M5 and the sixth MOS transistor M6 as P-channel MOS transistors as examples, when the signal control end CTR-L receives the first control signal CTR1, the fifth MOS transistor M5 is turned off, the potential of the third node N3 is at a higher level, the sixth MOS transistor M6 is turned off, the fourth node N4 is pulled down to the potential of the negative-pressure power supply signal vn_l, and the second initialization end RESET-2 of the second initialization unit 32 may output the negative-pressure power supply signal vn_l or the ground signal VN as the second initialization signal XReset2; when the signal control terminal CTR-L receives the second control signal CTR2, the fifth MOS transistor M5 is turned on, the potential of the third node N3 is at a lower level, the sixth MOS transistor M6 is turned on, the fourth node N4 is pulled up to the potential of the first voltage signal VP1 of the first voltage terminal VP-1, and the second initialization terminal RESET-2 of the second initialization unit 32 can output the first voltage signal VP1 of the first voltage terminal VP-1 as the second initialization signal XReset2.

It can be understood that the sixth MOS transistor M6 may be an N-channel MOS transistor, and the principle is the same, so that when the signal control terminal CTR-L receives the first control signal CTR1, the second initializing unit 32 outputs the negative voltage power signal vn_l or the ground signal VN of the negative voltage power source VNL as the second initializing signal XReset2, and when the signal control terminal CTR-L receives the second control signal CTR2, the second initializing unit 32 outputs the first voltage signal VP1 of the first voltage terminal VP-1 as the second initializing signal XReset2.

In an alternative embodiment, the initialization module 30 further includes a fourth initialization terminal RESET-4; the fourth initializing terminal RESET-4 is electrically connected to the output terminal of the fifth inverter 35; under the control of the first control signal ctr1, the fourth initialization terminal RESET-4 of the second initialization unit 32 outputs the first voltage signal vp1 as the fourth initialization signal RESET4; the fourth initialization terminal RESET-4 of the second initialization unit 32 outputs the negative voltage power supply signal vn_l or the ground signal VN as the fourth initialization signal RESET4 under the control of the second control signal ctr 2.

The fourth initializing signal Reset4 is also electrically connected to the circuit of the negative voltage power supply domain in the load for controlling the initializing state of the circuit of the negative voltage power supply domain, however, the potential level of the fourth initializing signal Reset4 is opposite to the potential level of the second initializing signal XReset2, when the fourth initializing signal Reset4 is at a higher potential, the second initializing signal XReset2 is at a lower potential, and when the fourth initializing signal Reset4 is at a lower potential, the second initializing signal XReset2 is at a higher potential. Thus, through the fourth initializing terminal RESET-4, the initializing module 30 can output the fourth initializing signal RESET4 with the same driving capability and opposite potential level as the second initializing signal XReset2, and can simultaneously control the initializing states of the circuits of the plurality of negative voltage power domains in the load, or simultaneously control the initializing states of different paths in the circuit of one negative voltage power domain in the load, so as to control the circuit of the negative voltage power domain in the load to be non-conductive when the power detecting module 10 outputs the first control signal ctr1, and protect the load and the functional modules therein from being damaged easily.

Optionally, the second initializing unit 32 further includes a second current source IB; the input end of the second current source IB is electrically connected with the fourth node N4; the output end of the second current source IB is electrically connected to the negative voltage power supply VNL. Therefore, the current of the passage where the sixth MOS transistor M6 is located can be limited in a smaller range, which is beneficial to reducing the energy consumption of the power supply detection circuit 01.

Optionally, fig. 10 is a schematic structural diagram of a power detection circuit according to another embodiment of the present invention. Referring to fig. 10, the second initializing unit 32 further includes a seventh inverter 37 and an eighth inverter 38; the seventh inverter 37 and the eighth inverter 38 are connected in series between the third node N3 and the gate of the sixth MOS transistor M6; the first power supply terminal of the seventh inverter 37 and the first power supply terminal of the eighth inverter 38 are electrically connected to the first voltage terminal VP-1; the second power supply terminal of the seventh inverter 27 and the second power supply terminal of the eighth inverter 38 are both grounded (ground connection is not shown for simplicity of the drawing).

Specifically, when the third node N3 is pulled up to the potential of the second voltage signal VP2 of the second voltage terminal VP-2, the potential of the gate of the sixth MOS transistor M6 is the potential of the first voltage signal VP1 of the first voltage terminal VP-1 through the seventh inverter 37 and the eighth inverter 38. When the third power supply VPH2 is powered up normally, the first power supply VPL and/or the second power supply VPH1 is not powered up normally, the potential of the second voltage signal vp2 is greater than the potential of the first voltage signal vp 1. In this way, the potential of the gate of the sixth MOS transistor M6 can be reduced to the potential of the first voltage signal vp1 through the seventh inverter 37 and the eighth inverter 38, so that the voltage difference between the gate and the second electrode of the sixth MOS transistor M6 is reduced while the on/off of the sixth MOS transistor M6 is not affected, and the breakdown of the sixth MOS transistor M6 due to the excessive voltage difference is avoided.

Optionally, fig. 11 is a schematic structural diagram of a power detection circuit according to another embodiment of the present invention. Referring to fig. 11, the voltage adjustment module 20 includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, and a fourth MOS transistor M4; the grid electrode of the first MOS tube M1 receives a first type control signal con1; the first electrode of the first MOS tube M1 is electrically connected with a second power supply VPH 1; the grid electrode of the second MOS tube receives a second type control signal con2; the first electrode of the second MOS tube M2 is electrically connected with a first power supply VPL; the second electrode of the first MOS tube M1 and the second electrode of the second MOS tube M2 are electrically connected to the first node N1; the substrate of the first MOS tube M1 and the substrate of the second MOS tube M2 are electrically connected with a first node N1; the first MOS transistor M1 and the second MOS transistor M2 are configured to output a power signal with a larger potential in the first power supply VPL and the second power supply VPH1 as a first voltage signal vp1 to the first node N1. The grid electrode of the third MOS tube M3 receives a third type control signal con3; the first electrode of the third MOS tube M3 is electrically connected with a third power supply VPH 2; the grid electrode of the fourth MOS tube M4 receives a fourth type control signal con4; the first electrode of the fourth MOS transistor M4 is electrically connected with the first node N1; the second electrode of the third MOS tube M3 and the second electrode of the fourth MOS tube M4 are electrically connected to the second node N2; the substrate of the third MOS tube M3 and the substrate of the fourth MOS tube M4 are electrically connected with the second node N2; the third MOS transistor M3 and the fourth MOS transistor M4 are configured to output the first voltage signal vp1 and a signal with a larger potential in the third power supply VPH2 as the second voltage signal vp2 to the second node N2.

For example, taking the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 as P-channel MOS transistors as examples, when the second power supply VPH1 is powered on normally, the first control signal con1 is a signal with a lower potential, the second control signal con2 is a signal with a higher potential, the first MOS transistor M1 is turned on, the second MOS transistor M2 is turned off, and the second power supply signal vph_1 of the second power supply VPH1 is a first voltage signal vp1; when the first power supply VPL is normally powered on and the second power supply VPH1 is not normally powered on, the first control signal con1 is a higher potential signal, the second control signal con2 is a lower potential signal, the first MOS transistor M1 is turned off, the second MOS transistor M2 is turned on, and the first power supply signal vp_l of the first power supply VPL is a first voltage signal VP1; when the third power supply VPH2 is normally powered on, the third control signal con3 is a signal with a lower potential, the fourth control signal con4 is a signal with a higher potential, the third MOS transistor M3 is turned on, the fourth MOS transistor M4 is turned off, and the third power supply signal vph_2 of the third power supply VPH2 is a second voltage signal vp2; when the third power supply VPH2 is not normally powered on, the third control signal con3 is a higher potential signal, the fourth control signal con4 is a lower potential signal, the third MOS transistor M3 is turned off, the fourth MOS transistor M4 is turned on, and the second voltage signal vp2 is equal to the first voltage signal vp1. The first node N1 is electrically connected to the first voltage terminal VP-1 of the initialization module 30 to provide a first voltage signal VP1 to the first voltage terminal VP-1; the second node N2 is electrically connected to the second voltage terminal VP-2 of the initialization module 30 to provide the first voltage signal VP2 to the second voltage terminal VP-2.

It should be noted that, on the premise that the above situation can be satisfied, the embodiment of the present invention does not limit which circuits or structures the first type control signal con1, the second type control signal con2, the third type control signal con3 and the fourth type control signal con4 come from. The following describes the specific cases of the first type control signal con1, the second type control signal con2, the third type control signal con3 and the fourth type control signal con4 in the voltage adjustment module 20 according to the embodiment of the present invention with reference to the accompanying drawings.

Optionally, fig. 12 is a schematic structural diagram of a power detection circuit according to another embodiment of the present invention. Referring to fig. 12, the first power source signal vp_l of the first power source VPL is a first type control signal con1; the second power supply signal vph_1 of the second power supply VPH1 is the second type control signal con2; the first voltage signal vp1 is a third type control signal con3; the third power supply signal vph_2 of the third power supply VPH2 is the fourth type control signal con4.

Specifically, the gate of the first MOS transistor M1 is electrically connected to the first power supply VPL; the grid electrode of the second MOS tube M2 is electrically connected with a second power supply VPH 1; the grid electrode of the third MOS tube M3 is electrically connected with the first node N1; the gate of the fourth MOS transistor M4 is electrically connected to the third power supply VPH 2.

For example, taking the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 as P-channel MOS transistors as examples, when the first power supply VPL is powered on normally and the second power supply VPH1 is not powered on normally, the voltage difference between the gate (first power supply VPL) and the source (second power supply VPH1, 0) of the first MOS transistor M1 is greater than the threshold voltage thereof, the first MOS transistor M1 is turned off, the voltage difference between the gate (second power supply VPH1, 0) and the source (first power supply VPL) of the second MOS transistor M2 is less than the threshold voltage thereof, the second MOS transistor M2 is turned on, and the first voltage signal VP1 is the first power supply signal vp_l of the first power supply VPL; if the second power supply VPH1 is turned back to normal and is powered on normally, the voltage difference between the gate potential (first power supply VPL) of the first MOS transistor M1 and the source (second power supply VPH1, active) thereof is smaller than the threshold voltage thereof, the first MOS transistor M1 is turned on, and meanwhile, the voltage difference between the gate potential (second power supply VPH 1) of the second MOS transistor M2 and the source (first power supply VPL) thereof is larger than the threshold voltage thereof, the second MOS transistor M2 is turned off, and the first voltage signal vp1 is the second power supply signal vph_1 of the second power supply VPH 1.

Similarly, if the first power supply VPL is not normally powered on, the first MOS transistor M1 is turned on, the second MOS transistor M2 is turned off, and the first voltage signal vp1 is a second power supply signal vph_1 of the second power supply VPH 1; if the first power supply VPL is turned back to normal and is powered up normally after that, the first voltage signal vp1 is still the second power supply signal vph_1 of the second power supply VPH 1.

When the third power supply VPH2 is not normally powered on, the voltage difference between the gate (the first voltage signal vp 1) and the source (the third power supply VPH2, 0) of the third MOS transistor M3 is greater than the threshold voltage thereof, the third MOS transistor M3 is turned off, the voltage difference between the gate (the third power supply VPH2, 0) and the source (the first voltage signal vp 1) of the fourth MOS transistor M4 is less than the threshold voltage thereof, the fourth MOS transistor M4 is turned on, and the second voltage signal vp2 is the first voltage signal vp1; if the third power supply VPH2 is turned back to normal and is powered on normally, the voltage difference between the gate potential (the first voltage signal vp 1) of the third MOS transistor M3 and the source (the third power supply VPH2, active) thereof is smaller than the threshold voltage thereof, the third MOS transistor M3 is turned on, and meanwhile, the potential between the gate potential (the third power supply VPH 2) of the fourth MOS transistor M4 and the source (the first voltage signal vp 1) thereof is larger than the threshold voltage thereof, the fourth MOS transistor M4 is turned off, and the second voltage signal vp2 is the third power supply signal vph_2 of the third power supply VPH 2.

Therefore, the power supply signals of different power supplies can be respectively connected to the grid electrode and the source electrode of the MOS tube, the on/off state of the MOS tube is determined according to the grid source voltage of the MOS tube, and then the power supply signal with higher potential is output.

Optionally, fig. 13 is a schematic structural diagram of a power detection circuit according to another embodiment of the present invention. Referring to fig. 13, the voltage regulation module 20 further includes a first inverter 21; the power supply terminal of the first inverter 21 is electrically connected to the first power supply VPL and the ground signal VN, respectively; the input end of the first inverter 21 is electrically connected with the first power supply detection unit 11; the output terminal of the first inverter 21 outputs a first type control signal con1; the second power supply signal vph_1 of the second power supply VPH1 is the second type control signal con2; the first voltage signal vp1 is a third type control signal con3; the third power supply signal vph_2 of the third power supply VPH2 is the fourth type control signal con4.

Specifically, the first power detection unit 11 is configured to output a first enable signal Ready1 to the logic unit 13 with 0 when the second power VPH1 is not normally powered on, and output a second enable signal Ready2 to the logic unit 13 with 1 when the second power VPH1 is normally powered on, and the first power detection unit 11 includes a first enable terminal Ready-MV for outputting the first enable signal Ready1 or the second enable signal Ready 2; the input end of the first inverter 21 is electrically connected with the first enabling end Ready-MV; the output end of the first inverter 21 is electrically connected with the grid electrode of the first MOS tube M1; the grid electrode of the second MOS tube M2 is electrically connected with a second power supply VPH 1; the grid electrode of the third MOS tube M3 is electrically connected with the first node N1; the gate of the fourth MOS transistor M4 is electrically connected to the third power supply VPH 2.

Taking the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 as examples, when the first power supply VPL is normally powered on and the second power supply VPH1 is not normally powered on, the first enable terminal Ready-MV outputs a first enable signal Ready1 of 0, the first inverter 21 outputs a first power supply signal vp_l of the first power supply VPL as the first control signal con1, a voltage difference between a gate electrode (the first power supply VPL) of the first MOS transistor M1 and a source electrode (the second power supply VPH1 signal, 0) thereof is greater than a threshold voltage thereof, the first MOS transistor M1 is turned off, a voltage difference between a gate electrode (the second power supply VPH1, 0) of the second MOS transistor M2 and a source electrode (the first power supply VPL) thereof is less than the threshold voltage thereof, the second MOS transistor M2 is turned on, and the first voltage signal VP1 is the first power supply signal vp_l of the first power supply VPL; if the second power supply VPH1 is turned back to normal and is powered on normally, the first enable terminal Ready-MV outputs the second enable signal Ready2 with 1, the first inverter 21 outputs the ground signal VN as the first control signal con1, the voltage difference between the gate potential (ground signal VN) of the first MOS transistor M1 and the source (second power supply VPH1, active) thereof is smaller than the threshold voltage thereof, the first MOS transistor M1 is turned on, and simultaneously, the voltage difference between the gate potential (second power supply VPH 1) of the second MOS transistor M2 and the source (first power supply VPL) thereof is larger than the threshold voltage thereof, the second MOS transistor M2 is turned off, and the first voltage signal vp1 is the second power supply signal vph_1 of the second power supply VPH 1.

Similarly, if the first power supply VPL is not normally powered on, and the second power supply VPH1 is normally powered on, the first inverter 21 outputs the ground signal VN as the first type control signal con1, the first MOS transistor M1 is turned on, the second MOS transistor M2 is turned off, and the first voltage signal vp1 is the second power supply signal vph_1 of the second power supply VPH 1; if the first power supply VPL is restored to normal power-up after that, since the potential of the first power supply signal vp_l of the first power supply VPL is smaller than the potential of the second power supply signal vph_1 of the second power supply VPH1, the first voltage signal VP1 is still the second power supply signal vph_1 of the second power supply VPH 1.

The on/off states of the third MOS transistor M3 and the fourth MOS transistor M4 are the same as those of the voltage adjustment module 20 shown in fig. 12, and will not be described here again.

Therefore, when the first power supply VPL and the second power supply VPH1 are powered on normally, the potential difference of the first power supply VPL and the second power supply VPH1 is similar, the potential difference of the first power supply VPL and the second power supply VPH1 is larger than the threshold voltage of the first MOS tube M1, when the second MOS tube M2 is turned off, the first MOS tube M1 is also turned off, and the condition that an effective first voltage signal vp1 cannot be output is avoided, so that the reliability of the voltage regulating module 20 is improved, and the reliability of the power supply detecting circuit 01 is further improved.

Optionally, fig. 14 is a schematic structural diagram of a power detection circuit according to another embodiment of the present invention. Referring to fig. 14, the first power detecting unit 11 is further electrically connected to a third power VPH 2; the first power detection unit 11 is configured to output a first enable signal Ready1 to the logic unit 13 when the second power VPH1 and/or the third power VPH2 are not normally powered on, and output a second enable signal Ready2 to the logic unit 13 when the second power VPH1 and the third power VPH2 are both normally powered on; the first power source signal vp_l of the first power source VPL is a first type control signal con1; the second power supply signal vph_1 of the second power supply VPH1 is the second type control signal con2; the voltage regulation module 20 further includes a second inverter 22; the power supply terminal of the second inverter 22 is electrically connected to the first power supply VPL and the ground signal VN, respectively; the input end of the second inverter 22 is electrically connected with the first power supply detection unit 11; the output terminal of the second inverter 22 outputs a third type control signal con3; the third power supply signal vph_2 of the third power supply VPH2 is the fourth type control signal con4.

Specifically, the first power detection unit 11 is configured to output a first enable signal Ready1 to the logic unit 13 with 0 when the second power VPH1 and/or the third power VPH2 are not normally powered on, and output a second enable signal Ready2 to the logic unit 13 with 1 when the second power VPH1 and the third power VPH2 are both normally powered on, and the first power detection unit 11 includes a first enable terminal Ready-MV for outputting the first enable signal Ready1 or the second enable signal Ready 2; the grid electrode of the first MOS tube M1 is electrically connected with a first power supply VPL; the grid electrode of the second MOS tube M2 is electrically connected with a second power supply VPH 1; the grid electrode of the third MOS tube M3 is electrically connected with the output end of the second inverter 22; the gate of the fourth MOS transistor M4 is electrically connected to the third power supply VPH 2.

For example, taking the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 as P-channel MOS transistors as examples, the on/off states of the first MOS transistor M1 and the second MOS transistor M2 are the same as those of the voltage adjustment module 20 shown in fig. 12, and will not be described herein. When the third power supply VPH2 is not normally powered on, the first enable terminal Ready-MV outputs a first enable signal Ready1 with 0, the second inverter 22 outputs a first power supply signal vp_l of the first power supply VPL as a third type control signal con3, a voltage difference between a gate (the first power supply VPL) of the third MOS transistor M3 and a source (the third power supply VPH2, 0) thereof is greater than a threshold voltage thereof, the third MOS transistor M3 is turned off, a voltage difference between a gate (the third power supply VPH2, 0) of the fourth MOS transistor M4 and a source (the first voltage signal VP 1) thereof is less than the threshold voltage thereof, the fourth MOS transistor M4 is turned on, and the second voltage signal VP2 is the first voltage signal VP1; if the third power supply VPH2 is turned back to normal and is powered on normally, the first enable terminal Ready-MV outputs the second enable signal Ready2 with 1, the second inverter 22 outputs the ground signal VN as the third control signal con3, the voltage difference between the gate potential (ground signal VN) of the third MOS transistor M3 and the source (third power supply VPH2, active) thereof is smaller than the threshold voltage thereof, the third MOS transistor M3 is turned on, and simultaneously, the potential between the gate potential (third power supply VPH 2) of the fourth MOS transistor M4 and the source (first voltage signal vp 1) thereof is larger than the threshold voltage thereof, the fourth MOS transistor M4 is turned off, and the second voltage signal vp2 is the third power supply signal vph_2 of the third power supply VPH 2.

Therefore, when the second power supply VPH1 and the third power supply VPH2 are powered on normally, the potential difference between the second power supply VPH1 and the third power supply VPH2 is similar, the potential difference between the second power supply VPH1 and the third power supply VPH2 is larger than the threshold voltage of the third MOS transistor M3, and when the fourth MOS transistor M4 is turned off, the third MOS transistor M3 is also turned off, and an effective second voltage signal vp2 cannot be output, so that the reliability of the voltage regulating module 20 is improved, and the reliability of the power supply detection circuit 01 is further improved.

Based on the same inventive concept, the embodiment of the present invention further provides a silicon-based display panel, and fig. 15 is a schematic structural diagram of the silicon-based display panel provided by the embodiment of the present invention, as shown in fig. 15, the silicon-based display panel 02 includes: a silicon-based substrate 010, a display unit 020, and a power module 030; the power module 030 includes the power detection circuit 01 provided in the embodiment of the invention; wherein the power supply module 030 and the display unit 020 are both formed on the silicon-based substrate 010.

Illustratively, the silicon-based display panel 02 includes a silicon-based substrate 010, a display unit 020, a power module 030, and circuitry 040 electrically connected to the power module 030, the circuitry 040 including circuitry for a positive power domain and circuitry for a negative power domain. The display unit 020 may include a plurality of pixels (not shown in the figure) arranged in an array, and each pixel of the display unit 020 can perform display light emission under the control of the circuit system 040; and the power module 030 can avoid uncontrollable abnormal large current of the circuit system 040 through the power detection circuit 01 inside the power module 030, the circuit system 040 is protected from being damaged, and proper driving signals are provided to each pixel of the display unit 020. Meanwhile, the power module 030, the circuit system 040 and the display unit 020 of the silicon-based display panel 02 are all formed on one side of the silicon-based substrate 010.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, and fig. 16 is a schematic structural diagram of the display device provided by the embodiment of the present invention, as shown in fig. 16, where the display device 03 includes a silicon-based display panel 02 provided by the embodiment of the present invention. The display device 03 provided by the embodiment of the present invention may be an intelligent glasses as shown in fig. 16, or any electronic product with a display function, including but not limited to the following categories: the embodiment of the invention is not particularly limited to a mobile phone, a television, a notebook computer, a desktop display, a tablet computer, a digital camera, a smart bracelet, a vehicle-mounted display, medical equipment, industrial control equipment, a touch interaction terminal and the like.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. A power supply detection circuit, comprising: the power supply detection module, the voltage regulation module and the initialization module;

the power supply detection module is electrically connected with the first power supply, the second power supply and the initialization module respectively; the power supply detection module is used for outputting a first control signal to the initialization module when the first power supply and/or the second power supply are/is not powered on normally; the power supply detection module is further used for outputting a second control signal to the initialization module when the first power supply and the second power supply are powered on normally;

the voltage regulating module is respectively and electrically connected with the first power supply, the second power supply, the third power supply and the initializing module; the voltage regulating module is used for outputting a power supply signal with larger potential in the first power supply and the second power supply as a first voltage signal to the initializing module, and outputting a power supply signal with the largest potential in the first power supply, the second power supply and the third power supply as a second voltage signal to the initializing module; the potential of the first power supply is less than the potential of the second power supply is less than the potential of the third power supply;

The initialization module is used for outputting the second voltage signal to a load as a first initialization signal under the control of the first control signal, and outputting a power signal or a ground signal of a negative-pressure power supply electrically connected with the second voltage signal to the load as a second initialization signal; the initialization module is further configured to output a ground signal as the first initialization signal to the load under control of the second control signal, and output the first voltage signal as the second initialization signal to the load.

2. The power supply detection circuit according to claim 1, wherein when the first power supply, the second power supply, and the third power supply are all normally powered up, a potential of the first power supply is smaller than a potential of the second power supply, and a potential of the second power supply is smaller than a potential of the third power supply.

3. The power detection circuit of claim 1, wherein the power detection module comprises a first power detection unit, a second power detection unit, and a logic unit;

the first power supply detection unit is electrically connected with the second power supply and the logic unit respectively; the first power supply detection unit is used for outputting a first enabling signal to the logic unit when the second power supply is not powered on normally, and outputting a second enabling signal to the logic unit when the second power supply is powered on normally;

The second power supply detection unit is electrically connected with the first power supply and the logic unit respectively; the second power supply detection unit is used for outputting a third enabling signal to the logic unit when the first power supply is not powered on normally, and outputting a fourth enabling signal to the logic unit when the first power supply is powered on normally;

the logic unit is configured to output the first control signal to the initialization module when the first enable signal and the third enable signal, the first enable signal and the fourth enable signal, or the second enable signal and the third enable signal are received; the logic unit is further configured to output the second control signal to the initialization module when the second enable signal and the fourth enable signal are received.

4. The power detection circuit of claim 3, wherein the voltage regulation module comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor;

the grid electrode of the first MOS tube receives a first type of control signal; the first electrode of the first MOS tube is electrically connected with the second power supply; the grid electrode of the second MOS tube receives a second type of control signal; the first electrode of the second MOS tube is electrically connected with the first power supply; the second electrode of the first MOS tube and the second electrode of the second MOS tube are electrically connected to a first node; the substrate of the first MOS tube and the substrate of the second MOS tube are electrically connected with the first node;

The first MOS tube and the second MOS tube are used for outputting power supply signals with larger potential in the first power supply and the second power supply as first voltage signals to the first node;

the grid electrode of the third MOS tube receives a third type of control signal; the first electrode of the third MOS tube is electrically connected with the third power supply; the grid electrode of the fourth MOS tube receives a fourth type of control signal; the first electrode of the fourth MOS tube is electrically connected with the first node; the second electrode of the third MOS tube and the second electrode of the fourth MOS tube are electrically connected to a second node; the substrate of the third MOS tube and the substrate of the fourth MOS tube are electrically connected with the second node;

the third MOS transistor and the fourth MOS transistor are used for outputting the first voltage signal and the signal with larger potential in the third power supply to the two nodes as a second voltage signal.

5. The power detection circuit of claim 4, wherein the first power source is the first type of control signal; the second power supply is the second type control signal;

the first voltage signal is the third type of control signal; the third power supply is the fourth type of control signal.

6. The power detection circuit of claim 4, wherein the voltage regulation module further comprises a first inverter; the power end of the first inverter is electrically connected with the first power supply; the input end of the first inverter is electrically connected with the first power supply detection unit; the output end of the first inverter outputs the first type control signal; the second power supply is the second type control signal;

7. The power detection circuit of claim 4, wherein the first power detection unit is further electrically connected to the third power supply; the first power supply detection unit is used for outputting a first enabling signal to the logic unit when the second power supply and/or the third power supply are/is not powered on normally, and outputting a second enabling signal to the logic unit when the second power supply and the third power supply are powered on normally;

the first power supply is the first type control signal; the second power supply is the second type control signal;

the voltage regulation module further comprises a second inverter; the power end of the second inverter is electrically connected with the first power supply; the input end of the second inverter is electrically connected with the first power supply detection unit; the output end of the second inverter outputs the third type control signal; the third power supply is the fourth type of control signal.

8. The power supply detection circuit according to claim 1, wherein the initialization module includes a fifth MOS transistor, a first initialization unit, and a second initialization unit;

the initialization module further comprises a first voltage end for receiving the first voltage signal, a second voltage end for receiving the second voltage signal, a signal control end for receiving the first control signal or the second control signal, a first initialization end for outputting the first initialization signal, and a second initialization end for outputting the second initialization signal;

the second voltage end, the first electrode of the fifth MOS tube, the input control end of the first initializing unit and the input control end of the second initializing unit are electrically connected to a third node; the second electrode of the fifth MOS tube is grounded; the grid electrode of the fifth MOS tube is electrically connected with the signal control end; the output end of the first initializing unit is electrically connected with the first initializing end; the output end of the second initializing unit is electrically connected with the second initializing end.

9. The power detection circuit of claim 8, wherein the initialization module further comprises a first current source;

The input end of the first current source is electrically connected with the second voltage end; the output end of the first current source is electrically connected with the third node.

10. The power supply detection circuit according to claim 8, wherein the first initialization unit includes a third inverter and a fourth inverter;

the input end of the third inverter is electrically connected with the third node; the output end of the third inverter is electrically connected with the input end of the fourth inverter; the output end of the fourth inverter is electrically connected with the first initialization end; the first power supply end of the third inverter and the first power supply end of the fourth inverter are electrically connected with the second voltage end; the second power supply end of the third inverter and the second power supply end of the fourth inverter are grounded.

11. The power detection circuit of claim 10, wherein the initialization module further comprises a third initialization terminal; the third initialization end is electrically connected with the output end of the third inverter;

under the control of the first control signal, the ground signal is output to the load as a third initialization signal through the third initialization terminal;

Under the control of the second control signal, the second voltage signal is output to the load as the third initialization signal through the third initialization terminal.

12. The power detection circuit of claim 8, wherein the second initialization unit comprises a sixth MOS transistor, a fifth inverter, and a sixth inverter;

the grid electrode of the sixth MOS tube is electrically connected with the third node; the first electrode of the sixth MOS tube is electrically connected with the first voltage end; the second electrode of the sixth MOS tube and the input end of the fifth inverter are electrically connected to a fourth node; the fourth node is coupled to a negative-pressure power supply; the output end of the fifth inverter is electrically connected with the input end of the sixth inverter; the output end of the sixth inverter is electrically connected with the second initialization end; the first power supply end of the fifth inverter and the first power supply end of the sixth inverter are electrically connected with the first voltage end; the second power end of the fifth inverter and the second power end of the sixth inverter are electrically connected with the negative-pressure power supply or are grounded.

13. The power detection circuit of claim 12, wherein the initialization module further comprises a fourth initialization terminal; the fourth initialization end is electrically connected with the output end of the fifth inverter;

Under the control of the first control signal, the first voltage signal is output to the load as a fourth initialization signal through the fourth initialization terminal;

under the control of the second control signal, the power signal or the ground signal of the negative-pressure power supply is used as the fourth initialization signal to be output to the load through the fourth initialization terminal.

14. The power supply detection circuit of claim 12, wherein the second initialization unit further comprises a second current source;

the input end of the second current source is electrically connected with the fourth node; and the output end of the second current source is electrically connected with the negative pressure power supply.

15. The power supply detection circuit according to claim 12, wherein the second initialization unit further includes a seventh inverter and an eighth inverter;

the seventh inverter and the eighth inverter are connected in series between the third node and the grid electrode of the sixth MOS tube; the first power supply end of the seventh inverter and the first power supply end of the eighth inverter are electrically connected with the first voltage end; the second power supply terminal of the seventh inverter and the second power supply terminal of the eighth inverter are both grounded.

16. A silicon-based display panel, comprising: the display device comprises a silicon-based substrate, a display unit and a power module; the power supply module comprising the power supply detection circuit of any one of claims 1-15;

the power module and the display unit are both formed on the silicon-based substrate.

17. A display device, comprising: a silicon-based display panel as defined in claim 16.