CN117389946A - FFT (fast Fourier transform) implementation structure capable of dynamically expanding points - Google Patents
FFT (fast Fourier transform) implementation structure capable of dynamically expanding points Download PDFInfo
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Abstract
The invention discloses an FFT (fast Fourier transform) realization structure capable of dynamically expanding the number of points, which belongs to the technical field of digital signal processing and comprises a system bus, an N-point FFT calculation unit, an expansion control unit and a DMA (direct memory access) controller; the DMA controller is connected with the system bus, the system bus is correspondingly connected with the N-point FFT computing unit, the DMA controller writes data into the N-point FFT computing unit through the system bus by taking the N-point as a unit, and completes the N-point FFT computing, the system bus is connected with the system sharing storage unit, and the system bus sequentially stores the FFT computing results of a plurality of N points into the system sharing storage unit SRAM0, SRAM1, … and SRAM M-1, and each SRAM stores the N-point FFT computing value. In the invention, based on N-point FFT IP hard cores, according to the capacity of the SOC shared memory space, N multiplied by M-point FFT operation can be realized, wherein M is a positive integer greater than 0, the upper limit value depends on the size of the SOC shared memory space, the dynamic matching of FFT points is realized, and the use efficiency of SOC storage resources is improved.
Description
Technical Field
The invention belongs to the technical field of digital signal processing, and particularly relates to an FFT (fast Fourier transform) implementation structure capable of dynamically expanding points.
Background
In SOC (System on Chip), the implementation manner of FFT is usually encapsulated in a dedicated FFT IP core (Intellectual Property, intellectual property core), the number of FFT points that can be implemented is determined by the SRAM (Static Random-Access Memory) resources occupied by the FFT, and since the SRAM resources occupied by the FFT IP core are already solidified after the SOC Chip is designed, the System requirements and resource usage situation cannot be expanded, and when there are more unused SRAM resources in the System and operation of more FFT points is needed, the FFT implementation structure obviously does not meet the requirements.
Based on the above, the invention designs an FFT implementation structure capable of dynamically expanding the number of points so as to solve the problems.
Disclosure of Invention
The invention aims at: in order to solve the problem that after the design of the SOC chip is finished, SRAM resources occupied by FFT IP core are solidified and cannot be expanded according to the system requirements and resource use conditions, when the unused SRAM resources in the system are more and the operation of FFT with more points is needed, the FFT implementation structure obviously does not meet the requirements, and the FFT implementation structure capable of dynamically expanding the points is provided.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
the FFT implementation structure capable of dynamically expanding the number of points comprises a system bus, an N-point FFT calculation unit, an expansion control unit and a DMA controller;
the DMA controller is connected with the system bus, the system bus is correspondingly connected with the N-point FFT computing unit, and the DMA controller writes data into the N-point FFT computing unit through the system bus by taking the N point as a unit and completes the N-point FFT computation;
the system bus is connected with the system sharing storage unit, and sequentially stores a plurality of N-point FFT calculation results to the system sharing storage units SRAM0, SRAM1, … and SRAM M-1 through the system bus, wherein each SRAM stores N-point FFT calculation values;
the N-point FFT calculation unit is connected with the expansion control unit, the expansion control unit respectively reads data from SRAM0, SRAM1, … and SRAM M-1, and obtains FFT output values of M multiplied by N points through a radix-M butterfly operation unit in the FFT calculation engine according to M N-point FFT calculation values, and the FFT output values are stored in SRAM0, SRAM1, … and SRAM M-1.
As a further description of the above technical solution:
in the system software configuration FFT related parameters, an expansion control unit is configured, the FFT point number is set to be N multiplied by M points, the value of M is a positive integer larger than 0, a DMA controller is configured, N point data are written into an FFT calculation unit each time, and data writing is completed in M times.
As a further description of the above technical solution:
in the system shared memory unit, M memory units of SRAM0, SRAM1, … and SRAM M-1 are divided in an SOC shared memory space, and each memory unit has a length of N.
As a further description of the above technical solution:
and the FFT calculation unit receives DMA write-in data from the interface, performs address mapping according to the calculation sequence of the N-point FFT, and writes the address mapping into an SRAM in the FFT.
As a further description of the above technical solution:
and after receiving the N-point data, the FFT calculation unit pulls down a write request signal of the DMA controller, pauses the data writing action of the DMA, and starts the FFT calculation of the N points.
As a further description of the above technical solution:
after the FFT calculation unit completes the FFT calculation of N points, the FFT output value of N points is written into the shared memory space SRAM0 through a main interface and a system bus.
As a further description of the above technical solution:
in the system software configuring the FFT related parameters, if M=1, the FFT extension control unit sends an interrupt to the CPU to inform the CPU that the FFT calculation of the N×M point is completed; if M >1, receiving DMA write data again, starting FFT calculation of N points again, writing the FFT output value of N points into the shared memory space SRAM1 through a main interface and a system bus, repeating the step until the SRAM0, the SRAM1, the SRAM … and the SRAM M-1 are fully written, and entering the next step.
As a further description of the above technical solution:
in the system software, setting the address pointers of the SRAMs 0 and … and the SRAMM-1 as i, enabling the i=0, enabling the FFT expansion control unit to read M data from the SRAMs 0 and … and the SRAMM-1 address i respectively through a main interface built in the FFT calculation unit, storing the M data into a buffer built in the expansion control unit, completing one-time base-M butterfly operation through an FFT calculation engine built in the calculation unit to obtain M calculation values, and writing back the M calculation values into the SRAMs 0 and … and the SRAMM-1 address i respectively through the main interface built in the calculation unit.
As a further description of the above technical solution:
in the system software configuration FFT related parameters, an address pointer is added with 1, i.e. i=i+1, an FFT expansion control unit reads M data from SRAM0, … and an SRAM M-1 address i+1 respectively through a main interface built in the FFT calculation unit, the M data are stored in a buffer built in the expansion control unit, a primary-M butterfly operation is completed through an FFT calculation engine built in the calculation unit to obtain M calculated values, and the M calculated values are written back to SRAM0, … and an SRAM M-1 address i respectively through the main interface built in the calculation unit until i=N-1, which means that FFT calculation of N×M points is completed, and the FFT expansion control unit sends an interrupt to a CPU to inform the CPU that FFT calculation of N×M points is completed.
In summary, due to the adoption of the technical scheme, the beneficial effects of the invention are as follows:
in the invention, based on N-point FFT IP hard cores, according to the capacity of the SOC shared memory space, N multiplied by M-point FFT operation can be realized, wherein M is a positive integer greater than 0, the upper limit value depends on the size of the SOC shared memory space, the dynamic matching of FFT points is realized, and the use efficiency of SOC storage resources is improved.
Drawings
FIG. 1 is a block diagram of an FFT implementation architecture with dynamic point expansion according to the present invention;
FIG. 2 is a schematic diagram of a radix-M butterfly operation unit in an FFT implementation structure with dynamically expandable points according to the present invention;
fig. 3 is a schematic diagram of a processing flow of i=0 and i=i+1 in an FFT implementation structure capable of dynamically expanding the number of points according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-3, the present invention provides a technical solution: the FFT implementation structure capable of dynamically expanding the number of points comprises a system bus, an N-point FFT calculation unit, an expansion control unit and a DMA controller;
the DMA controller is connected with the system bus, the system bus is correspondingly connected with the N-point FFT computing unit, and the DMA controller writes data into the N-point FFT computing unit through the system bus by taking the N point as a unit and completes the N-point FFT computation;
the system bus is connected with the system sharing storage unit, and sequentially stores a plurality of N-point FFT calculation results to the system sharing storage units SRAM0, SRAM1, … and SRAM M-1 through the system bus, wherein each SRAM stores N-point FFT calculation values;
the N-point FFT calculation unit is connected with the expansion control unit, the expansion control unit respectively reads data from SRAM0, SRAM1, … and SRAM M-1, and obtains FFT output values of M multiplied by N points through a radix-M butterfly operation unit in the FFT calculation engine according to M N-point FFT calculation values, and the FFT output values are stored in SRAM0, SRAM1, … and SRAM M-1.
Specifically, in the system software configuring the relevant parameters of the FFT, an expansion control unit is configured, the number of FFT points is set to be N multiplied by M points, the value of M is a positive integer larger than 0, a DMA controller is configured, N-point data is written into the FFT calculation unit each time, and data writing is completed in M times.
Specifically, in the system shared memory unit, M memory units of SRAM0, SRAM1, … and SRAM M-1 are divided in the SOC shared memory space, and each memory unit has a length of N.
Specifically, the FFT computation unit receives DMA write-in data from an interface, performs address mapping according to the computation sequence of the N-point FFT, and writes the data into the SRAM inside the FFT.
Specifically, after receiving the N-point data, the FFT computation unit pulls down a write request signal of the DMA controller, suspends the data writing action of the DMA, and starts the FFT computation of the N-point.
Specifically, after the FFT calculation unit completes the FFT calculation of N points, the FFT output value of N points is written into the shared memory space SRAM0 through the main interface and the system bus.
Specifically, in the system software configuring FFT related parameters, if m=1, it indicates that FFT computation of n×m points has been completed, and the FFT extension control unit sends an interrupt to the CPU to inform the CPU that FFT computation of n×m points has been completed; if M >1, receiving DMA write data again, starting FFT calculation of N points again, writing the FFT output value of N points into the shared memory space SRAM1 through a main interface and a system bus, repeating the step until the SRAM0, the SRAM1, the SRAM … and the SRAM M-1 are fully written, and entering the next step.
Specifically, in the system software, setting the address pointers of the SRAMs 0 and … and the SRAM M-1 as i, enabling the i=0, respectively reading M data from the SRAMs 0 and … and the SRAM M-1 address i through a main interface built in the FFT computation unit by the FFT expansion control unit, storing the M data into a buffer built in the expansion control unit, completing one-time radix-M butterfly operation through the FFT computation engine built in the computation unit to obtain M computation values, and respectively writing back the M computation values into the SRAMs 0 and … and the SRAM M-1 address i through the main interface built in the computation unit.
Specifically, in the system software configures FFT related parameters, an address pointer is added with 1, i.e., i=i+1, the FFT extension control unit reads M data from the SRAM0, … and the SRAM M-1 address i+1 respectively through a main interface built in the FFT calculation unit, and stores the M data in a buffer built in the extension control unit, completes one-time radix-M butterfly operation through an FFT calculation engine built in the calculation unit to obtain M calculated values, and writes back the M calculated values to the SRAM0, … and the SRAM M-1 address i respectively through the main interface built in the calculation unit until i=n-1, which indicates that FFT calculation of n×m points is completed, and the FFT extension control unit sends an interrupt to the CPU to inform the CPU that FFT calculation of n×m points has been completed.
Working principle, when in use:
firstly, configuring an expansion control unit in FFT related parameters by system software, setting the number of FFT points to be N multiplied by M points, setting the value of M to be a positive integer larger than 0, configuring a DMA controller, writing N point data into an FFT calculation unit each time, finishing data writing in M times, and dividing M storage units SRAM0, SRAM1, … and SRAM M-1 in an SOC shared memory space, wherein the length of each storage unit is N;
secondly, the FFT calculation unit receives DMA write-in data from the interface, performs address mapping according to the calculation sequence of the N-point FFT, writes the data into an SRAM in the FFT, pulls down a write request signal of the DMA controller after the FFT calculation unit receives the N-point data, pauses the data write-in action of the DMA, and starts the FFT calculation of the N-point;
third, after finishing the FFT calculation of N points, the FFT calculation unit writes the FFT output value of N points into the shared memory space SRAM0 through a main interface and a system bus;
a fourth unit for indicating that FFT computation of n×m points has been completed if m=1, the FFT extension control unit sending an interrupt to the CPU informing the CPU that FFT computation of n×m points has been completed; if M >1, receiving DMA write data again, starting FFT calculation of N points again, writing the FFT output value of N points into a shared memory space SRAM1 through a main interface by a system bus, and entering a fifth step after the SRAM0, the SRAM1, the … and the SRAM M-1 are all fully written;
setting the address pointer of the SRAM0, … and the SRAM M-1 as i, enabling i=0, enabling the FFT expansion control unit to read M data from the SRAM0, … and the SRAM M-1 address i respectively through a main interface built in the FFT calculation unit, storing the M data into a buffer built in the expansion control unit, completing one-time base-M butterfly operation through an FFT calculation engine built in the calculation unit to obtain M calculation values, and writing back the M calculation values into the SRAM0, … and the SRAM M-1 address i respectively through the main interface built in the calculation unit;
and step six, adding 1 to the address pointer, namely i=i+1, enabling the FFT expansion control unit to read M data from the SRAMs 0 and … and the SRAMM-1 address i+1 respectively through a main interface built in the FFT calculation unit, storing the data into a buffer built in the expansion control unit, completing one-time base-M butterfly operation through an FFT calculation engine built in the calculation unit to obtain M calculated values, and writing back the M calculated values into the SRAMs 0 and … respectively through the main interface built in the calculation unit and the SRAMM-1 address i until i=N-1, wherein the FFT expansion control unit sends an interrupt to the CPU to inform the CPU that the FFT calculation of the N×M point is completed.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art, who is within the scope of the present invention, should make equivalent substitutions or modifications according to the technical scheme of the present invention and the inventive concept thereof, and should be covered by the scope of the present invention.
Claims (9)
1. The FFT implementation structure capable of dynamically expanding the number of points is characterized by comprising a system bus, an N-point FFT calculation unit, an expansion control unit and a DMA controller;
the DMA controller is connected with the system bus, the system bus is correspondingly connected with the N-point FFT computing unit, and the DMA controller writes data into the N-point FFT computing unit through the system bus by taking the N point as a unit and completes the N-point FFT computation;
the system bus is connected with the system sharing storage unit, and sequentially stores a plurality of N-point FFT calculation results to the system sharing storage units SRAM0, SRAM1, … and SRAM M-1 through the system bus, wherein each SRAM stores N-point FFT calculation values;
the N-point FFT calculation unit is connected with the expansion control unit, the expansion control unit respectively reads data from SRAM0, SRAM1, … and SRAM M-1, and obtains FFT output values of M multiplied by N points through a radix-M butterfly operation unit in the FFT calculation engine according to M N-point FFT calculation values, and the FFT output values are stored in SRAM0, SRAM1, … and SRAM M-1.
2. The FFT implementation structure of claim 1, wherein in the system software configures FFT related parameters, an expansion control unit is configured, the FFT point is set to an nxm point, the value of M is a positive integer greater than 0, a DMA controller is configured, N-point data is written into the FFT computation unit each time, and data writing is completed M times.
3. The FFT implementation structure of claim 2, wherein M memory cells SRAM0, SRAM1, …, SRAM M-1 are divided in the SOC shared memory space in the system shared memory unit, and each memory cell has a length of N.
4. The FFT implementation structure of claim 3, wherein the FFT computation means receives DMA write data from an interface, performs address mapping according to the computation order of the N-point FFT, and writes the data into the SRAM inside the FFT.
5. The FFT implementation structure of claim 4 wherein the FFT computation means pulls down a write request signal of the DMA controller, suspends a data writing operation of the DMA, and starts FFT computation of N points after receiving N-point data.
6. The FFT implementation structure of claim 5, wherein after the FFT calculation unit completes the FFT calculation of N points, the FFT output value of N points is written into the shared memory space SRAM0 through the main interface via the system bus.
7. The FFT implementation structure of claim 6, wherein the system software configures FFT-related parameters, if m=1, to indicate that FFT computation of n×m points has been completed, and the FFT extension control unit sends an interrupt to the CPU, informing the CPU that FFT computation of n×m points has been completed; if M >1, receiving DMA write data again, starting FFT calculation of N points again, writing the FFT output value of N points into the shared memory space SRAM1 through a main interface and a system bus, repeating the step until the SRAM0, the SRAM1, the SRAM … and the SRAM M-1 are fully written, and entering the next step.
8. The FFT implementation structure of claim 7, wherein in the system software configures FFT related parameters, SRAM0, … is set, the address pointer of SRAM M-1 is i=0, the FFT expansion control unit reads M data from SRAM0, … and SRAM M-1 address i through the main interface built in the FFT computation unit, and stores the M data in the buffer built in the expansion control unit, and completes one radix-M butterfly operation through the FFT computation engine built in the computation unit to obtain M computation values, and writes back SRAM0, … and SRAM M-1 address i through the main interface built in the computation unit.
9. The FFT implementation structure of claim 8, wherein the system software configures FFT-related parameters, wherein the system software adds 1 to an address pointer, i.e., i=i+1, and the FFT expansion control unit reads M data from the SRAM0, … and the SRAM M-1 address i+1 through a main interface built in the FFT computation unit, and stores the M data in a buffer built in the expansion control unit, and completes one radix-M butterfly operation through an FFT computation engine built in the computation unit to obtain M computation values, and writes back the M computation values to the SRAM0, … and the SRAM M-1 address i through the main interface built in the computation unit until i=n-1, respectively, to indicate that FFT computation of n×m points has been completed, and the FFT expansion control unit sends an interrupt to the CPU to inform the CPU that FFT computation of n×m points has been completed.
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